Chip encapsulation unit with double-sided RDL and method for manufacturing the same

Abstract

The present invention provides a chip encapsulation unit equipped with double-sided RDL and a method for manufacturing the same. [Solution] A chip encapsulation unit 1 equipped with a double-sided redistribution layer (RDL) and a method for manufacturing the same, wherein the chip encapsulation unit 1 has a chip 10, a first RDL 20 installed on the first surface 11 of the chip 10, a second RDL 30 installed on the second surface 12 of the chip 10, and at least one side connecting wiring 40, and the chip 10 is electrically connected to a plurality of external connectors 33 on each second connecting wiring 32 via a plurality of die pads 13 of the chip 10, a plurality of first connecting wirings 22 in the first RDL 20, each side connecting wiring 40 and a plurality of second connecting wirings 32 in the second RDL 30, and is electrically connected to the outside via each external connector 33, solving the problem that conventional chip encapsulation units 1 have a complex structure and increased overall thickness due to the provision of multilayer wiring layers or through-silicon vias, and is advantageous in reducing manufacturing costs.

Description

Technical Field

[0001] The present invention relates to a chip encapsulation unit and a method for manufacturing the same, and particularly to a chip encapsulation unit having double-sided RDL (RDL, Redistribution Layer) and a method for manufacturing the same.

Background Art

[0002] In the field of chip encapsulation technology, a conventional chip encapsulation unit forms a plurality of TSV through-vias on the chip encapsulation unit by means of a stacked multilayer wiring layer or using a through-silicon via (TSV) process, whereby an internal chip is electrically connected from one surface of the chip encapsulation unit to the other surface and further electrically connected to the outside. However, the design of the multilayer wiring layer and the design of the TSV through-via are relatively complex. As a result, the manufactured chip encapsulation unit becomes thick and does not meet the trend of "light, thin, short, and small" in current chip encapsulation. Moreover, it is not easy to reduce the manufacturing cost, and when using the TSV process, there is also a risk of damaging the chip structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventional chip encapsulation units require the use of multilayer wiring structures or through-silicon via (TSV) processes to achieve electrical connections between chips. However, these structures and processes are complex in design, resulting in high manufacturing costs. Furthermore, they increase the overall thickness of the encapsulation unit, making it difficult to meet the "light, thin, and small" requirements. In addition, the use of TSV processes carries the risk of damaging the chip structure. The present invention provides a chip encapsulation unit equipped with a double-sided RDL (Redistribution Layer) and a method for manufacturing the same, which solve these problems. [Means for solving the problem]

[0005] To achieve the above objective, the present invention provides a chip encapsulation unit equipped with a double-sided RDL (Redistribution Layer) and a method for manufacturing the same. The chip encapsulation unit comprises a chip, a first RDL installed on the first surface of the chip, a second RDL installed on the second surface of the chip, and at least one side connecting wiring. The chip is electrically connected to multiple external connectors on each of the second connection wires via multiple die pads of the chip, multiple first connection wires in the first RDL, each of the side connection wires, and multiple second connection wires in the second RDL, and is further electrically connected to the outside via each of the external connectors. This solves the problem of conventional chip encapsulation units becoming structurally complex and thicker due to the provision of multilayer wiring layers or through-silicon vias, and is advantageous for reducing manufacturing costs. A chip encapsulation unit comprising a double-sided RDL according to the present invention, wherein the chip encapsulation unit is a rectangular structure having four sides, and the chip encapsulation unit includes a chip, a first RDL, a second RDL, and at least one side-connecting wiring. The chip is a rectangular structure having a first surface, a second surface opposite the first surface, and four sides, and has a plurality of die pads on the first surface of the chip, and the first RDL is formed on the first surface of the chip using an RDL process. The first RDL includes a plurality of first connection wires, each of which is made of a metallic material and is electrically connected to each of the die pads. The second RDL is formed on the second surface of the chip by the RDL process, and the second RDL includes a plurality of second connection wires and a plurality of external connectors, each of the second connection wires being made of a metallic material, each of the external connectors being made of a metallic material and mounted on each of the second connection wires, each of the side connection wires being made of a metallic material, each of the side connection wires being mounted on each of the side positions of the chip sealing unit, i.e., on at least one side of the chip, and each of the side connection wires is connected to the first RDL and the second RDL. The chips are positioned between the first and second connection wires and are electrically connected to each of the first and second connection wires, and the chips are electrically connected to each of the external connectors via each of the die pads, each of the first connection wires, each of the side connection wires and each of the second connection wires, and are further electrically connected to external circuits via each of the external connectors, and the chip encapsulation units are formed by cutting them out individually by cutting on the wafer, and the wafer has a first surface and a second surface opposite to the first surface, and a plurality of the chip encapsulation units are arranged on the wafer The chips are arranged adjacent to each other in an array, with a cutting region between each adjacent chip encapsulation unit, and a plurality of through vias are formed on each cutting region, penetrating axially from the first surface to the second surface, each through via is located on the outer edge of at least one side surface of the chip of each chip encapsulation unit, and each through via contains an axial connecting wiring made of a metallic material, each axial connecting wiring is located between the first RDL and the second RDL of each chip encapsulation unit and is electrically connected to each first connecting wiring and each second connecting wiring, the cutting operation is performed by moving a cutting tool along each cutting region of the wafer, and after cutting, a dicing groove smaller in width than each cutting region is formed in each cutting region, and at the same time as the formation of each dicing groove, some of each through via and some of each axial connecting wiring are cut off, and the parts of each axial connecting wiring and each through via that were not cut off are left on the outer edge of at least one side surface of each chip, thereby forming each of the side connecting wirings of each chip encapsulation unit.

[0006] In one embodiment of the present invention, the hole diameter of each of the through vias on the wafer is greater than the width of each of the dicing grooves.

[0007] In one embodiment of the present invention, the first RDL further includes a first insulating layer having a plurality of first recesses, each of which exposes each of the die pads of the chip to the outside, and each of the first connection wirings is made of metal paste filled in each of the first recesses; the second RDL further includes a second insulating layer having a plurality of second recesses, and each of the second connection wirings is made of metal paste filled in each of the second recesses.

[0008] In one embodiment of the present invention, the metal paste used by each of the first and second connecting wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

[0009] In one embodiment of the present invention, each of the external connectors is a solder ball.

[0010] A method for manufacturing a chip encapsulation unit having double-sided RDL, further provided by the present invention, includes the following steps: Step S1: A wafer is provided, the wafer having a first surface and a second surface opposite to the first surface, and a plurality of chips are arranged adjacently on the wafer in an array, each chip having four sides, each chip having a first surface and a second surface, each chip having a plurality of die pads on the first surface, each adjacent chip having a cutting region, each cutting region having a plurality of through vias formed axially through from the first surface of the wafer to the second surface, each through via is located on the outer edge of at least one side of each chip, each through via includes axial connecting wiring, each axial connecting wiring is made of a metallic material. Step S2: Using the RDL process, the first RDL is formed on the first surface of each chip, the first surface of the wafer, and one end of each axial connecting wiring, wherein the first RDL has a plurality of first connecting wirings, and each first connecting wiring is made of a metallic material and is electrically connected to each axial connecting wiring. Step S3: Using the RDL process, a second RDL is formed on the second surface of each chip, on the second surface of the wafer, and on one end of each axial connecting wiring, the second RDL layer having a plurality of second connecting wirings, each of which is electrically connected to each axial connecting wiring, and is made of a metallic material, further having a plurality of external connectors installed thereon, each of which is also made of a metallic material, Step S4: Using a cutting tool, the wafer is cut along each of the cutting regions, and after cutting, a dicing groove smaller in width than each cutting region is formed on each cutting region, and simultaneously with the formation of each dicing groove, some of the through vias and some of the axial connecting wirings are removed, and the remaining portion of the axial connecting wirings, together with the remaining portion of the through vias, is left on the outer edge of at least one side surface of each chip, thereby forming at least one side connecting wiring, each side connecting wiring located between the first RDL and the second RDL and electrically connected to each of the first and second connecting wirings. Step S5: Once the wafer cutting is complete, a plurality of chip encapsulation units are formed, and the chips in each chip encapsulation unit are electrically connected to each external connector via each die pad, each first connection wiring, each side connection wiring, and each second connection wiring, and are further electrically connected to an external circuit via each external connector.

[0011] In one embodiment of the present invention, in step S2, the first RDL first fills a recessed groove with metal paste and then polishes it to form a connection wiring, thereby forming a plurality of first connection wirings on each chip, first laying a first insulating layer on the first surface of each chip, the first surface of the wafer and on one end of each axial connection wiring, then forming a plurality of first recessed grooves horizontally on the first insulating layer, and moreover, one end of each axial connection wiring is exposed from each first recessed groove, Next, metal paste is filled into each of the first recesses, and the thickness of the metal paste is greater than the surface of the first insulating layer. Finally, the metal paste that fills the surface higher than the surface of the first insulating layer is polished to make the surface of the metal paste flat with the surface of the first insulating layer, thereby forming each of the first connection wires.

[0012] In one embodiment of the present invention, the second RDL in step S3 utilizes a process in which a metal paste is first filled into a recessed cavity and then polished to form a connection wiring, thereby forming a plurality of the second connection wirings on each of the chips, and a second insulating layer is laid on the second surface of each of the existing chips, on the second surface of the wafer, and on one end of each of the axial connection wirings. Next, a plurality of second recesses are formed horizontally on the second insulating layer, and one end of each axial connecting wire is exposed to the outside from each of the second recesses. Next, metal paste is filled into each of the second recesses, and the thickness of the metal paste is greater than the surface of the second insulating layer. Finally, the metal paste that fills the surface of the second insulating layer higher than the surface of the second insulating layer is polished to make the surface of the metal paste flat with the surface of the second insulating layer, thereby forming each of the second connecting wires. [Effects of the Invention]

[0013] According to the present invention, by forming first and second RDLs on both sides of the chip, the complexity of the multilayer wiring layer design can be avoided and manufacturing costs can be reduced. In addition, by adopting a configuration in which the wirings on both sides of the chip are electrically connected via side connection wirings, the through-silicon via (TSV) process can be eliminated, simplifying the process and facilitating the wiring design. Furthermore, by using a manufacturing method in which side connection wirings are formed simultaneously with the cutting process, the process of forming side wirings can be simplified, contributing to an improvement in production efficiency and cost reduction.

Brief Description of the Drawings

[0014] [Figure 1] It is a side cross-sectional view of an embodiment of a chip encapsulation unit according to the present invention. [Figure 2] It is a top view of an embodiment of a wafer according to the present invention. [Figure 3] It is a side cross-sectional view of an embodiment of a wafer according to the present invention. [Figure 4] It is a partial enlarged view of FIG. 3. [Figure 5] It is a side cross-sectional view of a chip according to the present invention. [Figure 6] It is a diagram showing a state in which axial connection wirings are installed on the outer edge of the side surface of the chip in FIG. 5. [Figure 7] It is a diagram showing a state in which a first insulating layer is installed on the chip in FIG. 6. [Figure 8] It is a diagram showing a state in which a metal paste is filled in the first recess in FIG. 7. [Figure 9] It is a diagram showing a state in which the metal paste in FIG. 8 is polished to form a first connection wiring. [Figure 10] It is a diagram showing a state in which a second insulating layer is installed on the chip in FIG. 9. [Figure 11] It is a diagram showing a state in which a metal paste is filled in the second recess in FIG. 10. [Figure 12] It is a diagram showing a state in which the metal paste in FIG. 11 is polished to form a second connection wiring. [Figure 13] It is a diagram showing a state in which an external connector is installed on the second connection wiring in FIG. 12. [Figure 14] It is a top plan view of another embodiment of a wafer according to the present invention. [Figure 15] This is a side view cross-sectional view of another embodiment of the chip encapsulation unit according to the present invention. [Modes for carrying out the invention]

[0015] As shown in Figure 1, in the chip encapsulation unit 1 equipped with a double-sided RDL (Redistribution Layer) according to the present invention, the chip encapsulation unit 1 is a rectangular structure and has four sides 1a. The chip encapsulation unit 1 includes a chip 10, a first RDL 20, a second RDL 30, and at least one side-connecting wiring 40.

[0016] The chip 10 has a first surface 11 and a second surface 12 facing the first surface 11, and has a plurality of die pads 13 on the first surface 11 of the chip 10 (see Figure 5). The chip 10 is a rectangular structure and has four sides 14 (see Figure 2). In Figure 1, two die pads 13 are shown as an example, but the number of die pads 13 is not limited to these.

[0017] The first RDL20 is formed on the first surface 11 of the chip 10 using an RDL process, and the first RDL20 includes a plurality of first connection lines 22 (see Figure 1). Each of the first connecting wires 22 is made of a metal material and is electrically connected to each of the die pads 13.

[0018] As shown in Figure 1, the second RDL 30 is formed on the second surface 12 of the chip 10 by the RDL process, and the second RDL 30 includes a plurality of second connection wires 32 and a plurality of external connectors 33. Each of the second connecting wires 32 is made of a metal material. Each of the external connectors 33 is made of a metal material and is installed on each of the second connecting wires 32 (see Figures 1, 13, and 15).

[0019] As shown in Figure 1, each of the side connecting wirings 40 is made of a metal material and is installed on each side 1a of the chip sealing unit 1, i.e., on at least one side 14 of the chip 10. Each of the side connecting wires 40 is located between the first RDL20 and the second RDL30 and is electrically connected to each of the first connecting wires 22 and each of the second connecting wires 32.

[0020] As shown in Figures 1 and 15, the chip 10 is electrically connected to each of the external connectors 33 in order via each of the die pads 13, each of the first connection wirings 22, each of the side connection wirings 40, and each of the second connection wirings 32, and is further electrically connected to an external circuit via each of the external connectors 33.

[0021] Each chip encapsulation unit 1 is formed by cutting it out individually on the wafer 2, and the wafer 2 has a first surface 2a and a second surface 2b facing the first surface 2a (see Figure 3). Multiple chip encapsulation units 1 are arranged adjacently in an array on the wafer 2, with a cutting region 2c between each pair of adjacent chip encapsulation units 1 (see Figure 2). Multiple through vias 2d are formed on each of the cut regions 2c, extending axially from the first surface 2a to the second surface 2b (see Figures 3 and 4). Each of the through vias 2d is located on the outer edge of at least one side surface 14 of the chip 10 of each chip sealing unit 1 (see Figure 2). Each of the through vias 2d contains an axial connecting wire 2e made of a metallic material (see Figures 2 and 14). Furthermore, each axial connecting wiring 2e is located between the first RDL20 and the second RDL30 of each chip sealing unit 1 (see Figures 3 and 4) and is electrically connected to each first connecting wiring 22 and each second connecting wiring 32 (see Figure 13). The cutting operation is performed by moving the cutting tool along each cutting region 2c of the wafer 2. In each cutting region 2c, after cutting, a dicing groove 2f smaller in width than the cutting region 2c is formed (see Figures 2 to 4). Moreover, at the same time as the formation of each dicing groove 2f, some of the through vias 2d and some of the axial connecting wirings 2e are simultaneously cut off (see Figure 2). The portions of each axial connecting wire 2e and each through via 2d that were not removed are left on the outer edge of at least one side surface 14 of each chip 10, thereby forming each of the side connecting wires 40 of each chip sealing unit 1 (see Figure 2).

[0022] As shown in Figure 2, the hole diameter of each through via 2d on the wafer 2 is larger than the width of each dicing groove 2f.

[0023] As shown in Figure 7, the first RDL20 further includes a first insulating layer 21, the first insulating layer 21 having a plurality of first recesses 211, each of which exposes each of the die pads 13 of the chip 10 to the outside. Each of the first connecting wires 22 is made of metal paste 22a filled in each of the first recessed grooves 211 (see Figure 9). The second RDL30 further includes a second insulating layer 31, and the second insulating layer 31 has a plurality of second recessed grooves 311 (see Figure 10). Each of the second connecting wires 32 is made of metal paste 32a filled in each of the second recessed grooves 311 (see Figure 12).

[0024] As shown in Figures 9 and 12, the metal pastes 22a and 32a used by each of the first connecting wires 22 and second connecting wires 32 include silver paste, nanosilver paste, copper paste, or nanocopper paste.

[0025] As shown in Figure 15, each of the external connectors 33 is a solder ball, which allows the product to be used in a variety of applications.

[0026] The method for manufacturing the chip encapsulation unit 1 of the present invention includes the following steps. Step S1: A wafer 2 is provided, the wafer 2 having a first surface 2a and a second surface 2b facing the first surface 2a (see Figure 3). Furthermore, multiple chips 10 are arranged adjacently in an array on the wafer 2, and each chip 10 has four sides 14 (see Figure 2). Each of the chips 10 has a first surface 11 and a second surface 12, and a plurality of die pads 13 are formed on each of the first surfaces 11 (see Figure 5). A cutting region 2c is provided between each of the two adjacent chips 10 (see Figure 2). Multiple through vias 2d are formed on each of the cut regions 2c, penetrating axially from the first surface 2a of the wafer 2 to the second surface 2b (see Figures 3 and 4). Each of the through vias 2d is located on the outer edge of at least one of the side surfaces 14 of each chip 10, and each of the through vias 2d contains an axial connecting wire 2e (see Figure 2). Each of the aforementioned axial connecting wires 2e is made of a metal material.

[0027] Step S2: Using the RDL process, a first RDL 20 is formed on the first surface 11 of each chip 10, the first surface 2a of the wafer 2, and one end of each axial connection wiring 2e (see Figure 7). The first RDL20 has a plurality of first connection wires 22, each of which is electrically connected to each of the axial connection wires 2e (see Figure 9). Each of the first connecting wires 22 is made of a metallic material. Each first connecting wire 22 is made of a metal material.

[0028] Step S3: Using the RDL process, a second RDL 30 is formed on the second surface 12 of each chip 10, the second surface 2b of the wafer 2, and one end of each axial connection wiring 2e (see Figure 10). The second RDL30 has a plurality of second connecting wires 32, and each of the second connecting wires 32 is electrically connected to each of the axial connecting wires 2e (see Figure 12). Each of the second connecting wires 32 is made of a metal material. Multiple external connectors 33 made of metal material are installed on each of the second connection wires 32 (see Figure 13).

[0029] Step S4: Using a cutting tool, the wafer 2 is cut along each of the cutting regions 2c. After cutting, a dicing groove 2f smaller in width than each cutting region 2c is formed on each cutting region 2c. Simultaneously with the formation of each dicing groove 2f, some of the through vias 2d and some of the axial connecting wirings 2e are removed. The remaining axial connecting wirings 2e and some of the through vias 2d are left on the outer edge of at least one side surface 14 of each chip 10, thereby forming at least one side connecting wiring 40 (see Figure 2). Each of the side connecting wires 40 is located between the first RDL20 and the second RDL30 and is electrically connected to each of the first connecting wires 22 and each of the second connecting wires 32 (see Figure 1).

[0030] Step S5: Once the cutting of the wafer 2 is complete, a plurality of the chip encapsulation units 1 are formed (see Figure 3). Each chip 10 of the chip encapsulation unit 1 is electrically connected to each external connector 33 in order via each die pad 13, each first connection wiring 22, each side connection wiring 40, and each second connection wiring 32, and is further electrically connected to an external circuit via each external connector 33 (see Figures 1, 13, and 15).

[0031] In step S2, the first RDL20 further forms a plurality of first connecting wires 22 on each of the chips 10 by first filling a recessed groove with metal paste and then polishing it to form the connecting wires. First, a first insulating layer 21 is laid on the first surface 11 of each chip 10, the first surface 2a of the wafer 2, and one end of each axial connecting wiring 2e. Next, a plurality of first recesses 211 are formed horizontally on the first insulating layer 21, and each recess 211 exposes one end of each axial connecting wiring 2e to the outside (see Figure 7). Next, metal paste 22a is filled into each of the first recessed grooves 211, and the thickness of the metal paste 22a is greater than the surface of the first insulating layer 21 (see Figure 8). Finally, the metal paste 22a that fills the surface higher than the surface of the first insulating layer 21 is polished to make the surface of the metal paste 22a flat with the surface of the first insulating layer 21, thereby forming each of the first connecting wires 22 (see Figure 9).

[0032] In step S3, the second RDL30 first fills a recessed cavity with metal paste, then polishes it to form connecting wires, thereby forming a plurality of second connecting wires 32 on each of the chips 10. First, a second insulating layer 31 is formed on the second surface 12 of each chip 10, the second surface 2b of the wafer 2, and one end of each axial connecting wiring 2e. Next, a plurality of second recesses 311 are formed horizontally on the second insulating layer 31, and each recess 311 exposes one end of the axial connecting wiring 2e to the outside (see Figure 10). Next, metal paste 32a is filled into each of the second recessed grooves 311, at which point the thickness of the metal paste 32a becomes greater than the surface of the second insulating layer 31 (see Figure 11). Finally, the metal paste 32a that fills the surface higher than the surface of the second insulating layer 31 is polished to make the surface of the metal paste 32a flat with the surface of the second insulating layer 31, thereby forming each of the second connecting wires 32 (see Figure 12).

[0033] The process of forming each of the first and second connecting wires 22 and 32 is an important step in the RDL of the chip encapsulation unit 1 and is a process that can be carried out precisely. Therefore, the process is simplified, and each of the connecting wires in the RDL maintains electrical extension and interconnection in the XY plane while simultaneously achieving a certain degree of thinning and miniaturization. The formation process described herein is an example of a preferred embodiment of the present invention and does not limit the scope of the present invention.

[0034] The chip encapsulation unit 1 of the present invention has the following advantages compared to conventional chip encapsulation unit technology: (1) In order to form the first and second RDLs 20 and 30 of the present invention on the first and second surfaces 11 and 12 of the chip 10, respectively, in the RDL process, the problem of the complexity of conventional multilayer wiring layer design can be solved and manufacturing costs can be reduced. (2) The chip 10 of the present invention allows the first and second connecting wires 22 and 32 on both surfaces to be electrically connected through each of the side connecting wires 40, thus eliminating the need for through-silicon via (TSV) processes, which is advantageous for simplifying the process and reducing the difficulty and cost of wiring design on the manufacturing side. (3) In step S4 of the manufacturing method of the chip sealing unit 1 of this invention, each of the side connecting wires 40 is formed on each of the side surfaces 1a of the chip sealing unit 1 at the same time as cutting, so the process of forming each of the side connecting wires 40 can be simplified, which is advantageous in reducing manufacturing costs. [Explanation of symbols]

[0035] 1 Chip encapsulation unit 1a side 10 chips 11 1st surface 12 Second surface 13 Die Pad 14 Side 20 1st RDL 21 First insulating layer 211 1st concave tank 22 First connection wiring 22a Metal paste 30 2nd RDL 31. Second insulating layer 311 Second concave tank 32 Second connection wiring 32a Metal paste 33 External connectors 40 Side-mounted wiring 2 wafers 2a First surface 2b Second surface 2c Cut-off area 2d Piercing View 2e axis direction connection wiring 2f ダイシング ditch

Claims

1. In a chip encapsulation unit having a double-sided redistribution layer (RDL), the chip encapsulation unit is a rectangular structure having four sides, The chip encapsulation unit includes a chip, a first RDL, a second RDL, and at least one side-connecting wiring. The chip has a first surface 11 and a second surface opposite to the first surface, and has a plurality of die pads on the first surface of the chip, and the chip is a rectangular structure and has four sides, The first RDL is formed on the first surface of the chip using an RDL process, and the first RDL includes a plurality of first connecting wires made of a metallic material, and each of the first connecting wires is electrically connected to each of the die pads. The second RDL is formed on the second surface of the chip using an RDL process, and the second RDL includes a plurality of second connecting wires and a plurality of external connectors made of a metallic material, each of which is made of a metallic material and installed on each second connecting wire. The at least one side-connecting wiring is made of a metal material and is installed on each of the sides of the chip encapsulation unit, i.e., on at least one side of the chip, and each side-connecting wiring is located between the first RDL and the second RDL and is electrically connected to each of the first connecting wiring and each of the second connecting wiring. The chips are electrically connected to each external connector via each die pad, each first connection wiring, each side connection wiring, and each second connection wiring, and are further electrically connected to an external circuit via each external connector. Each chip encapsulation unit is formed by cutting out an individual chip from a wafer, the wafer having a first surface and a second surface opposite to the first surface, a plurality of chip encapsulation units are arranged adjacently in an array on the wafer, there is a cutting region between each pair of adjacent chip encapsulation units, a plurality of through vias are formed on each cutting region, penetrating axially from the first surface to the second surface, each through via is located on the outer edge of at least one side of the chip of each chip encapsulation unit, and each through via contains an axial connecting wiring made of a metal material, each axial connecting wiring is located between the first RDL and the second RDL of each chip encapsulation unit and is electrically connected to each first connecting wiring and each second connecting wiring. The chip encapsulation unit and its manufacturing method, comprising a double-sided RDL, wherein the cutting operation is performed by moving a cutting tool along each cutting region of the wafer, and in each cutting region, after cutting, a dicing groove smaller in width than the cutting region is formed, and simultaneously with the formation of each dicing groove, some of each through via and some of each axial connecting wiring are simultaneously cut off, and the parts of each axial connecting wiring and each through via that are not cut off are left on the outer edge of at least one side surface of each chip, thereby forming each of the side connecting wirings of each chip encapsulation unit.

2. A chip encapsulation unit comprising a double-sided RDL according to claim 1, wherein the hole diameter of each of the through vias on the wafer is greater than the width of each of the dicing grooves.

3. A chip encapsulation unit comprising a double-sided RDL according to claim 1, wherein the first RDL further includes a first insulating layer, the first insulating layer having a plurality of first recesses, each of the first recesses exposing each of the die pads of the chip to the outside, and each of the first connection wirings is composed of metal paste filled in each of the first recesses, and the second RDL further includes a second insulating layer, the second insulating layer having a plurality of second recesses, and each of the second connection wirings is composed of metal paste filled in each of the second recesses.

4. The chip encapsulation unit comprising a double-sided RDL according to claim 1, wherein each of the external connectors is a solder ball.

5. A method for manufacturing a chip encapsulation unit having a double-sided redistribution layer (RDL) includes the following steps: Step S1: A wafer is provided, the wafer having a first surface and a second surface opposite to the first surface, and a plurality of chips are arranged adjacently on the wafer in an array, each chip having four sides, each chip having a first surface and a second surface, each chip having a plurality of die pads on the first surface, each adjacent chip having a cutting region, each cutting region having a plurality of through vias formed axially through from the first surface of the wafer to the second surface, each through via is located on the outer edge of at least one side of each chip, and an axial connecting wiring made of a metal material is installed inside each through via. Step S2: Using the RDL process, a first RDL is formed on the first surface 11 of each chip, the first surface of the wafer, and one end of each axial connecting wiring, wherein the first RDL has a plurality of first connecting wirings made of a metallic material, and each of the first connecting wirings is electrically connected to each of the axial connecting wirings. Step S3: Using the RDL process, a second RDL is formed on the second surface of each chip, on the second surface of the wafer, and on one end of each axial connecting wiring, wherein the second RDL has a plurality of second connecting wirings made of a metallic material, and each of the second connecting wirings is electrically connected to each of the axial connecting wirings, and a plurality of external connectors made of a metallic material are installed on each of the second connecting wirings. Step S4: Using a cutting tool, the wafer is cut along each of the cutting regions, and after cutting, a dicing groove smaller in width than each cutting region is formed on each cutting region, and simultaneously with the formation of each dicing groove, some of the through vias and some of the axial connecting wirings are removed, and the parts of the axial connecting wirings and through vias that were not removed are left on the outer edge of at least one side surface of each chip, thereby forming at least one side connecting wiring, each side connecting wiring is located between the first RDL and the second RDL, and each side connecting wiring is electrically connected to each first connecting wiring and each second connecting wiring. Step S5: A method for manufacturing a chip encapsulation unit comprising a double-sided redistribution layer (RDL), wherein, upon completion of cutting the wafer, a plurality of the chip encapsulation units are formed, and the chips of each chip encapsulation unit are electrically connected to each external connector via each die pad, each first connection wiring, each side connection wiring, and each second connection wiring, and are further electrically connected to an external circuit via each external connector.

6. In step S2, the first RDL is formed on each of the chips by first filling a recessed cavity with metal paste and then polishing it to form the connection wiring, First, a first insulating layer is laid on the first surface of each chip, on the first surface of the wafer, and on one end of each axial connection wiring. Next, a plurality of first recesses are formed horizontally on the first insulating layer, and each of the recesses exposes one end of each of the axial connecting wires to the outside. Next, metal paste is filled into each of the first recesses, and the thickness of the metal paste is greater than the surface of the first insulating layer. Finally, the metal paste that fills the surface higher than the surface of the first insulating layer is polished to make the surface of the metal paste flat with the surface of the first insulating layer to form each of the first connecting wires. In step S3, the second RDL first fills a recessed cavity with metal paste, then polishes it to form connecting wires, thereby forming a plurality of the second connecting wires on each of the chips. First, a second insulating layer is formed on the second surface of each chip, the second surface of the wafer, and one end of each axial connection wiring. Next, a plurality of second recesses are formed horizontally on the second insulating layer, and each of the recesses exposes one end of the axially connected wiring to the outside. Next, metal paste is filled into each of the second recessed grooves, and at this time the thickness of the metal paste becomes higher than the surface of the second insulating layer. Finally, the method for manufacturing a chip encapsulation unit comprising a double-sided redistribution layer (RDL) according to claim 5, comprising polishing the metal paste that is filled higher than the surface of the second insulating layer to make the surface of the metal paste flat with the surface of the second insulating layer to form each of the second connection wirings.

7. A method for manufacturing a chip encapsulation unit comprising a double-sided RDL according to claim 6, wherein in step S2, each of the first connecting wires and the metal paste used by each of the first connecting wires in step S2 include silver paste, nano-silver paste, copper paste, or nano-copper paste.

8. A method for manufacturing a chip encapsulation unit comprising a double-sided RDL according to claim 6, wherein each of the external connectors in step S3 is a solder ball.

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