A method for flexible design of refractive index confinement in vertical cavity surface-emitting lasers using overgrowth

Abstract

To provide a vertical-cavity surface-emitting laser (VCSEL). [Solution] The vertical cavity surface-emitting laser (VCSEL) has a body comprising a vertical stack of overlapping semiconductor layers, the body comprising a current-confined region including a low-current-resistance area defined by a high-current-resistance area, and a first lower epitaxial layer positioned adjacent to the current-confined region, wherein the first lower epitaxial layer, including a protrusion or recess, defines the main cavity, and the remainder of the first lower epitaxial layer defines the outer cavity, the protrusion or recess being defined by a physical step h predetermined by the formula qλ0 - mλ1 = n0h, where λ0 is the resonant wavelength of light in the main cavity, λ1 is the resonant wavelength of light in the outer cavity, q is a positive half-integer, n0 is the effective refractive index in the main cavity, and m is a constant.

Description

Technical Field

[0001] The present disclosure describes a vertical-cavity surface-emitting laser (VCSEL) having customizable refractive-index confinement constraints.

Background Art

[0002] Conventionally, a VCSEL having an oxide aperture has an effective refractive-index contrast of about 1% to 2%, thus providing a guiding waveguide that efficiently confines the optical mode. In a prior art VCSEL, the oxide aperture is used to define both current confinement and refractive-index confinement or optical confinement. When single-mode operation is required, it can be seen that the oxide aperture needs to be made smaller than 4 μm, which is difficult to achieve reproducibly.

[0003] To provide mode selectivity, additional mode-selective elements may be used at the top of the VCSEL device. For example, a small metallic aperture may be introduced at the top of the VCSEL device to filter out unwanted higher-order modes. (See Ueki et al., "Single-Transverse-Mode 3.4-mW Emission of Oxide-Confined 780-nm VCSELs," IEEE Photonics Technology.Letters, vol.11, no.12, pp.1539-1541, 1999). In another example, the "mode filtering" approach may involve providing a surface relief on the top surface of the VCSEL device within the emission area. This technique has been reported to produce VCSELs with single-mode powers up to 6.5 mW (See Haglund et al., "High-Power Single Transverse and Polarization Mode VCSEL for Silicon Photonics Integration," Vol.27, No.13, Optics Express 18892, 2019). Another example involves utilizing impurity-induced disorder in a top-mounted distributed Bragg reflector (DBR) mirror to suppress higher-order modes by reducing reflectivity. This resulted in a VCSEL emitting a single-mode power of approximately 10 mW (see Su et al., "High-power single-mode vertical-cavity surface-emitting lasers using strain-controlled disorder-defined apertures," Appl. Phys. Lett. 119, 241101, 2021). All of these methods rely on introducing optical losses for higher-order modes.

[0004] Another example involves customizing mode shapes by designing refractive index confinement, for instance, by etching a photonic crystal-like structure onto the epitaxial layer (see Siriani et al., "Mode Control in Photonic Crystal Vertical-Cavity Surface-Emitting Lasers and Coherent Arrays," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 15, No. 3, pp. 909-917, 2009). The methods discussed so far utilize one or more current confinement layers, which typically leads to optical confinement by introducing an increase in refractive index in the VCSEL aperture. However, there are often inherent technical limitations to the range of refractive indexes that can be introduced in this way.

[0005] Mode control in VCSELs is crucial in many applications. In some cases, single-mode or minority-mode operation is beneficial, and in some cases, necessary. This is true, for example, in optical communications where the presence of numerous optical modes can worsen relative noise or increase optical dispersion due to linewidth expansion. In other cases, such as when VCSELs are used as projection sources in sensing applications, higher-order mode operation is beneficial because it provides a uniform energy distribution across the entire emission angle. In both cases, the degree of freedom that defines the optical modes can be an advantage in achieving the required performance.

[0006] In conventional oxide aperture VCSELs, the oxide aperture defines the refractive index confinement region along with current confinement. While this process is simple, this approach has limitations. For example, it cannot define very small mode volumes to facilitate single-mode operation, or it has variations in oxidation depth, which also affects mode shape and overall wafer yield. In addition, the magnitude of the refractive index contrast between the luminescent region and the surroundings is substantially fixed by the difference in refractive index between the oxidized and unoxidized portions of the oxide aperture formed in the AlGaAs layer, a material commonly used in the manufacture of oxide aperture VCSELs.

[0007] Several methods rely on defining refractive index confinement by modifying the structure within the resonant cavity of a VCSEL. In some cases, this structuring can define both refractive index confinement and current confinement, for example, by implementing different thicknesses and / or etching the tunnel junction or barrier layer. Refractive index confinement can be used interchangeably with mode confinement, optical confinement, or light confinement, as understood as the induced propagation of electromagnetic waves through a restricted area. Refractive index confinement often faces limitations because it relies on several factors (material, temperature, carriers) that make it difficult to maintain subtle changes in a controlled manner.

[0008] Therefore, it is desirable to provide a VCSEL with a less restrictive refractive index confinement related to a modifiable physical structure. [Overview of the project] [Problems that the invention aims to solve]

[0009] [Means for solving the problem]

[0010] Disclosed herein are VCSELs fabricated by epitaxial growth techniques such as metal-organic chemical vapor deposition (MOCVD). Overgrowth implementation means that the complete epitaxial structure of the VCSEL is fabricated in two steps. In the first growth step, the last epitaxial layer is patterned and partially etched away to define the current-confining region that defines the VCSEL aperture. The VCSEL structure is then completed by a second epitaxial growth (overgrowth) on top of the patterned structure, which may add a second epitaxial layer and an upper DBR mirror layer.

[0011] Between the two epitaxial growth processes, the first epitaxial layer is patterned to create protrusions or recesses that define refractive index confinement. The patterning of this layer defines the characteristics of the luminescent area of ​​the VCSEL. This characteristic, specified by a height h, can be obtained by a lithography process that involves masking the epitaxial layer with a suitable mask (e.g., a resist), exposing it, and developing a portion of it. The exposed area is then etched over the entire depth h by standard wet etching or dry etching techniques. The remaining mask is then removed, the surface is cleaned, and prepared for the subsequent epitaxial growth process (overgrowth).

[0012] In non-limiting embodiments or aspects, provided is a vertical-cavity surface-emitting laser (VCSEL) comprising a body having a vertical stack of semiconductor layers that overlap each other, the stack of semiconductor layers having a current-confining region including a low-current-resistance region defined by a high-current-resistance region, wherein the vertical current flow in the stack of semiconductor layers is guided by the high-current-resistance region of the current-confining region to pass through the low-current-resistance region of the current-confining region, and a first disposed adjacent to the current-confining region A lower epitaxial layer comprising a first lower epitaxial layer including a projection or recess positioned adjacent to a low current resistance area in the current confinement region, wherein the projection or recess defines a main cavity, and the remainder of the first lower epitaxial layer defines an outer cavity, the projection or recess being defined by a physical step h predetermined by the equation qλ0 - mλ1 = n0h, where λ0 is the resonant wavelength of light in the main cavity, λ1 is the resonant wavelength of light in the outer cavity, q is a positive half-integer, n0 is the effective refractive index in the main cavity, and m is a constant.

[0013] In non-limiting embodiments or embodiments, a stack of semiconductor layers includes, in order, a first distributed Bragg reflection (DBR) mirror layer, a cavity layer including an active region, a first lower epitaxial layer and a current confinement region, and a second DBR mirror layer. In non-limiting embodiments or embodiments, a stack of semiconductor layers further includes a substrate below the stack of semiconductor layers, a first contact on the side of the stack of semiconductor layers opposite to the substrate layer, and a second contact on the side of the substrate layer opposite to the stack of semiconductor layers, or on the side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact electrically contacts only the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact electrically contacts only the side of the substrate layer opposite to the stack of semiconductor layers.

[0014] In non-limiting embodiments or embodiments, the high-current-resistance area of ​​the current-confinement region surrounds the low-current-resistance area of ​​the current-confinement region. In non-limiting embodiments or embodiments, the projection or recess of the first lower epitaxial layer is positioned to align with the low-current-resistance area of ​​the current-confinement region. In non-limiting embodiments or embodiments, the low-current-resistance area of ​​the current-confinement region is circular. In non-limiting embodiments or embodiments, the projection or recess of the first lower epitaxial layer is coaxial with the circular current-confinement region.

[0015] In non-limiting embodiments or configurations, the projection comprises one or more tunnel joints.

[0016] In non-limiting embodiments or configurations, the recess comprises one or more etched regions.

[0017] In non-limiting embodiments or configurations, the current confinement region comprises one or more oxidized or injected semiconductor layers.

[0018] In a non-limiting embodiment or configuration, m is selected from a set of positive half-integer values.

[0019] In non-limiting embodiments or configurations, λ0 is in the range of approximately 680 nm to 2600 nm.

[0020] In non-limiting embodiments or configurations, h is selected within the range of -500 nm to 500 nm.

[0021] In non-limiting embodiments or configurations, the first lower epitaxial layer includes a recess, and h is a negative value.

[0022] In a non-limiting embodiment or aspect, the VCSEL operates in a first guiding mode defined by a refractive index contrast Δn < 0, where in the above equation, Δn is the effective refractive index confinement given by Δn / n0 = (λ1 - λ0) / λ0. In a non-limiting embodiment or aspect, h is a negative value and λ1 < λ0. In a non-limiting embodiment or aspect, the VCSEL also includes a section that supports an anti-guiding mode with a refractive index contrast Δn > 0.

[0023] In a non-limiting embodiment or aspect, the VCSEL further includes a second underlying epitaxial layer proximate to the first underlying epitaxial layer. In a non-limiting embodiment or aspect, the stack of semiconductor layers further includes a substrate layer below the stack of semiconductor layers, a first contact on the side of the stack of semiconductor layers opposite the substrate layer, and a second contact on the side of the substrate layer opposite the stack of semiconductor layers, or on the side of the body, or on the side of the stack of semiconductor layers opposite the substrate layer. The first contact is in electrical contact only with the side of the stack of semiconductor layers opposite the substrate layer, and the second contact is in electrical contact only with the side of the substrate layer opposite the stack of semiconductor layers.

[0024] In a non-limiting embodiment or aspect, for the VCSEL, when the first underlying epitaxial layer includes a protrusion, the second underlying epitaxial layer also includes a protrusion aligned with the protrusion of the first underlying epitaxial layer, and the protrusion of the second underlying epitaxial layer protrudes into a space surrounded by a high-current resistance area of the current confinement region.

[0025] Further embodiments or aspects are described in the numbered clauses below.

[0026] Clause 1: A body comprising a vertical stack of semiconductor layers that overlap each other, the stack of semiconductor layers being a current confinement region including a low current resistance region defined by a high current resistance region, wherein the vertical current flow in the stack of semiconductor layers is guided by the high current resistance region of the current confinement region to pass through the low current resistance region of the current confinement region, the current confinement region, and a first lower epitaxial layer disposed adjacent to the current confinement region, the first lower epitaxial layer including a protrusion or a recess disposed adjacent to the low current resistance region of the current confinement region, the protrusion or the recess defining a main cavity, the remainder of the first lower epitaxial layer defining an outer cavity, the protrusion or the recess being defined by a physical step h determined in advance by the formula qλ0 - mλ1 = n0h, where λ0 is the resonance wavelength of light in the main cavity, λ1 is the resonance wavelength of light in the outer cavity, q is a positive half-integer, n0 is the effective refractive index in the main cavity, and m is a constant, a vertical cavity surface emitting laser (VCSEL).

[0027] Clause 2: The stack of semiconductor layers of the VCSEL according to Clause 1 includes, in order, a first distributed Bragg reflector (DBR) mirror layer, a cavity layer including an active region, a first lower epitaxial layer and a current confinement region, and a second DBR mirror layer.

[0028] Clause 3: The stack of semiconductor layers further includes a substrate layer below the stack of semiconductor layers, a first contact on the side of the stack of semiconductor layers opposite to the substrate layer, and a second contact on the side of the substrate layer opposite to the stack of semiconductor layers, or on the side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, the first contact being in electrical contact only with the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact being in electrical contact only with the side of the substrate layer opposite to the stack of semiconductor layers, the VCSEL according to Clause 1 or 2.

[0029] Clause 4: The high current resistance region of the current confinement region surrounds the low current resistance region of the current confinement region, the VCSEL according to any one of Clauses 1 to 3.

[0030] Clause 5: The VCSEL according to any one of Clauses 1 to 4, wherein the protrusion or recess of the first lower epitaxial layer is positioned to align with the low current resistance area of ​​the current confinement region.

[0031] Clause 6: The low current resistance area of ​​the current confinement region is circular, as described in any of Clauses 1-5 for a VCSEL.

[0032] Clause 7: A VCSEL according to any one of Clauses 1 to 6, wherein the projection or recess of the first lower epitaxial layer is coaxial with the circular current confinement region.

[0033] Clause 8: The projection comprises one or more tunnel joints, as described in any of Clauses 1 to 7.

[0034] Clause 9: The VCSEL according to any of Clauses 1 to 8, wherein the recess comprises one or more etched regions.

[0035] Clause 10: The VCSEL according to any one of Clauses 1 to 9, wherein the current confinement region comprises one or more oxidized or injected semiconductor layers.

[0036] Clause 11: m is a VCSEL as described in any of Clauses 1-10, selected from a set of positive half-integer values.

[0037] Clause 12: A VCSEL as described in any of Clauses 1 to 11, wherein λ0 is in the range of approximately 680 nm to 2600 nm.

[0038] Clause 13: A VCSEL as described in any of Clauses 1 to 12, wherein h is selected within the range of -500nm to 500nm.

[0039] Clause 14: The VCSEL described in any of Clauses 1 to 13, wherein the first lower epitaxial layer includes a recess and h is a negative value.

[0040] Clause 15: A VCSEL as described in any of Clauses 1 to 14, which operates in a first guide mode defined by a refractive index contrast Δn < 0, where Δn is the effective refractive index confinement given by Δn / n0 = (λ1 - λ0) / λ0.

[0041] Clause 16: A VCSEL as described in any of Clauses 1-15, where h is a negative value and λ1 < λ0.

[0042] Clause 17: The VCSEL described in any of Clauses 1 to 16, also comprising a section supporting an anti-guide mode where the refractive index contrast is Δn > 0.

[0043] Clause 18: A VCSEL according to any one of Clauses 1 to 17, further comprising a second lower epitaxial layer adjacent to a first lower epitaxial layer.

[0044] Clause 19: The VCSEL according to any one of Clauses 1 to 18, wherein the stack of semiconductor layers further includes a substrate below the stack of semiconductor layers, a first contact on the side of the stack of semiconductor layers opposite to the substrate layer, and a second contact on the side of the substrate layer opposite to the stack of semiconductor layers, or on the side of the body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact electrically contacts only the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact electrically contacts only the side of the substrate layer opposite to the stack of semiconductor layers.

[0045] Clause 20: A VCSEL according to any one of Clauses 1 to 19, wherein if the first lower epitaxial layer includes a projection, the second lower epitaxial layer also includes a projection aligned with the projection of the first lower epitaxial layer, the projection of the second lower epitaxial layer protruding into a space surrounded by a high-current-resistance area of ​​the current-confinement region. [Brief explanation of the drawing]

[0046] [Figure 1]This is an enlarged schematic side view of an exemplary VCSEL in accordance with the principles of the present disclosure, comprising a first lower epitaxial layer including a tunnel junction and / or current confinement region, and a second lower epitaxial layer above the current confinement region.

[0047] [Figure 2] Figure 1 shows a schematic side view of the first lower epitaxial layer, current confinement region, and second lower epitaxial layer, which are representative of a VCSEL.

[0048] [Figure 3] This is an enlarged schematic side view of another example of a VCSEL according to the principles of the present disclosure, comprising a first lower epitaxial layer including a recess, a current confinement region adjacent to the first lower epitaxial layer, and a second lower epitaxial layer above the current confinement region.

[0049] [Figure 4] Figure 3 shows a schematic outline of the first lower epitaxial layer, current confinement region, and second lower epitaxial layer, which are exemplary of the VCSEL.

[0050] [Figure 5] This is an enlarged schematic side view of an exemplary VCSEL according to the principles of the present disclosure, comprising a first lower epitaxial layer including a tunnel junction having height h, a current confinement region adjacent to the first lower epitaxial layer, and a second lower epitaxial layer above the current confinement region.

[0051] [Figure 6] This is an enlarged schematic side view of an exemplary VCSEL according to the principles of the present disclosure, comprising a first lower epitaxial layer including a tunnel junction having height h, a current confinement region adjacent to the first lower epitaxial layer, and a second lower epitaxial layer above the current confinement region.

[0052] [Figure 7]This is an enlarged schematic side view of another example of a VCSEL according to the principles of this disclosure, comprising a first lower epitaxial layer including a tunnel junction and a current confinement region adjacent to the first lower epitaxial layer, but without a second lower epitaxial layer as shown in Figure 1.

[0053] [Figure 8] This is an enlarged schematic side view of another example of a VCSEL according to the principles of this disclosure, comprising a first lower epitaxial layer including a recess and a current confinement region adjacent to the first lower epitaxial layer, but without a second lower epitaxial layer as shown in Figure 3.

[0054] [Figure 9] This is an enlarged schematic side view of another example of a VCSEL according to the principles of the present disclosure, comprising a first lower epitaxial layer including a tunnel junction, a current confinement region adjacent to the first lower epitaxial layer, and a second lower epitaxial layer including an optional protrusion or bulge above the protrusion or bulge of the current confinement region.

[0055] [Figure 10] This is an enlarged schematic side view of another example of a VCSEL according to the principles of the present disclosure, comprising a first lower epitaxial layer including a recess, a current confinement region adjacent to the first lower epitaxial layer, and a second lower epitaxial layer including an optional recess above the recess in the current confinement region.

[0056] [Figure 11A] This is an enlarged schematic side view of an exemplary VCSEL according to the principles of the present disclosure, including a first lower epitaxial layer having a tunnel junction, on which optical guide sections and optical anti-guide sections, combined with a current confinement region, are mounted by etching the first lower epitaxial layer.

[0057] [Figure 11B] Figure 11A is an extracted top view of an exemplary VCSEL shown in Figure 11A.

[0058] [Figure 11C] Figure 11A shows the effective refractive index profile of an exemplary VCSEL.

[0059] [Figure 12A] This is an enlarged schematic side view of an exemplary VCSEL in accordance with the principles of the present disclosure, illustrating a confinement region including a first lower epitaxial layer having a current-blocking layer, on which an optical guide section and an optical anti-guide section, combined with a current-confinement section, are mounted by etching the first lower epitaxial layer.

[0060] [Figure 12B] Figure 12A is an extracted top view of an exemplary VCSEL shown in Figure 12A.

[0061] [Figure 12C] Figure 12A shows the effective refractive index profile of an exemplary VCSEL. [Modes for carrying out the invention]

[0062] Here, various non-limiting examples are explained with reference to the attached drawings. In the drawings, similar reference numbers correspond to similar or functionally equivalent elements.

[0063] Hereafter, for the purposes of explanation, terms such as “end,” “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “lateral,” “longitudinal,” and their derivatives shall be used in relation to the examples oriented in the drawings. However, it should be understood that these examples may be subject to various alternative variations and sequences of steps, unless otherwise explicitly stated. Furthermore, it should be understood that the specific examples shown in the accompanying drawings and described in the following specification are merely illustrative examples or embodiments of the disclosure. Accordingly, the specific examples or embodiments disclosed herein should not be construed as limitations.

[0064] Referring to Figures 1 and 2, one non-limiting embodiment or exemplary VCSEL relating to the principles of the present disclosure comprises a body 2 including a vertical stack 4 of semiconductor layers, such as layers of GaAs, AlGaAs, AlInGaAsP, InGaAs, InP, or InAlGaN, grown or deposited in overlapping layers, for example, by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The stack 4 of semiconductor layers may include, from the bottom to the top of the body 2, a substrate 6, a lower distributed Bragg reflection (DBR) mirror layer 8, a cavity layer 10 including an active region 12, a first lower epitaxial layer 14, a current confinement region 18 which may be part of or separate from the first lower epitaxial layer 14, a second lower epitaxial layer 16, and an upper DBR mirror layer 20. Due to the continued growth of the upper DBR mirror layer 20, an optional cap layer may be formed or defined as part of the upper DBR mirror layer 20.

[0065] As used herein, the first epitaxial layer is everything grown on the substrate 6 in the first growth process. Thus, the first epitaxial layer in Figure 1 includes the underlying layers 8, 10, and 14. Similarly, the second epitaxial layer is everything grown in the second growth process and includes the underlying layers 16 and 20. As shown in Figure 1, each of the underlying layers of the first and second epitaxial layers is generally flat.

[0066] In this specification, when used in relation to the DBR mirror layers 8 and 20, the terms “first,” “lower,” “second,” and “upper” are used solely for explanatory, illustrative, and clarifying purposes and should not be interpreted as restrictive. In addition, when used in relation to the DBR mirror layers 8 and 20, the terms “lower” and “upper” are used solely in relation to the orientation shown in the figures and should not be interpreted as restrictive. Furthermore, in this specification, for explanatory, illustrative, and clarifying purposes, one of the DBR mirror layers may be referred to as the first DBR mirror layer and the other as the second DBR mirror layer, and should not be interpreted as restrictive.

[0067] The first electrical contact 24 may be positioned in electrical contact with the upper surface of the upper DBR mirror layer 20. In one example, the first electrical contact 24 may be ring-shaped, including an aperture D for the passage of light generated by the operation of the VCSEL. However, this should not be interpreted in a restrictive sense, as the first electrical contact 24 may be any suitable and / or desirable shape or geometry that allows light generated by the operation of the VCSEL (discussed below) to exit the upper surface of the upper DBR mirror layer 20.

[0068] In one example, the second electrical contact 25 may be positioned in electrical contact with the bottom surface of the substrate layer 6 opposite to the lower DBR mirror layer 8. In another example, the second electrical contact 25, shown by the dashed line in Figure 1, may be positioned on the side of the body 2 in electrical contact with the substrate 6. In this specification, the terms “first” and “second” are used in reference to contacts 24 and 25 solely for illustrative and illustrative purposes and should not be construed as restrictive.

[0069] Similarly, in yet another example shown by a dashed line in Figure 1, the second electrical contact 25 may be located on the upper surface of the upper DBR mirror layer 20, for example, in close proximity to or adjacent to the first electrical contact 24. In this example, the second electrical contact 25 may be electrically isolated from the upper surface of the upper DBR mirror layer 20, for example, by an oxide layer, and may be electrically connected to the substrate layer 6 through the body 2 or via a conductor (not shown) disposed on the side of the body 2.

[0070] Regardless of where the second electrical contact 25 is located or may be located, the first electrical contact 24 is electrically in contact only with the upper surface of the cap layer 22, and the second electrical contact 25 is electrically in contact only with the substrate layer 6. An electrical bias may be applied to the body 2 through the first and second electrical contacts 24 and 25. This electrical bias may cause a current 22 (shown as a dashed line in Figure 1) to flow in the body 2 between the substrate layer 6 and the first electrical contact 24.

[0071] Details relating to the growth or manufacture of the substrate 6, the lower DBR mirror layer 8, the cavity layer 10 including the active region 12, the upper DBR mirror layer 20, and / or one or more of the first and second electrical contacts 24 and 25 are known in the art and are not described herein for the sake of brevity. In addition, details relating to the growth or manufacture of one or more of the first lower epitaxial layer 14 and the second lower epitaxial layer 16 are known in the art and are not described herein for the sake of brevity, except as may be necessary for this description.

[0072] For example, VCSELs can be fabricated by epitaxial growth techniques such as metal-organic chemical vapor deposition (MOCVD). Overgrowth implementation means that the complete epitaxial structure of the VCSEL is fabricated in two steps. In the first growth step, the first lower epitaxial layer 14 is patterned and removed by etching to define the current-confining region that defines the VCSEL aperture. The VCSEL structure is then completed by a second epitaxial growth (overgrowth) which adds a second lower epitaxial layer 16 and an upper DBR mirror layer 20 on top of the patterned structure.

[0073] As described above, between the two epitaxial growth processes, the first lower epitaxial layer 14 is patterned to create protrusions or recesses 30 that define refractive index confinement. Thus, in some embodiments, the current confinement region may be the same as the optical confinement region, and in other embodiments, the current confinement region may be independent of optical confinement. The patterning of this layer defines the characteristics of the luminescent region of the VCSEL. This characteristic, specified by a height h, can be obtained by a lithography process that includes masking the first lower epitaxial layer 14 with a suitable mask (e.g., a resist), exposing it, and developing a portion of it. The exposed area is then etched over the entire depth h by standard wet etching or dry etching techniques. The remaining mask is then removed, the surface is cleaned, and prepared for the subsequent growth of the second epitaxial layer 16.

[0074] As shown, the first lower epitaxial layer 14 includes or defines one or more raised or protruding portions 30 on its top surface 29, which have the properties of tunnel junctions formed on the top surface 29 of the first lower epitaxial layer 14 by lithography processes known in the art. Hereinafter, the terms “raised portion,” “protruding portion,” and “tunnel junction” may be used interchangeably in relation to reference no. 30. The tunnel junction 30 is conductive and is etched away at all locations except the central part of the structure, at which point the tunnel junction 30 has a height h. This protrusion 30 results in current confinement because the formation of the tunnel junction 30 between the first lower epitaxial layer 14 and the second lower epitaxial layer 16 creates a current confinement region 18, which includes one or more interruption regions 18a, 18b that stop the flow of current and a region 18c having a width D through which current 22 can flow.

[0075] In another embodiment with the same manufacturing technique, instead of etching around the aperture, a pre-existing barrier layer (not shown) on the first lower epitaxial layer 14 is etched away before overgrowth to create a current-confined region 18 (see Figure 3). In both cases, the central part of the structure is where the current can flow, and stimulated emission results in laser emission. As shown, the current-confined region 18 is flat and runs along the first and second lower epitaxial layers.

[0076] In some embodiments, the barrier layer may include an oxide layer, a reverse-biased pn junction, an implantation region, and the like. In some embodiments, the barrier layer can be created in a subsequent process, as in the case of oxides and ion implantation. See, for example, the discussion in Figure 9 below.

[0077] In one example, the current confinement region 18 may be present as part of the first lower epitaxial layer 14 (e.g., integrally or together) or may be mounted above the first lower epitaxial layer 14 by, for example, an oxidation process. In an example where the current confinement region 18 and the first lower epitaxial layer 14 are provided by different layers, the first lower epitaxial layer 14 may include the current confinement region 18 (e.g., an oxide layer) as shown in Figure 3.

[0078] In some embodiments, the current confinement region 18 includes a low current resistance area 18c defined by high current resistance areas 18a and 18b, and as a result, the current flow in the body 2 is directed or confined through the low current resistance area 18c by the high current resistance areas 18a and 18b. In one non-limiting example, the high current resistance areas 18a and 18b surround the low current resistance area 18c, and as a result, the current flow in the body 2 is directed through the low current resistance area 18c by the high current resistance areas 18a and 18b.

[0079] In one example, the resistance per unit area of ​​the high-current resistance areas 18a and 18b is, for example, ohms / cm². 2 It is at least 10 times greater than the resistance per unit area of ​​the low-current resistance area. In one example, the low-current resistance area 18c is 10 -3 Ohm cm 2 The following resistances may be present, and the high-current resistance areas 18a and 18b may have a resistance of 0.1 ohms / cm². 2 The above resistance is permissible. However, this should not be interpreted in a restrictive sense.

[0080] In one particular non-limiting example shown in Figures 1 and 2, the low-current resistance area 18c may be circular, defined by the inner diameter of the ring shape of the high-current resistance areas 18a and 18b. However, since the use of other shapes or geometries for one or both of the low-current resistance areas and / or high-current resistance areas is also possible, these shapes or geometries should not be interpreted in a limiting sense.

[0081] In one example, high-current-resistance areas 18a and 18b may be formed or defined, for example, by oxidation, injection, or growth of an area of ​​the current-confining region 18 that defines the high-current-resistance areas. In this example, the low-current-resistance area 18c is an area of ​​the current-confining region 18 that is not oxidized or injected.

[0082] Generally, the optical mode of laser emission is defined by refractive index confinement. Refractive index confinement is defined by the etching depth h in layer 4, as will be explained later. Often, there are physical or technical limitations on the value of h, such as the following: • The minimum thickness h (see Figure 1) that the current-conducting layer (e.g., tunnel junction) can have, i.e., the minimum required etching depth. • The minimum thickness that the current-blocking layer may need to have (see Figure 3). • The minimum etchable depth (e.g., the technical limit) that can be reliably or reproducibly etched.

[0083] Furthermore, in the case of the geometry obtained in Figure 1, optical confinement is promoted, but in the case of Figure 3, optical confinement is not introduced (e.g., anti-guiding). In all these cases, the amount of refractive index confinement that can be introduced is limited. This disclosure provides a method to overcome this limitation by leveraging the characteristics of the physical mechanism that brings about refractive index confinement.

[0084] Referring again to Figure 1, in the illustrated VCSEL, the first lower epitaxial layer 14 may be positioned in close proximity to a current confinement region 18 located below or positioned below the second lower epitaxial layer 16. In one example, the first lower epitaxial layer 14 may include or define one or more tunnel junctions or projections 30 positioned in close proximity to and aligned with the low current resistance area 18c of the current confinement region 18 at its top surface 29. As shown in Figure 1, the current confinement region 18 is shown as the junction between the first lower epitaxial layer 14 and the second lower epitaxial layer 16.

[0085] Referring next to Figure 2, the tunnel junction 30 of the first lower epitaxial layer 14 may be circular and may be aligned with or coaxial with the circular low-current-resistance area 18c of the current-confinement region 18. However, this should not be interpreted in a restrictive sense, as it is conceivable that the tunnel junction 30 of the first lower epitaxial layer 14 may have any suitable and / or desirable shape or geometry (described in more detail below), and / or the low-current-resistance area 18c of the current-confinement region 18 may have any suitable and / or desirable shape or geometry that is the same as or different from the shape or geometry of the tunnel junction 30 of the first lower epitaxial layer 14.

[0086] Referring to Figures 5 and 6, in some examples, the patterning of the first lower epitaxial layer 14 can create two regions or cavities: a primary region or primary cavity 62 that is vertically aligned with the tunnel junction 30 (e.g., with width D) and emits light 32, and a secondary region or secondary cavity 64 that is vertically aligned with the area of ​​the first lower epitaxial layer 14 that is not vertically aligned with the tunnel junction 30, i.e., the area surrounding the tunnel junction or projection 30. Figures 5 and 6 show VCSELs similar to those in Figure 1, but with added details and differences in the height of the projection 30. For example, both Figures 5 and 6 show VCSELs with a physical step h, but h in Figure 6 is much larger than h in Figure 5.

[0087] In some embodiments, the current confinement region is adjacent to a first lower epitaxial layer and a second lower epitaxial layer above the current confinement region. In some embodiments, the current confinement region may be included in the first and / or second lower epitaxial layers, or it may be independent of the lower epitaxial layers.

[0088] The resonant wavelengths of light 32 in the main region 62 and the secondary region 64 are different and may be equal to λ0 and λ1, respectively. The difference between these wavelengths defines the effective refractive index confinement of the first lower epitaxial layer 14 that determines the optical mode. In particular, the effective refractive index confinement (Δn) is given by the following: Δn / n0 = (λ1 - λ0) / λ0 (Equation 1) In the formula, n0 is the effective refractive index in the main region 62. Δn determines the refractive index contrast and, along with a given shape or geometry of the first lower epitaxial layer 14, for example, the maximum size of the light guide pattern D in Figure 1, defines the supported transverse optical modes for single-optical-mode operation.

[0089] In other words, the larger Δn is, the smaller D must be to achieve single-mode operation. Therefore, the magnitude of Δn determines the maximum size of D required for single-mode operation. In some embodiments, λ1 is selected such that the refractive index contrast is in the range of approximately 0% to 50%.

[0090] λ0 > λ1 means the cavity is guided by the refractive index, while λ0 < λ1 means it is not guided (anti-guided). Guide behavior is usually necessary for efficient laser emission. By setting λ0 and λ1, it becomes possible to engineer the refractive index confinement.

[0091] Referring to Figures 1, 5, and 6, we see that qλ0 = n0L0, and in the above equation, we know that q is a positive half-integer (q = 1 / 2, 1, 3 / 2, 2, etc.). The physical height L0 refers to the distance light travels back and forth within the main cavity. The physical height L0 = qλ0 / n0 in this case is chosen so that the VCSEL emits light at the appropriate wavelength λ0. The resonant wavelength λ1 of the outer cavity is separately determined by its physical height L1. For any positive value of another half-integer m, we know that mλ1 = n0L1.

[0092] Controlling refractive index contrast is crucial in some applications. For example, a small refractive index contrast promotes single-mode operation in VCSELs. The refractive index contrast is proportional to the difference in lengths between the two cavities. Since there are often technical limitations on how small the physical step h = L1 - L0 can be manufactured, an alternative method for determining λ1, and thus the refractive index contrast, based on the ability to freely define m, is desirable. Indeed, the step h can be varied over a wide range of values ​​while still obtaining the required values ​​for λ0 and λ1. A general formulation of this principle is: qλ0 - mλ1 = n0h (Equation 2) Given by the above equation, λ0 is set based on the required emission wavelength, q determines the cavity height at λ0 and is often constrained based on the application, and λ1 is set to achieve the desired refractive index contrast (according to Equation 1).

[0093] It should be understood that q may be selected to determine λ0 based on Equation 1 and / or Equation 2. Similarly, m may be selected to determine a practical manufacturable value of h. For example, in some embodiments, λ0 is in the range of approximately 680 nm to 2600 nm.

[0094] Furthermore, referring to Figures 5 and 6, each shows different ways to obtain the same result. If both h in Figure 5 and h in Figure 6 satisfy Equation 2 for different values ​​of m, then the two devices have similar refractive index confinement characteristics. This provides a solution for implementing single-mode emission in VCSELs in further cases where it would normally be considered impractical. For example, in the case of refractive index guide (i.e., Δn < 0), the magnitude of Δn also sets the maximum size / diameter of the aperture (D) for single-mode behavior.

[0095] In some embodiments, a very small negative value for Δn means that a very low value of D, e.g., a small aperture, is required to achieve single-mode behavior. The simplest way to achieve a larger less negative Δn is to reduce h. However, due to technical limitations or process constraints, small h is often not practical or reliably achievable. By utilizing the alternative configuration shown in Figure 6, the same result can be obtained with a larger manufacturable value of h.

[0096] In some embodiments, increasing the value of h may be the only way to achieve the required refractive index contrast. For example, referring to Figure 3, the device is manufactured by etching a layer within the light-emitting region to create a recess 40 instead of a protrusion or projection. As will be described in more detail below, the current-blocking region is etched so that current flows through the aperture. It is worth noting that in this case h<0, because this represents a recess rather than a protrusion. Small etchings can lead to anti-guide behavior because λ1>λ0, and therefore Δn>0, which impairs efficient laser emission from the device. However, by etching to a depth greater than where h remains negative in Equation 2 (etching), assuming q=1 / 2 and setting m=1, it is still possible to create a guide refractive index profile (Δn<0, λ1<λ0).

[0097] In some embodiments, increasing the value of h may be the only way to achieve the required refractive index contrast. For example, referring to Figure 3, the device is manufactured by etching the first lower epitaxial layer 14 within the light-emitting region instead of a protrusion or projection. As will be described in more detail below, the current-blocking region is removed by etching so that current flows through the aperture D. It is worth noting that in this case h<0, because this represents a recess rather than a protrusion. Small etching leads to anti-guiding behavior, as λ1>λ0 and therefore Δn>0, which in turn h h h<0>0. However, by etching to a greater depth than where h is still negative in Equation 2 (etching), assuming q=1 / 2 and setting m=1, it is still possible to create a guide refractive index profile (Δn<0, λ1<λ0).

[0098] In some embodiments, h is selected within the range of approximately -500 nm to 500 nm. In some embodiments, h is selected within the range of approximately -300 nm to 300 nm. In some embodiments, h is selected within the range of approximately 100 nm to 300 nm. In some embodiments, h is selected within the range of approximately 200 nm to 300 nm.

[0099] In Figure 1, the refractive index contrast increases as the value of the height h of the protrusion or raised portion 30 increases. During use, the electrical bias applied to the first and second electrical contacts 24 and 25 causes a current 22 to flow vertically or substantially vertically between the substrate layer 6 and the first electrical contact 24 in the body 2. This flow of current 22 in the body 2 is guided or confined to flow through the low current resistance area 18c by the high current resistance areas 18a and 18b of the current confinement region 18. This current 22 also flows through the active region 12 of the cavity layer 10, which in turn emits light 32 (indicated by the ellipse in the body 2 and the arrows emanating from the upper surface of the upper DBR mirror layer 20). The emitted light 32 flows through the low current resistance area 18c of the current confinement region 18 due to the difference in refractive index between the main region of the first lower epitaxial layer 14 aligned with the tunnel junction 30 and the secondary region of the first lower epitaxial layer 14 not aligned with the tunnel junction 30, and is guided or confined to exit from the top surface of the upper DBR mirror layer 20 above the protrusion or bulge 30 and the low current resistance area 18c of the current confinement region 18.

[0100] The shape or geometry of the first subepitaxial layer 14 shown in Figure 2 is only one non-limiting example of the shape or geometry that the light confinement layer 14 may have, including one or more protrusions or ridges, such as tunnel junctions 30. Since the first subepitaxial layer 14 may have any suitable and / or desirable shape or geometry that is considered desirable for the VCSEL to emit light 32 having the desired shape, geometry, and / or mode for a particular application, the shape or geometry of the first subepitaxial layer 14 should not be interpreted in a limiting sense.

[0101] Referring to Figures 3 and 4, and continuing with Figures 1 and 2, other non-limiting embodiments or exemplary VCSELs relating to the principles of the present disclosure may be similar to the exemplary VCSELs shown in Figures 1 and 2 and described above, with one exception: the first lower epitaxial layer 14 of the VCSEL shown in Figures 3 and 4 may include one or more recesses or cavities 40 in the top surface 29 of the first lower epitaxial layer 14, instead of the top surface 29 of the first lower epitaxial layer 14 including one or more protrusions or ridges 30. The operating principles of the VCSELs shown in Figures 1 and 2 and described above are applicable to the operating principles of the VCSELs shown in Figures 3 and 4, respectively, and are not described further herein to avoid unnecessary redundancy.

[0102] Generally, the use of one or more protrusions or ridges 30 versus the use of one or more recesses or cavities 40 on the top surface 29 of the first lower epitaxial layer 14 may affect the shape, geometry, and / or mode of light 32 emanating from the top surface of the upper DBR mirror layer 20. In other words, for example, in the VCSELs shown in Figures 1 and 3, the light 32 emanating from the top surface of the upper DBR mirror layer 20 may have a different shape, geometry, and / or mode (suitable for different applications) due to the presence of one or more protrusions or ridges 30 on the top surface 29 of the first lower epitaxial layer 14 of the VCSEL shown in Figure 1 versus the presence of one or more recesses or cavities 40 on the top surface 29 of the first lower epitaxial layer 14 of the VCSEL shown in Figure 3.

[0103] As shown above, instead of etching around the aperture, a blocking layer (not shown) already present on the first lower epitaxial layer 14 is etched away before overgrowth to create a current-confined region 18. The current-confined region may include one or more areas of the blocking layers 18a and 18b adjacent to the first lower epitaxial layer 14. In some embodiments, the blocking layers 18a and 18b represent a ring-shaped region centered on a circular recess 40. The etched-away portion forms the recess 40, which coincides with a low-current-resistance area 18c to the flow of current.

[0104] In some embodiments, the barrier layer may include an oxide layer, an inverse pn junction, an injection region, and the like.

[0105] The shape or geometry of the first sub-epitaxial layer 14 shown in Figure 4 is only one non-limiting example of the shape or geometry that the light confinement layer 14 may have, including one or more recesses or cavities 40. Since the first sub-epitaxial layer 14 may have any suitable and / or desirable shape or geometry that is considered desirable for the VCSEL to emit light 32 having the desired shape, geometry, and / or mode for a particular application, the shape or geometry of the first sub-epitaxial layer 14 should not be interpreted in a limiting sense.

[0106] Referring to Figure 7, another non-limiting embodiment or exemplary VCSEL relating to the principles of this disclosure may be similar to the exemplary VCSEL shown in Figure 1 and described above, with some exceptions. One exception is that in the VCSEL shown in Figure 7, the second lower epitaxial layer 16 shown in Figure 1 may be omitted or absent.

[0107] The protrusions or ridges 30 of the first lower epitaxial layer 14 in Figure 7 may have any shape or geometry that is deemed suitable and / or desirable for the VCSEL to emit light 32 having a desired shape, geometry, and / or mode for a particular application. A non-limiting example of such a shape or geometry is the first lower epitaxial layer 14 having one or more protrusions or ridges 30, as shown in Figure 2, for example. Therefore, the shape of the protrusions or ridges 30 shown in Figure 7 should not be interpreted in a limiting sense.

[0108] Referring to Figure 8, another non-limiting embodiment or exemplary VCSEL relating to the principles of this disclosure may be similar to the exemplary VCSEL shown in Figure 3 and described above, with some exceptions. One exception is that in the VCSEL shown in Figure 8, the second lower epitaxial layer 16 shown in Figure 3 may be omitted or absent.

[0109] The recesses 40 of the first lower epitaxial layer 14 in Figure 8 may have any shape or geometry that is deemed suitable and / or desirable for the VCSEL to emit light 32 having a desired shape, geometry, and / or mode for a particular application. Non-limiting examples of such shapes or geometries include, for example, the first lower epitaxial layer 14 having one or more recesses or cavities 40, as shown in Figure 4. Therefore, the shape of the recesses 40 shown in Figure 8 should not be interpreted in a limiting sense.

[0110] Referring to Figure 9, and continuing with Figures 1 and 2, another non-limiting embodiment or exemplary VCSEL relating to the principles of the present disclosure may, in one example, include one or more projections or protrusions 30 on the top surface 29 of the first lower epitaxial layer 14 resulting in one or more corresponding projections or protrusions (not shown in Figure 1 for simplicity) formed on the first lower epitaxial layer 14 during its growth in some or all of the subsequent layers. These are, namely, projections or protrusions 50 of the second lower epitaxial layer 16 and / or projections or protrusions 54 (shown by dashed lines) of the upper DBR mirror layer 20. In another example, the second lower epitaxial layer 16 and the upper DBR mirror layer 20 may have projections or protrusions (with respect to height h) that gradually decrease in size above the one or more projections or protrusions 30 on the top surface 29 of the first lower epitaxial layer 14. This includes, in one example, that the upper surface of the upper DBR mirror layer 20 is flat. However, the upper surfaces of each layer above the protrusion or ridge 30 on the top surface 29 of the first lower epitaxial layer 14 may have protrusions or ridges, or they may be flat as shown in Figures 1 and 2, so these examples should not be interpreted in an exclusive sense.

[0111] In addition, as shown in Figure 9, the difference in doping type between the first lower epitaxial layer 14 and the second lower epitaxial layer 16, and the polarity bias applied during operation, can cause the current confinement layer 18 to become a carrier depletion region. Carrier depletion in the current confinement region 18 prevents current from being supplied. The protrusion or raised portion 30 may include two layers doped at a higher level. Higher doping levels enable conduction by Esaki's interband tunneling. By tunneling the protrusion or raised portion 30, it becomes possible to supply current.

[0112] Referring to Figure 10, and continuing with Figures 3 and 4, another non-limiting embodiment or exemplary VCSEL relating to the principles of the present disclosure may, in one example, include one or more recesses or cavities 40 in the top surface 29 of the first lower epitaxial layer 14 resulting in one or more corresponding recesses or cavities 40 (not shown in Figures 3 and 4 for brevity) formed on the first lower epitaxial layer 14 during its growth in some or all of the subsequent layers, namely, recesses 53 in the second lower epitaxial layer 16 and / or recesses 55 (shown by dashed lines) in the upper DBR mirror layer 20. In another example, the second lower epitaxial layer 16 and the upper DBR mirror layer 20 may have recesses or cavities that gradually decrease in size (with respect to height H) above one or more recesses or cavities 40 in the top surface 29 of the first lower epitaxial layer 14. This includes, in one example, that the upper surface of the upper DBR mirror layer 20 is flat. However, these examples should not be interpreted as restrictive, as the upper surfaces of each layer above one or more recesses or cavities 40 in the top surface 29 of the first lower epitaxial layer 14 may have recesses or be flat as shown in Figures 3 and 4.

[0113] Finally, in this specification, light 32 is described and illustrated as exiting upward from the upper surface of the upper DBR mirror layer 20. However, in one example, each of the non-limiting embodiments or exemplary VCSELs shown and described herein may be modified such that the upper DBR layer 20 has a higher reflectivity than the lower DBR layer 8, and as a result, light 32 can be reflected by the upper DBR layer 20 through the stack of semiconductor layers 4 and exit downward through the substrate layer 6 remaining at the bottom of the stack of semiconductor layers 4.

[0114] In this example, the second electrical contact 25 may be positioned to electrically contact the bottom surface of the substrate layer 6 and may be formed to have an opening O' similar to the opening O shown in Figures 1, 3, and 7-10, indicated by a dashed line in Figures 1, 3, and 7-10, in order to allow light 32 passing downward through the substrate layer 6 to exit from the bottom surface of the substrate layer 6 through the opening O'. In one example, the first electrical contact 24 may be positioned on the upper surface of the semiconductor layer stack 4, for example, on the upper surface of the upper DBR mirror layer 20, and its opening O may be omitted.

[0115] In another example, the second electrical contact 25 may be located on the side of the main body 2, electrically in contact with the substrate 6, as shown by dashed lines in Figures 1, 3, and 7-10. In yet another example, the second electrical contact 25 may be located on the upper surface of the semiconductor layer stack 4, i.e., on the upper surface of the upper DBR mirror layer 20, in close proximity to or adjacent to the first electrical contact 24, as shown by dashed lines in Figures 1, 3, and 7-10. In this latter example, the second electrical contact 25 may be electrically isolated from the upper surface of the semiconductor layer stack 4, for example, by an oxide layer, and may be electrically connected to the substrate layer 6 through the main body 2 or via a conductor (not particularly shown) located on the side of the main body 2.

[0116] This disclosure also enables the implementation of guide and anti-guide (coupling) sections in a single overgrowth step using a multi-step refractive index profile. Examples of this implementation configuration are shown in Figures 11A-11C and 12A-12C. By adjusting the etching depth according to Equation 2 and appropriately patterning the wafer, regions having guide and anti-guide (coupling) properties according to Equation 1 can be freely defined.

[0117] In the examples in Figures 11A–11C and 12A–12C, the etching depths of the guide and anti-guide sections are set such that the resonance wavelength of the intermediate section is lower than that of the guide section (λ2<λ0) but higher than that of the outermost cavity (λ2>λ1). Using Equation 2, this design can be implemented at the most manufacturable etching depth. This method allows for enhanced / controllable coupling strength of the multi-cavity / emitter VCSEL array. A schematic implementation with two cavities is shown in Figure 11A with a tunnel junction and in Figure 12A with a barrier layer. The flexibility of this technique allows for the selection of different etching depths to pattern the VCSEL cavities during the same lithography process steps when defining the refractive index profiles shown in Figures 11C and 12C, respectively.

[0118] Referring to Figures 11A–11C and 12A–12C, the “confinement” section is defined herein as the outer section of the VCSEL that functions as a “cladding” section by confining light toward the inner region. The confinement region is also generally the region with the lowest refractive index.

[0119] In addition to the confinement region, the disclosure provides any number of regions having different refractive index contrasts, i.e., different optical confinement and current confinement characteristics, based on VCSEL structures and methods used to confine current.

[0120] Figures 11A-11C and 12A-12C show examples of coupled cavities implemented to perform current confinement based on a tunnel junction 30 (Figure 11A) or a barrier layer 18 (Figure 12A). In Figure 11A, a combination of current confinement and optical confinement is provided by etching the tunnel junction 30 and profiling the cavities forming the guide section 62 and the coupled section 66. In Figure 11A, the etching depth h' is determined using this disclosure to obtain the effective refractive index profile shown in Figure 11C. Specifically, in order to perform current confinement within the inner section 64, after the first epitaxial growth, an etching depth h is first achieved by etching to at least the same depth as the tunnel junction 30. Next, a second epitaxial etching depth h' is implemented. Since the current flow must be confined only within the guide section 62, the second etching depth h' must be at least the same depth as that of the tunnel junction 30. However, implementing a lower refractive index contrast would mean that h' would be smaller than h, resulting in incomplete etching of the tunnel junction 30 and making it impossible to confine the current within the guide section 62. The method described herein allows for deeper etching while simultaneously achieving a smaller refractive index difference with respect to the guide section 62 and ensuring proper current confinement.

[0121] In Figure 12A, a combination of current confinement and optical confinement is provided by etching the current-blocking section and profiling the cavities forming the guide section 62 and the coupling section 66. In this embodiment, the current is blocked by the blocking layer 18, shown in black. Therefore, by etching the blocking layer 18, it becomes possible to allow the current to flow. Similar to Figure 11A, a shallow etching depth h is first implemented to introduce the outer refractive index confinement 64. In order to achieve current flow only in the guide section 62, etching must be performed to at least the same depth as the blocking layer 18, thereby removing the blocking layer and allowing the current to flow. By utilizing this disclosure, it becomes possible to design an epitaxial layer stack such that a very small effective refractive index difference is achieved between the guide section 62 and the coupling section 66 by etching to a deep depth h', while simultaneously achieving current confinement by removing the blocking layer 18. The resulting optical profile is shown in Figure 12C. The central part corresponds to the coupling section 66, which has an effective refractive index slightly lower than that of the guide section 62.

[0122] In these two embodiments, the current can be confined to flow within the guide section 62. To do so, the tunnel junction 30 should be preserved or the barrier layer 18 should be etched away only in the region where the current should flow. This sets a minimum technical requirement of an etching depth h equal to the thickness of the tunnel junction 30 or barrier layer 18.

[0123] In the embodiments shown in Figures 11C and 12C of Figures 11 and 12, the same refractive index profile can be obtained, but the etching depth h is different, which can then be determined using Equation 2. The effective optical refractive index of the coupling section 66 can be equal to, lower than, or higher than the effective optical refractive index of the guide section 62, depending on the requirements of the application.

[0124] In some embodiments, the number of coupled emitters can be any of the 2D array. The same technique may be used with a different geometry to achieve mode selection by one or more cavities. In some embodiments, the number of refractive index steps, as shown by the refractive index profiles in Figures 11C and 12C, is not limited to three.

[0125] This disclosure has been described in detail for illustrative purposes based on what is considered to be the most practical and suitable example at present. However, such details are for illustrative purposes only, and this disclosure is not limited to the examples disclosed. On the contrary, it is intended to encompass variations and equivalent configurations that fall within the spirit and scope of the attached claims. For example, this disclosure assumes, to the extent possible, that one or more features of any example may be combined with one or more features of any other example.

[0126] For example, the present disclosure provides a method for determining a facilitable etching depth h for a wide range of refractive index contrasts Δn in the case of cavity patterning defined by lithography. This method is also effective when the cavity patterning defines only the refractive index contrast, independently of current confinement.

[0127] The advantages associated with VCSELs fabricated according to the disclosed method include the following: VCSELs achieve the desired optical mode by etching sections of the epitaxial structure of any thickness and by overgrowth utilizing multiple resonances within the same cavity. VCSELs that have arbitrarily low refractive index contrast and maintain a facilitable etching depth of more than 10 nm. Mode selection is implemented by defining the bonding region and guide region using cavity patterning and a single overgrowth process in a VCSEL. VCSELs, where guiding and anti-guiding (bonding) properties are implemented in a single overgrowth process to enhance bonding between two or more cavities. • VCSELs where multiple refractive index steps exist within the same device to implement guide and coupling sections, and these are implemented in a single overgrowth step. VCSELs where multiple refractive index steps exist within the same device to realize guide and coupling sections, and current confinement is performed if they are implemented in a single overgrowth step and defined within the same processing step. [Explanation of symbols]

[0128] 2 Main unit 4 Semiconductor layer stack 6 circuit boards 8. Lower DBR mirror layer 10 Cavity layer 12 Active area 14. The first lower epitaxial layer 16. The second lower epitaxial layer 18 Current confinement region, barrier layer 18a High current resistance area, cutoff area 18b High current resistance area, cutoff region 18C Low current resistance area 20 Upper DBR mirror layer 22 Current 24 First electrical contact 25. Second electrical contact 29 Top surface 30. Protrusions, raised parts, projecting parts, tunnel joints 32 light 40 Recesses, cavities 50 Protrusions, protrusions 53 Recess 54 Protrusion, protrusion 62 Main region, main cavity, guide section 64 Secondary region, secondary cavity 66 Joined Sections

Claims

1. The device comprises a body having a vertical stack of semiconductor layers that overlap each other, and the stack of semiconductor layers is A current confinement region comprising a low current resistance area defined by a high current resistance area, wherein the vertical current flow in the stack of semiconductor layers is guided by the high current resistance area of ​​the current confinement region to pass through the low current resistance area of ​​the current confinement region, A first lower epitaxial layer is disposed adjacent to the current confinement region, and includes a protrusion or recess disposed adjacent to the low current resistance area of ​​the current confinement region, wherein the protrusion or recess defines a main cavity, and the remainder of the first lower epitaxial layer defines an outer cavity. The aforementioned protrusion or recess is, qλ ０ -mλ １ =n ０ h Defined by a predetermined physical step difference h, In the above equation, λ ０ The resonant wavelength of light in the main cavity is λ. １ is the resonant wavelength of light in the outer cavity, q is a positive half-integer, and n is a positive half-integer. ０ is the effective refractive index in the main cavity, and m is a constant. Vertical-cavity surface-emitting laser (VCSEL).

2. The stack of the aforementioned semiconductor layers is The first distributed Bragg reflection (DBR) mirror layer, A cavity layer containing the active region, The first lower epitaxial layer and the current confinement region, The VCSEL according to claim 1, comprising, in order, a second DBR mirror layer.

3. The stack of the aforementioned semiconductor layers is The substrate layer below the stack of the semiconductor layer, A first contact on the side of the semiconductor layer stack opposite to the substrate layer, The VCSEL according to claim 2, further comprising: a second contact on the substrate layer opposite to the stack of semiconductor layers, or on the side of the main body, or on the stack of semiconductor layers opposite to the substrate layer, wherein the first contact electrically contacts only the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact electrically contacts only the side of the substrate layer opposite to the stack of semiconductor layers.

4. The VCSEL according to claim 1, wherein the high-current resistance area of ​​the current confinement region surrounds the low-current resistance area of ​​the current confinement region.

5. The VCSEL according to claim 4, wherein the protrusion or recess of the first lower epitaxial layer is positioned in alignment with the low current resistance area of ​​the current confinement region.

6. The VCSEL according to claim 5, wherein the low-current resistance area of ​​the current confinement region is circular.

7. The VCSEL according to claim 6, wherein the protrusion or recess of the first lower epitaxial layer is coaxial with the circular current confinement region.

8. The VCSEL according to claim 1, wherein the protruding portion comprises one or more tunnel joints.

9. The VCSEL according to claim 1, wherein the recess comprises one or more etched regions.

10. The VCSEL according to claim 1, wherein the current confinement region comprises one or more oxidized or implanted semiconductor layers.

11. The VCSEL according to claim 1, wherein m is selected from a set of positive half-integer values.

12. λ ０ The VCSEL according to claim 1, wherein the wavelength is in the range of approximately 680 nm to 2600 nm.

13. The VCSEL according to claim 1, wherein h is selected within the range of -500 nm to 500 nm.

14. The VCSEL according to claim 1, wherein the first lower epitaxial layer includes a recess and h is a negative value.

15. The VCSEL operates in a first guide mode defined by the refractive index contrast △n < 0, where △n is Δ / / ０ =(λ) １ -l ０ ) / l ０ The VCSEL according to claim 1, which is an effective refractive index confinement given by

16. h is a negative value, λ １ <λ ０ The VCSEL according to claim 15.

17. The VCSEL according to claim 15, further comprising a section that supports an anti-guide mode in which the refractive index contrast is Δn > 0.

18. The VCSEL according to claim 1, further comprising a second lower epitaxial layer adjacent to the first lower epitaxial layer.

19. The stack of the aforementioned semiconductor layers is The substrate layer below the stack of the semiconductor layer, A first contact on the side of the semiconductor layer stack opposite to the substrate layer, The VCSEL according to claim 18, further comprising: a second contact on the side of the substrate layer opposite to the stack of semiconductor layers, or on the side of the main body, or on the side of the stack of semiconductor layers opposite to the substrate layer, wherein the first contact electrically contacts only the side of the stack of semiconductor layers opposite to the substrate layer, and the second contact electrically contacts only the side of the substrate layer opposite to the stack of semiconductor layers.

20. If the first lower epitaxial layer includes the protrusion, the second lower epitaxial layer also includes a protrusion aligned with the protrusion of the first lower epitaxial layer. The protrusion of the second lower epitaxial layer protrudes into the space surrounded by the high-current-resistance area of ​​the current-confinement region. The VCSEL according to claim 19.

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