Nitride semiconductor equipment

Abstract

Reduce on-resistance. [Solution] The nitride semiconductor device 10 comprises an electron transport layer 24, an electron supply layer 26, a gate electrode 40, a passivation layer 50, a source electrode 42, and a drain electrode 44. The electron supply layer 26 is located on the electron transport layer 24. The electron supply layer 26 has a larger band gap than the electron transport layer 24. The electron supply layer 26 includes a lower surface 26a and an upper surface 26b made of a material with a larger band gap than the lower surface 26a. The source electrode 42 and the drain electrode 44 penetrate the upper surface 26b of the electron supply layer 26 and are in contact with the interior of the electron supply layer 26.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductor devices using a two-dimensional electron gas as a channel are known. Patent Document 1 discloses a nitride semiconductor device having a source electrode and a drain electrode in contact with an electron supply layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-070020

[0004] [overview] In nitride semiconductor devices like those described above, it is sometimes desirable to reduce the on-resistance, which is the resistance in the conductive state.

[0005] A nitride semiconductor device according to one aspect of the present disclosure comprises an electron transport layer, an electron supply layer located on the electron transport layer and having a larger band gap than the electron transport layer, a gate electrode located on the electron supply layer, a source electrode in contact with the electron supply layer, and a drain electrode in contact with the electron supply layer, wherein the gate electrode is located between the source electrode and the drain electrode, the electron supply layer includes a bottom surface and an top surface, the top surface is made of a material with a larger band gap than the bottom surface, and the source electrode and the drain electrode penetrate the top surface of the electron supply layer and are in contact with the interior of the electron supply layer. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2]Figure 2 is a schematic plan view showing an enlarged portion of the internal structure of the nitride semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a schematic cross-sectional view of the line F3-F3 in Figure 2. [Figure 4] Figure 4 is a magnified view of a portion of Figure 3. [Figure 5] Figure 5 is a band gap diagram schematically showing the band gap in the electron supply layer directly below the gate layer. [Figure 6] Figure 6 is a band gap diagram schematically showing the band gap in the portion directly below the drain electrode in the electron supply layer. [Figure 7] Figure 7 is a schematic cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 8] Figure 8 is a magnified view of a portion of Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view of a nitride semiconductor device according to the third embodiment. [Figure 10] Figure 10 is a magnified view of a portion of Figure 9. [Figure 11] Figure 11 is a graph showing the change in the Al composition ratio within the electron supply layer. [Figure 12] Figure 12 is a band gap diagram schematically showing the band gap in the electron supply layer directly below the gate layer. [Figure 13] Figure 13 is a band gap diagram schematically showing the band gap in the electron supply layer directly below the drain electrode. [Figure 14] Figure 14 is a schematic cross-sectional view showing an example of a modification of the drain electrode in the first embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view showing an example of a modification of the drain electrode in the first embodiment. [Figure 16] Figure 16 is a schematic cross-sectional view showing an example of a modification of the electron supply layer in the first embodiment. [Figure 17] Figure 17 is a schematic cross-sectional view showing an example of a modification of the electron supply layer in the first embodiment. [Figure 18] Figure 18 is a schematic cross-sectional view showing a modified example of the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a modified example of the drain electrode of the third embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a modified example of the drain electrode of the third embodiment. [Figure 21] FIG. 21 is an explanatory diagram showing the Al composition ratio of a modified example of the electron supply layer of the third embodiment. [Figure 22] FIG. 22 is an explanatory diagram showing the Al composition ratio of a modified example of the electron supply layer of the third embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a modified example of the nitride semiconductor device. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a modified example of the nitride semiconductor device. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a modified example of the nitride semiconductor device.

[0007] [Detailed Description] Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn at a constant scale. Also, for ease of understanding, in the cross-sectional view, the hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for explanatory purposes and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] [First Embodiment] [Schematic Overall Configuration of Nitride Semiconductor Device] Referring to Figures 1 to 3, the schematic overall configuration of the nitride semiconductor device 10 according to the first embodiment will be described. In the first embodiment, the nitride semiconductor device 10 is a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0010] As shown in Figure 1, the nitride semiconductor device 10 includes a chip body 12. The chip body 12 is configured, for example, in the shape of a rectangular plate. The Z-axis direction of the mutually orthogonal XYZ axes shown in Figure 1 and other drawings is perpendicular to the main surface of the chip body 12 (top surface 13 in Figure 1). The term "plan view" as used in this disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction, unless otherwise explicitly stated. In this disclosure, the term "above" means both "on top of" and "above" unless otherwise explicitly stated. That is, the expression "the first layer is formed above the second layer" does not exclude a structure in which, in one embodiment, the first layer may be in contact with the second layer and directly placed on the second layer, but in other embodiments, another layer may be formed between the first layer and the second layer.

[0011] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. In the example shown in Figure 1, the nitride semiconductor device 10 includes one gate pad 14, multiple source pads 16, and multiple drain pads 18. The gate pad 14, multiple source pads 16, and multiple drain pads 18 are located on the upper surface 13 of the chip body 12. These pads 14, 16, and 18 can be used as external connection terminals for the nitride semiconductor device 10.

[0012] Each of the gate pad 14, source pad 16, and drain pad 18 is configured, for example, in a rectangular shape in a plan view. The gate pad 14 can be positioned, for example, at one corner of the top surface 13. Each of the source pad 16 and drain pad 18 extends in the Y-axis direction in a plan view. The source pad 16 and drain pad 18 are arranged alternately, one by one, in the X-axis direction which is perpendicular to the Y-axis direction. Thus, each of the source pad 16 and drain pad 18 can be said to extend in a direction (Y-axis direction) perpendicular to the direction in which these pads 16 and 18 are arranged (X-axis direction) in a plan view. Note that the shapes of each of the gate pad 14, source pad 16, and drain pad 18 in a plan view can be arbitrarily changed. Also, the arrangement of the gate pad 14, source pad 16, and drain pad 18 can be arbitrarily changed.

[0013] As shown in Figure 3, the nitride semiconductor device 10 includes a substrate 20, a buffer layer 22 provided on the substrate 20, an electron transport layer 24 provided on the buffer layer 22, and an electron supply layer 26 provided on the electron transport layer 24.

[0014] The substrate 20 may be made of a Si substrate, sapphire substrate, SiC substrate, GaN substrate, AlN substrate, or other substrate material. The AlN substrate may be a polycrystalline substrate or a single-crystal substrate. In one example, the substrate 20 is a single-crystal Si substrate. The thickness of the substrate 20 can be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction corresponds to the thickness direction of the substrate 20.

[0015] The buffer layer 22 is provided on the substrate 20, and the electron transport layer 24 is arranged on the buffer layer 22. The buffer layer 22 may be made of any material that can suppress the occurrence of wafer warping and cracking due to mismatch in thermal expansion coefficients between the substrate 20 and the electron transport layer 24. The buffer layer 22 may include one or more nitride semiconductor layers. The buffer layer 22 may include, for example, at least one of aluminum nitride (AlN) layers, aluminum gallium nitride (AlGaN) layers, and graded AlGaN layers having different aluminum (Al) composition ratios. For example, the buffer layer 22 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0016] In one example, the buffer layer 22 may include an AlN layer 22a, a first buffer layer 22b, a second buffer layer 22c, and a third buffer layer 22d. The AlN layer 22a, the first buffer layer 22b, the second buffer layer 22c, and the third buffer layer 22d are stacked sequentially from the substrate 20 upwards.

[0017] The AlN layer 22a is a nucleation layer provided on the substrate 20. The thickness of the AlN layer 22a may be, for example, 100 nm to 500 nm. The first buffer layer 22b is composed of an AlGaN layer provided on the AlN layer 22a. The thickness of the first buffer layer 22b is, for example, 100 nm to 300 nm.

[0018] The second buffer layer 22c is provided on the first buffer layer 22b. The second buffer layer 22c is composed of an AlGaN layer with a lower Al composition ratio than the first buffer layer 22b. The thickness of the second buffer layer 22c is, for example, 100 nm to 300 nm.

[0019] The third buffer layer 22d is provided on the second buffer layer 22c. The third buffer layer 22d is composed of an AlGaN layer with a lower Al composition ratio than the second buffer layer 22c. The thickness of the third buffer layer 22d is, for example, 100 nm to 300 nm.

[0020] In other words, the buffer layer 22 may be composed of multiple AlGaN layers in which the Al composition ratio decreases sequentially as you move from the substrate 20 towards the electron transport layer 24. Alternatively, the buffer layer 22 may be composed of multiple AlGaN layers in which the Ga composition ratio increases sequentially as you move from the substrate 20 towards the electron transport layer 24.

[0021] Furthermore, in order to suppress leakage current in the buffer layer 22, impurities may be introduced into a portion of the buffer layer 22 to make it semi-insulating. In that case, the impurities may be, for example, carbon (C) or iron (Fe). The concentration of the impurities may be, for example, 4 × 10⁻⁶. 16 cm -3 That's fine too.

[0022] The electron transport layer 24 is composed of a nitride semiconductor. The electron transport layer 24 may be composed of, for example, a GaN layer. The thickness of the electron transport layer 24 can be, for example, 0.5 μm or more and 2 μm or less. As an example, the thickness of the electron transport layer 24 may be 0.6 μm or more and 1 μm or less. The electron transport layer 24 may contain one or more nitride semiconductor layers. Furthermore, in order to suppress leakage current in the electron transport layer 24, an impurity may be introduced into a part of the electron transport layer 24 to make the area other than the surface region of the electron transport layer 24 semi-insulating. In this case, the impurity is, for example, carbon (C), and the concentration of the impurity is, for example, 4 × 10⁻¹⁶ at the peak concentration. 16 cm -3 This can be done.

[0023] The electron supply layer 26 is located on the electron transport layer 24 and is composed of a nitride semiconductor having a larger band gap than the electron transport layer 24. The electron supply layer 26 may be composed of, for example, an undoped AlGaN layer. Since the band gap of an AlGaN layer increases with increasing Al composition ratio, the electron supply layer 26, which is an AlGaN layer, has a larger band gap than the electron transport layer 24, which is a GaN layer.

[0024] The electron supply layer 26 includes a lower surface 26a and an upper surface 26b. In the first embodiment, the lower surface 26a of the electron supply layer 26 is in contact with the electron transport layer 24. That is, the lower surface 26a of the electron supply layer 26 can also be said to be the contact surface with the electron transport layer 24. However, it is not limited to this, and another layer may be provided between the lower surface 26a of the electron supply layer 26 and the electron transport layer 24.

[0025] The electron transport layer 24 and the electron supply layer 26 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transport layer 24 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 26 form a lattice-mismatched heterojunction. Due to the spontaneous polarization of the electron transport layer 24 and the electron supply layer 26, and the piezoelectric polarization caused by the compressive stress on the heterojunction portion of the electron transport layer 24, the energy level of the conduction band of the electron transport layer 24 near the heterojunction interface between the electron transport layer 24 and the electron supply layer 26 is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 28 is placed in the electron transport layer 24 at a position close to the heterojunction interface between the electron transport layer 24 and the electron supply layer 26 (e.g., a distance of a few nanometers from the interface). The 2DEG 28 in the electron transport layer 24 functions as a channel in the nitride semiconductor device 10.

[0026] The nitride semiconductor device 10 includes a gate layer 30 provided on a portion of the electron supply layer 26, and a gate electrode 40 provided on the gate layer 30. In other words, the gate electrode 40 is located on the electron supply layer 26.

[0027] (Exemplary structures of gate layer and gate electrode) As shown in Figure 3, the gate layer 30 is located between the source electrode 42 and the drain electrode 44 in the X-axis direction. The gate layer 30 is spaced apart from both the source electrode 42 and the drain electrode 44. In one example, the gate layer 30 is located closer to the source electrode 42 than to the drain electrode 44.

[0028] The gate layer 30 is made of a nitride semiconductor. In one example, the gate layer 30 has a smaller band gap than the electron supply layer 26 and is made of a nitride semiconductor containing acceptor-type impurities. In one example, the gate layer 30 is GaN (p-type GaN layer) containing acceptor-type impurities. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and carbon. The maximum concentration of acceptor-type impurities in the gate layer 30 is, for example, 7 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0029] In the first embodiment, the gate layer 30 is in contact with the upper surface 26b of the electron supply layer 26. That is, the upper surface 26b of the electron supply layer 26 can be said to be the contact surface with the gate layer 30. However, it is not limited to this, and another layer may be provided between the upper surface 26b of the electron supply layer 26 and the gate layer 30.

[0030] The gate layer 30 of the first embodiment includes a ridge portion 31 and a first extension portion 32 and a second extension portion 33 provided on both sides of the ridge portion 31 in the X-axis direction. The ridge portion 31 is provided between the gate electrode 40 and the electron supply layer 26. The gate electrode 40 is positioned on top of the ridge portion 31.

[0031] The first extension portion 32 and the second extension portion 33 are thinner than the ridge portion 31. For example, the ridge portion 31 may have a thickness of 80 nm or more and 150 nm or less. In one example, the ridge portion 31 may have a thickness greater than 110 nm. The first extension portion 32 and the second extension portion 33 may have a thickness of, for example, half or less of the thickness of the ridge portion 31. The upper surfaces of both extension portions 32 and 33 are positioned lower than the upper surface of the ridge portion 31, and more specifically, closer to the electron supply layer 26.

[0032] The extended portions 32 and 33 extend in the X-axis direction from the side surfaces 31a and 31b of the ridge portion 31. The first extended portion 32 extends from the first side surface 31a of the ridge portion 31 toward the source electrode 42. The first extended portion 32 and the source electrode 42 are separated.

[0033] The second extension portion 33 extends from the second side surface 31b of the ridge portion 31 toward the drain electrode 44. The second extension portion 33 and the drain electrode 44 are spaced apart. The length of the second extension portion 33 in the X-axis direction may be longer than the length of the first extension portion 32 in the X-axis direction. For example, the first extension portion 32 may have dimensions of, for example, 0.2 μm or more and 0.3 μm or less in the X-axis direction. On the other hand, the second extension portion 33 may have dimensions of, for example, 0.2 μm or more and 0.6 μm or less in the X-axis direction.

[0034] The upper surface of the gate layer 30 is formed by the upper surface of the ridge portion 31. The lower surface of the gate layer 30 is formed by the lower surface of the ridge portion 31 and the lower surfaces of both extension portions 32 and 33. The area of ​​the lower surface of the gate layer 30 is larger than the area of ​​the upper surface of the gate layer 30. The ridge portion 31 and both extension portions 32 and 33 may be integrally formed or separate.

[0035] The gate electrode 40 comprises one or more metal layers. In one example, the gate electrode 40 may be a titanium nitride (TiN) layer. In another example, the gate electrode 40 may consist of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 40 may be made of a material that has the property of forming a Schottky bond with the gate layer 30, for example. An example of such a material is TiN. The thickness of the gate electrode 40 can be, for example, 50 nm to 200 nm.

[0036] As shown in Figure 3, the nitride semiconductor device 10 includes a passivation layer 50. The passivation layer 50 covers the electron supply layer 26, the gate layer 30, and the gate electrode 40. The passivation layer 50 may be composed of one or any combination of, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 50 can be, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm.

[0037] The passivation layer 50 is provided with a source opening 51 and a drain opening 52. Both openings 51 and 52 are located on both sides of the gate layer 30 in the X-axis direction. Therefore, the gate electrode 40 located on the gate layer 30 is positioned between the source opening 51 and the drain opening 52. The gate electrode 40 is also positioned between the source electrode 42 and the drain electrode 44. Both openings 51 and 52 extend in the Y-axis direction. Part of the electron supply layer 26 is exposed by both openings 51 and 52. In the first embodiment, the source opening 51 corresponds to the "first opening" and the drain opening 52 corresponds to the "second opening".

[0038] The nitride semiconductor device 10 includes a source electrode 42 and a drain electrode 44. The source electrode 42 is located within the source opening 51 and is in contact with the electron supply layer 26 through the source opening 51. The source electrode 42 also includes a source overhang 43 that extends beyond the source opening 51. The source overhang 43 is located on the peripheral edge of the source opening 51 on the passivation layer 50.

[0039] The drain electrode 44 is located within the drain opening 52 and is in contact with the electron supply layer 26 through the drain opening 52. The drain electrode 44 also includes a drain overhang 45 that extends beyond the drain opening 52. The drain overhang 45 is located on the peripheral edge of the drain opening 52 on the passivation layer 50.

[0040] The source electrode 42 and the drain electrode 44 include one or more metal layers. In one example, the source electrode 42 and the drain electrode 44 may be made of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu).

[0041] In one example, the source electrode 42 and the drain electrode 44 may have a two-layer structure of Ti / Al. Specifically, the source electrode 42 and the drain electrode 44 may have a two-layer structure composed of a Ti layer in contact with the electron supply layer 26 and an Al layer provided on the Ti layer.

[0042] The source electrode 42 and drain electrode 44 may also have a four-layer structure of Ti / Al / Ni / Au, although this is not limited to the above. Specifically, the source electrode 42 and drain electrode 44 may have a four-layer structure composed of a Ti layer in contact with the electron supply layer 26, an Al layer provided on the Ti layer, a Ni layer provided on the Al layer, and an Au layer provided on the Ni layer.

[0043] The nitride semiconductor device 10 includes a field plate electrode 60 provided on a passivation layer 50. The field plate electrode 60 is electrically connected to the source electrode 42. In the example shown in Figure 3, the field plate electrode 60 is integrally configured with the source electrode 42. In the first embodiment, the field plate electrode 60 is the portion extending from the source overhang 43 toward the drain electrode 44. A voltage of the same potential as that of the source electrode 42 is applied to the field plate electrode 60. The field plate electrode 60 is also called the source field plate. In a plan view, the field plate electrode 60 covers the entire gate layer 30.

[0044] The field plate electrode 60 is separated from the drain electrode 44. In a plan view, the end of the field plate electrode 60 is located between the gate layer 30 and the drain electrode 44. When a drain voltage is applied to the drain electrode 44 in a zero-bias state where no voltage is applied to the gate electrode 40, the field plate electrode 60 mitigates the electric field concentration near the end of the gate electrode 40 and near the end of the gate layer 30.

[0045] (Exemplary planar layout of nitride semiconductor device) Next, an exemplary planar layout of the HEMT structure (nitride semiconductor device 10) will be described with reference to Figure 2. For clarity of the illustration, the passivation layer 50 is omitted from Figure 2, while the source opening 51 and drain opening 52 are shown with solid lines. The field plate electrode 60 is shown with a dashed line.

[0046] As shown in Figure 2, the nitride semiconductor device 10 includes a plurality of transistor elements, each having a HEMT structure, within the element region. Although Figure 2 only shows a plurality of transistor elements aligned in the X-axis direction, in reality, transistor elements can be arranged in both the X-axis and Y-axis directions.

[0047] A drain electrode 44 is provided for each transistor element. The drain electrode 44 extends in the Y-axis direction in a plan view. The source electrode 42 is provided, for example, so as to surround each drain electrode 44 in a plan view. The field plate electrode 60, which is integrally formed with the source electrode 42, extends toward the adjacent drain electrode 44 in a plan view. In the example shown in Figure 2, the source electrode 42 is provided continuously in the X-axis direction across multiple adjacent transistor elements in the X-axis direction, but it may be separated into multiple parts in the X-axis direction.

[0048] A gate layer 30 and a gate electrode 40 are provided for each transistor element. Each gate layer 30 and each gate electrode 40 are arranged in a ring shape so as to surround one of the drain electrodes 44 in a plan view.

[0049] The nitride semiconductor device 10 includes a gate wiring 72, a source wiring 74, and a drain wiring 76. The gate wiring 72, source wiring 74, and drain wiring 76 are provided on a first interlayer insulating layer (not shown) that covers the source electrode 42 and the drain electrode 44. In the example shown in Figure 2, each of the gate wiring 72, source wiring 74, and drain wiring 76 extends in the X-axis direction. The gate wiring 72, source wiring 74, and drain wiring 76 are spaced apart from each other in the Y-axis direction. The gate wiring 72 is located in a different position from the drain electrode 44, source opening 51, and drain opening 52 in the Y-axis direction. The source wiring 74 and drain wiring 76 are located in a position that overlaps with the drain electrode 44, source opening 51, and drain opening 52 in a plan view in the Y-axis direction.

[0050] For example, gate wiring 72 is connected to gate electrode 40 by gate connection conductor 73 which penetrates the first interlayer insulating layer and extends to gate electrode 40. Source wiring 74 is connected to source electrode 42 by source connection conductor 75 which penetrates the first interlayer insulating layer. Drain wiring 76 is connected to drain electrode 44 by drain connection conductor 77 which penetrates the first interlayer insulating layer. Each of the gate connection conductor 73, source connection conductor 75, and drain connection conductor 77 is, for example, a via that penetrates the first interlayer insulating layer. The number of each of the gate connection conductor 73, source connection conductor 75, and drain connection conductor 77 can be arbitrarily changed.

[0051] For example, the gate wiring 72, source wiring 74, and drain wiring 76 are covered by a second interlayer insulating layer (not shown). In one example, the gate pad 14, source pad 16, and drain pad 18 shown in Figure 1 are located on the second interlayer insulating layer. The second interlayer insulating layer constitutes, for example, the top surface 13.

[0052] For example, gate wiring 72 is connected to gate pad 14 by a gate connection conductor (not shown) that penetrates the second interlayer insulation layer and extends to gate pad 14. Source wiring 74 is connected to source pad 16 by a source connection conductor (not shown) that penetrates the second interlayer insulation layer. Drain wiring 76 is connected to drain pad 18 by a drain connection conductor (not shown) that penetrates the second interlayer insulation layer.

[0053] (Detailed configuration of the electron supply layer) Next, with reference to Figures 3 and 4, the electron supply layer 26 and the contact structure between the electron supply layer 26 and both electrodes 42 and 44 will be described in detail.

[0054] As shown in FIGS. 3 and 4, in the first embodiment, the lower surface 26a of the electron supply layer 26 is in contact with the electron transport layer 24. The lower surface 26a of the electron supply layer 26 can also be said to be the interface between the electron transport layer 24 and the electron supply layer 26. Also, the upper surface 26b of the electron supply layer 26 is in contact with the gate layer 30. The upper surface 26b of the electron supply layer 26 can also be said to be the interface between the electron supply layer 26 and the gate layer 30.

[0055] The electron supply layer 26 includes a first electron supply layer 81 including the lower surface 26a and a second electron supply layer 82 including the upper surface 26b. The second electron supply layer 82 is located on the first electron supply layer 81. The first electron supply layer 81 is disposed between the electron transport layer 24 and the second electron supply layer 82.

[0056] The first electron supply layer 81 is composed of an AlGaN layer with an Al composition ratio of x1. That is, the first electron supply layer 81 is composed of Al x1 Ga 1-x1 N. The Al composition ratio x1 of the first electron supply layer 81 is preferably, for example, greater than 0% and 20% or less. As an example, the Al composition ratio x1 of the first electron supply layer 81 may be 10% or more and 20% or less. Also, the Al composition ratio x1 of the first electron supply layer 81 may be 13% or more and 17% or less. In the first embodiment, the composition ratio in the first electron supply layer 81 is constant.

[0057] The second electron supply layer 82 is configured to have a larger bandgap than the first electron supply layer 81. For example, the second electron supply layer 82 is composed of an AlGaN layer having a larger Al composition ratio than the first electron supply layer 81. In other words, the second electron supply layer 82 is composed of Al x2 Ga 1-x2The second electron supply layer 82 is composed of N, and the Al composition ratio x2 of the second electron supply layer 82 is set to be greater than the Al composition ratio x1 of the first electron supply layer 81. The Al composition ratio x2 of the second electron supply layer 82 is, for example, greater than 20% and less than 80%. The Al composition ratio x2 of the second electron supply layer 82 may also be, for example, greater than 20% and 30% or less. As an example, the Al composition ratio x2 of the second electron supply layer 82 may be 23% or more and 27% or less. In the first embodiment, the composition ratio within the second electron supply layer 82 is constant.

[0058] In other words, in the first embodiment, the electron supply layer 26 is configured such that the band gap increases from the lower surface 26a to the upper surface 26b. Specifically, the band gap of GaN is 3.4 eV, while the band gap of AlN is 6.2 eV. The electron supply layer 26, which is composed of an AlGaN layer, varies within the range of 3.4 eV to 6.2 eV depending on the Al composition ratio, and specifically, the band gap increases with increasing Al composition ratio.

[0059] In this regard, in the first embodiment, the Al composition ratio x2 of the second electron supply layer 82 is greater than the Al composition ratio x1 of the first electron supply layer 81, so the band gap of the second electron supply layer 82 is larger than that of the first electron supply layer 81. As already explained, the upper surface 26b of the electron supply layer 26 is composed of the second electron supply layer 82, and the lower surface 26a of the electron supply layer 26 is composed of the first electron supply layer 81. For this reason, it can be said that the upper surface 26b of the electron supply layer 26 is composed of a material with a larger band gap than the lower surface 26a.

[0060] Here, the difference between the Al composition ratio x1 of the first electron supply layer 81 and the Al composition ratio x2 of the second electron supply layer 82 may be, for example, 8% or more and 20% or less. In other words, the electron supply layer 26 may have a configuration in which the Al composition ratio changes discontinuously within the electron supply layer 26.

[0061] The impurity concentrations in both electron supply layers 81 and 82 should be lower than, for example, the impurity concentration in the gate layer 30. For example, both electron supply layers 81 and 82 may be composed of undoped AlGaN layers.

[0062] As shown in Figure 4, the first thickness D1, which is the thickness of the first electron supply layer 81, and the second thickness D2, which is the thickness of the second electron supply layer 82, are set to be the same. For example, both thicknesses D1 and D2 may be between 5 nm and 10 nm.

[0063] (Regarding the contact between the electron supply layer 26 and both electrodes 42 and 44) Next, the contact structure between the electron supply layer 26 and both electrodes 42 and 44 will be described. Here, the contact structure between the source electrode 42 and the electron supply layer 26 is the same as the contact structure between the drain electrode 44 and the electron supply layer 26. For the sake of explanation, the contact structure between the drain electrode 44 and the electron supply layer 26 will be described, and the contact structure between the source electrode 42 and the electron supply layer 26 will be omitted.

[0064] As shown in Figure 4, the drain opening 52 in the first embodiment penetrates the passivation layer 50 and reaches into the electron supply layer 26. Correspondingly, the drain electrode 44 penetrates the upper surface 26b of the electron supply layer 26 through the drain opening 52 and reaches into the electron supply layer 26. In the first embodiment, the drain electrode 44 penetrates the second electron supply layer 82 and is in contact with the first electron supply layer 81. In detail, the lower end surface 44a of the drain electrode 44 is in contact with the first electron supply layer 81. The lower end surface 44a of the drain electrode 44 is the surface of the drain electrode 44 that faces the electron transport layer 24 in the Z-axis direction.

[0065] The electron supply layer 26 includes a drain thin film portion 90 that is locally thinned by the drain opening 52. The drain thin film portion 90 is the portion of the electron supply layer 26 between the lower end surface 44a of the drain electrode 44 and the electron transport layer 24. The drain thin film portion 90 is thinner than the portion of the electron supply layer 26 directly beneath the gate layer 30.

[0066] Incidentally, unless otherwise specified, the thickness D3 of the electron supply layer 26 is the combined thickness of both electron supply layers 81 and 82, that is, the combined thickness of both thicknesses D1 and D2. The thickness D3 of the electron supply layer 26 may be, for example, 10 nm or more and 20 nm or less. In the first embodiment, the thickness of the portion of the electron supply layer 26 directly below the gate electrode 40 is thickness D3. However, it is not limited to this, and the specific dimensions of both thicknesses D1 and D2 and the thickness D3 of the electron supply layer 26 are arbitrary.

[0067] The distance L1 between the lower end surface 44a of the drain electrode 44 and the electron transport layer 24 can be said to be either the thickness of the drain thin film portion 90 or the distance between the lower end surface 44a of the drain electrode 44 and the lower surface 26a of the electron supply layer 26.

[0068] In the first embodiment, the distance L1 between the lower end surface 44a of the drain electrode 44 and the electron transport layer 24 is set to be the same as the first thickness D1. In the first embodiment, the first thickness D1 and the second thickness D2 are the same. Therefore, the lower end surface 44a of the drain electrode 44 is located at the center of the thickness direction of the electron supply layer 26.

[0069] However, the distance L1 between the lower end surface 44a of the drain electrode 44 and the electron transport layer 24 may be smaller than the first thickness D1. That is, the lower end surface 44a of the drain electrode 44 may be located between the center of the electron supply layer 26 in the thickness direction and its lower surface 26a. In other words, the position of the lower end surface 44a of the drain electrode 44 does not have to coincide with the interface of both electron supply layers 81 and 82.

[0070] Similarly, as shown in Figure 3, the distance L2 between the lower end surface 42a of the source electrode 42 in the electron supply layer 26 and the electron transport layer 24 is shorter than the thickness D3 of the electron supply layer 26. Note that both distances L1 and L2 are the same. However, this is not limited to this, and the two distances L1 and L2 may be different from each other.

[0071] Incidentally, the source opening 51 and drain opening 52 are formed by etching while the passivation layer 50 is formed. More specifically, the manufacturing method of the nitride semiconductor device 10 includes the steps of forming a mask on the passivation layer 50 in areas other than the two openings 51 and 52, and etching the passivation layer 50. In the etching step, the etching conditions are adjusted so that the two openings 51 and 52 penetrate the passivation layer 50 and the second electron supply layer 82, exposing the first electron supply layer 81. The manufacturing method of the nitride semiconductor device 10 also includes the step of forming both electrodes 42 and 44 within the two openings 51 and 52. This allows both electrodes 42 and 44 to be formed within the electron supply layer 26 while suppressing additional steps.

[0072] (Operation of the first embodiment) The operation of the first embodiment will be explained using Figures 3, 5, and 6. As shown in Figure 3, a first electron supply layer 81 and a second electron supply layer 82 are stacked in the electron supply layer 26 directly beneath the gate electrode 40. Since the second electron supply layer 82 has a larger band gap than the first electron supply layer 81, 2DEG28 is more likely to occur compared to the case where only the first electron supply layer 81 is present. This allows for a larger amount of 2DEG28 directly beneath the gate electrode 40, thereby reducing the on-resistance.

[0073] Furthermore, in the first embodiment, both electrodes 42 and 44 penetrate the upper surface 26b of the electron supply layer 26 and enter the electron supply layer 26. This allows the distances L1 and L2 between both electrodes 42 and 44 and the electron transport layer 24 to be shortened, thereby further reducing the on-resistance.

[0074] Here, when electrodes 42 and 44 come into contact with a layer with a large band gap, the contact resistance tends to increase. Specifically, as shown in Figure 5, when a second electron supply layer 82 is provided, the band gap of the upper surface 26b of the electron supply layer 26 is increased. Therefore, when electrodes 42 and 44 come into contact with the upper surface 26b of the second electron supply layer 82, the contact resistance between electrodes 42 and 44 and the electron supply layer 26 tends to increase.

[0075] In contrast, in the first embodiment, a first electron supply layer 81 is provided on the electron transport layer 24, and a second electron supply layer 82 is provided on the first electron supply layer 81. Since the first electron supply layer 81 is positioned between the electron transport layer 24 and the second electron supply layer 82, both electrodes 42 and 44 that penetrate the upper surface 26b can be brought into contact with the first electron supply layer 81.

[0076] As shown in Figure 6, when the second electron supply layer 82 is absent and only the first electron supply layer 81 is present, the band gap of the electron supply layer 26 becomes smaller. Therefore, by bringing both electrodes 42 and 44 into contact with the first electron supply layer 81, the contact resistance can be reduced.

[0077] (Effects of the first embodiment) The first embodiment described in detail above provides the following effects. (1-1) The nitride semiconductor device 10 comprises an electron transport layer 24, an electron supply layer 26, a gate electrode 40, a source electrode 42, and a drain electrode 44. The electron supply layer 26 is located on the electron transport layer 24. The electron supply layer 26 has a larger band gap than the electron transport layer 24. The gate electrode 40 is located on the electron supply layer 26. The gate electrode 40 is located between the source electrode 42 and the drain electrode 44.

[0078] In this configuration, the electron supply layer 26 includes a lower surface 26a and an upper surface 26b made of a material with a larger band gap than the lower surface 26a. The source electrode 42 and the drain electrode 44 penetrate the upper surface 26b of the electron supply layer 26 and are in contact with the interior of the electron supply layer 26.

[0079] With this configuration, the band gap of the upper surface 26b is relatively large, which allows for a large amount of 2DEG28 to be generated. On the other hand, if the band gaps of both electrodes 42 and 44 are in contact with the upper surface 26b, the contact resistance tends to be large. In this regard, the source electrode 42 and drain electrode 44 penetrate the upper surface 26b, which has a relatively large band gap, and are in contact with the inside of the electron supply layer 26. Both electrodes 42 and 44 can be brought into contact with a location in the electron supply layer 26 where the contact resistance is smaller than that of the upper surface 26b. In addition, the distances L1 and L2 between both electrodes 42 and 44 and the electron transport layer 24 are shorter than the thickness D3 of the electron supply layer 26. From the above, the on-resistance can be reduced.

[0080] (1-2) The electron supply layer 26 includes a first electron supply layer 81 and a second electron supply layer 82. The first electron supply layer 81 includes a bottom surface 26a. The second electron supply layer 82 includes an top surface 26b. The second electron supply layer 82 is located on the first electron supply layer 81. The second electron supply layer 82 has a larger band gap than the first electron supply layer 81. The source electrode 42 and the drain electrode 44 penetrate the second electron supply layer 82.

[0081] With this configuration, the amount of 2DEG28 generated can be increased by the second electron supply layer 82. Also, since both electrodes 42 and 44 penetrate the second electron supply layer 82, the distances L1 and L2 between both electrodes 42 and 44 and the electron transport layer 24 are shortened by at least the second thickness D2, which is the thickness of the second electron supply layer 82. Therefore, the on-resistance can be reduced by that amount.

[0082] (1-3) The first electron supply layer 81 is composed of an undoped AlGaN layer. The second electron supply layer 82 is composed of an undoped AlGaN layer with a higher Al composition ratio than the first electron supply layer 81.

[0083] With this configuration, the band gap can be changed by changing the Al composition ratio. Furthermore, since an AlGaN layer with a large band gap is placed on top of an AlGaN layer with a small band gap, electrons are easily supplied to the electron transport layer 24. As a result, the necessary 2DEG28 can be secured even in an undoped state.

[0084] (1-4) The Al composition ratio x1 of the first electron supply layer 81 is greater than 0% and 20% or less. The Al composition ratio x2 of the second electron supply layer 82 is greater than 20% and 30% or less. This allows the above-mentioned effects to be obtained. In particular, since the Al composition ratio x2 of the second electron supply layer 82 is set to 30% or less, it is possible to suppress the disadvantages caused by an excessively high Al composition ratio, such as a decrease in crystallinity due to dislocations and defects, or the occurrence of cracks.

[0085] (1-5) The source electrode 42 and the drain electrode 44 penetrate the second electron supply layer 82 and are in contact with the first electron supply layer 81. With this configuration, since both electrodes 42 and 44 are in contact with the first electron supply layer 81, which has a smaller band gap than the second electron supply layer 82, the contact resistance between both electrodes 42 and 44 and the first electron supply layer 81 can be reduced. As a result, the contact resistance between both electrodes 42 and 44 and the electron supply layer 26 can be reduced, thereby reducing the on-resistance.

[0086] (1-6) The difference between the Al composition ratio x2 of the second electron supply layer 82 and the Al composition ratio x1 of the first electron supply layer 81 is between 8% and 20%. With this configuration, by creating a difference in the Al composition ratios x1 and x2 between the two electron supply layers 81 and 82 as described above, it is possible to achieve both an increase in the amount of 2DEG28 generated and a reduction in contact resistance. Furthermore, the Al composition ratio changes discontinuously between the first electron supply layer 81 and the second electron supply layer 82. This allows strain to be generated at the interface between the two electron supply layers 81 and 82, thereby promoting the generation of 2DEG28.

[0087] (1-7) The nitride semiconductor device 10 includes a passivation layer 50. The passivation layer 50 includes a source opening 51 as a first opening and a drain opening 52 as a second opening. The source electrode 42 is in contact with the electron supply layer 26 through the source opening 51. The drain electrode 44 is in contact with the electron supply layer 26 through the drain opening 52. The source electrode 42 includes a source overhang 43 provided on the periphery of the source opening 51 on the passivation layer 50. The drain electrode 44 includes a drain overhang 45 provided on the periphery of the drain opening 52 on the passivation layer 50.

[0088] With this configuration, since electrodes 42 and 44 overlap with the openings 51 and 52, it is possible to accommodate misalignment of both electrodes 42 and 44 with respect to the openings 51 and 52. (1-8) The nitride semiconductor device 10 includes a gate layer 30 containing acceptor impurities. The gate layer 30 is located between the electron supply layer 26 and the gate electrode 40. This enables normally-off operation.

[0089] (1-9) The nitride semiconductor device 10 comprises a substrate 20 and a buffer layer 22. The buffer layer 22 is provided on the substrate 20. The electron transport layer 24 is arranged on the buffer layer 22. This makes it possible to suppress problems that occur when the lattice constants of the substrate 20 and the electron transport layer 24 are different, such as the occurrence of defects.

[0090] (1-10) The buffer layer 22 includes an AlN layer 22a, a first buffer layer 22b, a second buffer layer 22c, and a third buffer layer 22d. The first buffer layer 22b is composed of an AlGaN layer laminated on the AlN layer 22a. The second buffer layer 22c is laminated on the first buffer layer 22b and is composed of an AlGaN layer with a lower Al composition ratio than the first buffer layer 22b. The third buffer layer 22d is laminated on the second buffer layer 22c and is composed of an AlGaN layer with a lower Al composition ratio than the second buffer layer 22c. This further suppresses the generation of dislocations.

[0091] <Second Embodiment> The nitride semiconductor device 10 of the second embodiment will be described with reference to Figures 7 and 8. Components common to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0092] As shown in Figures 7 and 8, the electron supply layer 26 of the second embodiment includes an etching stop layer 100 provided between the first electron supply layer 81 and the second electron supply layer 82. The etching stop layer 100 is composed of, for example, an AlN layer. The etching stop layer 100 is thinner than the first electron supply layer 81 and the second electron supply layer 82. For example, while the thicknesses D1 and D2 of both electron supply layers 81 and 82 are 5 nm to 10 nm, the thickness Dx of the etching stop layer 100 is 0.5 nm to 2 nm.

[0093] In the second embodiment, the lower end surface 44a of the drain electrode 44 is in contact with the etching stop layer 100. The lower end surface 44a of the drain electrode 44 faces the first electron supply layer 81 via the etching stop layer 100. The drain electrode 44 and the first electron supply layer 81 are electrically connected via the etching stop layer 100. In detail, because the etching stop layer 100 is very thin, the drain electrode 44 and the first electron supply layer 81 are electrically connected by the tunnel effect. In other words, the etching stop layer 100 is formed to be thin so that the drain electrode 44 and the first electron supply layer 81 are electrically connected. The same applies to the source electrode 42.

[0094] The manufacturing method for the nitride semiconductor device 10 of the second embodiment includes a step of stacking a first electron supply layer 81, an etching stop layer 100, and a second electron supply layer 82. In the step of forming both openings 51 and 52 by etching the passivation layer 50, etching is restricted by the etching stop layer 100. Specifically, a fluorine-based dry etching gas is used for etching. With a fluorine-based dry etching gas, dry etching is possible for AlGaN layers with a low Al composition ratio, while in an AlN layer, for example, Al and fluorine react to generate AlF, and this AlF inhibits the progress of dry etching. As a result, both openings 51 and 52 penetrate the second electron supply layer 82 through etching, while etching to the first electron supply layer 81 is less likely to occur. Therefore, even if there is variation in the dry etching rate, etching to the first electron supply layer 81 can be suppressed.

[0095] (Effects of the second embodiment) According to the second embodiment described in detail above, in addition to the effects of the first embodiment, the following effects are achieved.

[0096] (2-1) The electron supply layer 26 includes an etching stop layer 100 between the first electron supply layer 81 and the second electron supply layer 82. With this configuration, etching up to the first electron supply layer 81 can be suppressed. This prevents etching up to the first electron supply layer 81, which would reduce the amount of 2DEG28 generated in the region directly beneath both electrodes 42 and 44.

[0097] (2-2) Both electrodes 42 and 44 are in contact with the etching stop layer 100. The etching stop layer 100 is thinner than both electron supply layers 81 and 82. For example, the thickness Dx of the etching stop layer 100 is 0.5 nm to 2 nm.

[0098] With this configuration, the tunneling effect causes electrical conductivity between both electrodes 42 and 44 and the first electron supply layer 81 via the etching stop layer 100. As a result, even when both electrodes 42 and 44 are in contact with the etching stop layer 100, the contact resistance does not tend to increase. Therefore, the effect of (2-1) can be achieved while suppressing an increase in the contact resistance between both electrodes 42 and 44 and the electron supply layer 26.

[0099] The etching stop layer 100 is not limited to an AlN layer; for example, it may be an AlGaN layer having an Al composition ratio of 80% or more. Even in this case, etching can be inhibited.

[0100] <Third Embodiment> Referring to Figures 9 to 11, the schematic configuration of the nitride semiconductor device 10 of the third embodiment will be described. In the third embodiment, the structure of the electron supply layer 110 differs from that of the first embodiment. Components common to both the first and third embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0101] As shown in Figures 9 to 11, the electron supply layer 110 of the third embodiment is composed of an AlGaN layer in which the Al composition ratio increases from the lower surface 110a to the upper surface 110b. In the third embodiment, as shown in Figure 11, the Al composition ratio of the electron supply layer 110 may increase linearly from the lower surface 110a to the upper surface 110b. That is, the electron supply layer 110 of the third embodiment is configured to have a continuously changing Al composition ratio. For this reason, the electron supply layer 110 of the third embodiment is configured so that the band gap gradually decreases from the upper surface 110b to the lower surface 110a.

[0102] The Al composition ratio of the lower surface 110a may be greater than 0% and 20% or less. The Al composition ratio of the upper surface 110b may be greater than 20% and 30% or less. The difference between the Al composition ratio of the upper surface 110b and the Al composition ratio of the lower surface 110a may be, for example, 8% or more and 20% or less.

[0103] In this configuration, as shown in Figure 10, the lower end surface 44a of the drain electrode 44 penetrates the upper surface 110b and contacts the inside of the electron supply layer 110. In other words, the drain opening 52 removes the high Al composition ratio region of the electron supply layer 110, including the upper surface 110b, and the drain electrode 44 can be said to be in contact with the low Al composition ratio region, which has a lower Al composition ratio than the high Al composition ratio region.

[0104] In the third embodiment, the lower end surface 44a of the drain electrode 44 is located at the center of the thickness direction of the electron supply layer 110. The electron supply layer 110 in the third embodiment may be, for example, 10 nm or more and 20 nm or less.

[0105] (Operation of the third embodiment) The operation of the third embodiment will be explained using Figures 12 and 13. As shown in Figure 12, the band gap gradually increases from the lower surface 110a to the upper surface 110b, corresponding to the increasing Al composition ratio from the lower surface 110a to the upper surface 110b. As a result, 2DEG28 is more likely to occur in the region directly beneath the gate electrode 40 or the gate layer 30.

[0106] On the other hand, as shown in Figure 13, in the areas where the source electrode 42 and drain electrode 44 are provided, there are no areas with a high Al composition ratio, and the source electrode 42 and drain electrode 44 are in contact with a region with a smaller band gap than the upper surface 110b.

[0107] (Effects of the third embodiment) The third embodiment described in detail above provides the following effects. (3-1) The electron supply layer 26 is composed of AlGaN layers in which the Al composition ratio increases from the lower surface 26a to the upper surface 26b.

[0108] With this configuration, the lower end surface 42a of the source electrode 42 and the lower end surface 44a of the drain electrode 44 are in contact with a location where the band gap is smaller than that of the upper surface 26b of the electron supply layer 26. As a result, the contact resistance can be reduced compared to the case where the lower end surface 42a of the source electrode 42 and the lower end surface 44a of the drain electrode 44 are in contact with the upper surface 26b of the electron supply layer 26.

[0109] (3-2) The Al composition ratio of the lower surface 26a is greater than 0% and 20% or less, and the Al composition ratio of the upper surface 26b is greater than 20% and 30% or less. With this configuration, the Al composition ratio is greater than 0% and less than or equal to 20%, which allows the band gap on the lower surface 26a to be reduced, thereby reducing the contact resistance between the source electrode 42 and the drain electrode 44 and the electron supply layer 110.

[0110] On the other hand, since the Al composition ratio of the upper surface 110b is greater than 20% and less than or equal to 30%, the band gap on the upper surface 26b side can be increased. This allows for an increase in the amount of 2DEG28 generated, thereby lowering the on-resistance.

[0111] In particular, since the Al composition ratio of the upper surface 110b is 30% or less, it is possible to suppress the problems caused by an excessively high Al composition ratio, such as a decrease in crystallinity due to dislocations and defects, or the occurrence of cracks.

[0112] (3-3) The difference in the Al composition ratio between the lower surface 26a and the upper surface 26b is between 8% and 20%. With this configuration, it is possible to maintain the crystal quality of the electron supply layer 110 while balancing the reduction of contact resistance with the amount of 2DEG28 generated.

[0113] <Example of changes> The above embodiment can be implemented with the following modifications. The above embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically. The modifications shown in Figures 14 to 20 can also be applied to the source electrode 42.

[0114] As shown in Figure 14, in the first embodiment, the lower end surface 44a of the drain electrode 44 may be located between the center of the electron supply layer 26 in the thickness direction and the upper surface 26b. Even in this case, the drain electrode 44 can be said to penetrate the upper surface 26b of the electron supply layer 26. With this configuration, even if variations in etching rate occur, the first electron supply layer 81 is likely to remain directly beneath the drain electrode 44. In this case, the lower end surface 44a of the drain electrode 44 may be in contact with the second electron supply layer 82. Even in this case, the on-resistance can be reduced due to the increase in 2DEG28 by the second electron supply layer 82, and because the thickness of the drain thin film portion 90 (distance L1 between the lower end surface 44a of the drain electrode 44 and the electron transport layer 24) is shorter than the thickness D3 of the electron supply layer 26. The drain electrode 44 may also penetrate the electron supply layer 26 and be in direct contact with the electron transport layer 24. The same applies to the second and third embodiments.

[0115] As shown in Figure 15, in the first embodiment, the lower end surface 44a of the drain electrode 44 may be located between the central position in the thickness direction of the electron supply layer 26 and the lower surface 26a. This allows the thickness of the drain thin film portion 90 to be reduced, thereby further reducing the on-resistance. The same applies to the second and third embodiments.

[0116] In the first embodiment, the first thickness D1 and the second thickness D2 may be different from each other. For example, as shown in Figure 16, the first thickness D1 may be greater than the second thickness D2. In this case, the positional margin for positioning the lower end surface 44a of the drain electrode 44 within the first electron supply layer 81 can be increased, making it easier to bring the drain electrode 44 into contact with the first electron supply layer 81. This suppresses the inconvenience of the lower end surface 44a of the drain electrode 44 not being able to contact the first electron supply layer 81 due to misalignment or the like.

[0117] In this configuration, the lower end surface 44a of the drain electrode 44 may be located at the center of the thickness direction of the electron supply layer 26, or it may be located between the center and the lower surface 26a. The same applies to the second embodiment.

[0118] As shown in Figure 17, in the first embodiment, the second thickness D2 may be greater than the first thickness D1. In this case, since the second thickness D2, which has a higher Al composition ratio, is larger, the amount of 2DEG28 generated increases. This makes it possible to further reduce the on-resistance.

[0119] More specifically, the sheet carrier density of 2DEG28 generated in the electron transport layer 24 can be increased by increasing at least one of the Al composition ratio and thickness D3 of the electron supply layer 26. Therefore, by making the second thickness D2 larger than the first thickness D1, the sheet carrier density of 2DEG28 can be increased, and the on-resistance can be further reduced.

[0120] In this configuration, the lower end surface 44a of the drain electrode 44 may be positioned between the central position in the thickness direction of the electron supply layer 26 and its lower surface 26a so as to be in contact with the first electron supply layer 81.

[0121] As shown in Figure 18, in the second embodiment, the drain electrode 44 may penetrate the etching stop layer 100 and contact the first electron supply layer 81. In this case, the method for manufacturing the nitride semiconductor device 10 may include a step of etching the etching stop layer 100 using, for example, chlorine-based dry etching.

[0122] As shown in Figure 19, in the third embodiment, the lower end surface 44a of the drain electrode 44 may be located between the center of the electron supply layer 110 in the thickness direction and the upper surface 110b. In this case, even if variations in etching rate occur, the electron supply layer 110 is likely to remain directly beneath the drain electrode 44. The drain electrode 44 may also penetrate the electron supply layer 110 and be in direct contact with the electron transport layer 24.

[0123] In the second embodiment, the thickness Dx of the etching stop layer 100 is not limited to 0.5 nm to 2 nm. The thickness Dx of the etching stop layer 100 should be such that electrical conductivity can be established between both electrodes 42 and 44 and the first electron supply layer 81 through the etching stop layer 100 by the tunneling effect.

[0124] As shown in Figure 20, in the third embodiment, the lower end surface 44a of the drain electrode 44 may be located between the central position and the lower surface 110a of the electron supply layer 110. In this case, it will come into contact with AlGaN with a lower Al composition ratio, thus reducing the contact resistance.

[0125] In the third embodiment, the change in the Al composition ratio within the electron supply layer 110 is not limited to a linear change. For example, as shown in Figure 21, the Al composition ratio may change exponentially, with the amount of change increasing as one approaches the upper surface 110b. Alternatively, as shown in Figure 22, the Al composition ratio may change logarithmically, with the amount of change decreasing as one approaches the upper surface 110b.

[0126] As shown in Figure 23, the gate layer 30 does not necessarily have to have both extended portions 32 and 33. Alternatively, the gate layer 30 may have only one of the two extended portions 32 and 33.

[0127] As shown in Figure 24, the gate layer 30 may be omitted. In other words, the nitride semiconductor device 10 may be of the normally-on type. In the first to third embodiments, the electron supply layers 26,110 do not have to be undoped. The electrical resistance of the electron supply layers 26,110 can be arbitrarily changed by adding an n-type donor such as Si.

[0128] As shown in Figure 25, the nitride semiconductor device 10 may include a passivation layer 50 having a source opening 51, a drain opening 52, and a gate opening 53 as a third opening. The passivation layer 50 covers the electron supply layer 26 and both electrodes 42, 44. The gate opening 53 is located between the source opening 51 and the drain opening 52. The gate electrode 40 is in contact with the electron supply layer 26 via the gate opening 53.

[0129] The source opening 51 is located in the passivation layer 50 directly above the source electrode 42, and the source electrode 42 is exposed through the source opening 51. The source opening 51 is formed to be slightly smaller than the source electrode 42 when viewed from above. Therefore, the peripheral edge of the source opening 51 in the passivation layer 50 is positioned on the source electrode 42.

[0130] The drain opening 52 is located directly above the drain electrode 44 in the passivation layer 50, and the drain electrode 44 is exposed through the drain opening 52. The drain opening 52 is formed to be slightly smaller than the drain electrode 44 when viewed from above. Therefore, the peripheral edge of the drain opening 52 in the passivation layer 50 is positioned on the drain electrode 44.

[0131] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments described above. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0132] [Note 1] Electronic transport layer (24), An electron supply layer (26,110) located on the electron transport layer and having a larger band gap than the electron transport layer, A gate electrode (40) located on the electron supply layer, The source electrode (42) in contact with the electron supply layer, The drain electrode (44) in contact with the electron supply layer, Equipped with, The gate electrode is located between the source electrode and the drain electrode, The electron supply layer includes a lower surface (26a, 110a) and an upper surface (26b, 110b), The upper surface is made of a material with a larger band gap than the lower surface. The source electrode and the drain electrode penetrate the upper surface of the electron supply layer and are in contact with the interior of the electron supply layer. Nitride semiconductor equipment.

[0133] [Note 2] The aforementioned electron supply layer is The first electron supply layer (81) including the lower surface, A second electron supply layer (82) including the upper surface, located on the first electron supply layer, and having a larger band gap than the first electron supply layer, Includes, The source electrode and the drain electrode penetrate the second electron supply layer. Nitride semiconductor device as described in Appendix 1.

[0134] [Note 3] The first electron supply layer is composed of an undoped AlGaN layer. The second electron supply layer is composed of an undoped AlGaN layer with a higher Al composition ratio than the first electron supply layer. Nitride semiconductor device as described in Appendix 2.

[0135] [Note 4] The Al composition ratio of the first electron supply layer is greater than 0% and less than or equal to 20%. The Al composition ratio of the second electron supply layer is greater than 20% and less than or equal to 30%. Nitride semiconductor device as described in Appendix 3.

[0136] [Note 5] The difference between the Al composition ratio of the second electron supply layer and the Al composition ratio of the first electron supply layer is 8% or more and 20% or less. Nitride semiconductor device as described in Appendix 3 or Appendix 4.

[0137] [Note 6] The second electron supply layer is thicker than the first electron supply layer. Nitride semiconductor device as described in any one of the appendices 2 to 5.

[0138] [Note 7] The first electron supply layer is thicker than the second electron supply layer. Nitride semiconductor device as described in any one of the appendices 2 to 5.

[0139] [Note 8] The electron supply layer includes an etching stop layer (100) provided between the first electron supply layer and the second electron supply layer. The source electrode and the drain electrode penetrate the second electron supply layer and are in contact with the etching stop layer or the first electron supply layer. Nitride semiconductor device as described in any one of the appendices 2 to 7.

[0140] [Note 9] The etching stop layer is thinner than the first electron supply layer and the second electron supply layer. Nitride semiconductor device as described in Appendix 8.

[0141] [Note 10] The thickness of the etching stop layer is 0.5 nm to 2 nm. Nitride semiconductor device as described in Appendix 9.

[0142] [Note 11] The source electrode and the drain electrode penetrate the second electron supply layer and the etching stop layer and are in contact with the first electron supply layer. Nitride semiconductor device as described in Appendix 8.

[0143] [Note 12] The source electrode and the drain electrode penetrate the second electron supply layer and are in contact with the etching stop layer. Nitride semiconductor device as described in Appendix 8.

[0144] [Note 13] The electron supply layer is composed of an AlGaN layer in which the Al composition ratio increases from the bottom surface to the top surface. Nitride semiconductor device as described in Appendix 1.

[0145] [Note 14] The Al composition ratio of the lower surface is greater than 0% and less than or equal to 20%. The Al composition ratio of the upper surface is greater than 20% and less than or equal to 30%. Nitride semiconductor device as described in Appendix 13.

[0146] [Note 15] The difference between the Al composition ratio of the upper surface and the Al composition ratio of the lower surface is 8% or more and 20% or less. Nitride semiconductor device as described in Appendix 14.

[0147] [Note 16] The lower end surfaces (42a, 44a) of the source electrode and the drain electrode are located between the central position in the thickness direction of the electron supply layer and the lower surface. Nitride semiconductor device as described in any one of the appendices 1 to 15.

[0148] [Note 17] The lower end surfaces (42a, 44a) of the source electrode and the drain electrode are located between the central position in the thickness direction of the electron supply layer and the upper surface. Nitride semiconductor device as described in any one of the appendices 1 to 15.

[0149] [Note 18] The electron supply layer and the gate electrode are covered by a passivation layer which includes a first opening and a second opening. The source electrode is in contact with the electron supply layer through the first opening. The drain electrode is in contact with the electron supply layer through the second opening. The source electrode includes a source overhang (43) provided on the periphery of the first opening on the passivation layer. The drain electrode includes a drain overhang (45) provided on the periphery of the second opening on the passivation layer. Nitride semiconductor device as described in any one of the appendices 1 to 17.

[0150] [Note 19] The gate layer (30) is located between the electron supply layer and the gate electrode and contains acceptor impurities. Nitride semiconductor device as described in any one of the appendices 1 to 18.

[0151] [Note 20] The electron supply layer, the source electrode, and the drain electrode are covered by a passivation layer (50) including a first opening, a second opening, and a third opening. The first opening is provided in the passivation layer directly above the source electrode, and the source electrode is exposed through the first opening. The second opening is provided in the passivation layer directly above the drain electrode, and the drain electrode is exposed through the second opening. The third opening is positioned between the first and second openings, and the gate electrode is in contact with the electron supply layer through the third opening. Nitride semiconductor device as described in any one of the appendices 1 to 18.

[0152] [Note 21] Circuit board (20) and A buffer layer (22) provided on the substrate, Equipped with, The electron transport layer is arranged on the buffer layer, Nitride semiconductor device as described in any one of the appendices 1 to 20.

[0153] [Note 22] The aforementioned buffer layer, AlN layer (22a), A first buffer layer (22b) is stacked on the AlN layer and is composed of an AlGaN layer, A second buffer layer (22c) is stacked on the first buffer layer and is composed of an AlGaN layer having a smaller Al composition ratio than the first buffer layer, A third buffer layer (22d) is stacked on the second buffer layer and is composed of an AlGaN layer having a lower Al composition ratio than the second buffer layer, including, Nitride semiconductor device as described in Appendix 21.

[0154] [Note 23] The substrate is a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, or an AlN substrate. Nitride semiconductor device as described in Appendix 21 or Appendix 22.

[0155] [Note 24] The source electrode and the drain electrode have a Ti / Al or Ti / Al / Ni / Au layered structure. Nitride semiconductor device as described in any one of the appendices 1 to 23.

[0156] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0157] 10. Nitride semiconductor equipment 12…Chip body 20... Circuit board 22... Buffer layer 22a...AlN layer 22b...First buffer layer 22c...Second buffer layer 22d...Third buffer layer 24...Electron transport layer 26,110…electron supply layer 26a, 110a...bottom surface of electron supply layer 26b, 110b... Upper surface of the electron supply layer 28...2DEG 30...Gate layer 40… Gateway 42…Source electrode 43... Sauce overflow portion 44... Drain electrode 45...Drain protrusion 50… Passivation layer 51... Source opening 52...Drain opening 53...Gate opening 60…Field plate electrode 72…Gate wiring 74…Source wiring 76... Drain wiring 81...first electron supply layer 82…Second electron supply layer 100... Etching stop layer D1...First thickness (thickness of the first electron supply layer) D2...Second thickness (thickness of the second electron supply layer) D3...Thickness of the electron supply layer Dx...Thickness of the etching stop layer x1...Al composition ratio of the first electron supply layer x2...Al composition ratio of the second electron supply layer

Claims

1. Electronic transport layer, An electron supply layer located on the electron transport layer and having a larger band gap than the electron transport layer, A gate electrode located on the electron supply layer, The source electrode in contact with the electron supply layer, The drain electrode in contact with the electron supply layer, Equipped with, The gate electrode is located between the source electrode and the drain electrode, The electron supply layer includes a bottom surface and an top surface, The upper surface is made of a material with a larger band gap than the lower surface. The source electrode and the drain electrode penetrate the upper surface of the electron supply layer and are in contact with the interior of the electron supply layer. Nitride semiconductor equipment.

2. The aforementioned electron supply layer is The first electron supply layer including the lower surface, A second electron supply layer, including the upper surface, located on the first electron supply layer and having a larger band gap than the first electron supply layer, Includes, The source electrode and the drain electrode penetrate the second electron supply layer. The nitride semiconductor device according to claim 1.

3. The first electron supply layer is composed of an undoped AlGaN layer. The second electron supply layer is composed of an undoped AlGaN layer with a higher Al composition ratio than the first electron supply layer. The nitride semiconductor device according to claim 2.

4. The Al composition ratio of the first electron supply layer is greater than 0% and less than or equal to 20%. The Al composition ratio of the second electron supply layer is greater than 20% and less than or equal to 30%. The nitride semiconductor device according to claim 3.

5. The difference between the Al composition ratio of the second electron supply layer and the Al composition ratio of the first electron supply layer is 8% or more and 20% or less. The nitride semiconductor device according to claim 4.

6. The second electron supply layer is thicker than the first electron supply layer. The nitride semiconductor device according to claim 2.

7. The first electron supply layer is thicker than the second electron supply layer. The nitride semiconductor device according to claim 2.

8. The electron supply layer includes an etching stop layer provided between the first electron supply layer and the second electron supply layer. The source electrode and the drain electrode penetrate the second electron supply layer and are in contact with the etching stop layer or the first electron supply layer. The nitride semiconductor device according to claim 2.

9. The etching stop layer is thinner than the first electron supply layer and the second electron supply layer. The nitride semiconductor device according to claim 8.

10. The thickness of the etching stop layer is 0.5 nm to 2 nm. The nitride semiconductor device according to claim 9.

11. The source electrode and the drain electrode penetrate the second electron supply layer and the etching stop layer and are in contact with the first electron supply layer. The nitride semiconductor device according to claim 8.

12. The electron supply layer is composed of an AlGaN layer in which the Al composition ratio increases from the bottom surface to the top surface. The nitride semiconductor device according to claim 1.

13. The Al composition ratio of the lower surface is greater than 0% and less than or equal to 20%. The Al composition ratio of the upper surface is greater than 20% and less than or equal to 30%. The nitride semiconductor device according to claim 12.

14. The difference between the Al composition ratio of the upper surface and the Al composition ratio of the lower surface is 8% or more and 20% or less. The nitride semiconductor device according to claim 13.

15. The lower end surfaces of the source electrode and the drain electrode are positioned between the central position in the thickness direction of the electron supply layer and the lower surface. The nitride semiconductor device according to claim 1.

16. The lower end surfaces of the source electrode and the drain electrode are positioned between the central position in the thickness direction of the electron supply layer and the upper surface. The nitride semiconductor device as described in claim 1.

17. The electron supply layer and the gate electrode are covered by a passivation layer which includes a first opening and a second opening. The source electrode is in contact with the electron supply layer through the first opening. The drain electrode is in contact with the electron supply layer through the second opening. The source electrode includes a source overhang provided on the periphery of the first opening on the passivation layer. The drain electrode includes a drain overhang provided on the periphery of the second opening on the passivation layer. The nitride semiconductor device according to claim 1.

18. The gate layer, located between the electron supply layer and the gate electrode, includes an acceptor impurity. The nitride semiconductor device according to claim 1.

19. The electron supply layer, the source electrode, and the drain electrode are covered by a passivation layer including a first opening, a second opening, and a third opening. The first opening is provided in the passivation layer directly above the source electrode, and the source electrode is exposed through the first opening. The second opening is provided in the passivation layer directly above the drain electrode, and the drain electrode is exposed through the second opening. The third opening is positioned between the first opening and the second opening, and the gate electrode is in contact with the electron supply layer through the third opening. The nitride semiconductor device according to claim 1.

20. circuit board and A buffer layer provided on the substrate, Equipped with, The electron transport layer is arranged on the buffer layer, The nitride semiconductor device according to claim 1.

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