Semiconductor devices and methods for manufacturing the same

Abstract

An improved fork-seat FET is provided, which includes a gate extension to address capacitive coupling between the target device channel and the adjacent device gate. [Solution] The semiconductor device according to the present invention comprises a dielectric wall, a first semiconductor layer extending in a first direction perpendicular to the first side of the dielectric wall and having a first end closest to the dielectric wall, and a first gate electrode layer including a first gate extension that extends beyond the first end of the first semiconductor layer and closer to the first side of the dielectric wall.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly, to a forksheet FET device including a gate extension based on a field effect transistor (FET) and a method for manufacturing the same.

Background Art

[0002] A forksheet FET is an advanced variation of the nanosheet architecture, enabling a denser layout by adding a dielectric wall between n-channel metal-oxide-semiconductor (NMOS) devices and p-channel metal-oxide-semiconductor (PMOS) devices, i.e., nFET devices and pFET devices. More specifically, in a forksheet FET, both nFET and pFET devices are integrated within the same structure, and the dielectric wall separates the nFET device from the pFET device. This makes it possible to reduce the n-to-p spacing and enables reduction of area scaling.

[0003] FIG. 1 is a cross-sectional view showing a schematic configuration of a forksheet FET. Referring to FIG. 1, the forksheet FET includes a substrate 100, on which an nFET 101, a dielectric wall 103, and a pFET 102 are formed. As described above, the nFET 101 and the pFET 102 are separated by the dielectric wall 103 in order to reduce the n-to-p spacing and area scaling. The nFET 101 includes a plurality of semiconductor layers (or channels) 104 (i.e., NMOS) extending horizontally (or substantially horizontally) from the dielectric wall 103, and a gate electrode layer 105 surrounding the semiconductor layer 104. The pFET 102 includes a plurality of semiconductor layers (or channels) 106 (i.e., PMOS) extending horizontally (or substantially horizontally) from the dielectric wall 103, and a gate electrode layer 107 surrounding the semiconductor layer 106.

[0004] However, while fork-sheet FETs can offer improvements over other FET devices, such as reduced space between transistors and improved area scaling due to reduced gate-drain capacitance, they still have a problem: capacitive coupling can still occur between the nFET 101 and pFET 102 via the dielectric wall 103, which can lead to degradation of dynamic threshold voltage fluctuations and / or subthreshold swing. [Overview of the project] [Problems that the invention aims to solve]

[0005] The present invention has been made in view of the problems in the conventional fork-seat FETs described above, and the object of the present invention is to provide an improved fork-seat FET that includes a gate extension to address capacitive coupling between the target device channel and the adjacent device gate. Another object of the present invention is to provide a method for manufacturing a fork seat FET including a gate extension. [Means for solving the problem]

[0006] To achieve the above objective, the semiconductor device according to the present invention is characterized by comprising: a dielectric wall; a first semiconductor layer extending in a first direction perpendicular to the first side of the dielectric wall and having a first end closest to the dielectric wall; and a first gate electrode layer including a first gate extension that extends beyond the first end of the first semiconductor layer and closer to the first side of the dielectric wall.

[0007] A method for manufacturing a semiconductor device according to the present invention, made to achieve the above objective, is characterized by comprising the steps of: forming an initial structure including a dielectric wall; a first semiconductor layer in contact with a first side of the dielectric wall and extending in a first direction perpendicular to the first side; and a first gate electrode layer surrounding each side of the first semiconductor layer that is not in contact with the dielectric wall; removing the dielectric wall to form a trench; and removing a portion of the first semiconductor layer exposed in the trench to form a first recess. [Effects of the Invention]

[0008] According to the semiconductor device and its manufacturing method according to the present invention, the gate extension portion of the semiconductor device enhances gate control and shielding by the gate corresponding to the target channel, improves resistance to adjacent gates, and reduces dynamic threshold voltage fluctuations. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the schematic configuration of a fork seat FET. [Figure 2] This is a cross-sectional view showing a schematic configuration of a part of a fork seat FET including a gate extension according to an embodiment of the present invention. [Figure 3] This figure shows an example of a performance comparison of fork seat FETs including gate extensions of different depths according to embodiments of the present invention. [Figure 4] This figure illustrates a method for manufacturing a fork seat FET including a gate extension according to an embodiment of the present invention. [Figure 5] This is a flowchart illustrating a method for manufacturing a fork seat FET including a gate extension according to an embodiment of the present invention. [Figure 6] This block diagram shows a schematic configuration of an electronic system that can implement one or more electronic devices according to embodiments of the present invention. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for carrying out the semiconductor device and manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0011] Note that in drawings, the same reference number may refer to the same element throughout the entire drawing. However, the present invention can be embodied in various forms and should not be construed as being limited only to the embodiments illustrated herein. Rather, these embodiments are provided as examples to fully and completely convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for those skilled in the art to fully understand the aspects and features of the present invention may be omitted from the description.

[0012] In drawings, the relative sizes of elements, layers, and areas may be exaggerated and / or simplified for clarity. In this specification, for the sake of ease of explanation, spatially relative terms such as "beneath," "below," "lower," "under," "above," and "upper" may be used to describe the relationship between one element or feature and another, as shown in the figures. In terms of spatial relative terms, it is intended to include various orientations of the device during use or operation, in addition to the orientation shown in the diagram. For example, if the device in the diagram is turned upside down, elements described as "below," "beneath," or "under" other elements or features will face "up" relative to those other elements or features. Therefore, the terms "below" and "under" used as examples can encompass both upward and downward directions. The device may be in other orientations (for example, rotated 90 degrees or in other orientations), and spatially relative descriptions used herein shall be interpreted accordingly.

[0013] In this specification, terms such as "first", "second", "third", etc. may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, the first element, component, region, layer, or section described below can be referred to as the second element, component, region, layer, or section without departing from the spirit and scope of the present invention. When an element or layer is described as "on", "connected to", or "coupled to" another element or layer, it may be directly positioned, connected, or coupled on, to, or with the other element or layer, or it may be positioned, connected, or coupled through one or more intervening elements or layers. Furthermore, when an element or layer is described as "between" two elements or layers, it may be the only element or layer positioned between the two elements or layers, or it may be present through one or more intervening elements or layers.

[0014] The terms used in this specification are for the purpose of describing particular embodiments and are not intended to limit the present invention. In this specification, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it should be further understood that the terms "comprises", "comprising", "includes" and "including" as used herein identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements when preceding the list of elements, and do not modify the individual elements within the list. The terms "substantially", "about" and similar terms used herein are used as terms indicating approximation and are not used as terms indicating degree, and are intended to take into account the inherent variations in measured or calculated values that can be recognized by those skilled in the art. Furthermore, the term "may" used when describing embodiments of the present invention refers to "one or more embodiments of the present disclosure". As used herein, the terms "use", "using", and "used" may be considered to be synonymous with the terms "utilize", "utilizing", and "utilized", respectively. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0015] The electronic or electrical devices and / or other related devices or components according to embodiments of the present invention described herein can be implemented using appropriate hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware for processing data or digital signals. For example, the various components of these devices may be formed on a single integrated circuit (IC) chip, or they may be formed on separate IC chips. Furthermore, the various components of these devices may be mounted on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a single substrate. Circuit hardware may include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs) configured to execute instructions stored in non-temporary storage media, digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable gate arrays (FPGAs).

[0016] Figure 2 is a cross-sectional view showing a schematic configuration of a part of a fork seat FET including a gate extension according to an embodiment of the present invention. More specifically, Figure 2 shows one side of a fork-seat FET including the gate extension. Referring to Figure 2, the fork-seat FET includes a dielectric wall 203 and an FET 202. FET202 is either an nFET or a pFET.

[0017] The FET 202 includes a plurality of semiconductor layers 204 extending horizontally (or substantially horizontally) from the dielectric wall 203, and a gate electrode layer 205. Each semiconductor layer 204 includes a first end 211 closest to the dielectric wall 203. Furthermore, a dielectric extension portion 212 is provided to separate the semiconductor layer 204 from the dielectric wall 203. The dielectric wall 203 and the dielectric extension 212 may be formed from the same material or from different materials. The FET 202 also includes an interface layer 208 (e.g., silicon oxide (SiOx)) provided on the other side of the semiconductor layer 204, i.e., around the periphery, not on the first end 211, and a high dielectric constant dielectric layer 209 provided on the interface layer 208.

[0018] The gate electrode layer 205 is provided on the dielectric layer 209 (for example, the dielectric layer 209 is placed between the interface layer 208 and the gate electrode layer 205). The gate electrode layer 205 has a depth d and includes a gate extension 213 that extends toward the dielectric wall 203 beyond the first end 211 of the semiconductor layer 204. The gate extension 213 enhances gate control and shielding by the gate corresponding to the target channel, improves resistance to adjacent gates (for example, the gate of the FET located on the opposite side of the dielectric wall 203), and reduces dynamic threshold voltage fluctuations.

[0019] Figure 3 shows an example of a performance comparison of fork seat FETs including gate extensions of different depths according to an embodiment of the present invention. Referring to Figure 3, in scenario (a), if the fork-sheet FET includes a gate extension with a depth d = -1.5 nm (technically, there is no gate because the first edge of the semiconductor layer is closer to the dielectric wall than the gate electrode layer), the normalized measurement of the threshold voltage fluctuation (ΔVtsat) induced by device coupling (DVC) is 1 mV.

[0020] In scenario (b), if the fork-sheet FET includes a gate extension with a depth d=0nm (technically, there is no gate as the first edge of the semiconductor layer and the gate electrode layer are equidistant from the dielectric wall), the normalized measurement of the threshold voltage fluctuation (ΔVtsat) induced by device coupling (DVC) is significantly reduced.

[0021] Furthermore, in scenarios (c), (d), (e), and (f), the fork-sheet FETs include gate extensions with depths d = 1.5 nm, 2.5 nm, 3.5 nm, and 4.5 nm, respectively, and the normalized measurement of the device-coupled (DVC)-induced threshold voltage fluctuation (ΔVtsat) continues to decrease with increasing depth. Therefore, as the depth of the gate extension increases, the measured threshold voltage fluctuation (ΔVtsat) induced by device coupling (DVC) decreases, improving the performance of the fork-seat FET. For example, the difference in normalized measurements of device-coupled voltage (DVC)-induced threshold voltage fluctuation (ΔVtsat) between d=-1.5nm and d=1.5nm is approximately 5 times.

[0022] Figure 3 includes normalized measurements of the threshold voltage fluctuation (ΔVtsat) induced by device coupling (DVC) (DVC ΔVtsat) corresponding to the lengths of each gate extension shown in the figure, but these values ​​are merely examples provided to illustrate the significant reduction in “DVC ΔVtsat”, and the present invention is not limited thereto. For example, the value of "DVC ΔVtsat" can vary not only depending on the length of the gate extension but also on the materials used to manufacture the fork-seat FET.

[0023] Figure 4 is a diagram illustrating a method for manufacturing a fork seat FET including a gate extension according to an embodiment of the present invention. Referring to Figure 4, the fork sheet FET fabricated in (A) includes, for example, an nFET 401 and a pFET 402 separated by a dielectric wall 403, as shown in Figure 1.

[0024] Following this, as shown in (B), the dielectric wall 403 is etched to a predetermined depth to form a trench 405 that exposes the inner edges of the semiconductor layers (406, 407). The initial manufacturing of the fork seat FET in (A) is not directly related to the present invention, and therefore a detailed description thereof is omitted in this specification. For example, the initial manufacturing of the fork seat FET in (A) can be carried out as described in U.S. Patent Publication No. 2024 / 0379409, which is incorporated herein by reference.

[0025] Subsequently, as shown in (C), the semiconductor layers (406, 407) are etched from the trench 405 side to form recesses (408, 409), thereby causing the gate electrode layers (410, 411) to protrude horizontally into the trench 405 beyond the semiconductor layers (406, 407). For example, if we assume that the width of the semiconductor layer (406, 407) in (B) is 25 nm, then the depth of the recess (408, 409) will be 4 nm, and the width of the semiconductor layer (406, 407) in (C) will be 21 nm. The etching depth of the semiconductor layers (406, 407) from the trench 405 side is a factor related to the depth d of the gate extension.

[0026] Subsequently, as shown in (D), the recesses (408, 409) and a portion of the trench 405 are filled with dielectric walls 412 (e.g., silicon dioxide (SiO2), silicon monoxide (SiO)) to form smaller trenches 413. Then, as shown in (E), the smaller trench 413 is filled with another dielectric wall 414 (e.g., silicon nitride (SiN)) to complete the fork-seat FET, including the gate extensions (415, 416).

[0027] Figure 4 shows a two-step process for filling recesses (408, 409) and trench 405 using two different dielectric walls, but the present invention is not limited thereto. For example, the recesses (408, 409) and trench 405 may be filled in one step using a single dielectric wall, or the smaller trench 413 may be filled with a suitable non-dielectric material.

[0028] Figure 5 is a flowchart illustrating a method for manufacturing a fork sheet FET including a gate extension according to an embodiment of the present invention. Referring to Figure 5, in step S501, an initial structure is formed, which includes a dielectric wall, a first semiconductor layer in contact with the first side of the dielectric wall and extending in a first direction perpendicular to that first side, and a first gate electrode layer surrounding each side of the first semiconductor layer that is not in contact with the dielectric wall. As described above, this initial structure may be formed as described in U.S. Patent Publication No. 2024 / 0379409.

[0029] In step S502, the dielectric wall is removed to form a trench. For example, this trench is trench 405 shown in Figure 4(B). In step 503, a portion of the first semiconductor layer exposed in the trench is removed to form the first recess. For example, this recess is the recess 408 shown in Figure 4(C).

[0030] In step 504, the trench and the first recess are filled with at least one dielectric material. For example, this filling is carried out as shown in Figures 4(D) and (E). As described above, the dielectric material in the first recess makes it possible to form a gate extension that extends beyond the first end of the first semiconductor layer near the first side of the dielectric wall.

[0031] Figure 6 is a block diagram showing a schematic configuration of an electronic system that can implement one or more electronic devices according to embodiments of the present invention. Referring to Figure 6, an electronic system 600 according to an embodiment of the present invention may include a microprocessor 610 that performs data communication using a bus 640, a memory 620, and a user interface 630.

[0032] The microprocessor 610 may include a central processing unit (CPU) or an application processor (AP). The electronic system 600 may further include a random access memory (RAM) 650 that communicates with a microprocessor 610. The microprocessor 610 and / or RAM 650 can be implemented in a single module or package.

[0033] The user interface 630 is used for inputting data into the electronic system 600 and outputting data from the electronic system 600. For example, the user interface 630 may include a keyboard, touchpad, touchscreen, mouse, scanner, sound detector, liquid crystal display (LCD), micro-light-emitting device (LED), organic light-emitting diode (OLED) device, active-matrix light-emitting diode (AMOLED) device, printer, lighting, or various other input / output devices, not limited to these. Memory 620 stores the operating code of the microprocessor 610, data processed by the microprocessor 610, or data received from an external device. Memory 620 may include a memory controller, a hard disk, or a solid-state drive (SSD). At least a microprocessor 610, memory 620 and / or RAM 650 within the electronic system 600 include one or more fork-sheet FET structures as described in the embodiments above.

[0034] While the present invention may include details of many specific embodiments, these details should not be interpreted as limitations on the scope of the claimed subject matter, but rather as descriptions of features specific to a particular embodiment. Certain features described in the present invention in the context of a separate embodiment can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any appropriate combination of sub-embodiments in multiple embodiments. Furthermore, as mentioned above, features are described as acting in a specific combination, and even if a patent is initially claimed in this manner, one or more features may be removed from the claimed combination. In such cases, the claimed combination may relate to a subcombination or a variation thereof.

[0035] Similarly, although operations are depicted in a specific order in the drawings, this should not be understood as requiring that such operations be performed in a specific illustrated order or sequential order, or that all illustrated operations be performed, in order to achieve a preferred result. In some situations, multitasking or parallel processing can be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be understood as necessary in all embodiments, and the described program components and systems can generally be integrated in a single software product or packaged in multiple software products.

[0036] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, favorable results can still be obtained by performing the operations described in the claims in a different order. Furthermore, the steps depicted in the attached diagram do not necessarily require the specific order or sequence shown to obtain the desired results. In certain implementations, multitasking and parallel processing can be advantageous. As will be apparent to those skilled in the art, the innovative concepts described herein can be modified and adapted for a wide range of applications. Therefore, the scope of subject matter relating to the claims should not be limited to the specific exemplary teachings described above, but rather defined by the following claims and equivalents. [Explanation of symbols]

[0037] 202 FET 203, 403, 412, 414 Dielectric walls 204, 406, 407 semiconductor layers 205, 410, 411 Token layer 208 Interface layer 209 Dielectric layer 211 First end 212 Dielectric extension Gate extensions 213, 415, 416 401 nFET 402 pFET 405, 413 Trench 408, 409 recess

Claims

1. Semiconductor devices dielectric wall, A first semiconductor layer extending in a first direction perpendicular to the first side of the dielectric wall and having a first end closest to the dielectric wall, A semiconductor device characterized by having a first gate electrode layer including a first gate extension that extends closer to the first side of the dielectric wall beyond the first end of the first semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a first dielectric extension between the first end of the first semiconductor layer and the first side of the dielectric wall.

3. The semiconductor device according to claim 2, characterized in that the first dielectric extension contains silicon dioxide.

4. The semiconductor device according to claim 1, further comprising a first interface dielectric layer surrounding the first semiconductor layer except for the first end portion.

5. The semiconductor device according to claim 4, characterized in that the first interface dielectric layer contains silicon dioxide.

6. The semiconductor device according to claim 4, further comprising a first dielectric layer between the first interface dielectric layer and the first gate electrode layer.

7. A second semiconductor layer extending in a second direction perpendicular to the second side of the dielectric wall and having a first end closest to the dielectric wall, The semiconductor device according to claim 1, further comprising a second gate electrode layer including a second gate extension that extends beyond the first end of the second semiconductor layer to closer to the second side of the dielectric wall.

8. The semiconductor device according to claim 7, further comprising a second dielectric extension between the first end of the second semiconductor layer and the second side of the dielectric wall.

9. The semiconductor device according to claim 7, further comprising a second interface dielectric layer surrounding the second semiconductor layer except for the first end of the second semiconductor layer.

10. The semiconductor device according to claim 9, further comprising a second dielectric layer between the second interface dielectric layer and the second gate electrode layer.

11. A method for manufacturing semiconductor devices, The steps include forming an initial structure comprising: a dielectric wall; a first semiconductor layer in contact with a first side of the dielectric wall and extending in a first direction perpendicular to the first side; and a first gate electrode layer surrounding each side of the first semiconductor layer that is not in contact with the dielectric wall; The steps include removing the dielectric wall to form a trench, A method for manufacturing a semiconductor device, comprising the step of removing a portion of the first semiconductor layer exposed in the trench to form a first recess.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of filling the trench and the first recess with at least one dielectric material.

13. The step of filling the trench and the first recess with at least one dielectric material is: The steps include filling the first recess and a portion of the trench with the first dielectric material, A method for manufacturing a semiconductor device according to claim 12, comprising the step of filling the remaining portion of the trench with a second dielectric material.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that the first dielectric material contains silicon dioxide.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that the second dielectric material contains silicon nitride.

16. The initial structure further includes a second semiconductor layer that contacts the second side of the dielectric wall and extends in a second direction perpendicular to the second side, and a second gate electrode layer that surrounds each side of the second semiconductor layer that is not in contact with the dielectric wall. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of removing a portion of the second semiconductor layer exposed in the trench to form a second recess.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising the step of filling the trench, the first recess, and the second recess with at least one dielectric material.

18. The step of filling the trench, the first recess, and the second recess with at least one dielectric material is: The steps include filling the first recess, the second recess, and a portion of the trench with the first dielectric material, A method for manufacturing a semiconductor device according to claim 17, comprising the step of filling the remaining portion of the trench with a second dielectric material.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that the first dielectric material contains silicon dioxide.

20. The method for manufacturing a semiconductor device according to claim 18, characterized in that the second dielectric material contains silicon nitride.

Images