Semiconductor equipment

Abstract

To provide semiconductor and electronic devices with small circuit area and low power consumption. [Solution] The arithmetic circuit MAC1 is a circuit that performs a sum-of-products operation on a plurality of first data held in a plurality of memory cells described later and a plurality of input second data, and performs an activation function operation using the result of the sum-of-products operation, and comprises a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV. The memory cell array CA comprises memory cells AMx[1] to AMx[m] (where m is an integer of 1 or more), memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMR[1] to AMr[m]. In the memory cell array CA, each memory cell is arranged in a matrix of 2m rows and 2 columns.

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to objects, methods of operation, or methods of manufacture. Or, one aspect of the present invention. This refers to a process, machine, manufacture, or composition of matter. -) is the subject matter. Therefore, one aspect of the present invention disclosed herein is more specifically Technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, and imaging devices. Devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, and their drives Methods, their manufacturing methods, or their testing methods can be cited as examples. [Background technology]

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. The pathway is an electronic circuit that incorporates the brain's structure, and the "neurons" and "s It has a circuit equivalent to a "naps." Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "brain-morphic" or "brain-inspired." The integrated circuit has a non-von Neumann architecture, and its power consumption increases with increasing processing speed. Compared to the larger von Neumann architecture, it performs parallel processing with extremely low power consumption. It is expected to happen.

[0004] Information processing models that mimic neural networks with "neurons" and "synapses" are artificial This is called a neural network (ANN). It uses artificial neural networks. Therefore, it is possible to perform inferences with accuracy comparable to or exceeding that of humans. In networks, the primary operation is the sum-of-products operation, which involves the weighted sum of neuron outputs. That is the case.

[0005] As a circuit that performs multiply-accumulate operations, an OS transistor (also called an oxide semiconductor transistor) is used. In some cases, this may occur.) An invention utilizing a memory cell using this method is described in, for example, Patent Document 1. As shown, an OS transistor has a metal oxide semiconductor in the channel formation region. This refers to an inverter, which has been reported to have extremely low off-current (for example, non-patented). References 1, 2). Furthermore, various semiconductor devices using OS transistors have been fabricated. (For example, Non-Patent Documents 3 and 4). The manufacturing process of OS transistors is different from that of conventional Si transistors. In the CMOS process of DISTAS (transistors in which Si is included in the channel formation region) It can be embedded, and OS transistors can be stacked on Si transistors. For example, see Non-Patent Document 4). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2017-168099 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] When performing a sum-of-accumulate operation in a digital circuit, the digital data that becomes the multiplier (multiplier data) and The multiplication of the digital data that will be the multiplicand (multiplicand data) is performed using a digital multiplication circuit. Subsequently, the digital data (product data) obtained by the multiplication is added using a digital adder circuit. The operation is executed, and digital data (sum-accumulated data) is obtained as a result of the sum-accumulated operation. Multipliers and digital adders are preferably designed to handle multi-bit operations. However, in this case, the respective digital multiplier and digital adder circuits This can lead to larger circuit sizes, resulting in increased circuit area and power consumption for the entire arithmetic circuit. There is a risk of this happening.

[0009] In addition to sum-of-products operations, artificial neural networks also perform activation function calculations. If the activation function calculation is performed using a digital circuit, as mentioned above, the number of calculations required is... This could lead to an increase in the overall circuit area and, consequently, an increase in power consumption. Furthermore, it could also affect the sum-of-accumulate operation. If this is performed using analog circuits instead of digital multiplication and digital addition circuits, then Since the calculation result output by the analog circuit is an analog signal, the calculation result is activated To input into a digital circuit that performs calculations using a conversion function, the signal must first be converted from analog to digital. It needs to be converted. Furthermore, the digital circuit calculates the result of the activation function into a digital signal. In order to output it as such, in order to perform a sum-of-accumulate operation again using the calculation result, the analog circuit In order to input it, the digital signal of the calculation result needs to be converted into an analog signal. In particular, in artificial neural networks, sum-of-products operations and activation function calculations are performed repeatedly. Therefore, in circuits that mix analog and digital circuits, digital signals and analog signals Conversion between digital and analog signals is also performed frequently. Therefore, the number of times digital and analog signals are converted is The power consumption of the circuit may also increase.

[0010] One aspect of the present invention provides a semiconductor device capable of performing sum-of-products operations and / or activation function operations. One of the objectives is to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention provides a semiconductor device with low power consumption. One of the tasks is to do the following.

[0011] Alternatively, one aspect of the present invention aims to provide a novel semiconductor device, etc. One aspect of the present invention aims to provide an electronic device having the above-mentioned semiconductor device. ru.

[0012] Furthermore, the problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described below. This is an issue not mentioned in the section. Issues not mentioned in this section can be understood by those skilled in the art through the details. This can be derived from descriptions in documents or drawings, and can be appropriately extracted from these descriptions. It is possible. Furthermore, one aspect of the present invention addresses at least one of the problems listed above and other problems. This invention solves the following problems. One aspect of the present invention addresses the problems listed above, and other problems. You don't need to solve every single problem. [Means for solving the problem]

[0013] (1) One aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a current mirror. A semiconductor device having a circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. Each of the first, second, third, and fourth cells is the first transit. It has a first cell, a second cell, and a capacitor. In the fourth cell and in each of the others, the first terminal of the first transistor is connected to the first terminal of the capacitance. The gate of the second transistor is electrically connected to the second transistor of the first cell. The first terminal is electrically connected to the first wiring, and the second terminal of the first cell's capacitance is connected to the third wiring. They are electrically connected. The first terminal of the second transistor of the second cell is electrically connected to the first wiring. The second terminal of the second cell's capacity is connected to the fourth wire. The first terminal of the second transistor of the third cell is electrically connected to the second wiring, and the capacitance of the third cell is Terminal 2 is electrically connected to the third wiring. Terminal 1 of the second transistor of the fourth cell. The second terminal of the fourth cell's capacitance is electrically connected to the fourth wire. The current mirror circuit is electrically connected to the first wiring and the second wiring. A current mirror circuit has the function of supplying a current to the second wire that corresponds to the potential of the first wire. 1. Data shall be determined according to the difference between the first potential and the second potential, and 2. Data shall be It shall be determined according to the difference between the 3rd potential and the 4th potential. The capacity of the 1st cell is The first terminal has the function of holding a first potential, and the second cell has the capacity of the first terminal of the second cell. It has the function of maintaining two potentials, and the third cell maintains the second potential at the first terminal of the capacitance of the third cell. The fourth cell has the function of maintaining a first potential at the first terminal of the fourth cell's capacitance. When the third potential is input to the third wiring and the fourth potential is input to the fourth wiring, From the amount of current flowing from the Rentmirror circuit to the second wiring, the second transistor of the third cell from the second wiring can be determined. The amount of current flowing through the first terminal of the zista and the first terminal of the second transistor of the fourth cell from the second wiring. The amount of current flowing through the child and the amount of current obtained by subtracting the first data point and the second data point are quantities corresponding to the product of the first data point and the second data point. ru.

[0014] (2) Alternatively, one aspect of the present invention comprises m first cells (where m is an integer of 1 or more) and m second cells. Two cells, m third cells, m fourth cells, a current mirror circuit, and the first wiring, A semiconductor device having a second wire, m third wires, and m fourth wires. Each of the following is: 1st cell, m 2nd cells, m 3rd cells, and m 4th cells. It has a first transistor, a second transistor, and a capacitor. It has m first cells and m In the second cell, m third cells, and m fourth cells, the first transit The first terminal of the transistor is electrically connected to the first terminal of the capacitor and to the gate of the second transistor. The first terminal of the second transistor in each of the m first cells is connected to the first wiring. Connected electrically, the second end of the capacity of the i-th (where i is an integer between 1 and m) first cell The child is electrically connected to the i-th third wire. Each of the m second cells is connected to the second wire. The first terminal of the transistor is electrically connected to the first wiring, and the second capacitance of the i-th second cell The terminal is electrically connected to the i-th fourth wire. The first terminal of the transistor is electrically connected to the second wiring, and the capacitance of the i-th third cell is Terminal 2 is electrically connected to the i-th third wire. The first terminal of the two transistors is electrically connected to the second wiring, and the capacitance of the i-th fourth cell is The second terminal is electrically connected to the i-th fourth wire. The current mirror circuit is the first The current mirror circuit is electrically connected to the first wiring and the second wiring, and responds to the potential of the first wiring. It has the function of passing the current to the second wiring. The i-th third wiring is electrically connected to the i-th wire. In both the first and third cells, the first cell has a first terminal of the capacitance of the first cell. Wα [i] has the function of maintaining the potential, and the third cell has a voltage of V at the first terminal of the capacitance of the third cell. Wβ [ It has the function of maintaining the potential of [i]. It is also electrically connected to the i-th fourth wire. In both the second and fourth cells, the second cell has a V-value at the first terminal of the second cell's capacitance. W β [i] has the function of maintaining the potential, and the fourth cell has V at the first terminal of the capacitance of the fourth cell. Wα It has the function of maintaining the potential of [i]. The i-th third wire has V Xα The potential of [i] is input. Next, connect the i-th wire to the fourth wire V Xβ When the potential of [i] is input, the current mirror circuit From the amount of current flowing through the second wiring, the second transient of each of the m third cells from the second wiring can be calculated. The sum of the currents flowing through the first terminal of the station, and the second currents of each of the m fourth cells from the second wiring. The current obtained by subtracting the sum of the currents flowing through the first terminal of the transistor corresponds to the value of equation (A1). It becomes a quantity.

[0015]

number

[0016] (3) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first electric A current source, a second current source, a subtraction circuit, a first wire, a second wire, a third wire, a fourth wire It is a semiconductor device having a first cell, a second cell, a third cell, a fourth cell, and Each has a first transistor, a second transistor, and a capacitor. The first cell and In the second cell, the third cell, and the fourth cell, the first terminal of the first transistor The child is electrically connected to the first terminal of the capacitor and the gate of the second transistor. The first terminal of the second transistor in cell 1 is electrically connected to the first wiring, and the capacitance of cell 1 The second terminal is electrically connected to the third wiring. The first of the second transistor of the second cell The terminal is electrically connected to the first wiring, and the second terminal of the second cell's capacitance is electrically connected to the fourth wiring. It is connected to the second transistor of the third cell, and the first terminal of the second transistor is electrically connected to the second wiring. The second terminal of the third cell's capacitance is electrically connected to the third wiring. The first terminal of the two transistors is electrically connected to the second wiring, and the second terminal of the capacitance of the fourth cell is connected to the second terminal. It is electrically connected to the fourth wiring. The first current source is electrically connected to the first wiring, The second current source is electrically connected to the second wiring. The current is between 0.9 and 1.1 times the current that the second current source supplies to the second wiring. The first input terminal of the subtraction circuit is electrically connected to the first wiring, and the second input terminal of the subtraction circuit is , is electrically connected to the second wiring. The first data corresponds to the difference between the first potential and the second potential. The second data shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of holding a first potential at the first terminal of the capacitance of the first cell, Cell 2 has the function of holding a second potential at the first terminal of the capacitance of cell 2, and cell 3 has the function of The first terminal of the 3 cells has the function of holding the second potential, and the fourth cell has the capacity of the fourth cell The first terminal has the function of holding the first potential. The third potential is input to the third wiring, and the fourth wiring When a fourth potential is input to the line, the amount of current flowing from the first current source to the first wiring is used to determine the first wiring The amount of current flowing from the wire to the first terminal of the second transistor in the first cell and the second cell. The sum of the two currents is subtracted and the resulting current is input to the first input terminal of the subtraction circuit, and the second current source is connected to the second wiring From the amount of current flowing through it, the second transistors of the second wiring, the third cell, and the fourth cell are determined. The sum of the currents flowing through the first terminal of the subtraction circuit is subtracted from the current amount input to the second input terminal of the subtraction circuit. As a result, a voltage corresponding to the product of the first data and the second data is output from the output terminal of the subtraction circuit. Output.

[0017] (4) One aspect of the present invention comprises m first cells (where m is an integer greater than or equal to 1) and m second cells And, m third cells, m fourth cells, a first current source, a second current source, a subtraction circuit, A semiconductor device having a first wire, a second wire, m third wires, and m fourth wires. There are m first cells, m second cells, m third cells, m fourth cells, Each has a first transistor, a second transistor, and a capacitor. In each of the following: the first cell, m second cells, m third cells, and m fourth cells, The first terminal of the first transistor is connected to the first terminal of the capacitance and the gate of the second transistor. They are electrically connected. The first terminal of the second transistor in each of the m first cells is Electrically connected to one wire, the capacity of the i-th (where i is an integer between 1 and m) first cell The second terminal of each of the m second cells is electrically connected to the i-th third wire. The first terminal of the second transistor is electrically connected to the first wiring, and the i-th second cell The second terminal of the capacitance is electrically connected to the i-th fourth wire. The first terminal of each second transistor is electrically connected to the second wiring, and the i-th third cell The second terminal of the capacitor is electrically connected to the i-th third wiring. Each of the first terminals of the respective second transistors is electrically connected to the second wiring, and the second terminal of the capacitor of the i-th fourth cell is electrically connected to the i-th fourth wiring. The first current source is electrically connected to the first wiring, and the second current source is electrically connected to the second wiring. Note that the amount of current flowing from the first current source through the first wiring is 0.9 times or more and 1.1 times or less the amount of current flowing from the second current source through the second wiring. The first input terminal of the subtraction circuit is electrically connected to the first wiring, and the second input terminal of the subtraction circuit is electrically connected to the second wiring. In each of the first and third cells electrically connected to the i-th third wiring, the first cell has a function of holding the potential of V [i] at the first terminal of the capacitor of the first cell, and the third cell has a function of holding the potential of V [i] at the first terminal of the capacitor of the third cell. In each of the second and fourth cells electrically connected to the i-th fourth wiring, the second cell has a function of holding the potential of V [i] at the first terminal of the capacitor of the second cell, and the fourth cell has a function of holding the potential of V [i] at the first terminal of the capacitor of the fourth cell. When the potential of V [i] is input to the i-th third wiring and the potential of V [i] is input to the i-th fourth wiring, the amount of current obtained by subtracting the sum of the amounts of current flowing from the first wiring to the first terminals of the respective second transistors of the m first cells and the second cell from the amount of current flowing from the first current source through the first wiring is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the second wiring to the m first cells from the amount of current flowing from the second current source through the second wiring is input to the second input terminal of the subtraction circuit. Wα Wα [i] at the first terminal of the capacitor of the first cell, and the third cell has a function of holding the potential of V Wβ Wβ [i] at the first terminal of the capacitor of the third cell. In each of the second and fourth cells electrically connected to the i-th fourth wiring, the second cell has a function of holding the potential of V [i] at the first terminal of the capacitor of the second cell, and the fourth cell has a function of holding the potential of V Wβ Wβ [i] at the first terminal of the capacitor of the second cell, and the fourth cell has a function of holding the potential of V Wα Wα [i] at the first terminal of the capacitor of the fourth cell. When the potential of V Xα [i] is input to the i-th third wiring and the potential of V Xβ Xβ [i] is input to the i-th fourth wiring, the amount of current flowing from the first current source through the first wiring minus the sum of the amounts of current flowing from the first wiring to the first terminals of the respective second transistors of the m first cells and the second cell is input to the first input terminal of the subtraction circuit, and the amount of current flowing from the second current source through the second wiring minus the sum of the amounts of current flowing from the second wiring to the m first cells is input to the second input terminal of the subtraction circuit. The amount of current flowing from the first current source through the first wiring minus the sum of the amounts of current flowing from the first wiring to the first terminals of the respective second transistors of the m first cells and the second cell is input to the first input terminal of the subtraction circuit, and the amount of current flowing from the second current source through the second wiring minus the sum of the amounts of current flowing from the second wiring to the m first cells is input to the second input terminal of the subtraction circuit. The amount of current obtained by subtracting the sum of the amounts of current flowing from the first wiring to the first terminals of the respective second transistors of the m first cells and the second cell from the amount of current flowing from the first current source through the first wiring is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the second wiring to the m first cells from the amount of current flowing from the second current source through the second wiring is input to the second input terminal of the subtraction circuit. The amount of current flowing from the second current source through the second wiring minus the sum of the amounts of current flowing from the second wiring to the m first cells is input to the second input terminal of the subtraction circuit. The sum of the currents flowing through the first terminal of the second transistor in the third and fourth cells is The subtracted current is input to the second input terminal of the subtraction circuit. This then leads to the output terminal of the subtraction circuit. A voltage corresponding to the value of equation (A2) is output.

[0018]

number

[0019] (5) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first distribution A semiconductor device having a wire, a second wiring, and a third wiring. A first cell, a second cell, The third cell and the fourth cell each contain the first transistor and the second transistor, It has a quantity and, in addition, the first cell, the second cell, the third cell, the fourth cell and, each In this configuration, the first terminal of the first transistor is connected to the first terminal of the capacitance and the gateway of the second transistor. The gate of the first transistor is electrically connected to the first wiring. Furthermore, the second wiring connects the second terminal of the first transistor of the first cell to the first terminal of the fourth cell. The second terminal of the transistor is electrically connected to the third wire, and the first transistor of the second cell is electrically connected to the second terminal of the transistor. The second terminal of the transistor and the second terminal of the first transistor of the third cell are electrically connected. ru.

[0020] (6) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first distribution The wire, the second wire, the third wire, the fourth wire, the fifth wire, the sixth wire, the seventh wire, It is a semiconductor device having a first cell, a second cell, a third cell, a fourth cell, Each has a first transistor, a second transistor, and a capacitor. In the second cell, the third cell, and the fourth cell, the first transistor The terminals are electrically connected to the first terminal of the capacitor and the gate of the second transistor. The first terminal of the second transistor of the first cell is electrically connected to the fourth wire, and the capacity of the first cell The second terminal of the quantity is electrically connected to the sixth wire, and the second terminal of the first transistor of the first cell. It is electrically connected to the second wiring, and the gate of the first transistor of the first cell is connected to the first wiring. They are electrically connected. The first terminal of the second transistor of the second cell is electrically connected to the fourth wiring. The second terminal of the second cell's capacitance is connected to the seventh wiring, and the second terminal of the second cell's capacitance is electrically connected to the seventh wiring. The second terminal of transistor 1 is electrically connected to the third wiring, and the first transistor of cell 2 The gate of the transistor is electrically connected to the first wiring. The first of the second transistor of the third cell The terminal is electrically connected to the 5th wire, and the 2nd terminal of the 3rd cell's capacitance is electrically connected to the 6th wire. The second terminal of the first transistor of the third cell is electrically connected to the third wiring, The gate of the first transistor in the third cell is electrically connected to the first wiring. The first terminal of the second transistor is electrically connected to the fifth wiring, and the second capacitance of the fourth cell The terminal is electrically connected to the 7th wire, and the 2nd terminal of the 1st transistor of the 4th cell is connected to the 2nd The gate of the first transistor of the fourth cell is electrically connected to the wiring, and the gate of the first transistor is electrically connected to the first wiring. It is connected.

[0021] (7) Alternatively, in one aspect of the present invention, the configuration in (6) above includes a current mirror circuit. It is preferable that the current mirror circuit is electrically connected to the fourth wiring and the fifth wiring. It is preferable that they are connected. The current mirror circuit corresponds to the potential of the fourth wiring. It has the function of supplying current to the fifth wiring.

[0022] (8) Alternatively, in one aspect of the present invention, in (7) above, the product of the first data and the second data is performed. It is preferable to set it to a result. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data point shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell has the function of The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a capacitance The first terminal of the quantity has the function of holding the second potential, and the fourth cell has the first terminal of the capacity of the fourth cell. It has the function of holding the first potential. The third potential is input to the sixth wire, and the fourth potential is input to the seventh wire. When a position is input, the amount of current flowing from the current mirror circuit to the 5th wire is used to determine the 5th wire. The amount of current flowing from the third cell to the first terminal of the second transistor, and from the fifth wiring to the fourth cell The amount of current flowing through the first terminal of the second transistor and the amount of current obtained by subtracting from the first data and the second data are... It becomes a quantity corresponding to the product with .

[0023] (9) Alternatively, in one aspect of the present invention, in (6) above, a first current source, a second current source, and a subtraction cycle It is preferable to have a configuration that includes a circuit. Furthermore, the first current source is electrically connected to the fourth wiring. Furthermore, it is preferable that the second current source is electrically connected to the fifth wiring. The first input terminal of the circuit is electrically connected to the fourth wire, and the second input terminal of the subtraction circuit is connected to the fifth wire. It is preferable that the wiring is electrically connected. Also, the current that the first current source supplies to the fourth wiring. The quantity is preferably between 0.9 and 1.1 times the amount of current that the second current source supplies to the fifth wiring. It's nice.

[0024] (10) Alternatively, in one aspect of the present invention, in (9) above, the product of the first data and the second data is performed. It is preferable to set it to a result. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data point shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell has the function of The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a capacitance The first terminal of the quantity has the function of holding the second potential, and the fourth cell has the first terminal of the capacity of the fourth cell. It has the function of holding the first potential. The third potential is input to the sixth wire, and the fourth potential is input to the seventh wire. When a position is input, the amount of current flowing from the first current source to the fourth wiring is used to determine the current flowing from the fourth wiring to the first Subtract the sum of the currents flowing through the first terminal of the second transistor in each of the first and second cells. The amount of current is input to the first input terminal of the subtraction circuit, and the current flowing from the second current source to the fifth wiring is also input. From the flow rate, the first terminal of the second transistor in each of the 5th wiring, 3rd cell, and 4th cell. The sum of the currents flowing through the children is subtracted, and the resulting current is input to the second input terminal of the subtraction circuit. Then, a voltage corresponding to the product of the first data and the second data is output from the output terminal of the subtraction circuit. .

[0025] (11) Alternatively, one aspect of the present invention comprises m first cells (where m is an integer of 1 or more) and m second cells. 2 cells, m third cells, m fourth cells, a current mirror circuit, and m first circuits A wire, a second wire, a third wire, a fourth wire, a fifth wire, m wires of a sixth wire, and m wires of a It is a semiconductor device having 7 wirings. It also has m first cells, m second cells, and m Each of the m third cells and m fourth cells contains a first transistor and a second transistor It has a capacity and a number of first cells, m second cells, m third cells, In each of the m fourth cells, the first terminal of the first transistor is the first terminal of the capacitance. The child is electrically connected to the gate of the second transistor. The m first cells are electrically connected to it. The first terminal of each second transistor is electrically connected to the fourth wire, and the i-th (where i is 1 or less) The second terminal of the capacitance of the first cell (which is an integer less than or equal to m) is electrically connected to the i-th sixth wire. Connected, the second terminal of the first transistor of each of the m first cells is connected to the second wiring. They are connected in a linear fashion, and the gate of the first transistor of the i-th first cell is connected to the i-th first wire. They are electrically connected. The first terminal of the second transistor of each of the m second cells is Electrically connected to 4 wires, the second terminal of the i-th second cell's capacitance is connected to the i-th seventh wire. Electrically connected, the second terminal of the first transistor in each of the m second cells is connected to the third Electrically connected to the line, the gate of the first transistor of the i-th second cell is connected to the i-th first The wiring is electrically connected. The first terminal of the second transistor in each of the m third cells. The child is electrically connected to the fifth wiring, and the second terminal of the capacity of the i-th third cell is connected to the i-th Electrically connected to 6 wires, the second terminal of the first transistor of each of the m third cells is The third wire is electrically connected, and the gate of the first transistor of the i-th third cell is i It is electrically connected to the first wiring of the eye. Each of the m fourth cells has a second transistor. The first terminal is electrically connected to the fifth wire, and the second terminal of the i-th fourth cell's capacitance is i The seventh wire is electrically connected to the first transistor of each of the m fourth cells. Terminal 2 is electrically connected to the second wire and the gate of the first transistor of the i-th fourth cell. It is electrically connected to the i-th first wire. Furthermore, the current mirror circuit is connected to the fourth wire. It is electrically connected to the wire and the 5th wire. The current mirror circuit is connected to the 4th wire. It has the function of supplying current to the fifth wiring according to the potential. Also, the i-th sixth wiring is electrically supplied In each of the connected first and third cells, the first cell has a capacity of V at terminal 1 Wα [i] has the function of maintaining the potential, and the third cell has the capacity of the third cell. V at terminal 1 Wβ It has the function of maintaining the potential of [i]. Also, the i-th seventh wire has electrical In each of the second and fourth cells connected to it, the second cell has the capacity of the second cell. V at the first terminal Wβ [i] has the function of maintaining the potential, and the fourth cell has the capacity of the fourth cell V at terminal 1 Wα It has the function of maintaining the potential of [i]. V is connected to the i-th sixth wire. Xα [i A potential of ] is input, and V is applied to the i-th wire (the 7th wire). Xβ When the potential of [i] is input, Carre From the amount of current flowing from the mirror circuit to the fifth wiring, the current flowing from the fifth wiring to m third cells is calculated. The sum of the currents flowing through the first terminal of the second transistor, and the m fourth cells from the fifth wiring. The current obtained by subtracting the sum of the currents flowing through the first terminal of each second transistor is given by equation (A The amount will depend on the value of (3).

[0026]

number

[0027] (12) Alternatively, one aspect of the present invention comprises m first cells (where m is an integer of 1 or more) and m second cells. Two cells, m third cells, m fourth cells, a first current source, a second current source, and a subtraction cycle. A road, m first wirings, second wirings, third wirings, fourth wirings, fifth wirings, and m the This is a semiconductor device having 6 wires and m seventh wires. It also has m first cells and m Each of the m second cells, m third cells, and m fourth cells is a first transient It has a first transistor, a second transistor, and a capacitor. It has m first cells and m second cells. In each of the m third cells and m fourth cells, the first terminal of the first transistor The child is electrically connected to the first terminal of the capacitor and the gate of the second transistor. The first terminal of the second transistor of each of the first cells is electrically connected to the fourth wire. The second terminal of the capacity of the i-th (where i is an integer between 1 and m) first cell is the i-th Electrically connected to the sixth wire, and to the second terminal of the first transistor of each of the m first cells. It is electrically connected to the second wiring, and the gate of the first transistor of the i-th first cell is i It is electrically connected to the first wiring of the m second cells. The first terminal of the terminal is electrically connected to the fourth wiring, and the second terminal of the capacity of the i-th second cell is, The i-th seventh wire is electrically connected, and each of the m second cells has a first transistor. The second terminal is electrically connected to the third wire and is the gateway of the first transistor of the i-th second cell. The first wire is electrically connected to the i-th first wire. Each of the m third cells has a second wire. The first terminal of the transistor is electrically connected to the fifth wire, and the second capacitance of the i-th third cell. The terminal is electrically connected to the i-th sixth wire, and to the first transistor of each of the m third cells. The second terminal of the zista is electrically connected to the third wiring, and the first transistor of the i-th third cell The gate of the first cell is electrically connected to the i-th first wiring. The first terminal of the second transistor is electrically connected to the fifth wire, and the capacity of the i-th fourth cell The second terminal of the quantity is electrically connected to the i-th seventh wire, and each of the m fourth cells The second terminal of one transistor is electrically connected to the second wiring, and the first terminal of the i-th fourth cell The gate of the transistor is electrically connected to the i-th first wire. Furthermore, the first current source The second current source is electrically connected to the fourth wiring, and the second current source is electrically connected to the fifth wiring. Furthermore, the amount of current that the first current source supplies to the fourth wiring is equal to 0 times the amount of current that the second current source supplies to the fifth wiring. It is between 9 times and 1.1 times. Also, the first input terminal of the subtraction circuit is electrically connected to the fourth wire. The second input terminal of the subtraction circuit is electrically connected to the fifth wire. In each of the first and third cells electrically connected to the wiring, the first cell is the V is connected to the first terminal of the capacitance of one cell. Wα [i] has the function of maintaining the potential, and the third cell is the third V at the first terminal of the cell capacitance Wβ It has the function of maintaining the potential of [i]. In each of the second and fourth cells electrically connected to the 7th wiring, the second cell is: V is connected to the first terminal of the capacitance of the second cell. Wβ [i] has the function of maintaining the potential, and the fourth cell is V is connected to the first terminal of the 4-cell capacitance.Wα It has the function of maintaining the potential of [i]. The i-th sixth wire V in the line Xα [i] is input, and V is applied to the i-th wire, the 7th wire. Xβ The potential of [i] is input. By doing so, the amount of current flowing from the first current source to the fourth wiring is used to determine the number of first cells from the fourth wiring. The current obtained by subtracting the sum of the currents flowing through the first terminal of each second transistor in the second cell. The quantity is input to the first input terminal of the subtraction circuit, and the amount of current flowing from the second current source to the fifth wiring is used. From the fifth wiring, to the first terminal of the second transistor of each of the m third cells and the fourth cell The sum of the currents flowing through the circuit minus that sum is input to the second input terminal of the subtraction circuit. As a result, A voltage corresponding to the value of equation (A4) is output from the output terminal of the subtraction circuit.

[0028]

number

[0029] (13) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first cell It comprises a current mirror circuit, a second current mirror circuit, and a third current mirror circuit. It is a semiconductor device. Also, the first cell, the second cell, the third cell, and the fourth cell This has a first transistor, a second transistor, and a capacitor. The first cell and the second In each of the cells, the third cell, and the fourth cell, the first terminal of the first transistor is It is electrically connected to the first terminal of the capacitance and the gate of the second transistor. The gate of the first transistor in the first cell is connected to the gate of the first transistor in the second cell, and the third The gate of the first transistor of the cell and the gate of the first transistor of the fourth cell are electrically connected. It is connected to the second transistor of the first cell. The first terminal of the first current mirror circuit is connected to the second transistor of the first cell. The first terminal of the first current mirror circuit is electrically connected to the second terminal of the fourth cell, and the second terminal of the first current mirror circuit is connected to the second terminal of the fourth cell. It is electrically connected to the first terminal of the transistor. First terminal of the second current mirror circuit It is electrically connected to the first terminal of the second transistor of the third cell, and the second current mirror circuit The second terminal of the circuit is electrically connected to the first terminal of the second transistor of the second cell. The first terminal of the 3-current mirror circuit is electrically connected to the first terminal of the second transistor of the second cell. Connected, the second terminal of the third current mirror circuit is connected to the first terminal of the second transistor of the fourth cell. It is electrically connected to the child. Also, the first current mirror circuit is the first current mirror circuit The current corresponding to the potential of the first terminal of the circuit is transmitted to the first terminal and the second terminal of the first current mirror circuit. It has the function of sending current to the outside. In addition, the second current mirror circuit has the function of sending current to the outside. The current corresponding to the potential of the first terminal of the circuit is transmitted to the first and second terminals of the second current mirror circuit. It has the function of sending current to the outside. In addition, the third current mirror circuit has the function of sending current to the outside. The current corresponding to the potential of the first terminal of the circuit is transmitted to the first and second terminals of the third current mirror circuit. It has the function of flowing from there into the interior.

[0030] (14) Alternatively, in one aspect of the present invention, in (13) above, the second terminal of the capacitance of the first cell is the third The second terminal of the cell's capacitance is electrically connected, and the second terminal of the first transistor of the first cell is, Electrically connected to the second terminal of the first transistor of the fourth cell, and the second terminal of the capacitance of the second cell. However, it is electrically connected to the second terminal of the capacitance of the fourth cell, and the second of the first transistor of the second cell. The terminal is electrically connected to the second terminal of the first transistor of the third cell. This is preferable.

[0031] (15) Alternatively, in one aspect of the present invention, in (14) above, the product of the first data and the second data is performed. It is preferable to have this configuration. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell is The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a function to maintain a second potential at the first terminal of the third cell The first terminal of the capacitance has the function of holding a second potential, and the fourth cell has the first terminal of the capacitance of the fourth cell. The child has the function of holding the first potential. The second terminal of the capacitance of the first cell, and the capacitance of the third cell. A third potential is input to each of the second terminals, and the second terminal of the capacitance of the second cell, and the fourth cell When a fourth potential is input to each of the second terminals of the capacitance, the first current mirror circuit The amount of current flowing from the second terminal to the first terminal of the second transistor of the fourth cell. The current flowing through the third terminal of the third current mirror circuit, and the current obtained by subtracting the first day, are This quantity corresponds to the product of the first and second data points.

[0032] (16) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first cell A current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a fourth current mirror circuit A semiconductor device having a mirror circuit. It also has a first cell, a second cell, and a third cell. Each of the four cells consists of a first transistor, a second transistor, and a capacitor. It has the following in each of the first cell, the second cell, the third cell, and the fourth cell, The first terminal of transistor 1 is connected to the first terminal of the capacitance and to the gate of transistor 2, and electrical current is supplied to it. They are connected precisely. Also, the gate of the first transistor of the first cell is connected to the first transistor of the second cell. The gate of the transistor, the gate of the first transistor of the third cell, and the first transistor of the fourth cell. It is electrically connected to the gate of the zistor. The first terminal of the first current mirror circuit is It is electrically connected to the first terminal of the second transistor of the first cell, and the first current mirror circuit The second terminal is electrically connected to the first terminal of the second transistor of the fourth cell. The first terminal of the Rentmirror circuit is electrically connected to the first terminal of the second transistor of the third cell. The second terminal of the second current mirror circuit receives electrical signals from the first terminal of the third current mirror circuit. They are connected. The second terminal of the third current mirror circuit is connected to the second transistor of the fourth cell. It is electrically connected to the first terminal of the TA. The first terminal of the fourth current mirror circuit is connected to the second SEC. It is electrically connected to the first terminal of the second transistor of the circuit and to the second terminal of the fourth current mirror circuit. The child is electrically connected to the first terminal of the second transistor of the fourth cell. First current The mirror circuit outputs a current corresponding to the potential of the first terminal of the first current mirror circuit. It has the function of sending current to the outside from the first and second terminals of the mirror circuit. The mirror circuit outputs a current corresponding to the potential of the first terminal of the second current mirror circuit to the second current It has the function of supplying current to the outside from the first and second terminals of the mirror circuit. The mirror circuit outputs a current corresponding to the potential of the first terminal of the third current mirror circuit to the third current It has the function of supplying current internally from the first and second terminals of the mirror circuit. Also, the fourth current The mirror circuit outputs a current corresponding to the potential of the first terminal of the fourth current mirror circuit, to the fourth current It has the function of sending current to the outside from the first and second terminals of the mirror circuit.

[0033] (17) Alternatively, in one aspect of the present invention, in (16) above, the second terminal of the capacitance of the first cell is the third The second terminal of the cell's capacitance is electrically connected, and the second terminal of the first transistor of the first cell is, Electrically connected to the second terminal of the first transistor of the fourth cell, and the second terminal of the capacitance of the second cell. It is electrically connected to the second terminal of the capacitance of the fourth cell, and the second of the first transistor of the second cell. The terminal is configured to be electrically connected to the second terminal of the first transistor of the third cell. This is preferable.

[0034] (18) Alternatively, in one aspect of the present invention, in (17) above, the product of the first data and the second data is performed. It is preferable to have this configuration. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell is The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a function to maintain a second potential at the first terminal of the third cell The first terminal of the capacitance has the function of holding a second potential, and the fourth cell has the first terminal of the capacitance of the fourth cell. The child has the function of holding the first potential. The second terminal of the capacitance of the first cell, and the capacitance of the third cell. A third potential is input to each of the second terminals, and the second terminal of the capacitance of the second cell, and the fourth cell When a fourth potential is input to each of the second terminals of the capacitance, the first current mirror circuit The amount of current flowing from the second terminal and the amount of current flowing from the second terminal of the fourth current mirror circuit, From the sum of these, the amount of current flowing to the first terminal of the second transistor of the fourth cell and the third current mirror - The current flowing through the third terminal of the circuit, minus the product of the first data and the second data, is the current obtained by subtracting the product of the first data and the second data. The amount will depend on the situation.

[0035] (19) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first distribution A semiconductor device having a wire, a second wiring, and a third wiring. A first cell, a second cell, The third cell and the fourth cell each contain the first transistor and the second transistor, It has a quantity and, in particular, the capacitances of the second cell and the third cell may have ferroelectric properties. The material is present in each of the first, second, third, and fourth cells. The first terminal of the first transistor is connected to the first terminal of the capacitance and the gate of the second transistor. Electrically connected, the gate of the first transistor is electrically connected to the first wiring. Furthermore, the second wiring connects the second terminal of the first transistor of the first cell to the first transistor of the fourth cell. The second terminal of the transistor is electrically connected to the third wire, and the third wire is connected to the first transistor of the second cell. It is electrically connected to terminal 2 and terminal 2 of the first transistor of the third cell.

[0036] (20) Alternatively, in one aspect of the present invention, in (19) above, the material that may have ferroelectric properties is a hydroxyl oxide. Hunium, zirconium oxide, HfZrO X (Let X be a real number greater than 0.) Tria-stabilized zirconia, barium titanate, PbTiO X Lead zirconate titanate, Barium strontium tannate, strontium titanate, bismuth tantalate It is preferable to have a configuration that includes one or more materials selected from nitrite.

[0037] (twenty one) Alternatively, one aspect of the present invention comprises a first cell, a second cell, a third cell, a fourth cell, and a first distribution The wire, the second wire, the third wire, the fourth wire, the fifth wire, the sixth wire, the seventh wire, It is a semiconductor device having a first cell, a second cell, a third cell, and a fourth cell. This has a first transistor, a second transistor, and a capacitor. In particular, the second cell and The capacity of the third cell and the material having ferroelectric properties. The first cell and the second cell In the third cell and the fourth cell, the first terminal of the first transistor is The first terminal of the capacitor is electrically connected to the gate of the second transistor, and the first of the first cell The second terminal of the transistor is electrically connected to the second wiring. Also, the capacitance of the first cell The second terminal is electrically connected to the sixth wire, and the first terminal of the second transistor of the first cell is The gate of the first transistor of the first cell is electrically connected to the fourth wire, and the gate of the first transistor is electrically connected to the first wire. They are electrically connected. Also, the second terminal of the first transistor of the second cell is electrically connected to the third wiring. The second terminal of the second cell's capacitance is electrically connected to the seventh wiring, and the second cell The first terminal of the second transistor is electrically connected to the fourth wire, and the first transistor of the second cell The gate of the zista is electrically connected to the first wiring. Also, the first transient of the third cell The second terminal of the sta is electrically connected to the third wiring, and the second terminal of the capacitance of the third cell is connected to the sixth wiring. The wire is electrically connected, and the first terminal of the second transistor of the third cell is electrically connected to the fifth wire. The gate of the first transistor in the third cell is electrically connected to the first wiring. Furthermore, the second terminal of the first transistor of the fourth cell is electrically connected to the second wiring, and the fourth The second terminal of the cell's capacitance is electrically connected to the seventh wire, and the second transistor of the fourth cell The first terminal is electrically connected to the fifth wire, and the gate of the first transistor of the fourth cell is It is electrically connected to one wire.

[0038] (twenty two) Alternatively, in one aspect of the present invention, in (21) above, the material that may have ferroelectric properties is a hydroxyl oxide. Hunium, zirconium oxide, HfZrO X (Let X be a real number greater than 0.) Tria-stabilized zirconia, barium titanate, PbTiO X Lead zirconate titanate, Barium strontium tannate, strontium titanate, bismuth tantalate It is preferable to have a configuration that includes one or more materials selected from nitrite.

[0039] (twenty three) Alternatively, in one aspect of the present invention, in (21) or (22) above, the first circuit and the second It is preferable to have a configuration that includes a circuit. In particular, in this configuration, the second wiring is powered to the first circuit. The third wire is electrically connected to the second circuit, and the first circuit is analog-digital. It is preferable to have a configuration in which a conversion circuit is included and the second circuit has a voltage source.

[0040] (twenty four) Alternatively, in one aspect of the present invention, in any one of (21) to (23) above, current It is preferable to have a configuration that includes a mirror circuit. In particular, this configuration is a current mirror circuit The fourth wire and the fifth wire are electrically connected, and the current mirror circuit is at the potential of the fourth wire. It is preferable to have a configuration that has the function of supplying a corresponding current to the fifth wiring.

[0041] (twenty five) Alternatively, in one aspect of the present invention, in (24) above, the product of the first data and the second data is performed. It is preferable to have this configuration. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell is The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a function to maintain a second potential at the first terminal of the third cell The first terminal of the capacitance has the function of holding a second potential, and the fourth cell has the first terminal of the capacitance of the fourth cell. The child has the function of holding the first potential. The third potential is input to the sixth wire, and the fourth potential is input to the seventh wire. When an electric potential is input, the amount of current flowing from the current mirror circuit to the fifth wiring is used to determine the fifth wiring The amount of current flowing from the wire to the first terminal of the second transistor in the third cell, and from the fifth wiring to the fourth cell The amount of current flowing through the first terminal of the second transistor and the amount of current obtained by subtracting from the first data and the second The quantity will be determined by the product of the data.

[0042] (26) Alternatively, in one aspect of the present invention, in (21) or (22) above, a first current source and a second It is preferable to have a configuration that includes a current source and a subtraction circuit. Furthermore, the first current source is the fourth The second current source is electrically connected to the wiring, and it is preferable that the second current source is electrically connected to the fifth wiring. Furthermore, the first input terminal of the subtraction circuit is electrically connected to the fourth wiring, and the second input terminal of the subtraction circuit The input terminal is preferably electrically connected to the fifth wiring. The amount of current flowing through the 4th wire is between 0.9 and 1.1 times the amount of current flowing from the 2nd current source through the 5th wire. It is preferable that this be the case.

[0043] (27) Alternatively, in one aspect of the present invention, in (26) above, the product of the first data and the second data is performed. It is preferable to have this configuration. The first data is determined according to the difference between the first potential and the second potential. Furthermore, the second data shall be determined according to the difference between the third potential and the fourth potential. The first cell has the function of maintaining a first potential at the first terminal of the capacitance of the first cell, and the second cell is The second cell has a function to maintain a second potential at the first terminal of the capacitance, and the third cell has a function to maintain a second potential at the first terminal of the third cell The first terminal of the capacitance has the function of holding a second potential, and the fourth cell has the first terminal of the capacitance of the fourth cell. The child has the function of holding the first potential. The third potential is input to the sixth wire, and the fourth potential is input to the seventh wire. When an electric potential is input, the amount of current flowing from the first current source to the fourth wiring is used to determine the current flowing from the fourth wiring to the fourth Subtract the sum of the currents flowing through the first terminal of the second transistor in each of the first and second cells. The amount of current is input to the first input terminal of the subtraction circuit, and flows from the second current source to the fifth wiring. From the current, the first second transistor of each of the fifth wiring, third cell, and fourth cell is determined. The sum of the currents flowing through the terminals minus this current is input to the second input terminal of the subtraction circuit. Therefore, a voltage corresponding to the product of the first data and the second data is output from the output terminal of the subtraction circuit. ru.

[0044] (28) Alternatively, in one aspect of the present invention, in any one of (1) to (27) above, the first cell and In the second cell, the third cell, and the fourth cell, the first transistor and the second transistor are located. It is preferable that each of the zistas has a configuration in which a metal oxide is present in the channel-forming region. .

[0045] (29) Alternatively, one aspect of the present invention includes any one of the semiconductor devices described in (1) to (28) above, It is an electronic device having a housing.

[0046] In this specification, a semiconductor device is a device that utilizes semiconductor properties. Circuits containing structural elements (transistors, diodes, photodiodes, etc.), and circuits having the same This refers to devices, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, Integrated circuits, chips containing integrated circuits, and electronic components with chips housed in packages are semiconductors. This is an example of a device. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic equipment are also examples. They are semiconductor devices themselves, and may have semiconductor devices.

[0047] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). .

[0048] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more (electrodes, display devices, light-emitting devices, loads, etc.) are connected between X and Y. It is possible to do so. Furthermore, the switch has a function that controls on / off. In other words, the switch can be in a conductive state (on state) or a non-conductive state (off state), and current flows. It has a function to control whether or not to release the fluid.

[0049] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), changes the potential level of the signal Level shifter circuits, etc.), voltage sources, current sources, switching circuits, amplification circuits (signal amplitude or Circuits that can increase the amount of current, etc., operational amplifiers, differential amplifiers, source follower circuits, batteries One or more circuits (such as FA circuits, signal generation circuits, memory circuits, control circuits, etc.) are located between X and Y. It is possible to connect them. For example, if another circuit is placed between X and Y... However, if a signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be considered as such.

[0050] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are directly connected) This includes cases where the elements or other circuits are connected without any intervening elements.

[0051] Also, for example, "X and Y and the source (or first terminal, etc.) and drain of the transistor ( (or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor. (or the first terminal, etc.), the transistor drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor ( The first terminal (or the first terminal, etc.) is electrically connected to X, and the drain (or second terminal) of the transistor is connected to X. The terminals (or other terminals) are electrically connected to Y, and X is the source of the transistor (or the first terminal, etc.). The transistor's drain (or second terminal, etc.), Y, are electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal) (etc.), Y is provided in this connection order. By using a similar method of expression to specify the order of connections in the circuit configuration, Connect the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. By distinguishing between them, the technical scope can be determined. Note that these expressions are just examples. However, it is not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, (This refers to circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0052] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0053] Furthermore, in this specification, etc., "resistive element" refers, for example, to an element having a resistance value higher than 0Ω. It can be a circuit element, wiring, etc. Therefore, in this specification, etc., "resistive element "A wire has resistance, a transistor has current flowing between its source and drain, and a diode This includes components such as coils. Therefore, the term "resistor" is used to mean "resistor". It can be rephrased as terms such as "load" or "region with resistance," and conversely, "resistance," The terms "load" and "region having resistance" can be replaced with terms such as "resistive element." This can be done. As for the resistance value, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably It can be 5 mΩ or more and 5 Ω or less, more preferably 10 mΩ or more and 1 Ω or less. For example, 1Ω or more, 1 × 10 9 It can be less than or equal to Ω.

[0054] Furthermore, in this specification, "capacitive element" refers to, for example, a capacitance value higher than 0F. Circuit elements having, regions of wiring having capacitance values ​​higher than 0F, parasitic capacitance, transistor This can be used as the gate capacity of a zista, etc. Therefore, in this specification, etc., "capacity element" Terms such as "child," "parasitic capacity," and "gate capacity" can be replaced with terms like "capacity." In some cases, this is possible. Conversely, the term "capacitance" is used in the context of "capacitive elements" and "parasitic capacitance." It can sometimes be rephrased as terms such as "gate capacity". Also, the term "capacity" The term "pair of electrodes" is similar to "pair of conductors," "pair of conductive regions," and "pair of regions." This can be rephrased as follows. Note that the capacitance value is, for example, 0.05 fF or higher. It can be set to 10pF or less. Also, for example, it can be set to between 1pF and 10μF. can.

[0055] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain are interchangeable. In some cases, this may be possible. Furthermore, this specification explains the connection relationships of transistors. When doing so, "either the source or the drain" (or the first electrode or the first terminal), "source or drain The notation "Rain's other side" (or second electrode, or second terminal) is used. Depending on the structure of the terminal, it may have a back gate in addition to the three terminals mentioned above. In this specification, etc., one of the gate or back gate of the transistor is referred to as the first gate. The gate is referred to as the "gate," and the other of the transistor's gate or back gate is referred to as the "second gate." Furthermore, in the same transistor, the terms "gate" and "back gate" are interchangeable. In some cases, they can be swapped. Also, a transistor has 3 or more gates. In this specification, the gates are referred to as the first gate, the second gate, the third gate, etc. It is sometimes referred to as "to," etc.

[0056] For example, in this specification, an example of a transistor is one with two or more gate electrodes. A multi-gate transistor can be used. With a multi-gate structure, Because the channel formation regions are connected in series, the structure is such that multiple transistors are connected in series. Therefore, the multi-gate structure reduces off-current and improves the transistor's breakdown voltage (trust). (Improved reliability) can be achieved. Alternatively, the multi-gate structure can be used to operate in the saturation region. When this happens, even if the voltage between the drain and source changes, the current between the drain and source remains constant. A voltage-current characteristic with little change and a flat slope can be obtained. By utilizing the voltage-current characteristics, an ideal current source circuit or a very high resistance value can be created. This enables the realization of an active load. As a result, a differential circuit or current mirror with good characteristics can be achieved. - Circuits and other features can be implemented.

[0057] Furthermore, even if a single circuit element is shown in the circuit diagram, if there are multiple such circuit elements... It may have circuit elements. For example, if one resistor is shown on the circuit diagram This includes cases where two or more resistors are electrically connected in series. Also, for example... If only one capacitor is shown on the circuit diagram, it means that two or more capacitors are electrically connected in parallel. This includes cases where a single transistor is shown on the circuit diagram. If so, two or more transistors are electrically connected in series, and each This includes cases where the gates of transistors are electrically connected to each other. For example, if one switch is shown on the circuit diagram, then if there are two or more of those switches... Having the above transistor, two or more transistors are electrically connected in series or parallel. This includes the case where the gates of each transistor are electrically connected to each other. .

[0058] Furthermore, in this specification, etc., a node is defined as having terminals, distribution, etc., depending on the circuit configuration, device structure, etc. These can be rephrased as wire, electrode, conductive layer, conductor, impurity region, etc. Also, terminal, Wiring and other components can be referred to as nodes.

[0059] Furthermore, in this specification and other documents, "voltage" and "potential" may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential. For example, if the reference potential is ground... If we consider it as the ground potential, then "voltage" can be replaced with "potential." Round potential does not necessarily mean 0V. Also, potential is relative. The potential applied to the wiring, the potential applied to the circuit, etc., changes as the reference potential changes. The electric potential, including the potential output from circuits, also changes.

[0060] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" are used to mean "specifically" This does not mean that the potential is high. For example, in two wires, both are at a "high-level potential". If it is stated that it functions as a wiring that supplies the respective High-level potentials do not have to be equal to each other. Similarly, in two wires, both If both are described as "functioning as wiring that supplies a low level potential", then both wiring The low-level potentials provided by each do not necessarily have to be equal.

[0061] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction), for example, "electricity of a positively charged body." The statement "conduction is occurring" means "electrical conduction of a negatively charged body is occurring in the opposite direction." This can be rephrased as follows. Therefore, in this specification, the term "electric current" is not used unless otherwise specified. In this context, it refers to the phenomenon of charge transfer associated with carrier movement (electrical conduction). Carriers include electrons, holes, anions, cations, complex ions, etc., which are involved in the flow of electric current. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a line, etc., is defined as the direction in which the positively charged carriers move, and the amount of positive current is... This will be described as follows. In other words, the direction in which negatively charged carriers move is opposite to the direction of the current. It is in the direction and is expressed as a negative current quantity. Therefore, in this specification, the positive and negative (or If there is no mention of the direction of the current, a statement such as "current flows from element A to element B" is not acceptable. This can be rephrased as, "Current flows from element B to element A," etc. Descriptions such as "current is input to element A" should be rephrased as "current is output from element A." It shall be possible.

[0062] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0063] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. In some cases, positional relationships are used for convenience in explaining them by referring to diagrams. The relative positions of the elements change appropriately depending on the direction in which each element is depicted. Therefore, The terminology is not limited to what is explained in the detailed document, etc., and can be appropriately rephrased depending on the situation. For example, However, in the expression "insulator located on the upper surface of the conductor," the orientation of the diagram shown should be rotated 180 degrees. By rephrasing it, it can be described as "an insulator located on the underside of a conductor."

[0064] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly below. It does not necessarily mean that they are in contact. For example, the expression "electrode B on insulating layer A" Therefore, it is not necessary for electrode B to be directly in contact with insulating layer A, and insulating layer A and electrode B This does not exclude cases that include other components between them.

[0065] Furthermore, in this specification, terms such as "membrane" and "layer" may be interchanged depending on the context. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". It may be possible to change the terminology to this. Or, depending on the circumstances, or depending on the situation. Therefore, it is possible to replace terms such as "membrane" and "layer" with other terms without using them. For example, changing the term "conductive layer" or "conductive film" to the term "conductor" It may be possible. Or, for example, the terms "insulating layer" and "insulating film" could be changed to "insulator". It may be possible to change the terminology to this.

[0066] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not functionally limit the elements. For example, "electrode" is used as part of "wiring". This can happen, and vice versa. Furthermore, the terms "electrode" or "wiring" are, This also includes cases where multiple "electrodes," "wirings," etc., are formed as a single unit. For example, the term "terminal" can be used as part of "wiring," "electrode," etc., and vice versa. The same applies. Furthermore, the term "terminal" can refer to multiple things such as "electrode," "wiring," and "terminal." This also includes cases where they are formed as a single unit. For example, "electrode" is "wiring" or It can be part of a "terminal," and for example, a "terminal" can be a "wire" or an "electrode." It can be a part of it. Also, terms such as "electrode," "wiring," and "terminal" may be used depending on the context. This can sometimes be replaced with terms like "domain" or "area."

[0067] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. Therefore, or depending on the situation, they can be interchanged. For example, "wiring" In some cases, it is possible to change the term "signal line" to "signal line". Also, for example In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" are changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" should be changed to terms such as "signal lines." It is sometimes possible to do so. Conversely, terms like "signal line" can also be used for "power line." In some cases, it may be possible to change the terminology to terms such as the "potential" applied to the wiring. Depending on the situation, the term "signal" may be changed to a different term such as "traffic light." In some cases, this is possible. Conversely, terms like "signal" and "electric potential" are also possible. It may be possible to change the terminology.

[0068] In this specification, semiconductor impurities refer to, for example, components other than the main components that constitute the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. For example, the defect level density of the semiconductor increases, and carrier mobility decreases. In some cases, crystallinity may decrease. Examples of impurities that alter the properties of the body include Group 1 elements, Group 2 elements, and Group 13 elements. These include Group 14 elements, Group 15 elements, and transition metals other than the main component, and in particular, for example, hydrogen. (Also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, impurities that change the properties of the semiconductor exist. Examples include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, etc. (However, (It does not contain oxygen or hydrogen.)

[0069] In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows. One example is... Electrical switches, mechanical switches, etc. can be used. In other words, switches are Any device capable of controlling the current will suffice; it is not limited to any specific device.

[0070] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... For example, if the source and drain electrodes of a transistor are electrically short-circuited... This refers to a state in which current can flow between the source electrode and the drain electrode. Furthermore, the "non-conductive state" of a transistor refers to the state where the source and drain electrodes of the transistor are not conducting. This refers to a state in which the circuit can be considered electrically blocked. Note that a transistor is not simply a switch. When operating in this manner, the polarity (conductivity type) of the transistor is not particularly limited.

[0071] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There is a switch that uses STEMS technology. This switch is mechanically operated It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes.

[0072] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" or "approximately parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. It refers to a state in which two lines are aligned at an angle of 80° to 100°. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° to 120°. This refers to a state of being in a certain condition. [Effects of the Invention]

[0073] According to one aspect of the present invention, a semiconductor device capable of performing sum-of-products operations and / or activation function operations. It is possible to provide a semiconductor device with low power consumption according to one aspect of the present invention. It can be provided.

[0074] Alternatively, according to one aspect of the present invention, a novel semiconductor device, etc., can be provided. According to one aspect of the present invention, an electronic device having the above-mentioned semiconductor device can be provided.

[0075] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described below. This is an effect not mentioned in the item. An effect not mentioned in this item would be apparent to someone skilled in the art in the details. This can be derived from descriptions in documents or drawings, and can be appropriately extracted from these descriptions. It is possible. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the following effects. Therefore, in some cases, one aspect of the present invention may have the above-listed effects. It may not always be effective. [Brief explanation of the drawing]

[0076] [Figure 1] Figure 1 is a block diagram showing an example of a semiconductor device. [Figure 2] Figure 2 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 3]Figures 3A and 3B are circuit diagrams showing example configurations of circuits included in a semiconductor device. [Figure 4] Figures 4A to 4C are circuit diagrams showing example configurations of circuits included in a semiconductor device. [Figure 5] Figures 5A to 5C are circuit diagrams showing example configurations of circuits included in semiconductor devices. [Figure 6] Figure 6 is a circuit diagram showing an example of a semiconductor device. [Figure 7] Figure 7 is a timing chart showing an example of the operation of a semiconductor device. [Figure 8] Figure 8 is a block diagram showing an example of a semiconductor device. [Figure 9] Figure 9 is a block diagram showing an example of the circuit configuration included in a semiconductor device. [Figure 10] Figure 10 is a block diagram showing an example of a semiconductor device. [Figure 11] Figure 11 is a block diagram showing an example of a semiconductor device. [Figure 12] Figure 12 is a block diagram showing an example of a semiconductor device. [Figure 13] Figure 13 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 14] Figure 14 is a circuit diagram showing an example of a semiconductor device. [Figure 15] Figure 15 is a timing chart showing an example of the operation of a semiconductor device. [Figure 16] Figure 16 is a block diagram showing an example of a semiconductor device. [Figure 17] Figure 17 is a block diagram showing an example of a semiconductor device. [Figure 18] Figure 18 is a block diagram showing an example of a semiconductor device. [Figure 19] Figure 19 is a block diagram showing an example of a semiconductor device. [Figure 20] Figure 20 is a block diagram showing an example of a semiconductor device. [Figure 21]Figure 21 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 22] Figure 22 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 23] Figure 23 is a block diagram showing an example of the circuit configuration included in a semiconductor device. [Figure 24] Figure 24 is a timing chart showing an example of the operation of a semiconductor device. [Figure 25] Figure 25 is a timing chart showing an example of the operation of a semiconductor device. [Figure 26] Figure 26 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 27] Figure 27 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 28] Figure 28 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 29] Figure 29 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 30] Figure 30 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 31] Figures 31A and 31B illustrate a hierarchical neural network. [Figure 32] Figure 32 is a block diagram showing an example configuration of a semiconductor device. [Figure 33] Figure 33 is a block diagram showing an example configuration of a semiconductor device. [Figure 34] Figure 34 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 35] Figures 35A to 35C are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 36] Figure 36 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 37] Figures 37A and 37B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 38]Figure 38 is a schematic cross-sectional diagram showing an example of a transistor configuration. [Figure 39] Figure 39A illustrates the classification of IGZO crystal structures, Figure 39B illustrates the XRD spectrum of crystalline IGZO, and Figure 39C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 40] Figure 40A is a perspective view showing an example of a semiconductor wafer, Figure 40B is a perspective view showing an example of a chip, and Figures 40C and 40D are perspective views showing examples of electronic components. [Figure 41] Figure 41 is a schematic diagram showing an example of an electronic device. [Figure 42] Figures 42A to 42C are schematic diagrams showing an example of an electronic device. [Modes for carrying out the invention]

[0077] In artificial neural networks (hereinafter referred to as neural networks): The synaptic connection strength is determined by providing existing information to the neural network. It can change. In this way, by giving existing information to a neural network, The process of determining the overall strength is sometimes referred to as "learning."

[0078] Furthermore, for a neural network that has undergone "learning" (where connection strengths have been defined), By providing that information, new information can be output based on the bond strength. Thus, in a neural network, based on the given information and connection strength... The process of outputting new information is sometimes referred to as "inference" or "cognition."

[0079] Examples of neural network models include the Hopfield type and the hierarchical type. One example is a multi-layered neural network called a "deep neural network." It is called a "deep neural network" (DNN), and machine learning using deep neural networks is called It is sometimes referred to as "deep learning."

[0080] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into categories such as: For example, metal oxides are included in the channel formation region of transistors. In some cases, the metal oxide in question may be referred to as an oxide semiconductor. In other words, the metal oxide is amplified. A transistor channel having at least one of the following functions: action, rectification, and switching. If a region can be formed, the metal oxide is a metal oxide semiconductor (metal oxide It can be called IDE semiconductor. Also, OS Transigs When referred to as "transistor," it can be rephrased as a transistor having a metal oxide or oxide semiconductor. It is possible.

[0081] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It can be called tal oxynitride.

[0082] Furthermore, in this specification, the configurations shown in each embodiment are different from the configurations shown in other embodiments. By combining them as appropriate, one embodiment of the present invention can be formed. If multiple configuration examples are provided, it is possible to combine them as appropriate.

[0083] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0084] Furthermore, the contents described in each embodiment (or example) refer to the following: This refers to content described using various diagrams or text included in the specification. be.

[0085] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0086] Embodiments described herein will be explained with reference to the drawings. However, implementation may be difficult. The form can be implemented in many different ways, and it does not deviate from the purpose and scope. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the form of application, the same reference numeral is used for identical parts or parts having similar functions. In some cases, explanations of repetitions used across different drawings may be omitted. Also, perspective drawings. In some cases, the description of certain components may be omitted in order to ensure clarity in the drawings. be.

[0087] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted and written. Also, in drawings, etc., the symbols “_1”, “[n]”, “[ If identification codes such as "m, n" are attached, there is no need to distinguish them in this specification, etc. In some cases, the identification code may not be included.

[0088] Furthermore, in the drawings of this specification, the size, thickness of the layers, or the area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are for reference only. This is a schematic representation of a hypothetical example and is not limited to the shapes or values ​​shown in the drawing. This can be due to variations in signals, voltages, or currents caused by noise, or to timing discrepancies. This can include variations in signals, voltages, or currents.

[0089] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention is used for multiply-accumulate operations and function operations, An example of a arithmetic circuit capable of this will be described.

[0090] <Example 1 of semiconductor device configuration> Figure 1 shows the configuration of a semiconductor device capable of performing sum-of-accumulate operations with multiple first data and multiple second data. An example is shown.

[0091] The MAC1 arithmetic circuit shown in Figure 1 is an example of an arithmetic circuit configuration capable of multiply-accumulate operations and function calculations. This shows that the arithmetic circuit MAC1 holds multiple first memory cells, which will be described later. Perform a sum-of-products operation on the data and multiple input second data, and the result of the sum-of-products operation This is a circuit that performs activation function calculations using multiple first data points and multiple second data points. The data can be analog data or multi-level data (discrete data), for example. It is possible to group multiple first data points together and refer to them as the first data points of the first group, etc. This can happen. Similarly, multiple second data sets can be combined into a second group of second data sets, and so on. It is sometimes referred to as such.

[0092] The arithmetic circuit MAC1, as an example, consists of a memory cell array CA, a circuit CMS, and a circuit WD. It has circuits D, XLD, WLD, INT, and ACTV.

[0093] The memory cell array CA consists of memory cells AMx[1] to AMx[m] (m is It is an integer greater than or equal to 1.) and memory cell AMw[1] to memory cell AMw[m], Morisel AMu[1] or memory cell AMu[m] and memory cell AMr[1] or memo It contains Ricell AMr[m] and

[0094] In this specification, memory cell AMx[1] to memory cell AMx[m] are defined as circuits. The memory cells AMu[1] to AMu[m] are included in the CSX and are connected to the circuit CSU. The memory cells AMw[1] to AMw[m] are included in the circuit CSW, Memory cell AMr[1] or memory cell AMr[m] is included in the circuit CSR. This is sometimes used as an explanation.

[0095] In the memory cell array CA, each memory cell is arranged in a 2m x 2 matrix. It is located in the memory cell AMx[1] to AMx[m]. Located at addresses from row 1, column 1 to row m, column 1 of the recell array CA, memory cell AMw [1] The memory cell AMw[m] is in the m+1 row 1 to 2m row of the memory cell array CA. The memory cells AMu[1] to AMu[m] are located at addresses up to one row. The memory cells are located at addresses from row 1, column 2 to row m, column 2 of the memory cell array CA. AMr[1] or memory cell AMr[m] is located in the m+1 row and 2 columns of the memory cell array CA. It is located at an address up to 2m x 2 columns.

[0096] The memory cells AMx, AMw, AMu, and AMR Each has the function of holding the voltage corresponding to the first data. Voltage is, for example, the voltage held in memory cell AMu[i] and memory cell AMw[i] The voltage, the voltage held in memory cell AMx[i], and memory cell AMr[i], It can be treated as a difference.

[0097] Memory cell AMx[1] is connected to wiring WAD, wiring BAL, wiring WAL[1], and wiring XAL[1] is electrically connected to the wiring W. Also, the memory cell AMx[m] is connected to the wiring W. AD is electrically connected to wiring BAL, wiring WAL[m], and wiring XAL[m]. Furthermore, the memory cell AMw[1] is connected to wiring WAD, wiring BAL, and wiring WBL[ It is electrically connected to wiring XBL[1] and memory cell AMw[m ] is wiring WAD, wiring BAL, wiring WBL[m], wiring XBL[m], and electrical They are connected. Also, the memory cell AMu[1] is connected to wiring WBD and wiring BBL, It is electrically connected to wiring WAL[1] and wiring XAL[1]. Also, memory AMu[m] is the wiring WBD, wiring BBL, wiring WAL[m], and wiring XAL[m]. ] is electrically connected to and . In addition, the memory cell AMr[1] is connected to the wiring WBD and It is electrically connected to wire BBL, wiring WBL[1], and wiring XBL[1]. Furthermore, the memory cell AMr[m] is connected to wiring WBD, wiring BBL, wiring WBL[m], and It is electrically connected to line XBL[m].

[0098] Memory cell AMx[1] to memory cell AMx[m] and memory cell AMw[1] to Memory cell AMw[m], memory cell AMu[1], and memory cell AMu[m], Examples of detailed circuit configurations for each of the following: Morissel AMr[1] or memory cell AMr[m]. This will be discussed later.

[0099] Circuit CMS is electrically connected, for example, to wiring BAL and wiring BBL. The circuit CMS is routed from the BAL to the memory cell AMx[1] to the memory cell AMx[m]. and the device that supplies current to each of the memory cells AMw[1] to AMw[m] The function, and the wiring BBL to memory cell AMu[1] to memory cell AMu[m], and memory It has the function of supplying current to each of the cells AMr[1] to memory cells AMr[m]. The circuit CMS determines the amount of current flowing through wiring BAL and the current flowing through wiring BBL. The quantities should preferably be equal. Specifically, the amount of current flowing through wiring BAL should be equal to the amount flowing through wiring BBL. It is preferable that the current flowing is 0.85 times or more, 0.9 times or more, or 0.95 times or more. Furthermore, it is preferable that the ratio is 1.05 times or less, 1.1 times or less, or 1.15 times or less. The lower and upper limits mentioned above can be combined in any way.

[0100] Specific examples of circuit CMS configurations will be discussed later.

[0101] Circuit WDD is electrically connected, for example, to wiring WAD and wiring WBD. The circuit WDD is for storing in each memory cell of the memory cell array CA It has the function of transmitting data. For example, circuit WDD is a wiring WAD and wiring WBD. The first data or reference data can be sent to each as the relevant data.

[0102] Circuit WLD includes, for example, wiring WAL[1] to wiring WAL[m] and wiring WBL [1] or is electrically connected to wiring WBL[m]. Circuit WLD is a memory cell array When writing data to the memory cells of the CA, the memory cells that will be used as the destination for writing the data... It has the function to select memory cells A of memory cell array CA. Specifically, for example, memory cell A Data is stored in Mx[i] (where i is an integer between 1 and m, inclusive) and in the memory cell AMu[i]. When writing, circuit WLD applies a high-level potential to wiring WAL[i], and wiring W Wiring other than AL[i], WAL[1] to WAL[m], and wiring WBL[1] to By applying a low-level potential to the line WBL[m], memory cell A, which is the destination for data writing, is created. You can select Mx[i] and memory cell AMu[i]. Also, for example, memo Write data to the memory cells AMw[i] and AMR[i] of the recell array CA. When loading, circuit WLD applies a high-level potential to wiring WBL[i], and wiring WAL [1] or wiring WAL[m], and wiring WBL[1] or wiring WBL[i] other than wiring WBL[1] or wiring W By applying a low-level potential to BL[m], the memory cell AMw becomes the destination for data writing. [i] and memory cell AMr[i] can be selected.

[0103] Circuit XLD includes, for example, wiring XAL[1] to wiring XAL[m] and wiring XBL [1] or wiring XBL[m] is electrically connected. Circuit XLD is connected to the first data. The second data for multiplication is placed in each memory cell of the memory cell array CA. It has the function of transmitting. Specifically, for example, circuit XLD is wiring XAL[1] or wiring Apply the potential corresponding to the second data to XAL[m] and wiring XBL[1] to wiring XBL[m]. It can be given.

[0104] Circuit INT is electrically connected, for example, to wiring BAL and wiring BBL. Circuit INT has the function of inputting a predetermined voltage to, for example, wiring BAL and wiring BBL. It possesses. The voltage in question can be, for example, a low-level potential or ground potential. .

[0105] As a specific example of configuration, circuit INT has circuit SCI, and circuit SCI has switch S It has W5A and switch SW5B. The first terminal of switch SW5A is connected to wiring BAL The second terminal of switch SW5A is electrically connected to the wiring VSL. Also, the first terminal of switch SW5B is electrically connected to wiring BBL, and the switch The second terminal of SW5B is electrically connected to the wiring VSL. Also, switch SW5A The control terminals of the switch SW5B are electrically connected to wiring SL5. .

[0106] Switches SW5A and SW5B are, for example, analog switches, transistors Electrical switches such as the TA can be applied. Alternatively, switch SW5A and the SUI For example, a mechanical switch may be used as switch SW5B. When transistors are applied to W5A and switch SW5B, the transistors are O S transistors, or transistors containing Si in the channel formation region (hereinafter referred to as Si transistors) It can be called Zista.

[0107] In this embodiment, switch SW5A and switch SW5B are controlled It turns ON when a high-level potential is input to the terminal, and turns ON when a low-level potential is input. It will be assumed that it will be turned off at this time.

[0108] Wiring SL5, for example, can be used to check the continuity and non-continuity of switches SW5A and SW5B. It functions as wiring that supplies voltage to switch between conductive and non-conductive states. The voltage can be, for example, a high-level potential or a low-level potential.

[0109] Furthermore, the VSL wiring functions, for example, as wiring that provides a constant voltage. For example, this could be a low-level potential or ground potential.

[0110] Circuit ACTV is electrically connected, for example, to wiring BAL and wiring NIL. Circuit ACTV is, for example, a voltage corresponding to the amount of current flowing from wiring BAL to circuit ACTV. A function that outputs a voltage and a function that uses that voltage to perform calculations according to a predefined set of functions. It has the ability to perform the operation of the function and the ability to output the result of the operation of the function to the NIL wiring.

[0111] In particular, in the ACTV circuit, the function system in question could be, for example, the sigmoid function, tangent function, etc. Use functions such as the h function, softmax function, ReLU function (ramp function), and threshold function. These functions can also be used, for example, in activation in neural networks. It can be applied as a function.

[0112] <<Example configuration of memory cell array CA>> Next, memory cells AMx[1] to memory cell A included in memory cell array CA Mx[m], memory cell AMu[1], <memory cell AMu[m], memory cell AMw[ 1] to memory cell AMw[m], and memory cell AMr[1] to memory cell AMr[ Let's explain an example of the configuration of [m].

[0113] Figure 2 is a circuit diagram showing an example configuration of a memory cell array CA. It has the function of calculating the sum of products of multiple first data points and multiple second data points.

[0114] In the memory cell array CA shown in Figure 2, memory cell AMx, memory cell AMu, Each of the Morisel AMw and memory cell AMr is connected to transistor M1 and transistor It has a capacity M2 and a capacity C1.

[0115] Also, memory cell AMx, memory cell AMu, memory cell AMw, and memory cell AM It is preferable that the sizes of the transistors M1 included in each of r are equal. Furthermore, memory cells AMx, AMu, AMw, and AMR It is preferable that the size of the transistor M2 contained in each of them is equal to that of the others.

[0116] By making the sizes of the transistors equal to each other, the power of each transistor The air characteristics can be made nearly identical. Therefore, the AMx memory cell and the AMu memory cell... Transistor M1 contained in each of the memory cell AMw and memory cell AMr The sizes of the memory cells AMx, AMu, AMw, and By making the size of the transistor M2 contained in each memory cell AMr equal By means of, memory cell AMx, memory cell AMu, memory cell AMw, and memory cell Each of the AMr can perform almost the same operation under identical conditions. Yes, it is possible. Here, the same conditions refer to, for example, the source, drain, and gateway of transistor M1. Potential of the source, drain, and gate of transistor M2, memory cell A Inputs are entered into each of the following memory cells: Mx, memory cell AMu, memory cell AMw, and memory cell AMR. This refers to the voltage, etc.

[0117] Unless otherwise specified, transistor M1 functions as a switching element. This includes the case where the gate, source, and drain of transistor M1 are This is when the appropriate voltage is input within the range in which transistor M1 operates as a switching element. This includes cases where such a thing is happening. However, one aspect of the present invention is not limited thereto. For example, Transistor M1 can operate in the saturation region or the linear region when it is ON. Alternatively, in order to reduce the amount of current flowing through transistor M1, transistor M1 is configured as follows: It can operate in the subthreshold region. Alternatively, transistor M1 operates in the linear region. When operating in the saturation region, when operating in the subthreshold region And, can coexist. Alternatively, transistor M1 may operate in the linear region, It is possible for operation to occur in the saturation region and for other conditions to occur simultaneously, or for operation to occur in the saturation region and other conditions to occur. It can operate in the subthreshold region, or a mixture of both, or in the linear region. It is possible to have a mix of cases where the system is created and cases where it operates in the subthreshold region.

[0118] In this specification, the subthreshold region refers to the gate voltage of the transistor. In the graph showing the (Vg)-drain current (Id) characteristics, the gate voltage is equal to the threshold voltage. This refers to the region below a certain threshold. Alternatively, the subthreshold region is a gradient channel approximation. (A model that only considers drift current) is deviating from this model, where current flows due to carrier diffusion. This refers to a region, or subthreshold region, where the drain voltage is affected by an increase in gate voltage. This refers to the region where the flow increases exponentially. Alternatively, the subthreshold region is defined by the various theories mentioned above. This includes areas that can be considered part of the Ming Dynasty's domain.

[0119] Furthermore, the drain current when a transistor operates in the subthreshold region is subth This is called the threshold current. The subthreshold current is independent of the drain voltage and depends on the gate voltage. It increases exponentially with respect to pressure. In circuit operation using subthreshold current, Dre This can reduce the impact of variations in input voltage.

[0120] Furthermore, unless otherwise specified, transistor M2 operates in the saturation region when it is ON. This includes the case where the gate and saw of each of the transistors mentioned above are... The S and Drain should be properly supplied with voltages within the range that allow them to operate in the saturation region. This shall include, however, the present invention is not limited thereto. Fluctuation of the supplied voltage To reduce the width, transistor M2 can operate in the linear region. Or Therefore, in order to reduce the amount of current flowing through transistor M2, transistor M2 is a subthread It can operate in the sköld region. Alternatively, transistor M2 operates in the linear region. There are cases where it operates in the saturation region and cases where it operates in the subthreshold region, and these are mixed together. It is possible. Alternatively, transistor M2 operates in the linear region and in the saturation region. It is possible for it to operate in one state and for it to operate in another. Alternatively, transistor M2 may operate in the saturation region. It is possible for both operation in the subthreshold region and operation in the subthreshold region to coexist.

[0121] Furthermore, it is preferable that transistor M1 is an OS transistor. The channel-forming region of ZISTA M1 contains at least one of indium, gallium, and zinc. It is more preferable that an oxide is present. Alternatively, the channel formation region of transistor M1. Indium, element M (for example, aluminum, yttrium, copper, Vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium Molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, Alternatively, one or more selected from magnesium, etc., may be mentioned. ), zinc is low. It may also be an oxide containing 1. Furthermore, transistor M1 is as described in Embodiment 5. It is even more preferable that the transistor has a specific structure.

[0122] By using an OS transistor as transistor M1, the transistor M1 Because leakage current can be suppressed, it is sometimes possible to realize a multiply-accumulate circuit with high calculation accuracy. Yes. Also, by using an OS transistor as transistor M1, the transistor When st. M1 is in a non-conductive state, the holding node (for example, node Nx[1] described later, no Node Nx[m], Node Nu[1], Node Nu[m], Node Nw[1], Node Nw[ Write word lines (e.g., wiring) from node Nr[1], node Nr[m], etc. The leakage current to the WAD (wiring WBD) can be made very small. In other words, the holding current This reduces the refresh operation of the potential of the circuit, thus reducing the power consumption of the sum-of-accumulate circuit. This can be reduced.

[0123] Furthermore, by using an OS transistor for transistor M2, Since it can be fabricated at the same time as M1, the fabrication process for the multiply-accumulate circuit can be shortened. In some cases, this may be the case. Also, transistor M2 is a Si transistor, not an OS transistor. This is also acceptable. As for silicon, for example, amorphous silicon (hydrogenated amorphous silicon) (Sometimes referred to as "silicon"), microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, etc. It is possible.

[0124] Note that when the gate voltage of an OS transistor is less than the transistor's threshold voltage... , 1 x 10 -20 Less than A, 1 × 10 -22 Less than A, or 1 × 10 -24 Less than A It has a drain current per 1 μm of channel width. Also, the OS transistor has a gate voltage When this is the threshold voltage of the transistor, 1.0 × 10 -8 A or less, 1.0×10 -12 A The following, or 1.0 × 10 -15 Drain current per 1 μm of channel width, such as A or less. A current flows. In other words, the OS transistor operates in the subthreshold region. A wide voltage range can be used. Specifically, the threshold voltage of the OS transistor can be set to V th In that case, in the subthreshold region, (V th -1.0V) or more V th below, or (V th -0.5V) or more V th Circuit operation using gate voltages within the following voltage range: It is possible to do so.

[0125] On the other hand, Si transistors have a large off-current and operate in the subthreshold region. The gate voltage range is narrow. When using subthreshold current, the OS transistor is This allows for circuit operation over a wider gate voltage range than Si transistors.

[0126] In Figure 2, transistors M1 and M2 have back gates. The connection configuration of the back gate is not shown in the diagram, but the power of the back gate The destination of the air connection can be determined during the design phase. For example, a traffic light with a back gate. In a transistor, the gate and back gate are used to increase the on-current of the transistor. They may be electrically connected. That is, for example, the gate and back gate of transistor M1. The gate and back gate of transistor M2 may be electrically connected, or the gate and back gate of transistor M2 may be connected. They may be electrically connected. Also, for example, in a transistor having a back gate, To vary the threshold voltage of that transistor, or the off-current of that transistor To reduce the noise, the back gate of the transistor is electrically connected to external circuits, etc. Wiring is provided for this purpose, and the back gate of the transistor is controlled by the external circuit. A configuration that applies an electric potential may also be used.

[0127] Furthermore, transistors M1 and M2 shown in Figure 2 are back gates. Although it has such features, a semiconductor device according to one aspect of the present invention is not limited thereto. For example, Figure 2 shows Transistors M1 and M2 shown in the diagram are designed to not have a back gate. It may also be configured as a single-gate transistor. The ZISTA has a configuration that includes a back gate, and some other transistors also have a back gate. It is also acceptable to have a configuration that does not include a T.

[0128] Furthermore, transistors M1 and M2 shown in Figure 2 are n-channel type Although referred to as a transistor, the semiconductor device according to one aspect of the present invention is not limited to this. For example... If transistor M1 and part or all of transistor M2 are p-channel type transistors You can replace it with "sta".

[0129] Note that the above examples of changes to the structure and polarity of transistors are shown for transistor M1 and It is not limited to transistor M2. For example, transistor M3A, which will be discussed later, M3B, and furthermore, transistors, switches, circuits, etc. as described elsewhere in the specification. The same applies to transistors included in this diagram, as well as transistors illustrated in other diagrams. It appears that way.

[0130] The memory cells AMx, AMu, AMw, and AMR In each case, the first terminal of transistor M1 is electrically connected to the gate of transistor M2. They are connected. The first terminal of transistor M2 is electrically connected to the wiring VR. The first terminal of capacitor C1 is electrically connected to the gate of transistor M2.

[0131] In each of the memory cells AMx[1] to AMx[m], the transient The second terminal of transistor M1 is electrically connected to wiring WAD, and the second terminal of transistor M2 is It is electrically connected to the wiring BAL. Also, in the memory cell AMx[i], The gate of Zistor M1 is electrically connected to wiring WAL[i], and the second terminal of capacitance C1 is, It is electrically connected to wiring XAL[i]. Furthermore, in memory cell AMx[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nx[1], and in memory cell AMx[m], The electrical connections between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is denoted as node Nx[m].

[0132] In each of the cell memory AMu[1] to cell memory AMu[m], the transient The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 is connected to the wiring WBD. It is electrically connected to the wiring BBL. Also, in the memory cell AMu[i], The gate of Zistor M1 is electrically connected to wiring WAL[i], and the second terminal of capacitance C1 is, It is electrically connected to wiring XAL[i]. Note that in memory cell AMu[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nu[1], and in the memory cell AMu[m], The electrical connections between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is designated as node Nu[m].

[0133] In each of the cell memory AMw[1] to cell memory AMw[m], the transient The second terminal of transistor M1 is electrically connected to wiring WAD, and the second terminal of transistor M2 is It is electrically connected to the wiring BAL. Also, in the memory cell AMw[i], The gate of Zistor M1 is electrically connected to wiring WBL[i], and the second terminal of capacitor C1 is, It is electrically connected to wiring XBL[i]. Furthermore, in memory cell AMw[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nw[1], and in memory cell AMw[m], The electrical connections between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is designated as node Nw[m].

[0134] In each of the cell memory AMr[1] to cell memory AMr[m], the transient The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 is connected to the wiring WBD. It is electrically connected to the wiring BBL. Also, in the memory cell AMr[i], The gate of Zistor M1 is electrically connected to wiring WBL[i], and the second terminal of capacitor C1 is, It is electrically connected to wiring XBL[i]. Note that in memory cell AMr[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nr[1], and in the memory cell AMr[m], The electrical connections between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is denoted as node Nr[m].

[0135] The above nodes Nx[1], Nx[m], Nu[1], and Nu[m] Nodes Nw[1], Nw[m], Nr[1], and Nr[m] are, It functions as a holding node for each memory cell.

[0136] Wiring VR is used for memory cells AMx, AMu, AMw, and memory cells. Wiring for allowing current to flow between the first and second terminals of each transistor M2 in AMR. Therefore, the VR wiring functions as a wire for supplying a predetermined potential. In this embodiment, the potential supplied by the wiring VR is, for example, a low-level potential, a ground potential, or a contact The potential can be lower than the ground potential. By the way, the multiple wirings V shown in Figure 2 Each of R can be wired identically to each other, or they can be wired differently to each other. This can be done. Alternatively, some of the multiple wiring VRs shown in Figure 2 can be made to be the same wiring, The remaining wiring can be different. In particular, all or part of multiple wiring VRs can be different. In the case of this type of wiring, different potentials can be applied to each different wire. In other words, see Figure 13. Each of the multiple wiring VRs shown in the diagram can be given the same potential, or different potentials. It is possible to apply a certain electrical potential.

[0137] <<Example of Circuit CMS Configuration>> Next, we will describe an example of a circuit CMS configuration.

[0138] Figure 3A shows an example of a circuit configuration that can be applied to the circuit CMS in Figure 1, and the circuit C in Figure 3A MS has a circuit CM. Furthermore, the circuit CM is a p-channel transistor. Transistor M3A, transistor M3B, switch SW7A, switch SW7B , has.

[0139] The first terminal of transistor M3A is electrically connected to the first terminal of switch SW7A. The second terminal of transistor M3A is electrically connected to wiring VHE. Switch SW The second terminal of 7A is electrically connected to wiring BAL. Also, transistor M3B The first terminal is connected to the first terminal of switch SW7B, the gate of transistor M3A, and the transistor The gate of transistor M3B is electrically connected to the second terminal of transistor M3B, and the wiring V It is electrically connected to HE. The second terminal of switch SW7B is electrically connected to wiring BBL. They are connected. Also, the control terminals of switch SW7A and switch SW7B. It is electrically connected to wiring SL7.

[0140] Furthermore, transistors M3A and M3B each have a channel formation region. This is a transistor that contains silicon (hereinafter referred to as a Si transistor). Preferably, the silicon included in the channel-forming region is, for example, amorphous silicon. Silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon This can be made of materials such as silicon or single-crystal silicon.

[0141] Furthermore, transistors M3A and M3B are used in the following contexts, unless otherwise specified. The combination includes the case where it operates in the saturation region when it is ON. That is, as described above. Each transistor's gate, source, and drain have a range of operation in the saturation region. This includes cases where the voltage is appropriately input. However, one aspect of the present invention is this Not limited to, in order to reduce the amplitude value of the supplied voltage, transistor M3A, and Transistor M3B can operate in the linear region. Alternatively, transistor M3A , and in order to reduce the amount of current flowing through transistor M3B, transistor M3A, Transistor M3B can operate in the subthreshold region. Or, The M3A and M3B transistors operate in both the linear and saturation regions. It is possible for situations to be mixed, such as when it operates in the subthreshold region, or when it operates in the subthreshold region. It is possible for operation in the linear region and operation in the saturation region to coexist, or A mixture of operation in the saturation region and operation in the subthreshold region. This is possible, or it can be done in the linear region and in the subthreshold region. They can coexist.

[0142] Furthermore, as for switches SW7A and SW7B, for example, switch SW5A , and a switch applicable to switch SW5B can be used. Also, in this implementation form In this state, each of switch SW7A and switch SW7B has a high-level current connected to its control terminal. It turns on when a voltage is input and turns off when a low-level potential is input. It shall be considered as such.

[0143] Wiring VHE functions, for example, as wiring that provides a constant voltage. For example, it is preferable to set a high potential.

[0144] Furthermore, wiring SL7 is used, for example, to ensure continuity between switches SW7A and SW7B. It functions as wiring that supplies voltage to switch between a conductive and a non-conductive state. The voltage in question can be, for example, a high-level potential or a low-level potential.

[0145] The circuit CM shown in Figure 3A functions as a current mirror circuit based on the configuration described above. Specifically, the circuit CM in Figure 3A controls the potential of the first terminal (wiring BBL) of transistor M3B. Refer to the current corresponding to the potential, and then output the current to transistors M3A and M3B. It has the function of flowing between each source and drain. In other words, the circuit CMS has the function of transient A current approximately equal to the current flowing between the source and drain of transistor M3B is passed through transistor M It has the function of flowing 3A between the source and drain.

[0146] Furthermore, the configuration of the circuit CMS is not limited to the configuration shown in Figure 3A. For example, as shown in the circuit CMS in Figure 3B, transistors M3A and M4A The transistors M3B and M4B were connected in a cascode configuration. This configuration is also possible. Specifically, the first terminal of transistor M3A is connected to transistor M4A. The first terminal of transistor M3A is electrically connected, and the second terminal of transistor M3A is electrically connected to the wiring VHE. It is connected to the first terminal of transistor M3B. The terminal, the gate of transistor M3A, and the gate of transistor M3B are electrically connected. The second terminal of transistor M3B is electrically connected to wiring VHE. The second terminal of transistor M4A is electrically connected to wiring BAL. The second terminal of B is connected to the wiring BBL, the gate of transistor M4A, and transistor M4B. The gate is electrically connected to the circuit CMS shown in Figure 3B, and the circuit CM is included By connecting the transistors in a cascode configuration, a current mirror is created using a CM circuit. This can make the circuit's operation more stable.

[0147] Furthermore, in the circuit CMS shown in Figure 3A, the first terminal of transistor M3A is connected via switch SW7A. The wiring is then electrically connected to BAL, and the first terminal of transistor M3B is connected to switch SW7. The configuration is such that it is electrically connected to wiring BBL via B, but switch SW7 The electrical connection location between A and switch SW7B is not limited to this. For example, the rotation shown in Figure 3A. In circuit CMS, the second terminal of transistor M3A is connected to wiring VHE via switch SW7A. It can be configured to be electrically connected (not shown), and / or a transistor The second terminal of the M3B is electrically connected to the wiring VHE via the switch SW7B. The configuration can be as shown (not illustrated). Also, the circuit CMS in Figure 3B is transistor M The second terminal of 4A is electrically connected to wiring BAL via switch SW7A, and the transient The second terminal of the M4B is electrically connected to the BBL wiring via the SW7B switch. Although the configuration is as described, the electrical connection points of switch SW7A and switch SW7B are as follows: It is not limited to this. For example, in the circuit CMS in Figure 3B, the second terminal of transistor M3A is The configuration can be configured to be electrically connected to the wiring VHE via switch SW7A. Alternatively, the first terminal of transistor M3A is connected to transistor M4A via switch SW7A. The first terminal can be electrically connected to the first terminal. Also, for example, Figure 3B In circuit CMS, the second terminal of transistor M3B is connected to the wiring VHE via switch SW7B. It can be configured to be electrically connected to the first terminal of transistor M3B, or This is electrically connected to the first terminal of transistor M4B via switch SW7B. This configuration is possible. As described above, in Figures 3A and 3B, switch SW7 A. The electrical connection location of switch SW7B can be freely determined during the design phase. Therefore, in one embodiment of the present invention, the electrical The connection location is not particularly limited.

[0148] <<Example of ACTV circuit configuration>> Next, we will explain an example configuration of the ACTV circuit that can be applied to the MAC1 arithmetic circuit. do.

[0149] Figure 4A is a circuit diagram showing an example configuration of the ACTV circuit. The ACTV circuit is an example , has circuit ACP, circuit ACP is connected to circuit IVC, circuit ACF, and switch SW4A , has.

[0150] The first terminal of switch SW4A is electrically connected to wiring BAL, and the switch SW4A The second terminal is electrically connected to the first terminal of circuit IVC, and the second terminal of circuit IVC is connected to the circuit It is electrically connected to the first terminal of ACF. The second terminal of circuit ACF is electrically connected to wiring NIL. They are electrically connected. Also, the control terminal of switch SW4A is electrically connected to wiring SL4. It continues. In the second embodiment described later, the wiring BAL is replaced with the wiring BAN. It explains.

[0151] The IVC circuit has a function that outputs a voltage to the second terminal corresponding to the amount of current input to the first terminal. It possesses this function. In other words, the IVC circuit functions as a current-voltage conversion circuit.

[0152] The ACF circuit performs calculations according to a defined set of functions based on the voltage input to the first terminal. The function to be performed and the result of the calculation of the function system are output to the second terminal (wiring NIL) of the circuit ACF. It has a function. Examples of such function systems include the sigmoid function, the tanh function, and soft Examples include the Tomax function, ReLU function (ramp function), and threshold function.

[0153] Switch SW4A can be applied to, for example, switches SW5A and SW5B. You can use the available switches.

[0154] Wiring SL4, as an example, switches between the conductive and non-conductive states of switch SW4A. It functions as wiring that supplies the voltage necessary for the operation. Therefore, the voltage in question is, for example, The potential can be set to a high level or a low level.

[0155] Next, we will describe a specific example of the IVC circuit configuration. The ACTV circuit shown in Figure 4B is: The circuit configuration applicable to circuit ACTV in Figure 4A is shown in Figure 4B, and the specific circuit IVC is shown in Figure 4B. An example configuration is shown. In Figure 4B, the circuit IVC consists of an operational amplifier OP and a load LEA. , has. The inverting input terminal of the operational amplifier OP is connected to the first terminal of the circuit IVC and the load LEA. The first terminal is electrically connected to the second terminal of the load LEA, and the output terminal of the op-amp OP is connected to the second terminal of the load LEA. It is electrically connected to the second terminal of the circuit IVC. Also, the non-reverse of the operational amplifier OP The input terminal is electrically connected to the VRPL wiring. Note that the op-amp OP is non-inverting. The connection between the input terminal and the wiring VRPL is assumed to be via the third terminal of circuit IVC.

[0156] The load LEA can be, for example, a resistor, a diode, or a transistor.

[0157] Wiring VRPL functions, for example, as wiring that provides a constant voltage. This can be, for example, the ground potential or the low-level potential.

[0158] In particular, by setting the potential supplied by the wiring VRPL to the ground potential, the non-inverting input of the op-amp OP is controlled. The ground potential is input to the power terminal. Also, the inverting input terminal of the operational amplifier OP is connected to the load LEA. It is electrically connected to the output terminal of the op-amp OP via (a negative feedback connection configuration). Therefore, the potential of the inverting input terminal of the operational amplifier OP can be considered as virtual ground. .

[0159] In addition, the circuit configuration that can be applied to the ACTV circuit in Figure 4A is the circuit configuration in Figure 4B, as well as other circuit configurations. This can be the circuit ACTV shown in Figure 4C. Note that the circuit ACP shown in Figure 4C is a circuit In addition to the IVC and the ACF circuit, it also has a current source CCS. In Figure 4C, the IVC circuit is It has an operational amplifier OP, a load LEA, and a load LEB. The inverting input of the operational amplifier OP The power terminal is electrically connected to the first terminal of the circuit IVC and the first terminal of the load LEA. The output terminal of the p-amp OP is connected to the second terminal of the load LEA and the second terminal of the circuit IVC. They are connected precisely. Also, the non-inverting input terminal of the op-amp OP is connected to the output terminal of the current source CCS. The child is electrically connected to the first terminal of the load LEB, and the input terminal of the current source CCS is wired. The second terminal of the load LEB is electrically connected to the wiring VSSL, and the second terminal of the load LEB is electrically connected to the wiring VSSL. The connection between the non-inverting input terminal of the operational amplifier OP and the output terminal of the current source CCS is It is assumed that this is done via the third terminal of the circuit IVC.

[0160] For the load LEB, it is preferable to use the same circuit elements as the load LEA.

[0161] Wiring VDL functions, for example, as wiring that provides a constant voltage. For example, it can be set to a high-level potential.

[0162] Wiring VSSL functions, for example, as wiring that provides a constant voltage. This can be, for example, the ground potential or the low-level potential.

[0163] The circuit IVC shown in Figure 4C functions as a subtraction circuit. Specifically, it runs from the wiring BAL. The amount of current flowing through the first terminal of circuit IVC and the output terminal of the current source CCS to the third terminal of circuit IVC. The voltage corresponding to the difference between the amount of current flowing through the terminal and the second terminal of the circuit IVC is output to the second terminal of the circuit IVC. Yes, it is possible. Also, if the circuit IVC functions as a subtraction circuit, the load L included in the circuit IVC is... Preferably, EA and load LEB each have equal resistance values.

[0164] Furthermore, the current flowing from the output terminal of the current source CCS to the third terminal of the circuit IVC is set to 0A (current is (It can be said that no current flows) and the potential of the third terminal of circuit IVC is the wiring V in Figure 4B. When the potential supplied by RPL is the same, the ACTV circuit in Figure 4C is the same as the ACTV circuit in Figure 4B. This is equivalent to:

[0165] Next, we will describe a specific example of the ACF circuit configuration. Figure 5A shows the ACT circuit from Figure 4A. A circuit configuration applicable to V, and Figure 5A shows a specific example of the ACF circuit configuration. In Figure 5A, the circuit ACF is a p-channel transistor, transistor M5 It has a switch SW4F and the first terminal of transistor M5 is the first terminal of circuit ACF. The terminals are electrically connected, and the second terminal of transistor M5 is connected to the first terminal of switch SW4F. The second terminal of switch SW4F is electrically connected to the second terminal of circuit ACF. They are connected. Also, the gate of transistor M5 is electrically connected to wiring VBA. The control terminal of switch SW4F is electrically connected to wiring SL4.

[0166] Wiring VBA can function, for example, as wiring that provides an arbitrary constant voltage.

[0167] Switch SW4F can be applied to, for example, switches SW5A and SW5B. A switch can be used. Also, the control terminal of switch SW4F is connected to wiring SL4. Because they are electrically connected, switch SW4F is ON in sync with switch SW4A. It is possible to switch between the active and off states.

[0168] Transistor M5 acts as a pass transistor between wiring BAL and wiring NIL. It works. Also, the voltage output from the second terminal of transistor M5 is... The voltage input to the first terminal and the voltage applied to the gate of transistor M5, Therefore, it is determined. Here, the voltage at the first terminal of transistor M5 is V A Transistor M The voltage applied to gate 5 (the voltage applied by wiring VBA) is V BIASTrans The threshold voltage of the M5 is V th Let's consider the case where V A ga V BIAS +V th In the above case, transistor M5 outputs approximately V to the second terminal. A It outputs V. A ga V BI AS +V th When the voltage is less than V, transistor M5 outputs approximately V to the second terminal. BIAS +V th Leave To exert force. In other words, the voltage output to the second terminal of transistor M5 is the voltage of transistor M5. The voltage of the first terminal is used as the input value, and this is considered the result of the calculation of the ReLU function (ramp function). It is possible.

[0169] Furthermore, other circuit configurations that can be applied to the ACTV circuit ACF in Figure 4A include, for example, The circuit ACTV shown in Figure 5B can be converted to circuit ACF. The ACF has a comparator CMP. Specifically, the first terminal of the comparator CMP is connected to the circuit ACF. The first terminal of the comparator CMP is electrically connected, and the second terminal of the comparator CMP is electrically connected to the wiring VBA. The output terminal of the comparator CMP is electrically connected to the second terminal of the circuit ACF.

[0170] The wiring VBA here provides a voltage to be compared to the potential of the first terminal of comparator CMP. It functions as wiring. Therefore, the voltage can be any constant voltage.

[0171] By applying the circuit ACTV of Figure 5B to the circuit ACTV of the arithmetic circuit MAC1, Circuit ACF in 5B is the voltage supplied from circuit IVC and the voltage supplied by wiring VBA, Depending on the magnitude, a low-level potential or a high-level potential (binary digital signal) is applied to the NIL wiring. It can output. In other words, in the circuit ACF of Figure 5B, the second terminal of the circuit ACF can output. The output voltage is a step function (ramp function) with the voltage at the first terminal of the ACF circuit as the input value. It can be considered as the result of the operation )

[0172] Furthermore, other circuit configurations that can be applied to the ACTV circuit ACF in Figure 4A include, for example, The circuit ACTV shown in Figure 5C can be converted to circuit ACF. The ACF has an analog-to-digital conversion circuit (ADC). Specifically, it has an analog-to-digital conversion circuit (ADC). The input terminal of the ADC circuit is electrically connected to the first terminal of the ACF circuit, and the analog-to-digital The output terminal of the ADC converter is electrically connected to the second terminal of the ACF converter. The circuit ACF in Figure 5C converts the analog voltage at the first terminal of the circuit ACF into a digital value. The output is then sent to the second terminal of the ACF circuit. Note that the ACTV circuit in Figure 5C When applied to the ACTV circuit in Figure 4A, the wiring N electrically connected to the ACTV circuit It is preferable that the number of ILs (Input Levels) be provided in proportion to the number of bits.

[0173] <Example of operation of the arithmetic circuit> Next, we will explain an example of the operation of the MAC1 arithmetic circuit.

[0174] Furthermore, the arithmetic circuit MAC1 here, as shown in Figure 6, is the memory cell array CA The memory cell array CA shown in Figure 2 was applied, and the circuit CMS shown in Figure 3A was applied as the circuit CMS. Let's call the arithmetic circuit MAC1A. Note that the arithmetic circuit MAC1A shown in Figure 6 mainly consists of memory cells. The following are excerpts showing the ray CA, circuit CMS, circuit XLD, circuit WLD, and circuit INT. It is. Also, although not shown in the diagram, the circuit ACTV of the arithmetic circuit MAC1A in Figure 6 is The circuit ACTV shown in Figure 4A is applied.

[0175] Figure 7 shows a timing chart of an example of the operation of the arithmetic circuit MAC1A. The chart shows wiring WAL[1], wiring between time T01 and time T13, and in the vicinity thereof. WAL[m], Wiring WBL[1], Wiring WBL[m], Wiring SL4, Wiring SL5, Wiring S L7, wiring WAD, wiring WBD, wiring XAL[1], wiring XAL[m], wiring XBL[1 ], wiring XBL[m], node Nx[1], node Nx[m], node Nu[1], no Node Nu[m], Node Nw[1], Node Nw[m], Node Nr[1], and Node N This shows the potential fluctuation of r[m]. Note that in Figure 7, high-level potentials are denoted as High. Low-level potentials are indicated as "Low".

[0176] In this example, the voltage supplied by the wiring VR is considered to be the ground potential.

[0177] <<Before time T01>> At times prior to time T01, nodes Nx[1] to Nx[m], node Nu[ 1] to node Nu[m], node Nw[1] to node Nw[m], and node Nr[ The potentials of each node from [1] to Nr[m] are assumed to be at ground potential. In Figure 15, the ground potential is denoted as GND.

[0178] Furthermore, the circuit WDD (not shown in Figure 6) is used to create wiring WAD and wiring WBD. A low-level potential is input to each of them.

[0179] Furthermore, the circuit XLD connects wiring XAL[1] to wiring XAL[m] and wiring XBL [1], or each of the wiring XBL[m] has a reference potential V RFP This has been entered. Oh, V RFP This potential may be higher or lower than the ground potential.

[0180] Furthermore, the circuit WLD connects wiring WAL[1] to wiring WAL[m] and wiring WBL [1], or each of the wiring WBL[m] has a low-level potential input. Therefore, all memory cells AMx, AMu, and A of the memory cell array CA When the transistor M1 contained in Mw and the memory cell AMR is turned off... It is.

[0181] Furthermore, a low-level potential is input to each of the wires SL4, SL5, and SL7. Therefore, switches SW4A, SW5A, SW5B, and Switch SW7A and Switch SW7B are both set to the OFF state.

[0182] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential was input to wiring SL5. This is because the switch SW5A and switch SW included in the circuit INT are... Each of the 5Bs will be turned on.

[0183] When both switch SW5A and switch SW5B are turned ON, wiring B AL and wiring BBL are electrically connected to wiring VSL, and wiring BAL and Each of the wirings BBL is supplied with a potential from the wiring VSL. Wiring VSL then provides initialization potential to wiring BAL and wiring BBL, respectively. The wiring is configured so that the initialization potential is set to ground potential. Therefore, from time T01 to time T02 Between these points, the potentials of wiring BAL and wiring BBL are at ground potential.

[0184] Furthermore, all memory cells AMx, AMu, and memory cells of the memory cell array CA The first terminal of transistor M2 in each of the memory cells AMw and AMR Since the ground potential is supplied from the wiring VR, the first of each transistor M2 The voltage between terminal 1 and terminal 2 is 0V. Furthermore, nodes Nx[1] through Nx[m] , node Nu[1] to node Nu[m], node Nw[1] to node Nw[m], and Since the potentials of each node Nr[1] to node Nr[m] are at the ground potential, Each transistor M2 will be in the off state.

[0185] <<From time T02 to time T03>> Between time T02 and time T03, a high-level potential is applied to wiring WAL[1]. This is being done. As a result, in the memory cell array CA, the memory cell AMx[1], And the gate of transistor M1 contained in each of the memory cells AMu[1] has a high voltage When a bell potential is applied, each transistor M1 turns on.

[0186] Furthermore, between time T02 and time T03, the wiring WAD has a potential higher than ground potential. Wβ [1] A large potential is input. At this time, the transistor of memory cell AMx[1] Since M1 is in the ON state, there is conductivity between the wiring WAD and node Nx[1]. Furthermore, the first terminal (node ​​Nx[1]) of the capacitance C1 of the memory cell AMx[1] has a ground potential. V Wβ [1] A large potential is input.

[0187] Furthermore, between time T02 and time T03, the wiring WBD has a potential higher than ground potential. Wα [1] A large potential is input. At this time, the transistor of memory cell AMu[1] Since M1 is in the ON state, there is conductivity between the wiring WBD and node Nu[1]. Furthermore, the first terminal (node ​​Nu[1]) of the capacitance C1 of the memory cell AMu[1] has a ground potential. V Wα [1] A large potential is input.

[0188] Here, as shown in the following equation, V W [1] is defined.

[0189]

number

[0190] V W [1] is the voltage corresponding to the first of the m first data points. That is, V Wα [1], and V Wβ [1] Each of these is the voltage corresponding to the first of the m first data points. This can be said. Furthermore, if equation (1.1) is satisfied, then V Wα [1], and V W β [1] The voltage combination can be arbitrarily determined. For example, V Wα [1] is V Wβ [1] It may be higher than V Wβ [1] It may be lower than V Wβ [1] and The same voltage can be used. That is, V W[1] may be a positive voltage, 0, or a negative voltage.

[0191] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, in the memory cell AMx[1], the first terminal of transistor M2 Because the ground potential from the wiring VR is input, the first terminal - second terminal of transistor M2 The voltage across the terminals is almost 0V. Therefore, the transistor M2 of memory cell AMx[1] No current flows between the first and second terminals.

[0192] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, in memory cell AMu[1], the number of transistor M2 Since the ground potential from the wiring VR is input to terminal 1, the first terminal of transistor M2 The voltage between the child and the second terminal is also almost 0V. Therefore, the transient of the memory cell AMu[1] No current flows between the first and second terminals of the M2 transistor.

[0193] By the way, between time T02 and time T03, wiring WAL[2] to wiring W AL[m] and wiring WBL[1] to wiring WBL[m] have been connected since before time T02. A low-level potential is input. Therefore, in the memory cell array CA, the second row Memory cells AMx[2] to memory cells AMx[m] located from row m to row m and and memory cells AMu[2] to AMu[m], from row m+1 to row 2m The arranged memory cells AMw[1], <memory cells AMw[m], and memory cells AM The gate of transistor M1 contained in each of r[1] to memory cell AMr[m] A low-level potential is applied to the transistors, and each transistor M1 is in the off state. This allows the data input to the wiring WAD and wiring WBD to be processed by the node. Nx[2] to node Nx[m], node Nu[2] to node Nu[m], node Nw [1] to node Nw[m], and written to node Nr[1] to node Nr[m]. It won't happen.

[0194] <<From time T03 to time T04>> Between time T03 and time T04, a low-level potential is applied to wiring WAL[1]. This is being done. As a result, in the memory cell array CA, the memory cell AMx[1], And the gate of transistor M1 contained in each of the memory cells AMu[1] has a low resistor When a bell potential is applied, each transistor M1 turns off.

[0195] In memory cell AMx[1], when transistor M1 is turned off, The first terminal (node ​​Nx[1]) of the capacitance C1 of the memory cell AMx[1] has a potential greater than ground potential V Wβ [1] A large potential is maintained. Also, in the memory cell AMu[1], When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMu[1] (Node Nu[1]) has a potential greater than ground potential V Wα [1] A large potential is maintained.

[0196] Also, between time T03 and time T04, between time T02 and time T03 Voltage V to memory cell AMX[1] Wβ Similar to the write operation in [1], memory Memory cells AMx[2] located between row 2 and row m-1 of the Luar array CA For each of the memory cells AMx[m-1], the voltage V Wβ [2]~V Wβ [m -1] will be written sequentially. Also, memory cells AMx[2] to memory cells A Simultaneously with the voltage writing operation to each of Mx[m-1], the memory cell array CA 2 Memory cells AMu[2] to memory cells A located between row (1) and row (m-1) For each of Mu[m-1], the voltage V Wα [2]~V Wα [m-1] is written It shall be assumed that it is.

[0197] At this time, memory cell A located in row p (where p is an integer between 2 and m-1 inclusive) Mx[p] has a voltage V. Wβ [p] is retained, and the memory cell AMu[p] has a voltage V Wα [p] is retained. Here, similar to equation (1.1), the p-th of the m first data points Voltage V W [p] is defined as follows:

[0198]

number

[0199] V W [p] is the voltage corresponding to the p-th of the m first data points. That is, V Wα [p], and V Wβ Each of [p] is the voltage corresponding to the p-th of the m first data points. This can be said. Furthermore, if equation (1.2) is satisfied, then V Wα [p], and V W β The combination of voltages for [p] can be arbitrarily determined. For example, V Wα [p] is V Wβ [p] may be higher than, V Wβ may be lower than, or V Wβ [p] and may be the same voltage. That is, V W [p] may be a positive voltage, 0, or a negative voltage.

[0200] <<From time T04 to time T05>> During the period from time T04 to time T05, a high-level potential is applied to the wiring WAL[m]. As a result, in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMx[m], and the memory cell AMu[m], and each transistor M1 is turned on.

[0201] Also, during the period from time T04 to time T05, a potential greater than the ground potential by V Wβ [m] is input to the wiring WAD. At this time, since the transistor M1 of the memory cell AMx[m] is in the on state, the connection between the wiring WAD and the node Nx[m] becomes conductive, and a potential greater than the ground potential by V is input to the first terminal (node Nx[m]) of the capacitor C1 of the memory cell AMx[m]. Wβ [m]

[0202] Also, during the period from time T04 to time T05, a potential greater than the ground potential by V Wα [m] is input to the wiring WBD. At this time, since the transistor M1 of the memory cell AMu[m] is in the on state, the connection between the wiring WBD and the node Nu[m] becomes conductive, and a potential greater than the ground potential by V is input to the first terminal (node Nu[m]) of the capacitor C1 of the memory cell AMu[m]. Wα [m]

[0203] Here, as shown in the following equation, V W Define [m].

[0204]

number

[0205] V W [m] represents the voltage corresponding to the mth of the m first data points. That is, V Wα [m], and V Wβ Each of [m] is the voltage corresponding to the mth of the m first data points. This can be said. Furthermore, if equation (1.3) is satisfied, then V Wα [m], and V W β The combination of voltages for [m] can be arbitrarily determined. For example, V Wα [m] is V Wβ It can be higher than [m], V Wβ [m] may be lower than V Wβ [m] and The same voltage can be used. That is, V W [m] may be a positive voltage, 0, or a negative voltage.

[0206] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, in the memory cell AMx[m], the first terminal of transistor M2 Because the ground potential from the wiring VR is input, the first terminal - second terminal of transistor M2 The voltage across the terminals is almost 0V. Therefore, the transistor M2 of the memory cell AMx[m] No current flows between the first and second terminals.

[0207] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, in memory cell AMu[m], the number of transistor M2 Since the ground potential from the wiring VR is input to terminal 1, the first terminal of transistor M2 The voltage between the child and the second terminal is also almost 0V. Therefore, the transient of the memory cell AMu[m] No current flows between the first and second terminals of the M2 transistor.

[0208] By the way, between time T04 and time T05, wiring WAL[1] to wiring W AL[m-1] and wiring WBL[1] to wiring WBL[m] have been connected since before time T04. A low-level potential is still being input. Therefore, in the memory cell array CA, 1 Memory cells AMx[1] to memory cells AMx located from row m-1 [m-1] and memory cell AMu[1] or memory cell AMu[m-1], row m+1 Memory cells AMw[1] to memory cells AMw[m] located up to row 2m Each of the cell memory AMr[1] to AMr[m] contains transistors A low-level potential is applied to the gate of transistor M1, and each transistor M1 is O It is in a state of [unclear]. As a result, the inputs to wiring WAD and wiring WBD are The data is located at nodes Nx[1] through Nx[m-1], and nodes Nu[1] through N u[m-1], node Nw[1] to node Nw[m], and node Nr[1] to node Nw[m] It will never be written to Nr[m].

[0209] <<From time T05 to time T06>> Between time T05 and time T06, a low-level potential is applied to wiring WAL[m]. This is being done. As a result, in the memory cell array CA, the memory cell AMx[m], And the gate of transistor M1 contained in each of the memory cells AMu[m] has a low voltage When a bell potential is applied, each transistor M1 turns off.

[0210] In memory cell AMx[m], when transistor M1 is in the OFF state, The first terminal (node ​​Nx[m]) of the capacitance C1 of the memory cell AMx[m] has a potential greater than ground potential V Wβ A potential of [m] is maintained. Also, in the memory cell AMu[m], When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMu[m] (Node Nu[1]) has a potential greater than ground potential V Wα A large potential [m] is maintained.

[0211] <<From time T06 to time T07>> Between time T06 and time T07, a high-level potential is applied to wiring WBL[1]. This is achieved. As a result, in the memory cell array CA, the memory cell AMw[1], And the gate of transistor M1 contained in each of the memory cells AMr[1] has a high voltage When a bell potential is applied, each transistor M1 turns on.

[0212] Furthermore, between time T06 and time T07, the wiring WAD has a potential higher than ground potential. Wα [1] A large potential is input. At this time, the transistor of memory cell AMw[1] Since M1 is in the ON state, there is conductivity between the wiring WAD and node Nw[1]. Furthermore, the first terminal (node ​​Nw[1]) of the capacity C1 of the memory cell AMw[1] has a ground potential. V Wα [1] A large potential is input.

[0213] Furthermore, between time T06 and time T07, the wiring WBD has a potential higher than ground potential. Wβ [1] A large potential is input. At this time, the transistor of memory cell AMr[1] Since M1 is in the ON state, there is conductivity between the wiring WBD and node Nr[1]. Furthermore, the first terminal (node ​​Nr[1]) of the capacitance C1 of the memory cell AMr[1] has a ground potential. V Wβ [1] A large potential is input.

[0214] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, in the memory cell AMw[1], the first terminal of transistor M2 Because the ground potential from the wiring VR is input, the first terminal - second terminal of transistor M2 The voltage across the terminals is almost 0V. Therefore, the transistor M2 of memory cell AMw[1] No current flows between the first and second terminals.

[0215] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, in the memory cell AMr[1], the number of transistor M2 Since the ground potential from the wiring VR is input to terminal 1, the first terminal of transistor M2 The voltage between the child and the second terminal is also almost 0V. Therefore, the transient of the memory cell AMr[1] No current flows between the first and second terminals of the M2 transistor.

[0216] By the way, between time T06 and time T07, wiring WAL[1] to wiring W AL[m] and wiring WBL[2] to wiring WBL[m] have been connected since before time T06. A low-level potential is input. Therefore, in the memory cell array CA, the first row Memory cells AMx[1] to AMx[m] located from row m and and memory cells AMu[1] to AMu[m], from row m+2 to row 2m The arranged memory cells AMw[2] to memory cells AMw[m] and memory cells AM The gate of transistor M1 contained in each of r[2] to memory cell AMr[m] A low-level potential is applied to the transistors, and each transistor M1 is in the off state. This allows the data input to the wiring WAD and wiring WBD to be processed by the node. Nx[1] to node Nx[m], node Nu[1] to node Nu[m], node Nw [2] to node Nw[m], and written to node Nr[2] to node Nr[m] It won't happen.

[0217] <<From time T07 to time T08>> Between time T07 and time T08, a low-level potential was applied to wiring WBL[1]. This is achieved. As a result, in the memory cell array CA, the memory cell AMw[1], And the gate of transistor M1 contained in each of the memory cells AMr[1] has a low resistor When a bell potential is applied, each transistor M1 turns off.

[0218] In memory cell AMw[1], when transistor M1 is turned off, The first terminal (node ​​Nw[1]) of the capacitance C1 of the memory cell AMw[1] has a potential greater than ground potential V Wα [1] A large potential is maintained. Also, in the memory cell AMr[1], When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMr[1] (Node Nr[1]) has a potential greater than ground potential V Wβ [1] A large potential is maintained.

[0219] Also, between time T07 and time T08, between time T06 and time T07 Voltage V to memory cell AMw[1] Wα Similar to the write operation in [1], memory Memory cell AMw located between row m+2 and row 2m-1 of the Luar array CA [2] For each of the memory cells AMw[m-1], the voltage V Wα [2]~V W α [m-1] will be written sequentially. Also, the memory cell AMw[2] or memory Simultaneously with the voltage writing operation to each cell AMw[m-1], memory cell array C Memory cell AMr[2] located between row 2m+2 and row 2m-1 of A For each of the cells up to memory cell AMr[m-1], the voltage V Wβ [2]~V Wβ [m- 1] will be written to it.

[0220] <<From time T08 to time T09>> Between time T08 and time T09, a high-level potential was applied to wiring WBL[m]. This is being done. As a result, in the memory cell array CA, the memory cell AMw[m], And the gate of transistor M1 contained in each of the memory cells AMr[m] has a high voltage When a bell potential is applied, each transistor M1 turns on.

[0221] Furthermore, between time T08 and time T09, the wiring WAD has a potential higher than ground potential. Wα A potential of [m] large is input. At this time, the transistor of memory cell AMw[m] Since M1 is in the ON state, there is conductivity between the wiring WAD and node Nw[m]. Furthermore, the first terminal (node ​​Nw[m]) of the capacity C1 of the memory cell AMw[m] has a ground potential. V Wα [m] A large potential is input.

[0222] Furthermore, between time T08 and time T09, the wiring WBD has a potential higher than ground potential. Wβ A potential larger than [m] is input. At this time, the transistor of the memory cell AMr[m] Since M1 is in the ON state, there is conductivity between the wiring WBD and node Nr[m]. Furthermore, the first terminal (node ​​Nr[m]) of the capacity C1 of the memory cell AMr[m] has a ground potential. V Wβ [m] A large potential is input.

[0223] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, in the memory cell AMw[m], the first terminal of transistor M2 Because the ground potential from the wiring VR is input, the first terminal - second terminal of transistor M2 The voltage across the terminals is almost 0V. Therefore, the transistor M2 of the memory cell AMw[m] No current flows between the first and second terminals.

[0224] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, in memory cell AMr[m], the number of transistor M2 Since the ground potential from the wiring VR is input to terminal 1, the first terminal of transistor M2 The voltage between the child and the second terminal is also almost 0V. Therefore, the transient of the memory cell AMr[m] No current flows between the first and second terminals of the M2 transistor.

[0225] By the way, between time T08 and time T09, wiring WAL[1] to wiring W AL[m] and wiring WBL[1] to wiring WBL[m-1] have been used since before time T08. A low-level potential is still being input. Therefore, in the memory cell array CA, 1 Memory cells AMx[1] to memory cells AMx[m] located from row 1 to row m ] and memory cell AMu[1] to memory cell AMu[m], from row m+1 to row 2m-1 Memory cells AMw[1] to AMw[m-1] and memory cells located up to the eye The transistors contained in each of the Morisel AMr[1] to memory cell AMr[m-1] A low-level potential is applied to the gate of transistor M1, and each transistor M1 is O It is in a state of [unclear]. As a result, the inputs to wiring WAD and wiring WBD are The data is located at nodes Nx[1] through Nx[m], and nodes Nu[1] through Nu[ m], node Nw[1] to node Nw[m-1], and node Nr[1] to node N It will never be written to r[m-1].

[0226] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential was applied to wiring WBL[m]. This is being done. As a result, in the memory cell array CA, the memory cell AMw[m], And the gate of transistor M1 contained in each of the memory cells AMr[m] has a low voltage When a bell potential is applied, each transistor M1 turns off.

[0227] In memory cell AMw[m], when transistor M1 is turned off, The first terminal (node ​​Nw[m]) of the capacitance C1 of the memory cell AMw[m] has a potential greater than ground potential V Wα A potential of [m] is maintained. Also, in the memory cell AMr[m], the transient When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMr[m] (Node Nr[m] is at ground potential V Wβ A large potential [m] is maintained.

[0228] The operation between time T01 and time T10 results in the memory cell array CA being included The memory cells AMx, AMu, AMw, and AMR are Each can be programmed with a voltage corresponding to the first data point.

[0229] <<From time T10 to time T11>> Between time T10 and time T11, a low-level potential is input to wiring SL5. As a result, in circuit INT, switches SW5A and SW5B This will turn off.

[0230] <<From time T11 to time T12>> Between time T11 and time T12, wiring XAL[1] to wiring XAL[m] Each of these is input with a potential corresponding to m second data points. Here, for example, circuit X The potential input from LD to wiring XAL[1] is set to be V lower than the ground potential. Xα [1] High potential and The potential input from circuit XLD to wiring XAL[p] is set to be V higher than the ground potential. Xα [p] The potential is set to be high, and the potential input from circuit XLD to wiring XAL[m] is set to be V higher than the ground potential. Xα [m] The potential is set to be high.

[0231] The potential of wiring XAL[1] is V from the ground potential. Xα [1] Therefore, memory cell A The second terminal of the capacitance C1 of Mx[1] and memory cell AMu[1] is V Xα [1] will be applied. At this time, node Nx[1] and node Nu[1] Since each is electrically floating, the capacitive coupling of the capacitor C1 allows the node Nx[1 The potentials of ] and node Nu[1] change.

[0232] In each of the memory cell AMx[1] and the memory cell AMu[1], The increase in gate potential of sta M2 corresponds to the change in potential of wiring XAL[1], and the configuration of the memory cell. The potential is obtained by multiplying by the capacitive coupling coefficient determined by the capacitance C1. This is calculated based on the gate capacitance and parasitic capacitance of transistor M2. In this example, Let h be the capacitive coupling coefficient of the Moricell AMx and the memory cell AMu, respectively.

[0233] Therefore, the potential change of wiring XAL[1] is V Xα [1] When node Nx[1] The potential changes at node Nu[1] are, Xα [1] This means no. The potential of Nx[1] is V Wβ [1]+hV Xα [1], and the potential of node Nu[1] V Wα [1]+hV Xα [1]

[0234] In this example, the memory cell AMx[1] included in the memory cell array CA , and for memory cells other than memory cell AMu[1], the respective capacitive coupling coefficients are Let's explain it using h.

[0235] Therefore, the potential of wiring XAL[p] is V from the ground potential.Xα [p] rises, At the second terminal of the capacitance C1 of the Moricell AMx[p] and memory cell AMu[p] V Xα [p] will be applied. At this time, node Nx[p] and node N Since each of u[p] is in an electrically floating state, capacitive coupling with capacitor C1 results in no The potentials of node Nx[p] and node Nu[p] change. Specifically, the node The potential of Nx[p] is V Wβ [p] +hV Xα [p], and the potential of node Nu[p] is , V Wα [p] +hV Xα [p]

[0236] Furthermore, the potential of the wiring XAL[m] is V from the ground potential. Xα [m] increases, The second terminal of the capacitance C1 of cell AMx[m] and memory cell AMu[m] is: V Xα [m] will be applied. At this time, node Nx[m] and node Nu[ Since each of [m] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of x[m] and node Nu[m] change. Specifically, node Nx The potential at [m] is V Wβ [m]+hV Xα [m], and the potential at node Nu[m] is V Wα [m]+hV Xα [m]

[0237] Also, between time T11 and time T12, wiring XBL[1] to wiring XBL Each of [m] is input with a potential corresponding to m second data points. Here, for example, The potential input from circuit XLD to wiring XBL[1] is set to be V higher than the ground potential.Xβ [1] high Let the potential be such that the potential input from circuit XLD to wiring XBL[p] is V greater than the ground potential. Xβ [p] As a high potential, the potential input from circuit XLD to wiring XBL[m] is set to be higher than the ground potential. RimoV Xβ [m] The potential is set to be high.

[0238] The potential of wiring XBL[1] is V from the ground potential. Xβ [1] Therefore, memory cell A The second terminal of the capacitance C1 of Mw[1] and the memory cell AMr[1] is V Xβ [1] will be applied. At this time, node Nw[1] and node Nr[1] Since each is electrically floating, the capacitive coupling of capacitance C1 causes node Nw[1 The potentials of ] and node Nr[1] change.

[0239] In this example, the memory cell AMw and the memory cell included in the memory cell array CA are shown. The respective capacitive coupling coefficients of memory cell AMr are memory cell AMx and memory cell AM We will explain it using h, similar to u.

[0240] Therefore, the potential change of wiring XBL[1] is V Xβ [1] When node Nw[1] The potential changes at node Nr[1] are, Xβ [1] This means no. The potential of Nw[1] is V Wα [1]+hV Xβ [1], and the potential of node Nr[1] V Wβ [1]+hV Xβ [1]

[0241] Furthermore, the potential of wiring XBL[p] is V from the ground potential. Xβ [p] is raised, The second terminal of the capacitance C1 of cell AMw[p] and memory cell AMr[p] is: V Xβ [p] will be applied. At this time, node Nw[p] and node Nr[ Since each of p] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of w[p] and node Nr[p] change. Specifically, node Nw The potential of [p] is V Wα [p] +hV Xβ [p], and the potential at node Nr[p] is V Wβ [p] +hV Xβ [p]

[0242] Furthermore, the potential of wiring XBL[m] is V from the ground potential. Xβ [m] increases, The second terminal of the capacitance C1 of cell AMw[m] and memory cell AMr[m] is: V Xβ [m] will be applied. At this time, node Nw[m] and node Nr[ Since each of [m] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of w[m] and node Nr[m] change. Specifically, node Nw The potential at [m] is V Wα [m]+hV Xβ [m], and the potential at node Nu[m] is V Wβ [m]+hV Xβ [m]

[0243] Here, as shown in the following equation, V X [1], V X [p], and V X Define [m].

[0244]

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[0245] V X [1]~V X Each of the [m] values ​​should be the voltage corresponding to the second data. That is, V Xα [1]~V Xα [m], and V Xβ [1]~V Xβ Each of [m] is also the second It can be said that this is the voltage corresponding to the data. Furthermore, the equations (1.4) to (1.6) are satisfied. If so, V Xα [i], and V Xβ The combination of voltages in [i] can be arbitrarily determined. To be able to. For example, V Xα [i] is V Xβ [i] may be higher than V Xβ [i] It can be low, or V Xβ [i] may be the same voltage. That is, V X [i] is positive charge It may be a voltage, 0, or a negative voltage.

[0246] <<From time T12 to time T13>> Between time T12 and time T13, high levels were observed in wiring SL4 and wiring SL7. A potential is input. This activates switches SW7A and S in the circuit CMS. Both W7B and switch SW4A in circuit ACTV are turned ON.

[0247] At this time, memory cell AMx[1], <memory cell AMx[m], and memory cell AM The second terminal of transistor M2 contained in each of w[1] to memory cell AMw[m] This is in a conductive state with the first terminal of transistor M3A included in circuit CM via wiring BAL. This is the result. Also, memory cells AMx[1] to AMx[m], and memory cell A The second terminal of transistor M2 contained in each of Mw[1] to memory cell AMw[m] The child is in a conductive state with the first terminal of circuit IVC included in circuit ACTV via wiring BAL. It becomes so. Also, memory cell AMu[1] to memory cell AMu[m], and memory cell AM The second terminal of transistor M2 contained in each of r[1] to memory cell AMr[m] This is in a conductive state with the first terminal of transistor M3B included in circuit CM via wiring BBL. This is the result.

[0248] Here, memory cell AMx, memory cell AMu, memory cell AMw, and memory cell A Let's consider the current flowing from the second terminal to the first terminal of each transistor M2 in Mr.

[0249] Wiring BAL to the first terminal via the second terminal of transistor M2 of memory cell AMx[1] The current flowing through the child is I AMx[1] In that case, I AMx[1] It can be expressed by the following formula ru.

[0250]

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[0251] k is the channel length, channel width, mobility, and gate dielectric capacitance of transistor M2. It is a constant determined by factors such as V. th This is the threshold voltage of transistor M2. Oh, the constant k is not only for memory cell AMx, but also for memory cell AMu, memory cell AMw, and This also applies to memory cell AMr. Furthermore, it applies not only to memory cell AMx but also to The transistors of the memory cell AMu, memory cell AMw, and memory cell AMr The threshold voltage of M2 is also V th Let's assume that.

[0252] Furthermore, via the wiring BAL through the second terminal of transistor M2 of memory cell AMx[m] The current flowing through the first terminal is I AMx[m] In that case, I AMx[m] It can be expressed by the following formula. It is possible.

[0253]

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[0254] In other words, each of the wiring BALs from memory cell AMx[1] to memory cell AMx[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I x In that case, I x is, formula From equations (1.7) and (1.8), it can be expressed by the following equation.

[0255]

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[0256] Similarly, from the wiring BAL, via the second terminal of transistor M2 of memory cell AMw[1] The current flowing through the first terminal is I AMw[1] The wiring BAL is connected to the memory cell AMw[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMw[m] If that's the case K, I AMw[1] , and I AMw[m] It can be expressed by the following formula.

[0257]

number

[0258] In other words, each of the wiring BALs from memory cell AMw[1] to memory cell AMw[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I w In that case, I w is, formula From equations (1.10) and (1.11), it can be expressed by the following equation.

[0259]

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[0260] Similarly, from the wiring BBL through the second terminal of transistor M2 of memory cell AMu[1] The current flowing through the first terminal is I AMu[1] The wiring BBL is connected to the memory cell AMu[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMu[m] If that's the case K, I AMu[1] , and I AMu[m] It can be expressed by the following formula.

[0261]

number

[0262] In other words, each of the connections from the wiring BBL to the memory cell AMu[1] to the memory cell AMu[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I u In that case, I u is, formula From equations (1.13) and (1.14), it can be expressed by the following equation.

[0263]

number

[0264] Similarly, from the wiring BBL through the second terminal of transistor M2 of memory cell AMr[1] The current flowing through the first terminal is I AMr[1] The wiring BBL is connected to the memory cell AMR[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMr[m] If that's the case K, I AMr[1] , and I AMr[m] It can be expressed by the following formula.

[0265]

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[0266] In other words, each of the connections from wiring BBL to memory cell AMr[1] to memory cell AMr[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I r In that case, I r is, formula From equations (1.16) and (1.17), it can be expressed by the following equation.

[0267]

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[0268] Between time T12 and time T13, the switch SW included in circuit CMS 7B is in the ON state, and switch SW5B, which is included in circuit INT, is OFF. Because it is in this state, memory cell AMu[1] to memory cell A is connected via wiring BBL. Mu[m] and the total current flowing through memory cell AMR[1] to memory cell AMR[m] Japanese I u +I r This flows from the wiring VHE via the first terminal of transistor M3B. The voltage at the first terminal (gate) of transistor M3B is equal to the current I u +I r voltage corresponding to This is the result.

[0269] Furthermore, since circuit CM is a current mirror circuit, the first of transistor M3B The amount of current flowing between terminal 1 and terminal 2 is the same as the current flowing between terminal 1 and terminal 2 of transistor M3A. The amount of current becomes approximately equal to the current. Between time T12 and time T13, in circuit CMS The included switch SW7A is in the ON state, so the wiring from VHE to the transistor The amount of current flowing through the M3B to the wiring BAL is I u +I r This is the result.

[0270] Furthermore, the switch SW5B included in circuit INT is in the OFF state, and circuit A Since switch SW4A included in the CTV is in the ON state, the wiring BAL is... Current flows to the first terminal of circuit IVC, which is included in circuit ACTV, via switch SW4A. It flows. The amount of the current is I EV In that case, I EV This can be expressed by the following formula:

[0271]

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[0272] Equation (1.19) is derived from equations (1.1) through (1.6), equation (1.9), and equation (1.12). Using equations (1.15) and (1.18), the following equation can be written: It is possible.

[0273]

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[0274] From equation (1.20), the amount of current I input from wiring BAL to circuit ACTV is given by EV is, 1. Potential V corresponding to data W [1]~V W [m] and the potential V corresponding to the second data. X [1] ~V X It is proportional to the sum of the products of [m]. In other words, the sum of the products of the first and second data is proportional to the amount of current. I EV It can be expressed as follows.

[0275] I EV As the current flows, The third terminal of circuit IVC is connected to I EV A voltage corresponding to the value is output. Subsequently, that voltage is used in the circuit. The voltage is input to the first terminal of ACF, and this voltage is used to predefined by the ACF circuit. The calculation of the function system is performed, and the result of the calculation is expressed as voltage (or current, etc.) on the wiring N. Output from IL.

[0276] By the way, each of equations (1.1) through (1.3) is V Wα [i]=V Wβ [i] +V W It can be transformed into [i]. That is, memory cell AMu[i], and memory cell In AMw[i], V Wβ [i]+V W [i] is retained. V Wβ [i] is any Since it can be expressed as voltage, V Wβ [1]~V Wβ Each of the [m] is given the same voltage. This is also acceptable. For example, V Wβ [1]~V Wβ Each of [m] is V PR In that case, Memory cell AMx[i] contains V PR V is retained, and memory cell AMu[i] contains V PR +V W [i] is retained, and memory cell AMw[i] contains V PR +V W [i] is retained, memo RISEL AMR[i] contains V PRThis will be retained. In this way, V Wβ [1]~ V Wβ Each of [m] is V PR By doing so, V PR Using this as the reference voltage, memory The voltage obtained by adding a voltage corresponding to the first data to the reference voltage to cell AMu and memory cell AMw. By maintaining this, and by maintaining a reference voltage in memory cells AMX and AMR, Similarly, the operation in equation (1.20) can be performed.

[0277] Furthermore, each of equations (1.4) through (1.6) is V Xα [i]=V Xβ [i]+V X [i] can be transformed into this. That is, between time T11 and time T12 , wiring XAL[i] is V Xβ [i]+V X [i] is entered. V Xβ [i] is, Since it can be set to any voltage, V Xβ [1]~V Xβ Each of the [m] is the same It can also be expressed as voltage. For example, V Xβ [1]~V Xβ Each of [m] is V RFP so At that time, V is present in the wiring XAL[i]. RFP +V X [i] is input, and wiring XBL[i] has V RFP This will be input. In this way, V Xβ [1]~V Xβ Each of [m] V all RFP By doing so, V RFP Using this as the reference voltage, the wiring XAL is connected to the reference voltage. The voltage applied according to the second data is input, and the reference voltage is input to the wiring XBL. Similarly, the calculation in equation (1.20) can be performed.

[0278] <Example of semiconductor device configuration 2> Here, unlike the MAC1 arithmetic circuit in Figure 1, multiple first data and multiple second data are used. This document describes a semiconductor device capable of performing sum-of-accumulate operations.

[0279] The arithmetic circuit MAC2 in Figure 8, like the arithmetic circuit MAC1 in Figure 1, uses multiple first data and multiple This is an example of a semiconductor device capable of performing sum-of-products operations with a second numerical data point. The arithmetic circuit is MAC2. This refers to the circuit configuration of circuit CMS and the fact that wiring BBL is electrically connected to circuit ACTV. The point and the arithmetic circuit MAC1 are different.

[0280] The circuit CMS included in the arithmetic circuit MAC2 consists of current source CSA and current source CSB, It has. The input terminal of the current source CSA is electrically connected to the wiring VHE, and the output of the current source CSA The power terminal is electrically connected to wiring BAL. The input terminal of the current source CSB is connected to wiring VH Electrically connected to E, the output terminal of the current source CSB is electrically connected to wiring BBL. ru.

[0281] Furthermore, the circuit CMS included in the arithmetic circuit MAC2 has the circuit configuration described above. Therefore, it does not function as a current mirror circuit as shown in Figures 3A and 3B.

[0282] The wiring VHE is similar to the explanation given for circuit CMS in Figures 3A and 3B, as an example. This can be used as wiring to provide a constant voltage. For example, the constant voltage can be a high-level potential. It is preferable to do so.

[0283] Current source CSA and current source CSB each require that the power supply potential be input to their input terminals. It has the function of outputting a constant current to the output terminal. Note that current source CSA and current source CSB It is preferable that the amount of current each of these outputs to its output terminal is equal to that of the others. Specifically, The amount of current flowing from the output terminal of current source CSA to wiring BAL is the same as the amount of current flowing from the output terminal of current source CSB. The current flowing through the wiring BBL is 0.85 times or more, 0.9 times or more, or 0.95 times or more. It is preferable that the ratio be 1.05 times or less, 1.1 times or less, or 1.15 times or less. This is preferable. Note that the lower and upper limits mentioned above can be combined. Let's assume that.

[0284] Furthermore, as mentioned above, wiring BBL is electrically connected to circuit ACTV. (Figure 8) In this context, circuit ACTV is, for example, the current flowing from wiring BAL to circuit ACTV, and wiring A function that outputs a voltage corresponding to the difference in current flow from BBL to the ACTV circuit. The function of performing calculations according to a predefined set of functions using the said voltage, and the function It is preferable to have a configuration that includes a function to output the calculation result to the NIL wiring.

[0285] Specifically, the ACTV circuit included in the MAC2 arithmetic circuit in Figure 8 is, for example, The circuit ACTV shown in Figure 9 can be constructed using the circuit ACP. Circuit ACP includes switch SW4A, switch SW4B, circuit IVC, and circuit A It has CF and

[0286] The circuit IVC in Figure 9 has an operational amplifier OP, a load LEA, and a load LEB. The circuit configuration is the same as circuit IVC, which is included in circuit ACTV in Figure 4C. Therefore, for the explanation of the circuit IVC in Figure 9, please refer to the description of the circuit IVC in Figure 4C.

[0287] Furthermore, the circuit ACF in Figure 9 is included, for example, in the circuit ACTV described in Figures 4A to 4C. The circuit ACF in Figure 9 can be made to be the same as the circuit in Figure 4. Similar to the circuit ACF in Figures A through 4C, a defined relation is formed depending on the voltage input to the first terminal. A function that performs calculations according to a numerical system, and the result of the calculations of the said function system is sent to the second terminal of the circuit ACF (wiring). It can be configured to have a function to output to NIL.

[0288] The first terminal of switch SW4A is electrically connected to wiring BAL, and the switch SW4A The second terminal connects to the inverting input terminal of the operational amplifier OP and the load L via the first terminal of the circuit IVC. The first terminal of EA is electrically connected to the first terminal of circuit ACF. The first terminal of circuit IVC is electrically connected to the first terminal of circuit IVC. The output terminal of the operational amplifier OP and the second terminal of the load LEA are electrically connected via the second terminal. It is connected. The first terminal of switch SW4B is electrically connected to wiring BBL, and the switch The second terminal of switch SW4B connects to the non-inverting input of the op-amp OP via the third terminal of circuit IVC. The power terminal is electrically connected to the first terminal of the load LEB. Also, switch SW4 The control terminals of A and switch SW4B are electrically connected to wiring SL4. ru.

[0289] For example, switch SW4B can be switch SW4A, switch SW5A, and A switch that is compatible with switch SW5B can be used.

[0290] The ACTV circuit in Figure 9, for example, applies a high-level potential to the wiring SL4, and switches SW... By turning on both 4A and switch SW4B, the wiring BAL The current from circuit IVC can be passed to the first terminal of circuit I, and the current from wiring BBL can be passed to circuit I It can be routed to the third terminal of the VC.

[0291] For example, in the arithmetic circuit MAC2 in Figure 8, the current source CSA and the current source CSB This determines the amount of current that flows through wiring BAL and wiring BBL. CS And, wiring from BAL to memory The sum of the amounts of current flowing through cell AMx[1] to memory cell AMx[m] is I x and wiring The sum of the amounts of current flowing from BAL to memory cell AMw[1] to memory cell AMw[m] to I w Therefore, the amount of current flowing from wiring BAL to the first terminal of circuit IVC is I CS -I x -I w This is the result. Also, from wiring BBL, memory cell AMu[1] to memory cell AMu[m The sum of the amounts of current flowing through ] is I u And, from the wiring BBL, the memory cell AMr[1] or memo The sum of the amounts of current flowing through the recell AMR[m] is I r Therefore, the wiring from BBL to circuit IVC The amount of current flowing through the third terminal is I CS -I u -I r This is the result.

[0292] When the circuit IVC in Figure 9 is used as a subtraction circuit (for example, loads LEA and LEB are resistors) In this case, the second terminal of circuit IVC is connected to the amount of current input to the first terminal of circuit IVC. The difference between the amount of current input to the third terminal of the circuit IVC and (-I) u -I r +I x +I w ) It outputs a voltage corresponding to this. The current amount of this difference is given by equations (1.19) and (1.20), Since it is determined by the sum of the products of multiple first data and multiple second data, the second terminal of the circuit IVC The voltage output is a voltage corresponding to the sum of the products of multiple first data points and multiple second data points. It can be said that...

[0293] Subsequently, the voltage is input to the first terminal of the ACF circuit, and the ACF circuit is then used with this voltage. The calculation is performed by a predefined set of functions, and the result of the calculation is a voltage (or, It is output from the NIL wiring as current, etc.

[0294] <Example 3 of semiconductor device configuration> Next, there are several first arithmetic circuits that are different from the MAC1 arithmetic circuit in Figure 1 and the MAC2 arithmetic circuit in Figure 8. This document describes a semiconductor device capable of performing sum-of-accumulate operations with data and multiple second data points.

[0295] The arithmetic circuit MAC3 in Figure 10 is similar to the arithmetic circuits MAC1 and MAC2, and is multifaceted. This is an example of a semiconductor device capable of performing a sum-of-products operation between a first numerical data point and multiple second data points. Circuit MAC3 is a modified version of the arithmetic circuit MAC1 and is a memory included in circuit CSW. The number of memory cells AMr contained in cell AMw and circuit CSR is determined by the arithmetic circuit MAC. It is different from 1.

[0296] For example, in the arithmetic circuit MAC3, the number of memory cells AMw included in the circuit CSW Let the number be g (where g is an integer greater than or equal to 1 and not m), and include in the circuit CSR The number of memory cells AMr can be set to g. Therefore, the wiring XBL and the wiring The number of lines in each WBL is denoted as g.

[0297] First, let's explain the case where g is between 1 and m (exclusive of 1).

[0298] V is a voltage corresponding to multiple first data points. W [1]~V W Let [m] and equation (1.1) V satisfies equation (1.3) Wα [1]~V Wα [m], and V Wβ [1]~ V Wβ Define [m]. Also define memory cell AMw[1] to memory cell AMw[m], Each of the memory cells AMu[1] to AMu[m] has a voltage V Wα [1]No To V Wα [m] is held, memory cell AMx[1] to memory cell AMx[m], memo V in the recell AMR[1] or memory cell AMR[m] Wβ [1]~V Wβ [m] holds It is assumed that it is.

[0299] At this time, between time T11 and time T12 in the timing chart of Figure 7, When the change in potential of wiring XBL[1] to wiring XBL[m] is small, for example, V Xβ [ 1]~V Xβ Let's consider the case where each of [m] is set to 0V. Here, for example, wiring BA Current I flows from L to memory cell AMw[i] AMw [i] is equation (1.10) and equation ( 1.11) From I AMw [i]=k(V Wα [i]-V th ) 2 So, is the wiring BBL? The current I flowing through the memory cell AMr[i] AMr [i] is given by equation (1.16) and equation (1. 17) From I AMr [i]=k(V Wβ [i]-Vth ) 2 This is the result. At this time, V W [ i]=V Wα [i]-V Wβ If [i] is close to 0, I AMw [i] and I AMr [i] and These can be considered to be approximately the same amount of current. Therefore, a portion of the current flowing through wiring BBL A certain I AMr [i] is also part of the current that circuit CMS flows through wiring BAL, therefore wiring B In AL, I is a part of the current flowing through the circuit CMS. AMr [i] is a memory cell AM I flowing into w[i] AMw [i] is canceled.

[0300] Conversely, if data is written to memory cell AMw[i] and memory cell AMr[i] respectively... The voltage V Wα [i] and V Wβ If it is known in advance that the difference in [i] is close to 0, V Wα [i] and V W β [i] does not need to be written. This makes it possible to write memory cell A included in the circuit CSW. This allows for a reduction in the number of Mw cells and the number of memory cell AMR cells included in the circuit CSR. , memory cell AMw included in circuit CSW, memory cell A included in circuit CSR This can reduce the power consumption required by the manufacturer.

[0301] Furthermore, in the timing chart of Figure 7, between time T11 and time T12, the wiring The change in the potential of XAL[i] is V Xα [i](=V X [i]) When the wiring is BAL The amount of current flowing through the memory cell AMx[i] is IAMx [i]=k(V Wβ [i]+h V Xα [i]-V th ) 2 As a result, the current flows from the wiring BBL to the memory cell AMu[i]. The amount is I AMu [i]=k(V Wα [i]+hV Xα [i]-V th ) 2 This is the result. V X α The larger [i] becomes, I AMx [i] and I AMu The difference in current between [i] and [i] is large. Because this may occur, each of the memory cells AMx[i] and AMu[i] Unlike memory cell AMw[i] and memory cell AMr[i], it corresponds to the first data. It is preferable to write the voltage.

[0302] Next, we will explain the case where g exceeds m, for example, g = m + 1.

[0303] V is a voltage corresponding to multiple first data points. W [1]~V W Let [m] and equation (1.1) V satisfies equation (1.3) Wα [1]~V Wα [m], and V Wβ [1]~ V Wβ Define [m]. Also define memory cell AMw[1] to memory cell AMw[m], Each of the memory cells AMu[1] to AMu[m] has a voltage V Wα [1]No To V Wα [m] is held, memory cell AMx[1] to memory cell AMx[m], memo V in the recell AMR[1] or memory cell AMR[m] Wβ [1]~V Wβ [m] holds It is assumed that it is.

[0304] Furthermore, any voltage V can be applied to the memory cell AMr[m+1]. b The data is written to the memory cell AM The ground potential is written to w[m+1]. Also, the time T1 in the timing chart of Figure 7 Between time 1 and time T12, there is no change in the voltage of wiring XBL[m+1]. In this case, between time T12 and time T13 in the timing chart of Figure 15, The current flowing from wiring BBL to memory cell AMr[m+1] is I b In that case, I b , and Current I flowing from wiring BAL to circuit ACTV EV Each of them is as follows: .

[0305]

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[0306] Equation (1.22) corresponds to an expression that gives an arbitrary value to the result of the sum of products. For example, in computations in a hierarchical neural network, the weight coefficient and the neural A calculation that applies an arbitrary value of bias (deviation) to the result of a sum-of-products operation with Ron's signal. It can be used in various ways, such as...

[0307] In the above example, an arbitrary voltage V is applied to the memory cell AMr[m+1]. b Write to memory We have explained the case where the ground potential is written to the memory cell AMw[m+1], but Write the ground potential to [m+1] and set an arbitrary voltage V to the memory cell AMw[m+1]. b Write It is acceptable to connect them. In this case, the wiring BAL is connected to the memory cell AMw[m+1]. b The amount of current Because it flows, the amount of current I flowing from wiring BAL to circuit ACTV EV This is I of equation (1.21) b ga-I b The value is replaced by this. In other words, any given value can be used with respect to the result of the sum of products. It can also take negative values.

[0308] Furthermore, as mentioned above, the voltage V with a difference close to 0. Wα [i] and V Wβ [i] Omission of writing, Adding an arbitrary value to the result of a sum-of-products operation can be done simultaneously. Also, at this time, The value of g, which is the number of rows in the Morissel array CA, may be between 1 and m, and g may exceed m. That's good too.

[0309] Furthermore, the value of g may be m. In this case, for example, in the arithmetic circuit MAC1 in Figure 1... The voltage V written to memory cell AMw[i] and memory cell AMr[i] respectively. W α [i] and V Wβ If it is known in advance that the difference in [i] is close to 0, then, for example, memo V Wα [i] and V Wβ [ Instead of writing i), one of the memory cells AMw[i] or AMR[i] is written. Any voltage V b Write to memory cell AMw[i] or memory cell AMR[i] By writing the ground potential on the other side, the voltage V, which is close to 0 in difference, is obtained. Wα [i] and V Wβ [i] It is possible to omit writing and add an arbitrary value to the sum-of-products result simultaneously.

[0310] Furthermore, the semiconductor device according to one aspect of the present invention includes the arithmetic circuits MAC1 to described in this embodiment. It is not limited to the arithmetic circuit MAC3, etc. For example, using the same multiple second data, multiple To perform multiply-accumulate operations simultaneously, the MAC4 arithmetic circuit shown in Figure 11 should be used. MAC4 consists of n memory cell arrays CA of the arithmetic circuit MAC1 shown in Figure 1 (where n is an integer greater than or equal to 1). The arrangement is such that each element is placed in a separate column.

[0311] Figure 11 illustrates memory cell arrays CA[1] to CA[n]. Therefore, the memory cell array CA[1] to the memory cell array CA[n] are grouped together as a memory cell array. It is configured as a double array CAS. Furthermore, the arithmetic circuit MAC4 has n memory cell arrays CA. Therefore, in Figure 11, the circuit CMS is represented as n circuits CM, such as circuit CM[1] to Circuit CM[n] is present, and circuit INT consists of n circuits SCI, such as circuit SCI[1] to A circuit SCI[n] has a circuit ACTV, and the circuit ACP[1] has n circuits ACP. It has a circuit ACP[n]. In addition, the arithmetic circuit MAC4 is a distribution of the arithmetic circuit MAC1. The wiring BAL[1] to BAL[n], which correspond to the line BAL, and the arrangement of the arithmetic circuit MAC1 The wiring BBL[1] to BBL[n], which correspond to the line BBL, and the arrangement of the arithmetic circuit MAC1 Wiring WAD[1] to WAD[n], which correspond to the line WAD, and the arrangement of the arithmetic circuit MAC1 Wiring WBD[1] to WBD[n], which correspond to the line WBD, and the arrangement of the arithmetic circuit MAC1 It has wiring NIL[1] to wiring NIL[n], which correspond to line NIL.

[0312] Memory cell array CA[1] is connected to wiring BAL[1], wiring BBL[1], and wiring WA D[1], wiring WBD[1], wiring XAL[1] to wiring XAL[m], and wiring XB L[1] or wiring XBL[m], wiring WAL[1] or wiring WAL[m], and wiring WB L[1] to wiring WBL[m] is electrically connected to the circuit WDD, wiring WA D[1] is electrically connected to the wiring WBD[1]. Also, the circuit CMS CM[1] is electrically connected to wiring BAL[1] and wiring BBL[1], and circuit I The NT circuit SCI[1] is connected to wiring BAL[1], wiring BBL[1], and the ACTV circuit It is electrically connected to circuit ACP[1]. Circuit ACP[1] is connected to wiring NIL[1]. They are electrically connected.

[0313] Similarly, the memory cell array CA[n] consists of wiring BAL[n] and wiring BBL[n], Wiring WAD[n], wiring WBD[n], wiring XAL[1] to wiring XAL[m], Wiring XBL[1] to Wiring XBL[m] and Wiring WAL[1] to Wiring WAL[m], The circuit WDD is electrically connected to wiring WBL[1] through wiring WBL[m]. It is electrically connected to wiring WAD[n] and wiring WBD[n]. Also, circuit CM Circuit CM[n] of S is electrically connected to wiring BAL[n] and wiring BBL[n]. Circuit INT's circuit SCI[n] is connected to wiring BAL[n] and wiring BBL[n], and circuit A It is electrically connected to circuit ACP[n] of the CTV. Circuit ACP[n] is connected to wiring NIL. [n] is electrically connected.

[0314] The arithmetic circuit MAC4 in Figure 11 operates similarly to the timing chart in Figure 7, as does the memory cell. Each of arrays CA[1] to memory cell array CA[n] contains the first to the nth group. After writing the voltage corresponding to the first data of the group, wiring XAL[1] to wiring XAL Input a voltage corresponding to the second data to [m] and wiring XBL[1] to wiring XBL[m]. By doing so, the first data and second data of each of the first to nth groups The sum-of-accumulate operation can be output simultaneously to wiring NIL[1] through NIL[n].

[0315] <Example of semiconductor device configuration 4> Here, the above-mentioned arithmetic circuits MAC1, MAC1A, MAC2, and calculation The MAC3 circuit is capable of performing sum-of-products operations on multiple different first data points and multiple second data points. Let me explain semiconductor devices.

[0316] The arithmetic circuit MAC5 shown in Figure 12 performs a sum-of-accumulate operation, similar to the arithmetic circuit MAC1 described above. This shows an example of the configuration of an arithmetic circuit capable of performing calculations on functions. The arithmetic circuit MAC5 will be described later. Multiple first data stored in multiple memory cells, and multiple second data that are input, This is a circuit that performs a sum-of-products operation and then uses the result of that sum-of-products operation to perform a function operation.

[0317] The MAC5 arithmetic circuit, as an example, consists of a memory cell array CA, a circuit CMS, and a circuit WD. It has circuits D, XLD, WLD, INT, and ACTV.

[0318] The memory cell array CA consists of circuits CS[1] to CS[m] (where m is 1 or greater). It is an integer. ) It also has each of circuits CS[1] to CS[m], It has a recell AMu, a memory cell AMx, a memory cell AMw, and a memory cell AMR. Although not shown in Figure 12, in this specification, etc., the circuit CS[i] (where i is 1 or less) The memory cells AMu, AMx, and memory cells included in the above (where m is an integer less than or equal to) AMw and AMR are memory cells Amu[i] and AMX, respectively. [i], memory cell AMw[i], and memory cell AMr[i] may be used as descriptive terms.

[0319] In the memory cell array CA, each memory cell is arranged in a 2m x 2 matrix. It is located in the following position. In Figure 12, as an example, the memory cell AMu[i] is located in row 2i-1. The memory cell AMw[i] is located at the address of row 2i, column 1. The memory cell AMx[i] is located at the address 2i-1 row 2 column, and the memory cell AMr [i] is located at the address 2i row 2 column.

[0320] The memory cells AMx, AMw, AMu, and AMR Each has the function of holding the voltage corresponding to the first data. Voltage is, for example, the voltage held in memory cell AMu[i] and memory cell AMw[i] The voltage, the voltage held in memory cell AMx[i], and memory cell AMr[i], It can be treated as a difference.

[0321] Memory cell AMu[1] is connected to wiring WAD, wiring BBL, wiring WL[1], and wiring X AL[1] is electrically connected to WA. Also, the memory cell AMw[1] is connected to the wiring WA. D is electrically connected to wiring BAL, wiring WL[1], and wiring XBL[1]. Furthermore, the memory cell AMx[1] is connected to wiring WBD, wiring BAL, and wiring WL[1]. The wiring XAL[1] is electrically connected to the other. Also, the memory cell AMr[1] is Electrically connect wiring WBD, wiring BBL, wiring WL[1], and wiring XBL[1]. It is configured as follows: Furthermore, the memory cell AMu[m] is connected to wiring WAD, wiring BBL, and wiring WL. [m] and wiring XAL[m] are electrically connected. Also, memory cell AMw[ [m] is the electrical wiring WAD, BAL, WL[m], and XBL[m]. They are connected in a specific manner. Also, the memory cell AMx[m] is connected to wiring WBD and wiring BAL. It is electrically connected to wiring WL[m] and wiring XAL[m]. AMr[m] is the same as wiring WBD, wiring BBL, wiring WL[m], and wiring XBL[m]. It is electrically connected to it.

[0322] Each of circuits CS[1] to CS[m] contains a memory cell AMu, Detailed explanations of each of the memory cells AMw, AMx, and AMR Examples of road configurations will be discussed later.

[0323] Circuit CMS is electrically connected, for example, to wiring BAL and wiring BBL. The circuit CMS connects memory cells AMx[1] to memory cells AMx[m] via wiring BAL. ], and supply current to each of the memory cells AMw[1] to AMw[m] The function of transmitting memory cells AMu[1] to AMu[m] via wiring BBL, and Function to supply current to each of the memory cells AMr[1] to AMr[m] It has the following: Furthermore, the current flowing through wiring BAL and wiring BBL is determined by circuit CMS. It is preferable that the currents applied are equal.

[0324] Furthermore, specific configuration examples of the circuit CMS can be applied to the arithmetic circuit MAC1 described above. Refer to the explanation of the CMS circuit.

[0325] Regarding the WDD circuit, as an example, the WDD circuit can be applied to the MAC1 arithmetic circuit described above. We will take D's explanation into consideration.

[0326] Circuit WLD is, for example, electrically connected to wiring WL[1] to wiring WL[m]. The WLD circuit writes data to the memory cells of the memory cell array CA. It has a function to select the memory cell to which data will be written. Specifically, for example, The wiring WL[i] contains the memory cell AMu[i] and memory cell included in the circuit CS[i]. AMw[i], memory cell AMX[i], and memory cell AMR[i] are electrically connected. Because the circuit WLD is included in the memory cell array CA, the circuit CS[1] to the circuit By selecting one of the paths CS[m], the memory contained in the selected circuit CS is... Cell AMu, memory cell AMw, memory cell AMx, and memory cell AMr are the data writing It becomes the memory cell where data is written.

[0327] For example, data is stored in each memory cell included in the circuit CS[i] of the memory cell array CA. When writing, circuit WLD applies a high-level potential to wiring WL[i], and wiring WL By applying a low-level potential to wiring WL[1] to wiring WL[m] other than [i], the data The destination for writing is memory cell AMu[i] and memory cell A included in circuit CS[i]. You can select Mw[i], memory cell AMX[i], and memory cell AMR[i]. Cut.

[0328] As an example of circuit XLD, circuit XL can be applied to the above-mentioned arithmetic circuit MAC1. We will take D's explanation into consideration.

[0329] As an example of the INT circuit, the IN circuit can be applied to the MAC1 arithmetic circuit described above. We will take T's explanation into consideration.

[0330] As an example of circuit ACTV, circuit A can be applied to the above-mentioned arithmetic circuit MAC1. Please refer to the explanation provided by CTV.

[0331] <<Example configuration of memory cell array CA>> Next, in each of circuits CS[1] to CS[m] of the memory cell array CA The memory cells AMu, AMw, AMx, and AMR I will now explain an example of its configuration.

[0332] Figure 13 is a circuit diagram showing an example configuration of memory cell array CA. Memory cell array C A has the function of calculating the sum of products of multiple first data points and multiple second data points.

[0333] In the memory cell array CA shown in Figure 13, memory cell AMx, memory cell AMu, Each of the memory cells AMw and AMr is connected to transistor M1 and transistor It has a sta M2 and a capacity C1.

[0334] Also, memory cell AMx, memory cell AMu, memory cell AMw, and memory cell AM The transistors M1 and M2 included in each of r are as described above. The arithmetic circuit MAC1 has memory cells AMx, AMu, AMw, and Each of the memory cell AMr contains transistors M1 and M2 I will take the explanation into consideration.

[0335] The memory cells AMx, AMu, AMw, and AMR In each case, the first terminal of transistor M1 is electrically connected to the gate of transistor M2. They are connected. The first terminal of transistor M2 is electrically connected to the wiring VR. The first terminal of capacitor C1 is electrically connected to the gate of transistor M2.

[0336] In each of the cell memory AMu[1] to cell memory AMu[m], the transient The second terminal of transistor M1 is electrically connected to wiring WAD, and the second terminal of transistor M2 is It is electrically connected to the wiring BBL. Also, in the memory cell AMu[i], The gate of zista M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is connected to wiring It is electrically connected to line XAL[i]. Note that in memory cell AMu[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nu[1], and in the memory cell AMu[m], The electrical connection between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is designated as node Nu[m].

[0337] In each of the cell memory AMw[1] to cell memory AMw[m], the transient The second terminal of transistor M1 is electrically connected to wiring WAD, and the second terminal of transistor M2 is It is electrically connected to the wiring BAL. Also, in the memory cell AMw[i], The gate of zista M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is connected to wiring It is electrically connected to line XBL[i]. Note that in memory cell AMw[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nw[1], and in the memory cell AMw[m], The electrical connection between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is designated as node Nw[m].

[0338] In each of the memory cells AMx[1] to AMx[m], the transient The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 is connected to the wiring WBD. It is electrically connected to the wiring BAL. Also, in the memory cell AMx[i], The gate of zista M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is connected to wiring It is electrically connected to line XAL[i]. Note that in memory cell AMx[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nx[1], and in memory cell AMx[m], The electrical connection between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is denoted as node Nx[m].

[0339] In each of the cell memory AMr[1] to cell memory AMr[m], the transient The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 is connected to the wiring WBD. It is electrically connected to the wiring BBL. Also, in the memory cell AMr[i], The gate of zista M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is connected to wiring It is electrically connected to line XBL[i]. Note that in memory cell AMr[1], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, Let the electrical connection point be node Nr[1], and in the memory cell AMr[m], The electrical connection between the first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1 The connection point is denoted as node Nr[m].

[0340] The above nodes Nx[1], Nx[m], Nu[1], and Nu[m] Nodes Nw[1], Nw[m], Nr[1], and Nr[m] are, It functions as a holding node for each memory cell.

[0341] For information regarding the wiring VR, please refer to the explanation of the wiring VR included in the MAC1 calculation circuit described above. .

[0342] <Example of operation of the arithmetic circuit> Next, we will explain an example of the operation of the MAC5 arithmetic circuit.

[0343] Furthermore, the arithmetic circuit MAC5 here is configured as a memory cell array CA, as shown in Figure 14. Then, the memory cell array CA shown in Figure 13 is applied, and the circuit CMS shown in Figure 3A is applied as the circuit CMS. The arithmetic circuit MAC5A is defined below. Note that the arithmetic circuit MAC5A shown in Figure 14 mainly uses memory. Excerpts from the cell array CA, circuit CMS, circuit XLD, circuit WLD, and circuit INT. This is shown. Also, although not shown in the diagram, the circuit of the MAC5A arithmetic circuit in Figure 14 is ACTV. For this purpose, we will assume that the ACTV circuit shown in Figure 4A is applied.

[0344] Figure 15 shows a timing chart of an example of the operation of the MAC5A arithmetic circuit. The chart shows the wiring WL[1], wiring at times T21 to T29 and in the vicinity thereof. Wire WL [m], Wire SL4, Wire SL5, Wire SL7, Wire WAD, Wire WBD, Wire X AL[1], wiring XAL[m], wiring XBL[1], wiring XBL[m], node Nx[1 ], node Nx[m], node Nu[1], node Nu[m], node Nw[1], no This shows the potential fluctuations at node Nw[m], node Nr[1], and node Nr[m]. Oh, in Figure 15, high-level potentials are labeled "High" and low-level potentials are labeled "Low". ru.

[0345] In this example, the voltage supplied by the wiring VR is considered to be the ground potential.

[0346] <<Before time T21>> At times prior to time T21, nodes Nu[1] to Nu[m], node Nw[ 1] to node Nw[m], node Nx[1] to node Nx[m], and node Nr[ The potentials of each node from [1] to Nr[m] are assumed to be at ground potential. In Figure 15, the ground potential is denoted as GND.

[0347] Furthermore, the circuit WDD (not shown in Figure 14) is used to create wiring WAD and wiring WB. A low-level potential is input to each of D.

[0348] Furthermore, the circuit XLD connects wiring XAL[1] to wiring XAL[m] and wiring XBL [1], or each of the wiring XBL[m] has a reference potential V RFP This has been entered. Oh, V RFP This can be set to a potential higher than the ground potential, or a potential lower than the ground potential. Cut.

[0349] Furthermore, the circuit WLD provides low-level wiring to each of the wirings WL[1] through WL[m]. A bell potential is being input. Therefore, all memory cells AMx of the memory cell array CA are affected. Each of the following is contained in memory cell AMu, memory cell AMw, and memory cell AMr Transistor M1 is in the OFF state.

[0350] Furthermore, a low-level potential is input to each of the wires SL4, SL5, and SL7. Therefore, switches SW4A, SW5A, SW5B, and Switch SW7A and Switch SW7B are both set to the OFF state.

[0351] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential was input to wiring SL5. This is because the switch SW5A and switch SW included in the circuit INT are... Each of the 5Bs will be turned on.

[0352] When both switch SW5A and switch SW5B are turned ON, wiring B AL and wiring BBL are electrically connected to wiring VSL, and wiring BAL and Each of the wirings BBL is supplied with a potential from the wiring VSL. Wiring VSL then provides initialization potential to wiring BAL and wiring BBL, respectively. The wiring is configured so that the initialization potential is set to ground potential. Therefore, from time T21 to time T22 Between these points, the potentials of wiring BAL and wiring BBL are at ground potential.

[0353] Furthermore, all memory cells AMx, AMu, and memory cells of the memory cell array CA The first terminal of transistor M2 in each of the memory cells AMw and AMR Since the ground potential is supplied from the wiring VR, the first of each transistor M2 The voltage between terminal 1 and terminal 2 is 0V. Furthermore, nodes Nx[1] through Nx[m] , node Nu[1] to node Nu[m], node Nw[1] to node Nw[m], and Since the potentials of each node Nr[1] to node Nr[m] are at the ground potential, Each transistor M2 will be in the off state.

[0354] <<From time T22 to time T23>> Between time T22 and time T23, a high-level potential is input to wiring WL[1]. This is done. As a result, in the memory cell array CA, the memory cell AMu[1], Each of the Morisel AMw[1], memory cell AMx[1], and memory cell AMR[1] A high-level potential is applied to the gate of transistor M1 contained in it, and each The Rangista M1 is turned on.

[0355] Furthermore, between time T22 and time T23, the wiring WAD has a potential higher than ground potential. Wα [1] A large potential is input. At this time, the memory cell AMu[1] and the memory cell Each transistor M1 in AMw[1] is in the ON state, so wiring WAD The connection between and node Nu[1] is conductive, and between wiring WAD and node Nw[1] This leads to a conductive state. Therefore, the first terminal (node ​​N) of the capacity C1 of the memory cell AMu[1] u[1]), and the first terminal (node ​​Nw[1]) of the capacity C1 of the memory cell AMw[1] Each of them has a potential greater than the ground potential. Wα [1] A large potential is input.

[0356] Furthermore, between time T22 and time T23, the wiring WBD has a potential higher than ground potential. Wβ [1] A large potential is input. At this time, the memory cell AMx[1] and the memory cell Each transistor M1 in AMR[1] is in the ON state, so the wiring WBD The connection between and node Nx[1] is conductive, and between the wiring WBD and node Nr[1] This leads to a conductive state. Therefore, the first terminal (node ​​N) of the capacity C1 of the memory cell AMx[1] x[1]), and the first terminal (node ​​Nr[1]) of the capacity C1 of the memory cell AMar[1] Each of them has a potential greater than the ground potential. Wβ [1] A large potential is input.

[0357] Here, V W [1] is defined as shown in equation (1.1) described in this embodiment.

[0358] In equation (1.1), V W [1] is the voltage corresponding to the first of m first data points. Let's assume that V Wα [1], and V Wβ [1] Each of the m first data points It can be said that this is the voltage corresponding to the first element. Furthermore, if equation (1.1) is satisfied, V Wα [1], and V Wβ [1] The combination of voltages can be arbitrarily determined. For example Ba, V Wα [1] is V Wβ [1] A voltage higher than V Wβ [1] A voltage lower than that, or V Wβ [1] The voltage can be the same as in [1]. That is, V W [1] is positive voltage, 0, or A negative voltage may also be used.

[0359] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, each of the memory cells AMu[1] and AMw[1] In this configuration, the ground potential from the wiring VR is input to the first terminal of transistor M2. Therefore, the voltage between the first and second terminals of transistor M2 becomes approximately 0V. The first part of transistor M2 in each of the Morissel AMu[1] and memory cell AMw[1] No current flows between terminal 1 and terminal 2.

[0360] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, the memory cell AMx[1] and memory cell AMr[1] In each case, the ground potential from the wiring VR is input to the first terminal of transistor M2. Therefore, the voltage between the first and second terminals of transistor M2 is also approximately 0V. Therefore, the transistors of the memory cell AMx[1] and the memory cell AMr[1] No current flows between the first and second terminals of M2.

[0361] By the way, between time T22 and time T23, wiring WL[2] to wiring WL Each of the [m] values ​​has been continuously supplied with a low-level potential since before time T22. Therefore, in circuits CS[2] to CS[m] of the memory cell array CA, Each of the following is included in the memory cells Amu, AMw, AMX, and AMR. A low-level potential is applied to the gate of transistor M1, and each The Rangista M1 is in the off state. This means that the wiring WAD and wiring WBD are respectively The data entered into this node is from node Nu[2] to node Nu[m], node Nw[2 ] to node Nw[m], node Nx[2] to node Nx[m], and node Nr[2 It will not be written to node Nr[m] or any other node.

[0362] <<From time T23 to time T24>> Between time T23 and time T24, a low-level potential is input to wiring WL[1]. This is done. As a result, in the memory cell array CA, the memory cell AMu[1], Each of the Morisel AMw[1], memory cell AMx[1], and memory cell AMR[1] A low-level potential is applied to the gate of transistor M1 contained in this, and each The Rangista M1 will be turned off.

[0363] In each of the memory cells AMu[1] and AMw[1], transient When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMu[1] (Node Nu[1]), and the first terminal of the capacity C1 of the memory cell AMw[1] (Node Nw [1]) Each of these has a potential greater than the ground potential V Wα [1] A large potential is maintained. Also, note In each of the recell AMx[1] and memory cell AMr[1], transistor M When 1 is turned off, the first terminal of the capacitance C1 of the memory cell AMx[1] (NO Nx[1]), and the first terminal (node ​​Nr[1]) of the capacity C1 of the memory cell AMr[1] Each of the ) has a potential greater than the ground potential V Wβ [1] A large potential is maintained.

[0364] Also, between time T23 and time T24, between time T22 and time T23 The memory cells AMu[1], AMw[1], and memory in circuit CS[1]. The operation of writing potentials to cell AMx[1] and memory cell AMr[1] is the same as Similarly, memory cells AMu and A in circuits CS[2] to CS[m-1] The write operation of potentials to Mw, memory cell AMX, and memory cell AMR proceeds sequentially. Next, the following is performed. Specifically, for example, a signal that will be at a high potential for a certain period of time is wired WL[2] The signals are sequentially input to wiring WL[m-1], and wiring WAD and wiring W are connected according to the signal. By changing the potential of each of BD, the potential of circuits CS[2] to CS[m-1] can be changed. Each of the memory cells AMu, AMw, AMX, and AM A predetermined potential can be written to r. Here, the memory cell AMu[2] or memory Cell AMu[m-1], memory cell AMw[2] to memory cell AMw[m-1] contain, V Wα [2]~V Wα [m-1] will be written sequentially. Also, memory cell A Mu[2] to memory cell AMu[m-1], memory cell AMw[2] to memory cell A In parallel with the voltage writing operation to each of Mw[m-1], the memory cell AMx[2] Memory cell AMx[m-1], memory cell AMr[2], memory cell AMr[m- 1] contains V Wβ [2]~V Wβ [m-1] will be written sequentially.

[0365] At this time, memory cell A located in row p (where p is an integer between 2 and m-1 inclusive) Mx[p] has a voltage V. Wβ [p] is retained, and the memory cell AMu[p] has a voltage V Wα [p] is retained. Here, similar to equation (1.1), the p-th of the m first data points Voltage V W [p] is defined as shown in equation (1.2) described in this embodiment.

[0366] In equation (1.2), V W [p] is the voltage corresponding to the p-th of the m first data points. Let's assume that V Wα [p], and V Wβ Each of [p] also contains m first data points. This can be said to be the voltage corresponding to the p-th element. Furthermore, if equation (1.2) is satisfied, V Wα [p], and V Wβ The voltage combinations for [p] can be arbitrarily determined. For example Ba, V Wα [p] is V Wβ A voltage higher than [p], V Wβ A voltage lower than [p], or V Wβ It can be the same voltage as [p]. That is, V W [p] is positive voltage, 0, or A negative voltage may also be used.

[0367] <<From time T24 to time T25>> Between time T24 and time T25, a high-level potential is input to wiring WL[m]. This is done. As a result, in the memory cell array CA, the memory cell AMu[m], Each of the following: Morisel AMw[m], memory cell AMx[m], and memory cell AMu[m] A high-level potential is applied to the gate of transistor M1 contained in it, and each The Rangista M1 is turned on.

[0368] Furthermore, between time T24 and time T25, the wiring WAD has a potential higher than ground potential. WαA large potential [m] is input. At this time, the memory cell AMu[m] and the memory cell Each transistor M1 in AMw[m] is in the ON state, so wiring WAD The connection between and node Nu[m] is conductive, and between wiring WAD and node Nw[m] This leads to a conductive state. Therefore, the first terminal (node ​​N) of the capacity C1 of the memory cell AMu[m] u[m]), and the first terminal (node ​​Nw[m]) of the capacity C1 of the memory cell AMw[m] Each of them has a potential greater than the ground potential. Wα [m] A large potential is input.

[0369] Furthermore, between time T24 and time T25, the wiring WBD has a potential higher than ground potential. Wβ A potential of [m] large is input. At this time, the memory cell AMx[m] and the memory cell Each transistor M1 in AMR[m] is in the ON state, so the wiring WBD The connection between and node Nx[m] is conductive, and the connection between wiring WBD and node Nr[m] This leads to a conductive state. Therefore, the first terminal (node ​​N) of the capacity C1 of the memory cell AMx[m] x[m]), and the first terminal (node ​​Nr[m]) of the capacity C1 of the memory cell AMr[m] Each of them has a potential greater than the ground potential. Wβ [m] A large potential is input.

[0370] Here, V W [m] is defined as shown in equation (1.3) described in this embodiment.

[0371] In equation (1.3), V W [m] is the voltage corresponding to the mth of the m first data points. Let's assume that V Wα [m], and V Wβ Each of [m] also contains m first data points. This can be said to be the voltage corresponding to the mth element. Furthermore, if equation (1.3) is satisfied, V Wα [m], and V Wβ The combination of voltages [m] can be arbitrarily determined. For example Ba, V Wα [m] is V Wβ A voltage higher than [m], V Wβ A voltage lower than [m], or V Wβ It can be the same voltage as [m]. That is, V W [m] is positive voltage, 0, or A negative voltage may also be used.

[0372] Since switch SW5A is in the ON position, the ground potential is applied to wiring BAL. It is being powered. Also, in memory cell AMu[m] and memory cell AMw[m], Since the ground potential from the wiring VR is input to the first terminal of transistor M2, The voltage between the first and second terminals of the generator M2 is approximately 0V. Therefore, memory cell A Mu[m] and the first terminal-second terminal of transistor M2 of memory cell AMw[m] No current flows between the two terminals.

[0373] Similarly, since switch SW5B is in the ON position, wiring BBL is connected to ground. A potential is input. Also, the memory cell AMx[m] and memory cell AMr[m] In each case, the ground potential from the wiring VR is input to the first terminal of transistor M2. Therefore, the voltage between the first and second terminals of transistor M2 is also approximately 0V. Therefore, the respective transistors of memory cell AMx[m] and memory cell AMr[m] No current flows between the first and second terminals of M2.

[0374] By the way, between time T24 and time T25, wiring WL[1] to wiring WL Each of [m-1] has been continuously supplied with a low-level potential since before time T04. Therefore, in circuits CS[1] to CS[m-1] of the memory cell array CA, The memory cells AMu, AMw, AMx, and AMR A low-level potential is applied to the gate of transistor M1 contained within it, Transistor M1 is in the OFF state. As a result, wiring WAD and wiring WBD The data entered into each of these is from node Nu[1] to node Nu[m-1], no Node Nw[1] to node Nw[m-1], node Nx[1] to node Nx[m-1] It will not be written to nodes Nr[1] through Nr[m-1].

[0375] <<From time T25 to time T26>> Between time T25 and time T26, a low-level potential is input to wiring WL[m]. This is done. As a result, in the memory cell array CA, the memory cell AMu[m], Each of the following: Morisel AMw[m], memory cell AMx[m], and memory cell AMR[m] A low-level potential is applied to the gate of transistor M1 contained in this, and each The Rangista M1 will be turned off.

[0376] In each of the memory cells AMu[m] and AMw[m], transient When the M1 is turned off, the first terminal of the capacitance C1 of the memory cell AMu[m] (Node Nu[m]), and the first terminal of the capacity C1 of the memory cell AMw[m] (Node Nw [m]) Each of these is V greater than the ground potential Wα[m] A large potential is maintained. Also, note In each of the recell AMx[m] and memory cell AMr[m], transistor M When 1 is turned off, the first terminal of the capacitance C1 of the memory cell AMx[m] (NO The first terminal (node ​​Nr[m]) of the capacity C1 of the memory cell AMr[m] Each of the ) has a potential greater than the ground potential V Wβ A large potential [m] is maintained.

[0377] The operation between time T21 and time T26 resulted in the memory cell array CA being included The memory cells AMx, AMu, AMw, and AMR are Each can be programmed with a voltage corresponding to the first data point.

[0378] <<From time T26 to time T27>> Between time T26 and time T27, a low-level potential is input to wiring SL5. As a result, in circuit INT, switches SW5A and SW5B This will turn off.

[0379] <<From time T27 to time T28>> Between time T27 and time T28, wiring XAL[1] to wiring XAL[m] Each of these is input with a potential corresponding to m second data points. Here, for example, circuit X The potential input from LD to wiring XAL[1] is set to be V lower than the ground potential. Xα [1] High potential and The potential input from circuit XLD to wiring XAL[p] is set to be V higher than the ground potential. Xα [p] The potential is set to be high, and the potential input from circuit XLD to wiring XAL[m] is set to be V higher than the ground potential. Xα [m] The potential is set to be high.

[0380] The potential of wiring XAL[1] is V from the ground potential. Xα [1] Therefore, memory cell A The second terminal of the capacitance C1 of Mu[1] and the memory cell AMx[1] is V Xα [1] will be applied. At this time, node Nu[1] and node Nx[1] Since each is electrically floating, the capacitive coupling of capacitor C1 causes node Nu[1 The potentials of ] and node Nx[1] change.

[0381] In each of the memory cells AMu[1] and AMx[1], The increase in gate potential of sta M2 corresponds to the change in potential of wiring XAL[1], and the configuration of the memory cell. The potential is obtained by multiplying by the capacitive coupling coefficient determined by the capacitance C1. This is calculated based on the gate capacitance and parasitic capacitance of transistor M2. In this example, Let h be the capacitive coupling coefficient of the Moricell AMu and the memory cell AMx, respectively.

[0382] Therefore, the potential change of wiring XAL[1] is V Xα [1] When this is the case, node Nu[1] The potential changes at node Nx[1] are, Xα [1] This means no. The potential of Nu[1] is V Wα [1]+hV Xα [1], and the potential of node Nx[1] V Wβ [1]+hV Xα [1]

[0383] In this example, the memory cell AMu[1] included in the memory cell array CA , and for memory cells other than memory cell AMx[1], the respective capacitive coupling coefficients are Let's explain it using h.

[0384] Therefore, the potential of wiring XAL[p] is V from the ground potential. Xα [p] rises, At the second terminal of the capacitance C1 of the Moricell AMu[p] and memory cell AMx[p] V Xα [p] will be applied. At this time, node Nu[p] and node N Since each of x[p] is in an electrically floating state, capacitive coupling with capacitor C1 results in no The potentials of node Nu[p] and node Nx[p] change. Specifically, the node The potential of Nu[p] is V Wα [p] +hV Xα [p], and the potential at node Nx[p] is , V Wβ [p] +hV Xα [p]

[0385] Furthermore, the potential of the wiring XAL[m] is V from the ground potential. Xα [m] increases, The second terminal of the capacitance C1 of cell AMu[m] and memory cell AMx[m] is: V Xα [m] will be applied. At this time, node Nu[m] and node Nx[ Since each of [m] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of node u[m] and node Nx[m] change. Specifically, node Nu The potential at [m] is V Wα [m]+hV Xα [m], and the potential at node Nx[m] is V Wβ [m]+hV Xα [m]

[0386] Also, between time T27 and time T28, wiring XBL[1] to wiring XBL Each of [m] is input with a potential corresponding to m second data points. Here, for example, The potential input from circuit XLD to wiring XBL[1] is set to be V higher than the ground potential. Xβ [1] high Let the potential be such that the potential input from circuit XLD to wiring XBL[p] is V greater than the ground potential. Xβ [p] As a high potential, the potential input from circuit XLD to wiring XBL[m] is set to be higher than the ground potential. RimoV Xβ [m] The potential is set to be high.

[0387] The potential of wiring XBL[1] is V from the ground potential. Xβ [1] Therefore, memory cell A The second terminal of the capacitance C1 of Mw[1] and the memory cell AMr[1] is V Xβ [1] will be applied. At this time, node Nw[1] and node Nr[1] Since each is electrically floating, the capacitive coupling of capacitance C1 causes node Nw[1 The potentials of ] and node Nr[1] change.

[0388] In this example, the memory cell AMw and the memory cell included in the memory cell array CA are shown. The respective capacitive coupling coefficients of memory cell AMr are memory cell AMx and memory cell AM We will explain it using h, similar to how we explain u.

[0389] Therefore, the potential change of wiring XBL[1] is V Xβ [1] When node Nw[1] The potential changes at node Nr[1] are, Xβ [1] This means no. The potential of Nw[1] is V Wα [1]+hV Xβ [1], and the potential of node Nr[1] V Wβ [1]+hV Xβ [1]

[0390] Furthermore, the potential of wiring XBL[p] is V from the ground potential. Xβ [p] is raised, The second terminal of the capacitance C1 of cell AMw[p] and memory cell AMr[p] is: V Xβ [p] will be applied. At this time, node Nw[p] and node Nr[ Since each of p] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of w[p] and node Nr[p] change. Specifically, node Nw The potential of [p] is V Wα [p] +hV Xβ [p], and the potential at node Nr[p] is V Wβ [p] +hV Xβ [p]

[0391] Furthermore, the potential of wiring XBL[m] is V from the ground potential. Xβ [m] increases, The second terminal of the capacitance C1 of cell AMw[m] and memory cell AMr[m] is: V Xβ [m] will be applied. At this time, node Nw[m] and node Nr[ Since each of [m] is in an electrically floating state, the capacitive coupling of capacitor C1 leads to node N The potentials of w[m] and node Nr[m] change. Specifically, node Nw The potential at [m] is V Wα [m]+hV Xβ [m], and the potential at node Nu[m] is V Wβ [m]+hV Xβ [m]

[0392] Here, V X [1], V X [p], and V X Each of [m] is described in this embodiment. It is defined as shown in equations (1.4) through (1.6).

[0393] In each of equations (1.4) through (1.6), V X [1]~V X [m]'s That will be the voltage corresponding to the second data. In other words, V Xα [1]~V Xα [m], and V Xβ [1]~V Xβ Each of the [m] values ​​can be said to be a voltage corresponding to the second data. Furthermore, if equations (1.4) through (1.6) are satisfied, V Xα [i], and V X β The combination of voltages in [i] can be arbitrarily determined. For example, V Xα [i] is V Xβ [i] A voltage higher than V Xβ [i] A voltage lower than V Xβ [i] Same voltage It can be done that way. In other words, V X [i] may be a positive voltage, 0, or a negative voltage.

[0394] <<From time T28 to time T29>> Between time T28 and time T29, high levels occurred on wiring SL4 and wiring SL7. A potential is input. This activates switches SW7A and S in the circuit CMS. Both W7B and switch SW4A in circuit ACTV are turned ON.

[0395] At this time, memory cell AMx[1], <memory cell AMx[m], and memory cell AM The second terminal of transistor M2 contained in each of w[1] to memory cell AMw[m] This is in a conductive state with the first terminal of transistor M3A included in circuit CM via wiring BAL. This is the result. Also, memory cells AMx[1] to AMx[m], and memory cell A The second terminal of transistor M2 contained in each of Mw[1] to memory cell AMw[m] The child is in a conductive state with the first terminal of circuit IVC included in circuit ACTV via wiring BAL. It becomes so. Also, memory cell AMu[1] to memory cell AMu[m], and memory cell AM The second terminal of transistor M2 contained in each of r[1] to memory cell AMr[m] This is in a conductive state with the first terminal of transistor M3B included in circuit CM via wiring BBL. This is the result.

[0396] Here, memory cell AMx, memory cell AMu, memory cell AMw, and memory cell A Let's consider the current flowing from the second terminal to the first terminal of each transistor M2 in Mr.

[0397] Wiring BAL to the first terminal via the second terminal of transistor M2 of memory cell AMx[1] The current flowing through the child is I AMx[1] In that case, I AMx[1] This is as described in this embodiment. It can be expressed similarly to equation (1.7).

[0398] In equation (1.7), k is the channel length, channel width, and mobility of transistor M2. It is a constant determined by the capacitance of the gate insulating film, etc. Also, V th This is the transistor M2 This is the threshold voltage. Note that the constant k refers not only to the memory cell AMx but also to the memory cell AMu This also applies to memory cell AMw and memory cell AMr. In addition to Morisel AMx, this also includes memory cell AMu, memory cell AMw, and memory cell AM The threshold voltage of transistor M2 that r possesses is also V th Let's assume that.

[0399] Furthermore, via the wiring BAL through the second terminal of transistor M2 of memory cell AMx[m] The current flowing through the first terminal is I AMx[m] In that case, I AMx[m] In this embodiment, It can be expressed in the same way as equation (1.7) mentioned above.

[0400] In other words, each of the wiring BALs from memory cell AMx[1] to memory cell AMx[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I x In that case, I x is, formula From (1.7) and equation (1.8), it can be expressed in the same way as equation (1.9) described in this embodiment. It is possible.

[0401] Similarly, from the wiring BAL, via the second terminal of transistor M2 of memory cell AMw[1] The current flowing through the first terminal is I AMw[1] The wiring BAL is connected to the memory cell AMw[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMw[m] If that's the case K, I AMw[1] , and I AMw[m] Each of these is the formula (1. 10) and can be expressed similarly to equation (1.11).

[0402] In other words, each of the wiring BALs from memory cell AMw[1] to memory cell AMw[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I w In that case, I w is, formula From (1.10) and equation (1.11), a table can be formed similarly to equation (1.12) described in this embodiment. It is possible.

[0403] Similarly, from the wiring BBL through the second terminal of transistor M2 of memory cell AMu[1] The current flowing through the first terminal is I AMu[1] The wiring BBL is connected to the memory cell AMu[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMu[m] If that's the case K, I AMu[1] , and I AMu[m] Each of these is the formula (1. It can be expressed similarly to equation (13) and equation (1.14).

[0404] In other words, each of the connections from the wiring BBL to the memory cell AMu[1] to the memory cell AMu[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I u In that case, I u is, formula From (1.13) and equation (1.14), a table can be formed similarly to equation (1.15) described in this embodiment. It is possible.

[0405] Similarly, from the wiring BBL through the second terminal of transistor M2 of memory cell AMr[1] The current flowing through the first terminal is I AMr[1] The wiring BBL is connected to the memory cell AMR[m] The current flowing from the second terminal of transistor M2 to the first terminal is I AMr[m] If that's the case K, I AMr[1] , and I AMr[m] Each of these is the formula (1. Similar to equation (16) and equation (1.17), it can be expressed by the following equation.

[0406] In other words, each of the connections from wiring BBL to memory cell AMr[1] to memory cell AMr[m] The sum of the amounts of current flowing through the second terminal of transistor M2 is I r In that case, I r is, formula From (1.16) and equation (1.17), a table can be formed similarly to equation (1.18) described in this embodiment. It is possible.

[0407] Between time T28 and time T29, switch SW included in circuit CMS 7B is in the ON state, and switch SW5B, which is included in circuit INT, is OFF. Because it is in this state, memory cell AMu[1] to memory cell A is connected via wiring BBL. Mu[m] and the total current flowing through memory cell AMR[1] to memory cell AMR[m] Japanese I u +I r This flows from the wiring VHE via the first terminal of transistor M3B. The voltage at the first terminal (gate) of transistor M3B is equal to the current I u +I r voltage corresponding to This is the result.

[0408] Furthermore, since circuit CM is a current mirror circuit, the first of transistor M3B The amount of current flowing between terminal 1 and terminal 2 is the same as the current flowing between terminal 1 and terminal 2 of transistor M3A. The amount of current becomes approximately equal to the current. Between time T12 and time T13, in circuit CMS The included switch SW7A is in the ON state, so the wiring from VHE to the transistor The amount of current flowing through the M3A to the wiring BAL is I u +I r This is the result.

[0409] Furthermore, the wiring BAL contains memory cells AMx[1] to AMx[m], and Because the Morissel AMw[1] or memory cell AMw[m] is electrically connected, wiring From BAL to memory cell AMX[1] to memory cell AMX[m] x The amount of current that flows, Furthermore, wiring BAL to memory cell AMw[1] to memory cell AMw[m] w Current amount It plays.

[0410] Furthermore, switches SW5A and SW5B included in circuit INT are in the OFF state. In this state, the switch SW4A included in the ACTV circuit is in the ON position. Therefore, from wiring BAL, via switch SW4A, circuit I included in circuit ACTV Current flows through the first terminal of VC. The amount of this current is I EV In that case, I EV This implementation It can be expressed in the same way as equation (1.19) described in the section on form.

[0411] Therefore, equation (1.19) is derived from equations (1.1) through (1.6), equation (1.9), and equation ( By using equations (1.12), (1.15), and (1.18), we can obtain equation (1.20 Similar to the above, it can be written as follows:

[0412]

number

[0413] From equation (1.23), the amount of current I input from wiring BAL to circuit ACTV is given by EV is, 1. Potential V corresponding to data W [1]~V W [m] and the potential V corresponding to the second data. X [1] ~V X It is proportional to the sum of the products of [m]. In other words, the sum of the products of the first and second data is proportional to the amount of current. I EV It can be expressed as follows.

[0414] I EVAs the current flows, The third terminal of circuit IVC is connected to I EV A voltage corresponding to the value is output. Subsequently, that voltage is used in the circuit. The voltage is input to the first terminal of ACF, and this voltage is used to predefined by the ACF circuit. The calculation of the function system is performed, and the result of the calculation is expressed as voltage (or current, etc.) on the wiring N. Output from IL.

[0415] By the way, each of equations (1.1) through (1.3) is V Wα [i]=V Wβ [i] +V W It can be transformed into [i]. That is, memory cell AMu[i], and memory cell In AMw[i], V Wβ [i]+V W [i] is retained. V Wβ [i] is any Since it can be expressed as voltage, V Wβ [1]~V Wβ Each of the [m] is given the same voltage. This is also acceptable. For example, V Wβ [1]~V Wβ Each of [m] is V PR In that case, Each of the memory cells AMu[i] and AMw[i] contains V PR +V W [i ] is maintained, and each of the memory cells AMx[i] and AMr[i] contains V PR This will be retained. In this way, V Wβ [1]~V Wβ Each of [m] All V PR By doing so, V PR Using this as the reference voltage, the memory cell AMu and the memory cell AMw holds a voltage that is the reference voltage plus a voltage corresponding to the first data, and the memory cell By maintaining a reference voltage in AMx and memory cell AMr, the same can be expressed in equation (1.23). It can perform calculations.

[0416] Furthermore, each of equations (1.4) through (1.6) is V Xα [i]=V Xβ [i]+V X [i] can be transformed into this. That is, between time T11 and time T12 , wiring XAL[i] is V Xβ [i]+V X [i] is entered. V Xβ [i] is, Since it can be set to any voltage, V Xβ [1]~V Xβ Each of the [m] is the same It can also be expressed as voltage. For example, V Xβ [1]~V Xβ Each of [m] is V RFP so At that time, V is present in the wiring XAL[i]. RFP +V X [i] is input, and wiring XBL[i] has V RFP This will be input. In this way, V Xβ [1]~V Xβ Each of [m] V all RFP By doing so, V RFP Using this as the reference voltage, the wiring XAL is connected to the reference voltage. The voltage applied according to the second data is input, and the reference voltage is input to the wiring XBL. Similarly, the operation in equation (1.23) can be performed.

[0417] <Example of semiconductor device configuration 5> Here, unlike the MAC5 arithmetic circuit in Figure 12, multiple first data and multiple second data This document describes a semiconductor device capable of performing multiply-accumulate operations with respect to a specific component.

[0418] The arithmetic circuit MAC6 in Figure 16, like the arithmetic circuit MAC5 in Figure 12, processes multiple first data This is an example of a semiconductor device capable of performing sum-of-accumulate operations with multiple second data points. Note that the arithmetic circuit MA C6 is located in the circuit configuration of circuit CMS, and wiring BBL is electrically connected to circuit ACTV. It differs from the MAC5 arithmetic circuit in that respect.

[0419] The circuit CMS included in the arithmetic circuit MAC6 consists of current source CSA and current source CSB, It has. The input terminal of the current source CSA is electrically connected to the wiring VHE, and the output of the current source CSA The power terminal is electrically connected to wiring BAL. The input terminal of the current source CSB is connected to wiring VH Electrically connected to E, the output terminal of the current source CSB is electrically connected to wiring BBL. ru.

[0420] Furthermore, the circuit CMS included in the arithmetic circuit MAC6 has the circuit configuration described above. Therefore, it does not function as a current mirror circuit as shown in Figures 3A and 3B.

[0421] The wiring VHE is similar to the explanation given for circuit CMS in Figures 3A and 3B, as an example. This can be used as wiring to provide a constant voltage. For example, the constant voltage can be a high-level potential. It is preferable to do so.

[0422] Current source CSA and current source CSB each require that the power supply potential be input to their input terminals. It has the function of outputting a constant current to the output terminal. Note that current source CSA and current source CSB It is preferable that the amount of current each of these outputs to its output terminal is equal to that of the others. Specifically, The amount of current flowing from the output terminal of current source CSA to wiring BAL is the same as the amount of current flowing from the output terminal of current source CSB. The current flowing through the wiring BBL is 0.85 times or more, 0.9 times or more, or 0.95 times or more. It is preferable that the ratio be 1.05 times or less, 1.1 times or less, or 1.15 times or less. This is preferable. Note that the lower and upper limits mentioned above can be combined. Let's assume that.

[0423] Furthermore, as mentioned above, wiring BBL is electrically connected to circuit ACTV. Figure 1 In 6, circuit ACTV is, for example, the current flowing from wiring BAL to circuit ACTV, and A function that outputs a voltage corresponding to the difference in current between the current flowing from line BBL to circuit ACTV and the current flowing from line BBL to circuit ACTV. And, a function that performs calculations according to a predefined set of functions using the said voltage, and the function It is preferable to have a configuration that includes a function to output the result of the calculation to the NIL wiring.

[0424] Specifically, the ACTV circuit included in the MAC6 arithmetic circuit in Figure 16 is, for example, The circuit shown in Figure 9 can be configured as ACTV.

[0425] The ACTV circuit in Figure 9, for example, applies a high-level potential to the wiring SL4, and switches SW... By turning on both 4A and switch SW4B, the wiring BAL The current from circuit IVC can be passed to the first terminal of circuit I, and the current from wiring BBL can be passed to circuit I It can be routed to the third terminal of the VC.

[0426] For example, in the arithmetic circuit MAC6 in Figure 16, the current source CSA and the current source CSB The amount of current that each of them flows through wiring BAL and wiring BBL is I CS And, notes from the wiring BAL The sum of the amounts of current flowing through the recell AMX[1] or memory cell AMX[m] is I x and The total amount of current flowing from line BAL to memory cells AMw[1] to AMw[m] is defined as I w Then, the amount of current flowing from wiring BAL to the first terminal of circuit IVC is I CS -I x -I w This is the case. Also, the total amount of current flowing from wiring BBL to memory cells AMu[1] to AMu m] is defined as I u and the total amount of current flowing from wiring BBL to memory cells AMr[1] to AMr[m] is defined as I r Then, the amount of current flowing from wiring BBL to the third terminal of circuit IV C is I CS -I u -I r This is the case.

[0427] When circuit IVC in FIG. 9 is a subtraction circuit (for example, when loads LEA and LEB are resistors ), the second terminal of circuit IVC outputs a voltage corresponding to the difference between the amount of current input to the first terminal of circuit IVC and the amount of current input to the third terminal of circuit IVC (-I u -I r +I x +I w ). This difference in current amount is determined according to the sum of products of a plurality of first data and a plurality of second data. Therefore, the voltage output from the second terminal of circuit IVC can be said to be a voltage corresponding to the result of the sum of products of a plurality of first data and a plurality of second data. Subsequently, this voltage is input to the first terminal of circuit ACF, and by performing operations on a function system defined in advance by circuit ACF using this voltage, the operation result is output as a voltage (or,

[0428] current, etc.) from wiring NIL. ) and the operation result is output from wiring NIL as a voltage (or current, etc.). ​

[0429] <Semiconductor device configuration example 6> Next, there are several different arithmetic circuits, MAC5 in Figure 12 and MAC6 in Figure 16. This document describes a semiconductor device capable of performing sum-of-products operations between a first data point and multiple second data points.

[0430] The arithmetic circuit MAC7 in Figure 17 is similar to the arithmetic circuits MAC5 and MAC6, and is multifaceted. This is an example of a semiconductor device capable of performing a sum-of-products operation between a first numerical data point and multiple second data points. Circuit MAC7 is a modified version of arithmetic circuit MAC5, and the wiring X in arithmetic circuit MAC5 Combine BL[1] and wiring XBL[2] into a single wiring XBL[1,2], and perform calculations. In path MAC5, wiring XBL[m-1] and wiring XBL[m] are connected to a single wiring XBL[m- It differs from the MAC5 arithmetic circuit in that it is grouped as 1,m. In other words, Figure 17 The number of XBL wires in the MAC7 arithmetic circuit is m / 2. However, the number of arithmetic circuits shown in Figure 17 In MAC7, m is defined as an even number greater than or equal to 2.

[0431] Therefore, the arithmetic circuit MAC7 shown in Figure 17 has memory cell AMw[1] and memory cell AMr[1], memory cell AMw[2], and memory cell AMR[2] are connected via XBL. [1,2] are electrically connected to memory cell AMw[m-1] and memory cell AMr[m -1], memory cell AMw[m], and memory cell AMR[m] are connected via wiring XBL[m- It is configured to be electrically connected to [1,m].

[0432] Furthermore, in the memory cell array CA shown in Figure 17, each memory cell is connected to the arithmetic circuit M. Similar to AC5, it is arranged in a 2m x 2m matrix. Figure 17 shows an example. Memory cell AMu[i] is located at the address 2i-1 row 1 column, and memory cell AMw [i] is located at the address 2i row 1 column, and memory cell AMx[i] is at 2i-1 row 2 The memory cell AMr[i] is located at the address of row 2i, column 2. Memory cell AMu[i+1] is located at the address 2i+2 row 1 column, and memory cell A Mw[i+1] is located at the address 2i+1 row 1 column, and memory cell AMx[i+1] It is located at the address 2i+2 rows and 2 columns, and the memory cell AMr[i+1] is located at row 2i+1. It is located in two address columns. Note that in the arithmetic circuit MAC7 in Figure 17, i is 1 or less. It is an odd number less than or equal to m.

[0433] Therefore, although not shown in Figure 17, memory cell AMw[i] and memory cell AMr[ i], memory cell AMw[i+1], and memory cell AMR[i+1] are connected via wiring XB It is electrically connected to L[i,i+1].

[0434] Next, an example of the operation of the MAC7 arithmetic circuit in Figure 17 will be explained. For an example of operation, refer to the example of operation in the timing chart in Figure 15, and the timing This section will primarily explain the parts not covered in the chart.

[0435] V is a voltage corresponding to multiple first data points. W [1]~V W Let [m] and equation (1.1) V satisfies equation (1.3) Wα [1]~V Wα [m], and V Wβ [1]~ V Wβ Define [m]. Also define memory cell AMw[1] to memory cell AMw[m], Each of the memory cells AMu[1] to AMu[m] has a voltage V Wα [1]No To V Wα [m] is held, memory cell AMx[1] to memory cell AMx[m], memo V in the recell AMR[1] or memory cell AMR[m] Wβ [1]~V Wβ [m] holds It is assumed that it is.

[0436] Furthermore, the voltage corresponding to multiple second data points is V X [1]~V X Let [m] and equation (1. 4) V such that equations (1.6) are satisfied Xα [1]~V Xα [m], and V Xβ [1 ]~V Xβ Define [m]. However, V Xβ [i] and V Xβ [i+1] has the same voltage. Assuming, V Xβ [i]=V Xβ [i+1]=V Xβ Let [i,i+1]. Then, voltage V corresponding to multiple second data points. X [1]~V X By defining [m], the number of operations In circuit MAC7, a voltage V is applied to each of the wires XAL[1] to XAL[m]. Xα [ 1]~V Xα [m] can be entered, and wiring XBL[1,2] to wiring XBL V for each of [m-1,m] Xβ [1,2] to V Xβ Enter [m-1,m] It is possible.

[0437] Between time T27 and time T28, the arithmetic circuit MAC7, wiring XAL[1] Or, a voltage V is applied to each of the wires XAL[m]. Xα [1]~VXα Enter [m] and distribute V Xβ [1,2] to V Xβ By inputting [m-1,m], multiple first data are generated, similar to the MAC5 arithmetic circuit. It can perform sum-of-product operations and function operations between a data point and multiple second data points.

[0438] The MAC7 arithmetic circuit has fewer XBL wires than the MAC5 arithmetic circuit. Therefore, the circuit area of ​​the arithmetic circuit MAC7 can be made smaller than that of the arithmetic circuit MAC5. It can. Also, the number of voltage signals input to the wiring XBL of the arithmetic circuit MAC7 is the same as the number of voltage signals input to the arithmetic circuit MAC Since it is less than 5, the power consumption of the arithmetic circuit MAC7 is less than that of the arithmetic circuit MAC5. It can be done.

[0439] Note that in the above, V Xβ [i] and V Xβ [i+1] was assumed to be the same voltage, As explained in the example of operation of the MAC5 arithmetic circuit, V Xβ [1]~V Xβ [m]'s If they all have the same voltage (for example, V RFP ) may be made to be the case.

[0440] <Example of semiconductor device configuration 7> Next, the arithmetic circuit MAC5 in Figure 12, the arithmetic circuit MAC6 in Figure 16, and the arithmetic circuit in Figure 17. Unlike MAC7, this semiconductor is capable of performing sum-of-products operations with multiple first data points and multiple second data points. Let me explain the device.

[0441] The arithmetic circuit MAC8 in Figure 18 consists of arithmetic circuits MAC5, MAC6, and MAC Similar to 7, a semiconductor device capable of performing sum-of-accumulate operations with multiple first data and multiple second data. This is an example. The arithmetic circuit MAC8 is a modified version of the arithmetic circuit MAC5, and is a memory cell array. It differs from the MAC5 arithmetic circuit in that it has a circuit CSb in CA.

[0442] In the arithmetic circuit MAC8 shown in Figure 18, circuit CSb is a memory cell AMub, memory It has cell AMwb, memory cell AMxb, and memory cell AMrb. Note that memory cell A Mub is paired with the memory cell AMu in each of circuits CS[1] to CS[m]. In this case, the memory cell AMwb is located in each of circuits CS[1] to CS[m]. It corresponds to the Morissel AMw, and the memory cell AMxb is of circuit CS[1] to circuit CS[m] Each corresponds to a memory cell AMx, and the memory cell AMrb is located in circuit CS[1] This corresponds to the memory cell AMr in each of the circuits CS[m].

[0443] Next, we will explain an example of the operation of the MAC8 arithmetic circuit. Regarding this, refer to the example operation of the timing chart in Figure 15, and apply the following to the timing chart. This section will primarily explain the parts not mentioned.

[0444] V is a voltage corresponding to multiple first data points. W [1]~V W Let [m] and equation (1.1) V satisfies equation (1.3) Wα [1]~V Wα [m], and V Wβ [1]~ V Wβ Define [m]. Also define memory cell AMw[1] to memory cell AMw[m], Each of the memory cells AMu[1] to AMu[m] has a voltage V Wα [1]No To V Wα[m] is held, memory cell AMx[1] to memory cell AMx[m], memo V in the recell AMR[1] or memory cell AMR[m] Wβ [1]~V Wβ [m] holds It is assumed that it is.

[0445] Also, for example, between time T25 and time T26 in the timing chart of Figure 15 Furthermore, the memory cell AMub and memory cell AMwb have a voltage of V Wbα It holds memory and Memory cells AMxb and AMrb have a voltage of V Wbβ It shall retain V. W b =V Wbα -V Wbβ Voltage V that satisfies this condition Wb Define.

[0446] Also, for example, between time T27 and time T28 in the timing chart of Figure 15 And the wiring XALb has a voltage V Xbα The input is, and the voltage V is applied to the wiring XBLb. Xbβ Enter It shall be assumed that V Xb =V Xbα -V Xbβ Voltage V that satisfies this condition Xb Define ru.

[0447] At this time, between time T28 and time T29 in the timing chart of Figure 15 The amount of current flowing through the wiring BAL for each of the memory cells AMwb and AMxb. to I AMwb , I AMxb In that case, I AMwb , and I AMxb Each of them is I A Mwb =k(V Wbα +V Xbβ -V th )2 , I AMxb =k(V Wbβ +V Xbα - V th ) 2 It can be expressed as follows. Also, the memory cell AMub and memory cell AMrb Each of them determines the amount of current flowing through wiring BBL. AMub , I AMrb In that case, I AMub , and I AMrb Each of them is I AMub =k(V Wbα +V Xbα -V th ) 2 , I AMrb =k(V Wbβ +V Xbβ -V th ) 2 It can be expressed as follows.

[0448] Furthermore, between time T28 and time T29 in the timing chart of Figure 15, Current I flowing from line BAL to circuit ACTV EV This is given by the following equation. So, I b =I AMub +I AMrb +I AMxb +I AMwb That is what they say.

[0449]

number

[0450] Equation (1.24), like equation (1.22), can be expressed by giving any value to the result of the sum of products. This corresponds to the formula used in calculations in, for example, hierarchical neural networks. Then, the weight coefficient and the result of the sum-of-products operation with the neuron's signal are set to an arbitrary value. It can be used in calculations that introduce bias.

[0451] Also, for example, the flow from wiring BBL to memory cell AMub and memory cell AMrb Sum of currents I AMub +I AMrb Rather, wiring BAL to memory cell AMxb, and memory Sum of currents flowing through Ricell AMwb AMxb +I AMwb By increasing the formula (1.24) I b It is possible to make it a value less than 0. In other words, for the result of the sum of products Therefore, any given value can also be a negative value.

[0452] Note that the memory cells AMub, AMwb, AMxb, and memory cells In at least one of the AMrb transistors, the current flows between the first and second terminals of transistor M2. The current may be set to 0. For example, memory cell AMwb, memory cell AMxb, and memory The amount of current flowing between the first and second terminals of each transistor M2 in the Ricell AMrb. By setting it to 0, the current I in equation (1.24) b is, I b =I AMub It can be replaced with Yes, it is possible. Also, the memory cells AMub, AMxb, and AMrb By setting the current flowing between the first and second terminals of each transistor M2 to 0, the equation (1.24) Current quantity I b is, I b =I AMwb It can be replaced with this. In other words, product When setting an arbitrary value to be given for the result of a sum operation, the memory cell AMub, memory The transistors of cell AMwb, memory cell AMxb, and memory cell AMrb It is not necessary to use all of the current flowing between the first and second terminals of M2. Therefore, the arithmetic circuit MAC8, in circuit CSb, memory cells AMub, memory cells AMwb, memory cells Even in a configuration where at least one of the AMxb and AMrb memory cells is not provided, For example, circuit CSb has only memory cells AMub and AMxb. It can be a circuit, or it may have only memory cells AMwb and AMrb. A circuit that can be used as a path, or a circuit having only memory cell AMub and memory cell AMwb. This can be done, and the circuit will have only memory cells AMxb and AMrb. It is possible. Also, for example, circuit CSb, memory cell AMub, memory cell AMwb The configuration will have one of the following: memory cell AMxb, and memory cell AMrb. This can be done with memory cells AMub, AMwb, AMxb, and memory cells. It is possible to have a configuration in which only one memory cell selected from AMrb is not provided.

[0453] Furthermore, the semiconductor device according to one aspect of the present invention includes the arithmetic circuits MAC5 to described in this embodiment. It is not limited to the arithmetic circuit MAC8, etc. For example, using the same multiple second data, multiple To perform multiply-accumulate operations simultaneously, the MAC9 arithmetic circuit shown in Figure 19 should be used. MAC9 has n memory cell arrays CA of the arithmetic circuit MAC5 shown in Figure 12 (where n is 1 or more). (Assuming a number.) The arrangement is such that each element is placed in a column.

[0454] Figure 19 illustrates memory cell arrays CA[1] to CA[n]. Therefore, the memory cell array CA[1] to the memory cell array CA[n] are grouped together as a memory cell array. It is a double array CAS. In addition, the arithmetic circuit MAC9 has n memory cell arrays CA Therefore, in Figure 19, circuit CMS is represented as n circuits CM, such as circuit CM[1] to Circuit CM[n] is present, and circuit INT consists of n circuits SCI, such as circuit SCI[1] to A circuit SCI[n] has a circuit ACTV, and the circuit ACP[1] has n circuits ACP. It has a circuit ACP[n]. In addition, the arithmetic circuit MAC9 is a distribution of the arithmetic circuit MAC5. The wiring BAL[1] to wiring BAL[n], which correspond to the line BAL, and the arrangement of the arithmetic circuit MAC5 The wiring BBL[1] to BBL[n], which correspond to the line BBL, and the arrangement of the arithmetic circuit MAC5 The wiring WAD[1] to WAD[n], which correspond to the line WAD, and the arrangement of the arithmetic circuit MAC5 The wiring WBD[1] to WBD[n], which correspond to the wire WBD, and the arrangement of the arithmetic circuit MAC5 It has wiring NIL[1] to wiring NIL[n], which correspond to line NIL.

[0455] Memory cell array CA[1] is connected to wiring BAL[1], wiring BBL[1], and wiring WA D[1], wiring WBD[1], wiring XAL[1] to wiring XAL[m], and wiring XB L[1] to wiring XBL[m] and wiring WL[1] to wiring WL[m] are electrically connected. The circuit WDD is electrically connected to wiring WAD[1] and wiring WBD[1]. It is continued. Also, circuit CM[1] of circuit CMS is connected to wiring BAL[1] and wiring BBL [1] is electrically connected to the circuit INT, and the circuit SCI[1] of the circuit INT is connected to the wiring BAL[1]. The wiring BBL[1] is electrically connected to the circuit ACP[1] of the ACTV circuit. Circuit ACP[1] is electrically connected to wiring NIL[1].

[0456] Similarly, the memory cell array CA[n] consists of wiring BAL[n] and wiring BBL[n], Wiring WAD[n], wiring WBD[n], wiring XAL[1] to wiring XAL[m], Wiring XBL[1] to Wiring XBL[m] and Wiring WL[1] to Wiring WL[m], and They are electrically connected. Circuit WDD is electrically connected to wiring WAD[n] and wiring WBD[n]. They are electrically connected. Also, circuit CM[n] of circuit CMS is connected to wiring BAL[n] and The circuit SCI[n] of circuit INT is electrically connected to the line BBL[n], and the wiring BAL [n] is electrically connected to the wiring BBL[n] and the circuit ACTV ACP[n]. Circuit ACP[n] is electrically connected to wiring NIL[n].

[0457] The arithmetic circuit MAC9 in Figure 19 operates similarly to the timing chart in Figure 15, in memory storage. Each of the lure array CA[1] to memory cell array CA[n] has a first group to the second group After writing the voltage corresponding to multiple first data included in group n, the wiring XAL [1] to wiring XAL[m], and wiring XBL[1] to wiring XBL[m] with second data By inputting a voltage corresponding to the first to nth group, multiple The sum-of-products operation is performed on the first data and multiple second data, using wiring NIL[1] to wiring NIL[n]. It can output to both simultaneously.

[0458] Furthermore, in this embodiment, the trajectory included in the arithmetic circuits MAC5 to MAC9 We have explained the case where the transistor is an OS transistor or a Si transistor, but One aspect of the invention is not limited to this, but is included in arithmetic circuits MAC5 to MAC9. Transistors that include, for example, Ge, have a channel formation region. Compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe are used in the chat. Transistors and carbon nanotubes contained in the channel formation region are in the channel formation region. The transistors included are those in which organic semiconductors are included in the channel formation region. The following can be used.

[0459] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0460] (Embodiment 2) In this embodiment, a semiconductor device according to one aspect of the present invention performs multiple sum-of-accumulate operations simultaneously. An example of an arithmetic circuit that can perform this function will be described.

[0461] <Example 1 of semiconductor device configuration> Figure 20 shows the structure of a semiconductor device capable of performing sum-of-products operations on multiple first data and multiple second data. An example is shown. Furthermore, the semiconductor device shown in Figure 20 can, for example, perform multiple multiply-accumulate operations simultaneously. This can be done. Furthermore, the semiconductor device in Figure 20 uses the result of the sum-of-products operation as an input value. It can perform numerical calculations. Furthermore, the semiconductor device in Figure 20 can perform calculations of multiple functions simultaneously. It is possible to do so.

[0462] The arithmetic circuit MAC10 in Figure 20 is similar to the arithmetic circuit MAC5 described in the above embodiment. This includes multiple first data stored in multiple memory cells and multiple second data that have been input. This is a circuit that performs a sum-of-products operation and then uses the result of that sum-of-products operation to perform a function operation. For example, multiple first data and multiple second data could be analog data, or It can be treated as multi-valued data (discrete data).

[0463] The arithmetic circuit MAC10, as an example, consists of a memory cell array CA, a circuit CMS1, and a circuit CMS2, circuit WDD, circuit XLD, circuit WLD, circuit INT, and circuit ACTV It has, and

[0464] The memory cell array CA is a circuit CUW[1,1] to a circuit CUW[m,n] (where m and n are integers greater than or equal to 1. ) and circuits CXR[1] through CXR[m] It has and. In addition, each of circuits CUW[1,1] to CUW[m,n] is It has a Morissel AMu and a memory cell AMw, and has circuits CXR[1] to circuits CXR[m Each of the ] has a memory cell AMx and a memory cell AMr. Note that Figure 20 shows Although not shown in the diagram, in this specification, the circuit CUW[i,j] (where i is greater than or equal to m) is defined as follows: The memory cells AMu and memo (where j is an integer between 1 and n, and j is an integer between 1 and n) are included in the following integers. Each of the recell AMw cells is a memory cell AMu[i,j] and a memory cell AMw[i,j]. It may be written as follows. Also, in this specification, the memory included in circuit CXR[i] Cell AMx and memory cell AMR are, respectively, memory cell AMx[j] and memory cell AM It is sometimes written as r[j].

[0465] In the memory cell array CA, each memory cell is a matrix of 2m rows and n+1 columns. They are arranged in a V-shape. In Figure 20, as an example, the memory cell AMu[i,j] is 2i -Located at the address of row 1, column j, memory cell AMw[i,j] is located at the address of row 2i, column j. The memory cell AMx[i] is located at the address 2i-1 row n+1 column, The memory cell AMr[i] is located at address 2i rows and n+1 columns.

[0466] The memory cells AMx, AMw, AMu, and AMR Each has the function of holding the voltage corresponding to the first data. Voltage refers to, for example, the voltage stored in memory cells AMu[i,j] and AMw[i,j]. The voltage held and the electricity held in memory cell AMx[i] and memory cell AMr[i] It can be expressed as the difference between pressure and .

[0467] In particular, each of the memory cells in the first to nth columns of the memory cell array CA contains the first group Voltages corresponding to multiple first data points in a loop or the nth group are maintained. Specifically, for example, For example, each of the voltages corresponding to the multiple first data included in the first group is in the first column. Memory cells AMu[1,1] to AMu[m,1] located at the same location, and memory cells It is stored in memory cells AMw[1,1] to AMw[m,1], and also the nth Each of the voltages corresponding to the multiple first data points included in the group is located in the nth column. Memory cell AMu[1,n] to memory cell AMu[m,n], and memory cell AMw[ It is assumed that it is held in memory cell AMw[m,n] from 1,n]. Thus, the jth Each of the voltages corresponding to the multiple first data points included in the loop is located in column j. Morisel AMu[1,j], or memory cell AMu[m,j], and memory cell AMw[1 It shall be held in memory cell AMw[m,j] or [m,j].

[0468] Memory cell AMu[1,1] is connected to wiring WAD[1], wiring BAP[1], and wiring WL [1] is electrically connected to wiring XAL[1]. Also, the memory cell AMw[ 1,1] consists of wiring WAD[1], wiring BAN[1], wiring WL[1], and wiring XBL [1] and are electrically connected to the wiring WAD[n ] is electrically connected to wiring BAP[n], wiring WL[1], and wiring XAL[1]. Furthermore, the memory cell AMw[1,n] is connected to the wiring WAD[n] and the wiring BAN[n It is electrically connected to wiring WL[1] and wiring XBL[1]. AMx[1] is a combination of wiring WBD, wiring BBP, wiring WL[1], and wiring XAL[1]. , is electrically connected to. Also, the memory cell AMr[1] is connected to wiring WBD and wiring B BN is electrically connected to wiring WL[1] and wiring XBL[1]. AMu[m,1] is connected to wiring WAD[1], wiring BAP[1], and wiring WL[m]. The wiring XAL[m] is electrically connected to the memory cell AMw[m,1]. , wiring WAD[1], wiring BAN[1], wiring WL[m], wiring XBL[m], It is electrically connected to the wiring. The memory cell AMu[m,n] is connected to the wiring WAD[n] and the wiring It is electrically connected to BAP[n], wiring WL[m], and wiring XAL[m]. Furthermore, the memory cell AMw[m,n] is connected to the wiring WAD[n], the wiring BAN[n], and the wiring WL[m] and wiring XBL[m] are electrically connected. Memory cell AMx[m ] is an electrical connection between wiring WBD, wiring BBP, wiring WL[m], and wiring XAL[m]. It is connected to the following. Also, the memory cell AMr[m] is connected to the wiring WBD, the wiring BBN, and the wiring It is electrically connected to wire WL[m] and wiring XBL[m].

[0469] Each of the circuits CUW[1,1] through CUW[m,n] contains memory cells Each of the following: AMu and memory cell AMw, and circuits CXR[1] to CXR[m] Detailed circuit configurations of the included memory cells AMx and AMr. For example, a Morisel A that can be applied to the arithmetic circuit MAC5 described in the above embodiment. Mu, memory cell AMw, memory cell AMX, and memory cell AMR are treated the same. can.

[0470] Circuit CMS1 is, for example, a combination of circuits CMA[1] through CMA[n] and circuit CMB Circuit CMA[1] has wiring BAN[1] and wiring BAP[1], and electrical The circuit CMA[n] is connected to wiring BAN[n] and wiring BAP[n], and the electrical The circuit CMB is electrically connected to wiring BBN and wiring BBP. .

[0471] Circuit CMA[j] connects, for example, to memory cell AMu[1,j] via wiring BAP[j]. The function of supplying current to the memory cell AMu[m,j] and via the wiring BAN[j] The function of supplying current to the Moricell AMw[1,j] or memory cell AMw[m,j], It has. Furthermore, the amount of current flowing through wiring BAP[j] and wiring BA by circuit CMA[j] It is preferable that the current flowing through N[j] is equal. Specifically, for example, in the circuit CMA[ The amount of current flowing from [j] to wiring BAP[j] is equal to the amount of current flowing from circuit CMA[j] to wiring BAN[j]. It is preferable that the current flowing is 0.85 times or more, 0.9 times or more, or 0.95 times or more. Furthermore, it is preferable that the ratio is 1.05 times or less, 1.1 times or less, or 1.15 times or less. The lower and upper limits mentioned above can be combined in any way.

[0472] Furthermore, the circuit CMB connects, for example, to memory cells AMx[1] via wiring BBP to memory The function of supplying current to cell AMx[m] and memory cell AMr[1] via wiring BBN It has the function of supplying current to the memory cell AMr[m]. Furthermore, the circuit CMB Therefore, it is preferable that the amount of current flowing through wiring BBP and the amount of current flowing through wiring BBN are equal. Specifically, the amount of current flowing from circuit CMB to wiring BBP is from circuit CMB to wiring BBN It is preferable that the current flowing through it be 0.85 times or more, 0.9 times or more, or 0.95 times or more. It is preferable that the ratio is 1.05 times or less, 1.1 times or less, or 1.15 times or less. Furthermore, the lower and upper limits mentioned above can be combined in any way.

[0473] A specific example of the configuration of circuit CMS1 will be described later.

[0474] A circuit WDD, for example, consists of wiring WAD[1] through WAD[n] and wiring WBD. , is electrically connected to each of the memory cell array CA. It has the function of transmitting data to be stored in the memory cell. Furthermore, the circuit WDD is as described above. Refer to the description of the circuit WDD included in the arithmetic circuit MAC5 described in Embodiment 1.

[0475] The WLD circuit is included in the MAC5 arithmetic circuit described in Embodiment 1 above. Refer to the explanation of the WLD circuit.

[0476] Circuit XLD is included in the arithmetic circuit MAC5 described in Embodiment 1 above. Refer to the explanation of circuit XLD.

[0477] Circuit INT is, for example, a wiring BAP[1] to wiring BAP[n] and wiring BAN[ 1] to wiring BAN[n], wiring BBP, and wiring BBN are electrically connected. Circuit INT is, for example, a wiring BAP[1] through wiring BAP[n] and wiring BAN[1] A predetermined voltage is input to each of the following: wiring BAN[n], wiring BBP, and wiring BBN. It has the function of doing so. The voltage in question may be, for example, a low-level potential or ground potential. It can be done this way.

[0478] As a specific example of configuration, circuit INT is connected to circuits SCIA[1] through SCIA[n]. It has a circuit SCIB and a circuit SCIA[1] to a circuit SCIA[n] and a circuit Each of the paths SCIB and SCI is included in the INT circuit of the MAC5 arithmetic circuit. A similar configuration can be achieved. Specifically, circuit INT is shown in Figure 20 as circuit SCI A[1] or circuit SCIA[n] and circuit SCIB are each connected to switch SW5A The configuration includes a switch SW5B. Also, in circuit SCIA[j] The first terminal of switch SW5A is electrically connected to wiring BAN[j], and switch S The second terminal of W5A is electrically connected to the wiring VSL, and the first terminal of switch SW5B is, Electrically connected to wiring BAP[j], the second terminal of switch SW5B is electrically connected to wiring VSL. They are electrically connected. Also, the respective controls of switch SW5A and switch SW5B The terminal is electrically connected to wiring SL5. Similarly, in circuit SCIB, The first terminal of switch SW5A is electrically connected to wiring BBN, and the second terminal of switch SW5A The child is electrically connected to wiring VSL, and the first terminal of switch SW5B is electrically connected to wiring BBP. The second terminal of switch SW5B is electrically connected to wiring VSL. Furthermore, the control terminals of switches SW5A and SW5B are connected to wiring SL5. It is electrically connected to it.

[0479] In this embodiment, switch SW5A and switch SW5B are controlled It turns ON when a high-level potential is input to the terminal, and turns ON when a low-level potential is input. It will be assumed that it will be turned off at this time.

[0480] Wiring SL5, for example, can be used to check the continuity and non-continuity of switches SW5A and SW5B. It functions as wiring that supplies voltage to switch between conductive and non-conductive states. The voltage can be, for example, a high-level potential or a low-level potential.

[0481] Furthermore, the VSL wiring functions, for example, as wiring that provides a constant voltage. For example, this could be a low-level potential or ground potential.

[0482] Circuit CMS2, as an example, consists of wiring BAN[1] through wiring BAN[n] and wiring BBN It is electrically connected to and. Circuit CMS2, for example, eliminates the current flowing through wiring BBN. The function of outputting current and discharging the current flowing through each of the wiring BAN[1] to wiring BAN[n] It has the function of and the amount of current discharged from wiring BBN by circuit CMS2. , equal to the amount of current discharged from each of the wiring BAN[1] to wiring BAN[n]. This is preferable. Specifically, for example, the amount of current flowing from wiring BBN to circuit CMS2 is the wiring The current flowing from BAN[j] to circuit CMS2 is 0.85 times or more, 0.9 times or more, or 0. Preferably, the ratio is 0.95 times or more, and not 1.05 times or less, 1.1 times or less, or 1.15 times. It is preferable that it be less than or equal to double. Note that the lower and upper limits mentioned above are combined It shall be possible.

[0483] Circuit ACTV includes, for example, circuits ACP[1] to ACP[n]. ACP[1] is electrically connected to wiring BAN[1] and wiring NIL[1], and the circuit ACP[n] is electrically connected to wiring BAN[n] and wiring NIL[n]. Circuits ACP[1] to ACP[n] are, for example, as described in Embodiment 1 above. The MAC5 arithmetic circuit has a similar configuration to the ACCP circuit included in the ACTV circuit. Yes, it is possible. Note that in Figures 4A to 4C and Figures 5A to 5C, switch SW4A is used. The diagram shows a configuration in which the first terminal is electrically connected to the wiring BAL, but this embodiment Now, the wiring BALs shown in Figures 4A to 4C and 5A to 5C are used in the wiring BAN We will explain it by substituting it with the following.

[0484] <<Example configuration of memory cell array CA>> Next, the circuits CUW[1,1] through CUW[m,n] of the memory cell array CA. Each contains memory cells AMu and AMw, and circuits CXR[1] to circuits. The structure of memory cells AMx and AMr contained in each of the paths CXR[m] Let me explain the examples.

[0485] Figure 21 is a circuit diagram showing an example configuration of memory cell array CA. Memory cell array C A, similar to the arithmetic circuit MAC5 described in the above embodiment, has multiple first data and multiple It has the function of calculating the sum of products with the second data point.

[0486] Furthermore, the memory cells AMu, AMw, AMx, and shown in Figure 21, The configuration of Morissel AMr is shown in Figure 13: memory cell AMu, memory cell AMw, memory cell It has the same configuration as the AMx and AMr memory cells. Therefore, the AM The explanation of the circuit elements included in w, memory cell AMx, and memory cell AMR is as follows: The memory cells AMu, AMw, AMx, and the memory cells described in the embodiment We will consider the contents of each section of Morisel AMr.

[0487] In each of the memory cells AMu[i,1] to AMu[i,n], The gate of transistor M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is It is electrically connected to wiring XAL[i]. Also, memory cell AMu[i,1] The second terminal of transistor M1 is electrically connected to wiring WAD[1], and the transistor The second terminal of sta M2 is electrically connected to wiring BAP[1]. In AMu[i,n], the second terminal of transistor M1 is electrically connected to wiring WAD[n]. The second terminal of transistor M2 is connected to the wiring BAP[n]. Although not shown in Figure 21, in the memory cell AMu[i,j], The second terminal of transistor M1 is electrically connected to wiring WAD[j], and the second terminal of transistor M2 Terminal 2 is assumed to be electrically connected to wiring BAP[j]. Also, memory cell A In Mu[i,j], the first terminal of transistor M1 and the gate of transistor M2 The electrical connection point between the first terminal of capacitance C1 and the other terminal is defined as node Nu[i,j].

[0488] In each of the memory cells AMw[i,1] to AMw[i,n], The gate of transistor M1 is electrically connected to wiring WL[i], and the second terminal of capacitor C1 is It is electrically connected to wiring XBL[i]. Also, memory cell AMw[i,1] The second terminal of transistor M1 is electrically connected to wiring WAD[1], and the transistor The second terminal of sta M2 is electrically connected to wiring BAN[1]. In AMw[i,n], the second terminal of transistor M1 is electrically connected to wiring WAD[n]. The second terminal of transistor M2 is connected to the wiring BAN[n]. Although not shown in Figure 21, in the memory cell AMw[i,j], The second terminal of transistor M1 is electrically connected to wiring WAD[j], and the second terminal of transistor M2 Terminal 2 is assumed to be electrically connected to wiring BAN[j]. Also, memory cell A In Mw[i,j], the first terminal of transistor M1 and the gate of transistor M2 The first terminal of capacitance C1 and the electrical connection point are defined as node Nw[i,j].

[0489] In memory cell AMx[i], the gate of transistor M1 is connected to wiring WL[i]. The second terminal of capacitance C1 is electrically connected to wiring XAL[i], and the transistor The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 It is electrically connected to the wiring BBP. Also, in the memory cell AMx[i], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, The electrical connection points are designated as nodes Nx[i].

[0490] In the memory cell AMr[i], the gate of transistor M1 is connected to wiring WL[i]. The second terminal of capacitance C1 is electrically connected to wiring XBL[i], and the transistor The second terminal of transistor M1 is electrically connected to the wiring WBD, and the second terminal of transistor M2 It is electrically connected to the wiring BBN. ​​Also, in the memory cell AMr[i], The first terminal of transistor M1, the gate of transistor M2, and the first terminal of capacitor C1, The electrical connection points are designated as nodes Nr[i].

[0491] <<Example Configuration of Circuit CMS1>> Next, the circuits CMA[1] to CMA[n] included in the circuit CMS1 in Figure 20, and This section describes an example of a circuit configuration that can be applied to the CMB circuit.

[0492] The circuit CMS1 in Figure 21 includes circuits CMA[1] to CMA[n] and circuit CMB An example of a circuit configuration that can be applied is shown in Figure 21. Specifically, the circuit CMA[1] shown in Figure 21. The configuration of circuit CM in Figure 3A is applied as circuits CMA[n] and CMB. Therefore, the circuits CM...

Claims

[Claim 1] It has a first cell, a second cell, a third cell, a fourth cell, a current mirror circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. Each of the first cell, the second cell, the third cell, and the fourth cell has a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, the first terminal of the first transistor is electrically connected to the first terminal of the capacitor and to the gate of the second transistor. The first terminal of the second transistor of the first cell is electrically connected to the first wiring. The second terminal of the capacitance of the first cell is electrically connected to the third wiring, The first terminal of the second transistor of the second cell is electrically connected to the first wiring. The second terminal of the capacitance of the second cell is electrically connected to the fourth wiring, The first terminal of the second transistor of the third cell is electrically connected to the second wiring. The second terminal of the capacitance of the third cell is electrically connected to the third wiring. The first terminal of the second transistor of the fourth cell is electrically connected to the second wiring. The second terminal of the capacitance of the fourth cell is electrically connected to the fourth wiring. The current mirror circuit is electrically connected to the first wiring and the second wiring. The current mirror circuit has the function of supplying a current to the second wiring that corresponds to the potential of the first wiring. The first data is determined according to the difference between the first potential and the second potential. The first cell has the function of holding the first potential at the first terminal of the capacitance of the first cell, The second cell has the function of holding the second potential at the first terminal of the capacitance of the second cell, The third cell has the function of holding the second potential at the first terminal of the capacitance of the third cell, The fourth cell has the function of holding the first potential at the first terminal of the capacitance of the fourth cell, The second data is determined according to the difference between the third potential and the fourth potential. When the third potential is input to the third wiring and the fourth potential is input to the fourth wiring, the current obtained by subtracting the current flowing from the second wiring to the first terminal of the second transistor of the third cell and the current flowing from the second wiring to the first terminal of the second transistor of the fourth cell from the current flowing from the current mirror circuit to the second wiring becomes an amount corresponding to the product of the first data and the second data. Semiconductor equipment.

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