Semiconductor equipment

The semiconductor device addresses leakage path issues by incorporating a superjunction layer with annular loop portions and an outer breakdown structure, ensuring effective breakdown resistance and voltage control.

JP2026091090APending Publication Date: 2026-06-03DENSO CORP +2
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
DENSO CORP
Filing Date
2024-11-22
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

The superjunction structure in semiconductor devices may form a leakage path from the upper electrode to the outer peripheral end of the substrate due to the longitudinal ends of p-type and n-type columns reaching the same potential as the lower electrode, leading to potential breakdown issues.

Method used

A semiconductor device with a first and second superjunction layer structure, where the first superjunction layer is surrounded by annular loop portions of alternating conductivity types, and an outer perimeter breakdown structure is incorporated to control depletion layer propagation, isolating column ends from the substrate edge and optimizing breakdown voltage.

Benefits of technology

Prevents leakage paths and ensures good breakdown voltage by isolating column ends and optimizing depletion layer propagation, enhancing the semiconductor device's breakdown resistance.

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    Figure 2026091090000001_ABST
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Abstract

To improve the voltage resistance of the outer periphery of semiconductor devices. [Solution] The semiconductor substrate has an active region on which a device structure is formed, a first outer peripheral region surrounding the active region, and a second outer peripheral region surrounding the first outer peripheral region. In the first outer peripheral region, an outer peripheral breakdown structure is formed near the surface of the semiconductor substrate. The second outer peripheral region is located in the area up to the outer peripheral edge of the semiconductor substrate. The semiconductor substrate includes a first SJ layer disposed in the active region and the first outer peripheral region, and a second SJ layer disposed in the second outer peripheral region and surrounding the first SJ layer. In the first SJ layer, a first column of a first conductivity type and a second column of a second conductivity type extending in a first direction are alternately and repeatedly arranged in a second direction. In the second SJ layer, annular first loop portions of a first conductivity type and second loop portions of a second conductivity type surrounding the first SJ layer are alternately and repeatedly arranged in the second outer peripheral region from the first outer peripheral region side toward the outer peripheral edge of the substrate.
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