RF-DC circuit

Abstract

In the RF-DC circuit of a wireless power receiving device, the device connected to the power supply voltage terminal is not protected. [Solution] In an RF-DC circuit of a wireless power receiving device, the RF-DC circuit comprises a capacitor provided between the positive terminal of the antenna and the power supply voltage terminal, and a diode connected in parallel with the capacitor and capable of outputting an overvoltage input from the positive terminal of the antenna to the GND output, wherein the RF-DC circuit is not connected to an overvoltage protection element between the positive terminal of the antenna and the capacitor.

Description

Technical Field

[0001] This disclosure relates to RF-DC circuits.

Background Art

[0002] In recent years, wireless power transfer (WPT) has been used in various fields. By utilizing WPT, problems such as the burden, breakage, and maintenance of wiring can be avoided compared to the case of wired power transmission.

[0003] Patent Document 1 discloses a technique for providing means to prevent rectenna failure.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the RF-DC circuit of a wireless power receiving device, there is a problem that a device connected to a power supply voltage supply terminal cannot be protected. Therefore, this disclosure has been made to solve the above problems, and its object is to provide a technique for protecting a device connected to a power supply voltage supply terminal of an RF-DC circuit.

Means for Solving the Problems

[0006] In an RF-DC circuit for a wireless power receiving device, the RF-DC circuit comprises a capacitor located between the positive terminal of the antenna and the power supply voltage terminal, and a diode connected in parallel with the capacitor, capable of outputting an overvoltage input from the positive terminal of the antenna to the GND output, wherein the connection between the positive terminal of the antenna and the capacitor is not connected to an overvoltage protection element. [Effects of the Invention]

[0007] According to this disclosure, devices connected to the power supply voltage terminal of an RF-DC circuit can be protected. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram shows the overall configuration of the WPT system. [Figure 2] This is a block diagram illustrating an example configuration of a power transmission device and a power receiving device. [Figure 3] This is a block diagram showing the functional configuration of the first information processing device. [Figure 4] This is a block diagram showing the functional configuration of the second information processing unit. [Figure 5] This is a block diagram showing the functional configuration of an RF-DC circuit (first embodiment). [Figure 6] This is a cross-sectional view of an RF-DC circuit (first embodiment). [Figure 7] This block diagram shows the functional configuration of the RF-DC circuit (second embodiment). [Figure 8] This is a cross-sectional view of an RF-DC circuit (second embodiment). [Figure 9] This block diagram shows the functional configuration of an RF-DC circuit (third embodiment). [Figure 10] This is a first cross-sectional view of an RF-DC circuit (third embodiment). [Figure 11] This is a second cross-sectional view of the RF-DC circuit (third embodiment). [Figure 12] This is a block diagram showing the functional configuration of the RF-DC circuit (fourth embodiment). [Figure 13] Cross-sectional view of the RF-DC circuit (fourth embodiment). [Figure 14] Block diagram showing the basic hardware configuration of the computer 90.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In all the drawings for describing the embodiments, the same reference numerals are assigned to common components, and repeated descriptions are omitted. Note that the following embodiments do not unduly limit the content of the present disclosure described in the claims. Also, not all of the components shown in the embodiments are essential components of the present disclosure. Further, each figure is a schematic diagram and is not necessarily drawn precisely.

[0010] <Summary> <1 Configuration Diagram of the Entire System> FIG. 1 is a diagram showing the overall configuration of the WPT system 1 according to the present embodiment.

[0011] The WPT system 1 shown in FIG. 1 includes, for example, a transmitter 100, a receiver 200, a first information processing device 300, and a second information processing device 400. The WPT system 1 shown in FIG. 1 is used, for example, in a building or a factory. Note that the connection between the transmitter 100 and the first information processing device 300 and the connection between the first information processing device 300 and the second information processing device 400 may be wired or wireless.

[0012] In FIG. 1, an example in which the WPT system 1 includes three transmitters 100 is shown, but the number of transmitters 100 included in the WPT system 1 is not limited to three. The number of transmitters 100 included in the WPT system 1 may be two or less, or four or more.

[0013] In FIG. 1, an example is shown in which the WPT system 1 includes seven receivers 200. However, the number of receivers 200 included in the WPT system 1 is not limited to seven. The number of receivers 200 included in the WPT system 1 may be six or less, or may be eight or more.

[0014] In this specification, the transmitter 100 is a (power) transmitter 100 in the sense of wirelessly transmitting power. Similarly, the receiver 200 is a (power) receiver 200 in the sense of wirelessly receiving power. As will be described later, the receiver 200 may transmit information regarding the state of the receiver 200 or information regarding the measurement result by a sensor to the transmitter 100 as a data signal, and the transmitter 100 may receive such a data signal. In this case, the transmitter 100 is a receiver that receives the data signal, and the receiver 200 functions as a transmitter that transmits the data signal.

[0015] In FIG. 1, an example is shown in which the WPT system 1 includes two first information processing devices 300. However, the number of first information processing devices 300 included in the WPT system 1 is not limited to two. The number of first information processing devices 300 included in the WPT system 1 may be one, or may be three or more.

[0016] The transmitter 100 transmits, for example, a power supply signal or a data signal to the receiver 200. The transmitter 100 transmits a power supply signal to the receiver 200 by radio waves in the 920 MHz band, for example. The transmitter 100 transmits a data signal to the receiver 200 by radio waves in the 2.4 GHz band, for example. The transmitter 100 may transmit the data signal by radio waves in the 920 MHz band.

[0017] The transmission signal sent from the transmitter 100 may, for example, be a continuous wave (CW) with a predetermined power. The frequency band of the transmission signal is, for example, 920 MHz, taking into account the distance between the transmitter 100 and the receiver 200. If the frequency band is higher than the example frequency band, the receiver 200 may not be able to receive the predetermined power necessary for operation unless the distance between the transmitter 100 and the receiver 200 is shortened. Therefore, an appropriate frequency band can be determined by considering a practical range (for example, a distance of a few meters between the transmitter 100 and the receiver 200).

[0018] In this case, the laws of the country where the WPT system 1 is installed may impose restrictions on the intermittent transmission of power signals with a specified power level. For example, if the power signal from transmitter 100 falls under the provisions for radio stations as defined in Japan's Radio Law (regardless of whether a license is in place), it may be necessary to provide a certain pause period for the power signal in accordance with the Radio Law. In this case, considering it over a certain time axis, the power signal cannot be considered a continuous wave. However, it is important to provide a pause period, and since this pause period only needs to be short, the power signal transmitted from transmitter 100 can be considered a nearly continuous wave. The ratio of the power signal duration to the pause period should be such that the power signal transmitted from transmitter 100 can be considered a nearly continuous wave, as described above. For example, the pause period is about 1 / 50 to 1 / 100 of the power signal duration.

[0019] The transmitter 100 may, for example, supply power to one receiver 200 or to multiple receivers 200. The transmitter 100 may, for example, transmit a data signal to one receiver 200 or to multiple receivers 200. The transmitter 100 may, for example, transmit the same data signal as other transmitters 100 or transmit a different data signal from other transmitters 100. The transmitter 100 may, for example, transmit a predetermined command signal as a data signal to the receiver 200, or transmit a pre-set signal as a data signal to the receiver 200.

[0020] The transmitter 100 receives, for example, a data signal transmitted from the receiver 200. The transmitter 100 may receive a data signal transmitted from one receiver 200, or it may receive data signals transmitted from multiple receivers 200. The transmitter 100 transmits the data signal transmitted from the receiver 200 to the first information processing device 300. The transmitter 100 transmits information regarding the state of the transmitter 100 to the first information processing device 300.

[0021] The receiver 200 receives, for example, a power supply signal or a data signal transmitted from the transmitter 100. If the receiver 200 has, for example, a power storage unit, it converts the power supply signal transmitted from the transmitter 100 into power and stores the converted power in the power storage unit. If the receiver 200 has, for example, a predetermined sensor, it converts the power supply signal transmitted from the transmitter 100 into power and drives the sensor with the converted power.

[0022] The receiver 200 transmits, for example, information regarding the status of the receiver 200 or information regarding measurement results from sensors to the transmitter 100 as a data signal.

[0023] The first information processing device 300 is an information processing device that monitors the operation of the transmitter 100 and receiver 200 housed in the WPT system 1. For example, the first information processing device 300 determines whether the transmitter 100 or the receiver 200 is in a preset state based on information about the status of the transmitter 100 and the receiver 200 transmitted from the transmitter 100. If it determines that the transmitter is in a preset state, the first information processing device 300 transmits predetermined information to the second information processing device 400.

[0024] Furthermore, the first information processing device 300 stores information about the transmitter 100 and receiver 200 housed in the WPT system 1. For example, the first information processing device 300 stores information about the status of the transmitter 100 and receiver 200 transmitted from the transmitter 100 in a storage unit provided in the first information processing device 300.

[0025] Furthermore, the first information processing device 300 controls the operation of the transmitter 100, which is housed in the WPT system 1. For example, the first information processing device 300 transmits predetermined instructions or information to the transmitter 100.

[0026] Furthermore, the first information processing device 300 controls the operation of the second information processing device 400.

[0027] The second information processing device 400 is, for example, an information processing device operated by the administrator of the WPT system 1. When the second information processing device 400 receives a notification from the first information processing device 300 that the transmitter 100, receiver 200, or both thereof, which are connected to the WPT system 1, are in a predetermined state, it informs the user that the transmitter 100, receiver 200, or both thereof are in a predetermined state.

[0028] Furthermore, the second information processing device 400 analyzes the information regarding the status of the transmitter 100 and the receiver 200 stored in the first information processing device 300 and presents predetermined information to the user. The predetermined information is, for example, the following: Information regarding the placement of transmitter 100 • Information regarding the placement of receiver 200 • Information regarding power consumption • Information regarding the amount of electricity

[0029] <1.1 Transmitter and Receiver Configuration> Figure 2 is a block diagram showing an example configuration of the transmitter 100 and receiver 200 shown in Figure 1. As shown in Figure 2, the transmitter 100 and receiver 200 are separated from each other by a predetermined distance, for example. For example, the transmitter 100 and receiver 200 are installed at a distance of several meters from each other. Specifically, for example, the transmitter 100 is fixed and installed at a predetermined high position indoors, for example, on the ceiling or wall. The receiver 200 is installed in a predetermined device indoors or placed near a device that requires power supply. The receiver 200 may also be carried by the user. The transmitter 100 transmits a power supply signal to the receiver 200 using radio waves at a predetermined frequency, for example, in the 920 MHz band. The receiver 200 converts the power supply signal transmitted from the transmitter 100 into power and either charges the receiver with the converted power or supplies the converted power to the predetermined device.

[0030] The transmitter 100 includes, for example, an oscillator 101, a transmitting antenna 102, a microcontroller (controller) 103, a data transceiver 104, and a data transceiver antenna 105. The oscillator 101, microcontroller 103, data transceiver 104, data transceiver antenna 105, or at least a combination of these, may be mounted on a PCB (printed circuit board), for example.

[0031] The oscillator 101 generates a signal in a predetermined frequency band, for example, the 920 MHz band. The generated signal may be amplified as needed to remove unwanted frequency components.

[0032] The transmitting antenna 102 is configured to efficiently transmit, for example, radio waves in the 920 MHz band. The transmitting antenna 102 radiates the signal oscillated by the oscillator 101 as a feed signal.

[0033] The microcontroller 103 controls the operation of the transmitter 100. The microcontroller 103 is implemented, for example, by a semiconductor element equipped with an ARM processor. The microcontroller 103 controls, for example, the transmission of radio waves by the transmitting antenna 102.

[0034] The data transceiver 104 performs processing such as converting digital data to analog and modulating analog data. The data transceiver 104 also performs processing such as demodulating the data signal received by the data transmission antenna 105 and digitizing the demodulated data. For example, the data transceiver 104 extracts a predetermined signal from the data signal received by the data transmission antenna 105, converts it to digital data, and transmits it to the microcontroller 103.

[0035] The data transmission antenna 105 is configured to efficiently transmit and receive radio waves in the 2.4GHz band, for example. The data transmission antenna 105 radiates data signals supplied from the data transceiver 104. The data transmission antenna 105 also receives data signals transmitted from the receiver 200.

[0036] The receiver 200 includes, for example, a receiving antenna 201, a rectifier 202, a power management unit 203, a power storage unit 204, a microcontroller 205, a data transceiver 206, and a data transceiver antenna 207. The receiving antenna 201, rectifier 202, power management unit 203, power storage unit 204, microcontroller 205, data transceiver 206, data transceiver antenna 207, or at least a combination of these, may be mounted on, for example, a PCB or FPC (flexible printed circuit board).

[0037] The receiving antenna 201 is configured to efficiently receive, for example, radio waves in the 920 MHz band. The receiving antenna 201 receives the feed signal radiated from the transmitting antenna 102.

[0038] The rectifier 202 rectifies the radio waves received as a power supply signal and converts them into a DC voltage.

[0039] The power management unit 203 manages the DC voltage. For example, the power management unit 203 controls the charging voltage based on the DC voltage. By controlling the charging voltage, the power management unit 203 charges the energy storage unit 204. Also, for example, when the energy storage unit 204 has stored more than a predetermined capacity of power, the power management unit 203 supplies the DC voltage to the connected components.

[0040] Furthermore, the power management unit 203 releases the power stored in the energy storage unit 204 in response to control from the microcontroller 205.

[0041] The energy storage unit 204 stores power in response to instructions from the power management unit 203. The energy storage unit 204 is implemented, for example, by a battery or a capacitor. The energy storage unit 204 also releases the stored power in response to instructions from the power management unit 203.

[0042] The microcontroller 205 controls the operation of the receiver 200. The microcontroller 205 is driven by a DC voltage supplied from the power management unit 203 or by power stored in the energy storage unit 204. The microcontroller 205 controls the power management unit 203 to release the power stored in the energy storage unit 204.

[0043] Various sensors can be connected to the receiver 200. For example, heat sensors, temperature sensors, light sensors, humidity sensors, vibration sensors, magnetic sensors, etc. can be connected to the receiver 200. Force sensors, proximity sensors, gas sensors, acceleration sensors, human presence sensors, infrared sensors, illuminance sensors, flow sensors, current sensors, pressure sensors, etc. may also be connected to the receiver 200. Sensors connected to the receiver 200 are driven, for example, by a DC voltage supplied from the power management unit 203 or power emitted from the energy storage unit 204. The microcontroller 205 continuously or intermittently monitors the voltage value at a predetermined part of the receiver 200, the status of sensors connected to the receiver 200, and information detected by the sensors. The microcontroller 205 transmits the voltage value at a predetermined part of the receiver 200, the status of sensors connected to the receiver 200, and information detected by the sensors as digital data to the data transceiver 206. The sensors may also be built into the receiver 200.

[0044] The data transceiver 206 performs processing such as converting digital data supplied from the microcontroller 205 to analog and modulating analog data. The data transceiver 206 also performs processing such as demodulating the data signal received by the data transceiver antenna 207 and digitizing the demodulated data. The data transceiver 206 is driven, for example, by a DC voltage supplied from the power management unit 203 or power emitted from the energy storage unit 204.

[0045] The data transmission antenna 207 is configured to efficiently transmit and receive radio waves in the 2.4 GHz band, for example. The data transmission antenna 207 radiates data signals supplied from the data transceiver 206. The data transmission antenna 207 also receives data signals transmitted from the transmitter 100. For example, the data transmission antenna 207 is driven by, for example, a DC voltage supplied from the power management unit 203 or power emitted from the energy storage unit 204.

[0046] <2 RF-DC circuit 501> In this disclosure, the RF-DC circuit 501, which comprises the rectifier 202, power management unit 203, and energy storage unit 204 included in the receiver 200, will be described in detail below.

[0047] [RF-DC circuit 501 (basic configuration)] This invention relates to an RF-DC circuit 501 of a wireless power receiving device (receiver 200). The features of the RF-DC circuit 501 of the wireless power receiving device described herein are as follows. The RF-DC circuit 501 of this disclosure is configured as a semiconductor circuit. The RF-DC circuit 501 includes a capacitor (C521) located between the antenna positive terminal (ANTP511) and the power supply voltage supply terminal (VCC513) that outputs power received from the antenna positive terminal. The RF-DC circuit 501 is connected in parallel with the capacitor (C521) and includes a diode (D_ESD531) that can output overvoltage input from the antenna positive terminal (ANTP511) to the GND514 output. The Voltage Clamp circuit 541 can also protect the circuit connected after VCC513. There is no overvoltage protection element connected between the antenna positive terminal (ANTP511) and the capacitor (C521). An overvoltage protection element (Voltage Clamp ESD541) is connected between the capacitor (C521) and the power supply voltage terminal (VCC513).

[0048] The overvoltage protection element can output overvoltage to the GND514 output via the antenna positive terminal (ANTP511), diode (D_ESD531), and overvoltage protection element (Voltage Clamp ESD541). Specifically, when a positive overvoltage is input from the antenna positive terminal (ANTP511), it becomes forward biased and has the function of releasing current to GND514. The overvoltage protection element (Voltage Clamp ESD541) can protect devices (such as the microcontroller 205) connected to the power supply terminal (VCC513). The overvoltage protection element (Voltage Clamp ESD541) operates when the input voltage exceeds a predetermined voltage (set voltage), and protects the devices (such as the microcontroller 205) connected to the power supply terminal (VCC513) by outputting the input overvoltage to GND514 without outputting it to the power supply terminal (VCC513). VCC513 is connected to the power management unit 203, and the power supplied from ANTP511 is stored in the energy storage unit 204 via the rectifier 202 (RF-DC circuit 501 composed of capacitors, diodes, etc.) and the power management unit 203. The power stored in the energy storage unit 204 is supplied to the microcontroller 205, data transceiver 206, data transceiver antenna 207, etc., via the power management unit 203 through a separate path from the one used for storage, to drive the receiver 200. Under normal conditions, the overvoltage protection element (Voltage Clamp ESD541) maintains a reverse bias state, and in the event of an overvoltage, it switches to a forward bias state and releases current to GND514. The overvoltage protection element (Voltage Clamp ESD541) operates to protect devices (such as the microcontroller 205) connected to the energy storage unit 204 from overvoltage. Furthermore, if the antenna positive terminal (ANTP511) and the antenna negative terminal (ANTN512) can be configured in reverse order and the circuit still functions correctly, then they may be configured in that way. Specifically, the antenna negative terminal (ANTN512) may be placed in the position of the antenna positive terminal (ANTP511) in this disclosure, and the antenna positive terminal (ANTP511) may be placed in the position of the antenna negative terminal (ANTN512). In this disclosure, overvoltage includes ESD (Electrostatic Discharge), EOS (Electric Over Stress), etc. Specifically, it includes any electrical signal (voltage, current, radio waves, spatial power) input from antenna 201 that may damage internal circuits and connected devices.

[0049] The specific configuration of the RF-DC circuit 501 of the wireless power receiving device according to this disclosure will be described in the following embodiments.

[0050] [RF-DC circuit 501 (first embodiment)] Figure 5 is a block diagram showing the functional configuration of the RF-DC circuit 501 (first embodiment). Figure 6 is a cross-sectional view of the RF-DC circuit 501 (first embodiment). The RF-DC circuit 501 (first embodiment) is formed using bulk CMOS. Bulk CMOS is a method of forming devices directly on a single silicon substrate. Compared to SOI CMOS, the manufacturing process is relatively simpler and less expensive. Compared to SOI CMOS, it has superior heat dissipation because heat can be distributed across the entire silicon substrate. However, compared to SOI CMOS, there is a large parasitic capacitance between the substrate and the device, which can affect high-frequency characteristics.

[0051] [Basic configuration of RF-DC circuit 501 (first embodiment)] The components of the RF-DC circuit 501 (first embodiment) disclosed in Figures 5 and 6 are described below. ANTP511 (antenna positive terminal) is the positive terminal of antenna 201 and is the input point for RF (radio frequency) signals. ANTN512 (antenna negative terminal) is the negative terminal of antenna 201. VCC513 is a power supply voltage terminal (output terminal) that supplies power to devices connected to the circuit. GND514 is the ground terminal and serves as the reference potential point of the circuit. C521 is a capacitor used for rectifying RF (radio frequency) signals. C_storage522 is a storage capacitor that stores rectified power. D_ESD531 is an ESD (Electrostatic Discharge) protection diode that provides protection for C521 from overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress). D532A and D532B are rectifier diodes that convert RF (radio frequency) signals into DC (direct current) voltages and store them in C_storage522. DA_ISO534A and DSub_ISO534B are isolation diodes that electrically isolate D_ESD531 from the PSUB (board). The Voltage Clamp ESD541 is a voltage clamp ESD (electrostatic discharge) protection element that protects circuits from overvoltage. PSUB is a P-type substrate that forms the substrate portion of semiconductor devices. N+ is a highly doped N-type semiconductor region. P+ represents a highly doped P-type semiconductor region. P- represents a low-doped P-type semiconductor region. Shallow Trench Isolation (STI) is a shallow trench isolation structure that provides electrical isolation between devices.

[0052] [Connection relationship of RF-DC circuit 501 (first embodiment)] The RF-DC circuit 501 (first embodiment) includes a second diode (DA_ISO534A) and a third diode (DSub_ISO534B) connected between the antenna positive terminal (ANTP511) and the diode (D_ESD531). The diode, second diode, and third diode are formed in the channel region on the silicon substrate. specifically, The ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected between DSub_ISO534B and ANTP511. The cathode of DSub_ISO534B is connected between ANTP511 and one end of C521. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to GND514. One end of the Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the Voltage Clamp ESD541 is connected to GND514.

[0053] [Operation of RF-DC circuit 501 (first embodiment)] When an RF signal (the terminal input signal of ANTP511, referenced to the terminal voltage of ANTN512) is input from ANTP511, this high-frequency signal reaches C521. Since D_ESD531 is connected in parallel with C521, during the positive half-cycle of the RF signal, if C521 is charged above the forward voltage (Vf) of D_ESD531, it enters a reverse-biased state. As a result, D_ESD531 does not affect the normal RF signal, and the efficiency of the circuit can be maintained. D532A and D532B function as rectifiers, converting RF signals to DC. During the negative half-cycle of the RF signal, D532A conducts and charges C521. During the positive half-cycle of the RF signal, D532B conducts and charges C_storage522. When the charging voltage to C521 is less than or equal to the forward voltage (Vf) of D_ESD531, a rise in the ANTP511 voltage causes current to flow through the path of D_ESD531 and D532B, charging C_storage522. This allows for efficient power storage even in low-voltage conditions. The rectified and stored power is supplied to the connected device through the VCC513 terminal. The Voltage Clamp ESD541, connected between VCC513 and GND514, provides protection in case the output voltage rises excessively.

[0054] The case where a positive overvoltage is input from ANTP511 will be explained with reference to arrow 51 in Figure 5. When a positive overvoltage is input from ANTP511, the current is discharged through the path of ANTP511, D_ESD531, D532B, Voltage Clamp ESD541, and GND514, so the device connected to VCC513 is protected from the overvoltage. This protects the circuit and connected devices from positive overvoltage. The case where a negative overvoltage is input from ANTP511 will be explained with reference to arrow 52 in Figure 5. When a negative overvoltage is input from ANTP511, the current is discharged from GND514 through the path D532A and D_ESD531, thus protecting the device connected to VCC513 from the overvoltage. This protects the circuit and connected device from negative overvoltage.

[0055] Refer to Figure 6 to explain the operation as a semiconductor circuit. Figure 6 shows a semiconductor device formed on a P-type substrate (PSUB). The N+ region and the P+ region are arranged and separated by STI. DA_ISO534A is a diode that isolates the anode of D_ESD531 from the PSUB in the N+ region. Since the anode (P+) and cathode (N+:N+ region) of DA_ISO534A are short-circuited, no current can flow through it, and it functions to isolate the anode of D_ESD531 from the PSUB. The D_ESD531 is a diode formed between the P+ and N+ regions. When the RF signal is negative (ANTP is negative), it is reverse-biased and does not affect the rectification function. When the RF signal is positive (ANTP is positive), it is forward-biased, but since the cathode voltage of the D_ESD531 is normally higher than the anode voltage in circuit operation, no current flows and does not affect the rectification function. Also, in situations where the cathode voltage is lower than the anode for some reason, the D_ESD531 turns ON at a voltage difference greater than or equal to the forward bias voltage, assisting the rectification function. In the event of overvoltage, it becomes forward-biased and performs a protection function. DSub_ISO534B is, If a negative overvoltage is input from ANTP511, DA_ISO534A is forward-biased, and the excess current is diverted to PSUB. If a positive overvoltage is input from ANTP511, D_ESD531 and D532B are forward-biased, and the excess current is diverted to VCC513. As a result, the voltage of VCC513 rises, but the Voltage Clamp ESD541 limits the risen overvoltage to a constant voltage, thus providing protection. If a negative overvoltage is input from ANTP511, DA_ISO534A enters a voltage limiting state where D532A is forward-biased and D_ESD531 is reverse-biased (BreakDown), and performs a protection operation that diverts excess current to ANTP511 from ANTN512 or GND541 (arrow 53 in Figure 5).

[0056] [RF-DC circuit 501 (second embodiment)] Figure 7 is a block diagram showing the functional configuration of the RF-DC circuit 501 (second embodiment). Figure 8 is a cross-sectional view of the RF-DC circuit 501 (second embodiment). The RF-DC circuit 501 (second embodiment) is formed using bulk CMOS.

[0057] [Basic configuration of RF-DC circuit 501 (second embodiment)] The components of RF-DC circuit 501 (second embodiment) differ from those of RF-DC circuit 501 (first embodiment). Specifically, the difference lies in the fact that the cathodes of DA_ISO534A and DSub_ISO534B are connected to VCC513.

[0058] [Connection relationship of RF-DC circuit 501 (second embodiment)] Unlike the RF-DC circuit 501 (first embodiment), the RF-DC circuit 501 (second embodiment) does not have the DSub_ISO534B connected to the ANTP511 terminal, thus eliminating the parasitic capacitance of the ANTP511 and resulting in more favorable power reception efficiency. The ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected to VCC513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between the other end of C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to GND514. One end of the Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the Voltage Clamp ESD541 is connected to GND514.

[0059] [Operation of RF-DC circuit 501 (second embodiment)] The operation when a positive or negative overvoltage is input from ANTP511 is the same as in the first embodiment, and in the RF-DC circuit 501 (second embodiment), efficient RF-DC conversion can be achieved while providing effective circuit protection against overvoltage. The operation when a positive overvoltage is input from ANTP511 is the same as in the first embodiment, and in the RF-DC circuit 501 (second embodiment), efficient RF-DC conversion can be achieved while providing effective circuit protection against overvoltage. Unlike the first embodiment, the operation when a negative overvoltage is input from ANTP511 differs. In the RF-DC circuit 501 (second embodiment), when a negative overvoltage is input from ANTP511, D532A enters a forward-biased voltage limit state and D_ESD531 enters a reverse-biased (BreakDown) voltage limit state, and a protection operation is performed to divert excess current from ANTN512 or GND541 to ANTP511. Unlike the first embodiment, since there is no connection from the ANTP511 terminal to the cathode of DSub_ISO534B, the parasitic capacitance of DSub_ISO534B is eliminated, enabling efficient RF-DC conversion while also providing effective circuit protection against overvoltage. Refer to Figure 8 to explain the operation as a semiconductor circuit. Figure 8 shows a semiconductor device formed on a P-type substrate (PSUB). Its operation as a semiconductor circuit differs from that of the RF-DC circuit 501 (first embodiment). Specifically, when the terminal voltage of ANTP511 is higher than the forward voltage of D_ESD531 and DA_ISO534A than the VCC513 voltage, the forward bias of D_ESD531 or DA_ISO534A is lower, and it operates to store energy in the capacitor C_storage522 connected to VCC513, thereby contributing to improved rectification efficiency. Furthermore, under the condition that the ANTP terminal voltage is negative, the rectification efficiency is significantly improved because the Dsub_ISO534 is a connection that is not visible from the ANTP terminal, compared to the RF-DC circuit 501 (first embodiment), thus minimizing the effect of parasitic capacitance.

[0060] [RF-DC circuit 501 (third embodiment)] Figure 9 is a block diagram showing the functional configuration of the RF-DC circuit 501 (third embodiment). Figure 10 is a first cross-sectional view of the RF-DC circuit 501 (third embodiment). Figure 11 is a second cross-sectional view of the RF-DC circuit 501 (third embodiment). The RF-DC circuit 501 (third embodiment) is formed using bulk CMOS.

[0061] [Basic configuration of RF-DC circuit 501 (third embodiment)] The explanation of the configuration that overlaps with RF-DC circuit 501 (second embodiment) will be omitted. Q551A and Q551B are NMOS transistors that provide rectification functionality in place of diodes D532A and D532B in the RF-DC circuit 501 (first embodiment). Gate Ctrl552 is a circuit that independently controls the gate voltages of Q551A and Q551B. DBG_ISO561 is a back gate isolation diode that controls the back gates of Q551A and Q551B. DBG_ISO_Q561A is a back gate isolation diode for Q551A, providing electrical isolation and control between the back gate of Q551A and GND514. Dsub_ISO_Q561A is a diode between Isolation N+ (DBG_ISO_Q561A cathode) of Q551A and PSUB, and is a diode for isolating the drain and source of Q551A from PSUB (=GND513). Dsub_ISO_Q561B is a diode between Isolation N+ of Q551B (DBG_ISO=Q561C cathode) and PSUB, and is a diode that isolates the drain and source of Q551B from PSUB (=GND513). DBG_ISO=Q561C is a back gate isolation diode for Q551B, providing electrical isolation and control between the back gate of Q551B and PSUB (GND514). Gate565 is the gate electrode of an NMOS transistor and controls the operation of the transistor.

[0062] [Connection relationship of RF-DC circuit 501 (third embodiment)] The RF-DC circuit 501 (third embodiment) includes a fourth diode provided between the capacitor and the power supply voltage terminal, and a fifth diode provided between the capacitor and the GND 514 output. The fourth and fifth diodes are configured as NMOS transistors (Q551B and Q551A). specifically, The ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the N1 node. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected to node N1. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected to VCC513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to GND514. The anode of DBG_ISO=Q561C is connected to node N1. The cathode of DBG_ISO=Q561C is connected to VCC513. The drain of the Q551B (NMOS) is connected to node N1. The source of the Q551B is connected to VCC513. The gate of the Q551B is connected to Gate Ctrl552. The cathode of DSub_ISO_Q561B is connected between the source of Q551B and VCC513. The anode of DSub_ISO_Q561B is connected to GND514. The drain of the Q551A (NMOS) is connected to the ANTN512. The source of the Q551A is connected to the N1 node. The gate of the Q551A is connected to the Gate Ctrl552. The anode of DSub_ISO_Q561A is connected between the drain of Q551A and ANTN512. The cathode of DSub_ISO_Q561A is connected to the anode of DSub_ISO_Q561A and is connected to ANTN512 and GND514. Gate Ctrl552 is connected to gates Q551A and Q551B. One end of the voltage clamp ESD541 is connected to VCC513. The other end of the voltage clamp ESD541 is connected to GND514. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to GND514.

[0063] [Operation of RF-DC circuit 501 (third embodiment)] Unlike the RF-DC circuit 501 (first embodiment), the RF-DC circuit 501 (third embodiment), like the RF-DC circuit 501 (second embodiment), can suppress the effects of parasitic capacitance while providing overvoltage protection in low-cost bulk processes. When an RF signal is input from ANTP511, this high-frequency signal reaches C521. Since D_ESD531 is connected in parallel with C521, during the positive half-cycle of the RF signal, if C521 is charged above the forward voltage (Vf) of D_ESD531, it enters a reverse-biased state, which does not affect the normal RF signal and maintains the efficiency of the circuit. In the RF-DC circuit 501 (first embodiment), instead of diodes D532A and D532B, NMOS transistors Q551A and Q551B function as rectifiers, converting the RF signal to direct current (DC). The gate voltages of Q551A and Q551B are independently controlled by the Gate Ctrl552 circuit, and are set so that the Vt voltage at which the MOS turns ON is lower than the SBD Vf. During the negative half-cycle of the RF signal, Q551A turns on and charges C521. During the positive half-cycle of the RF signal, Q551B turns on and charges C_storage522. By controlling the NMOS gate voltage so that the IsolationNMOS Vt is approximately 0.1V for an SBD Vf of 0.3V, the efficiency gain resulting from the 0.2V difference is improved. With DBG_ISO=Q561C, the back gate potential of Q551B follows the drain potential. The rectified and stored power is supplied to the connected device through the VCC513 terminal. The Voltage Clamp ESD541 is connected between VCC513 and GND514, providing protection in case the output voltage rises excessively. If a negative overvoltage is input from ANTP511, the current is discharged from GND514 through the body diode of Q551A, D_ESD531, thus protecting the device connected to VCC513 from overvoltage. If a positive overvoltage is input from ANTP511, the current is discharged from D_ESD531 through the body diode of Q551B, Voltage Clamp ESD541, and GND514, thus protecting the device connected to VCC513 from overvoltage.

[0064] The operation as a semiconductor circuit will be explained with reference to Figures 10 and 11. Figures 10 and 11 show semiconductor devices formed on a P-type substrate (PSUB). On a P-type substrate (PSUB), N+ and P+ regions separated by STI are formed. Q551B, shown in Figure 11, is configured as an NMOS transistor and has an N+ source / drain region within the P-well. Q551A, shown in Figure 10, is configured separately as an NMOS transistor. Figure 10 is configured as an NMOS transistor and has an N+ source / drain region within the P-well. DSsub_ISO_Q561B is a diode formed between the N+ region and the PSUB. It isolates the source / drain of Q551B from the PSUB, enabling operation dependent on the VCC513 potential and suppressing parasitic effects. DBG_ISO_Q561A is a diode formed between the P+ and N+ regions of Q551A. It makes the back gate potential of Q551A follow the drain potential and optimizes the transistor characteristics. In Figure 11, DBG_ISO=Q561C is a diode formed between the P+ and N+ regions of Q551B. The back gate potential of Q551B is made to follow the drain potential, optimizing the transistor characteristics. DSub_ISO_Q561B is a diode formed between the N+ region PSUBs. It isolates the source / drain of Q551B from the PSUB, enabling operation dependent on the VCC513 potential and suppressing parasitic effects. The gate voltage is controlled by the Gate Ctrl552 circuit, and it turns on at a Vt voltage lower than the SBD's Vf. It turns on during the positive half-cycle of the RF signal and charges the C_storage522. During normal operation, the RF signal passes through C521, and Q551A and Q551B conduct alternately to perform rectification. If a negative overvoltage is input from ANTP511, the excess current is discharged through the body diode Q551A and D_ESD531. If a positive overvoltage is input from ANTP511, the excess current is discharged through D_ESD531 and the body diode Q551B.

[0065] [RF-DC circuit 501 (fourth embodiment)] Figure 12 is a block diagram showing the functional configuration of the RF-DC circuit 501 (fourth embodiment). Figure 13 is a cross-sectional view of the RF-DC circuit 501 (fourth embodiment). The RF-DC circuit 501 (fourth embodiment) is formed using SOI (Silicon-On-Insulator) CMOS. SOI CMOS is a manufacturing method in which a thin silicon layer is formed on a silicon substrate with an insulating layer (embedded oxide layer) in between, and the device is fabricated on top of it. The manufacturing process is complex and generally more expensive than bulk CMOS. Because heat conduction is inhibited by the insulating layer, self-heating problems are more likely to occur compared to bulk CMOS. Parasitic capacitance with the substrate is significantly reduced, and even if D532A and D532B are replaced with SOI process CMOS, the structure will basically be ISO2 insulating. As a result, compared to bulk CMOS, the parasitic capacitance is eliminated, improving high-frequency characteristics and efficiency.

[0066] [Basic configuration of RF-DC circuit 501 (fourth embodiment)] The RF-DC circuit 501 (fourth embodiment) is constructed using an SOI (Silicon-On-Insulator) process, is isolated from the PSUB by a BOX (SiO2), and has a process structure that does not have parasitic capacitance between the PSUB substrate and the transistor and diode configuration. The explanation of the configuration that overlaps with the RF-DC circuit 501 (first embodiment) will be omitted. The D_ESD531 is an ESD (electrostatic discharge) protection diode added in parallel to the C521. Because it acts as a capacitor in parallel with the C521 with reverse bias, its structure minimizes impact on circuit operation and efficiency. It provides protection for the C521 from overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress). BOX566 (Buried Oxide) represents the embedded oxide layer, a characteristic of SOI structures. This significantly reduces parasitic capacitance between devices. P- indicates a P-type region within the SOI layer, forming the anode side of D_ESD531. N+ indicates a high-concentration N-type region within the SOI layer, forming the cathode side of D_ESD531. PSUB indicates a P-type substrate at the bottom layer of the SOI structure. It is electrically isolated from the upper device layer by a BOX566 layer. This configuration leverages the advantages of the SOI process while achieving effective overvoltage protection. The addition of D_ESD531 and the modification of Voltage Clamp ESD541 allow for overvoltage protection while maintaining circuit operating efficiency.

[0067] [Connection relationship of RF-DC circuit 501 (fourth embodiment)] The RF-DC circuit 501 (fourth embodiment) is formed using an SOI process. For example, the RF-DC circuit 501 (fourth embodiment) is formed using SOI CMOS. In the RF-DC circuit 501 (fourth embodiment), the diode is formed in the silicon layer on the insulating layer. specifically, The ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between the other end of C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of C_storage522 is connected to VCC513. The other end of C_storage522 is connected to GND514. One end of the Voltage Clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the Voltage Clamp ESD541 is connected to GND514. D_ESD531 consists of a P- region (anode side) and an N+ region (cathode side), which are formed on a BOX566 (embedded oxide film) layer. The BOX566 layer electrically isolates the device layer from the PSUB (P-type substrate).

[0068] [Operation of RF-DC circuit 501 (fourth embodiment)] When an RF signal is input from ANTP511, this high-frequency signal reaches C521 directly. Since D_ESD531 is connected in parallel with C521, during the positive half-cycle of the RF signal, if C521 is charged above the forward voltage (Vf) of D_ESD531, it will be in a reverse-biased state. As a result, D_ESD531 does not affect the normal RF signal, and the efficiency of the circuit can be maintained. D532A and D532B function as rectifiers, converting the RF signal to DC. During the negative half-cycle of the RF signal, D532A conducts and charges C521. During the positive half-cycle of the RF signal, D532B conducts and charges C_storage522. When the charging voltage to C521 is less than or equal to the forward voltage (Vf) of D_ESD531, as the ANTP511 voltage rises, current flows through the path D_ESD531→D532B, charging C_storage522. This allows for efficient power storage even in low-voltage conditions (arrow 64 in Figure 12). The rectified and stored power is supplied to the connected device through the VCC513 terminal. Because the Voltage Clamp ESD541 is connected between VCC513 and GND514, it also provides protection in case the output voltage rises excessively (overvoltage).

[0069] When a positive overvoltage is input from ANTP511, refer to arrow 61 in Figure 12 for further explanation. When a positive overvoltage (electrostatic discharge, ESD) is input from ANTP511, the current is discharged from D_ESD531 through D532B, Voltage Clamp ESD541, and GND514, thus protecting the device connected to VCC513 from the overvoltage. When a negative overvoltage (electrostatic discharge, ESD) is input from ANTP511, refer to arrow 62 in Figure 12 for further explanation. When a negative overvoltage is input from ANTP511, the current is discharged from GND514 through D532A and D_ESD531, thus protecting the device connected to VCC513 from the overvoltage. If an overvoltage signal is input between ANTP511 and ANTN512, refer to arrow 63 in Figure 12 for further explanation. When an overvoltage signal is input between ANTP511 and ANTN512, the current is discharged from D_ESD531 through D532B, Voltage Clamp ESD541, and ANTN512, thus protecting the device connected to VCC513 from overvoltage. The internal circuitry of RF-DC circuit 501 is also protected.

[0070] Refer to Figure 13 to explain the operation as a semiconductor circuit. Figure 13 shows a semiconductor device in which BOX566 (embedded oxide layer, SiO2) is formed on a P-type substrate (PSUB). A P- layer (silicon active layer) is formed on a BOX566 layer, and N+ and P+ regions separated by STI (Shallow Trench Isolation) are arranged within it. This structure is called the SOI process. The D_ESD531 is a diode formed between the P+ and N+ regions. It is normally reverse-biased in response to the input signal from the ANTP511. Under overvoltage conditions, it becomes forward-biased, providing protection. The SOI structure significantly reduces parasitic capacitance between the device and the substrate. This improves high-frequency characteristics and enhances the efficiency of RF-DC conversion. D532A and D532B function as rectifiers. Depending on the positive and negative half-cycles of the RF signal, D532A and D532B alternately conduct, charging C521 and C_storage522. The D_ESD531 does not affect normal operation, but forms a protection path in the event of overvoltage. If a negative overvoltage is input from ANTP511, it is discharged through the path GND514, D532A, and D_ESD531, thus protecting the device connected to VCC513 from overvoltage. If a positive overvoltage is input from ANTP511, it is discharged through the path D_ESD531, D532B, Voltage Clamp ESD541, and GND514, thus protecting the device connected to VCC513 from overvoltage. Advantages of the SOI structure include improved isolation between devices and reduced parasitic effects. Capacitive coupling with the substrate is reduced, resulting in improved high-frequency characteristics.

[0071] <Basic Computer Hardware Configuration> Figure 14 is a block diagram showing the basic hardware configuration of computer 90. Computer 90 includes at least a processor 901, main memory 902, auxiliary memory 903, and a communication interface 991. These are electrically connected to each other by a communication bus 921.

[0072] The processor 901 is hardware for executing the instruction set written in a program. The processor 901 consists of an arithmetic unit, registers, peripheral circuits, etc.

[0073] Main memory 902 is used to temporarily store programs and data processed by programs, etc. For example, it is a volatile memory such as DRAM (Dynamic Random Access Memory).

[0074] Auxiliary storage device 903 refers to a storage device for saving data and programs. Examples include flash memory, HDD (Hard Disc Drive), magneto-optical disk, CD-ROM, DVD-ROM, and semiconductor memory.

[0075] The IF991 communication interface is an interface for inputting and outputting signals for communication with other computers via a network using wired or wireless communication standards. A network consists of various mobile communication systems, such as the internet, LANs, and wireless base stations. For example, a network includes 3G, 4G, and 5G mobile communication systems, LTE (Long Term Evolution), and wireless networks that can connect to the internet via designated access points (e.g., Wi-Fi®). When connecting wirelessly, communication protocols include, for example, Z-Wave®, ZigBee®, and Bluetooth®. When connecting via a wired connection, the network also includes connections made directly via USB (Universal Serial Bus) cables, etc.

[0076] Furthermore, by distributing all or part of each hardware configuration across multiple computers 90 and connecting them to each other via a network, a computer 90 can be virtually realized. Thus, the concept of computer 90 includes not only a computer 90 housed in a single enclosure or case, but also a virtualized computer system.

[0077] <Basic Functional Configuration of Computer 90> The functional configuration of the computer realized by the basic hardware configuration of computer 90 (Figure 14) will be explained. The computer comprises at least one functional unit: a control unit, a memory unit, and a communication unit.

[0078] Furthermore, the functional units of computer 90 can also be realized by distributing all or part of each functional unit across multiple computers 90 interconnected via a network. The concept of computer 90 includes not only a single computer 90 but also a virtualized computer system.

[0079] The control unit is realized when the processor 901 reads various programs stored in the auxiliary storage device 903, loads them into the main memory device 902, and executes processing according to those programs. The control unit can realize various functional units that perform information processing depending on the type of program. In this way, the computer is realized as an information processing device that performs information processing.

[0080] The memory unit is implemented by the main memory 902 and the auxiliary memory 903. The memory unit stores data, various programs, and various databases. The processor 901 can also reserve memory areas corresponding to the memory unit in the main memory 902 or the auxiliary memory 903 according to the program. The control unit can also cause the processor 901 to perform operations such as adding, updating, and deleting data stored in the memory unit according to the various programs.

[0081] A database, specifically a relational database, is used to manage and link together tabular data sets called masters, which are structurally defined by rows and columns. In a database, tables are called tables, masters are called masters, the columns of tables are called columns, and the rows of tables are called records. In a relational database, relationships can be established and linked between tables and masters. Typically, each table and master has a primary key column to uniquely identify records, but setting a primary key column is not mandatory. The control unit can instruct the processor 901 to add, delete, or update records in specific tables and masters stored in the memory unit, according to various programs. Furthermore, by storing data, various programs, and various databases in the memory unit, the information processing device and information processing system related to this disclosure can be considered to have been manufactured.

[0082] Furthermore, the databases and masters in this disclosure may include any data structures (lists, dictionaries, associative arrays, objects, etc.) in which information is structurally defined. Data structures also include data that can be considered as data structures by combining data with functions, classes, methods, etc., written in any programming language.

[0083] The communication unit is implemented by the communication IF991. The communication unit provides the functionality to communicate with other computers 90 via the network. The communication unit can receive information transmitted from other computers 90 and input it to the control unit. The control unit can cause the processor 901 to perform information processing on the received information according to various programs. The communication unit can also transmit information output from the control unit to other computers 90.

[0084] Furthermore, each of the above-mentioned configurations, functions, processing units, processing means, etc., may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. The present invention can also be implemented by software program code that realizes the functions of the embodiment. In this case, a storage medium on which the program code is recorded is provided to a computer, and the processor of that computer reads the program code stored in the storage medium. In this case, the program code read from the storage medium itself realizes the functions of the embodiment described above, and the program code itself and the storage medium on which it is stored constitute the present invention. Examples of storage media used to supply such program code include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs, optical disks, magneto-optical disks, CD-Rs, magnetic tapes, non-volatile memory cards, ROMs, and the like.

[0085] Furthermore, the program code that implements the functions described in this embodiment can be implemented in a wide range of programming or scripting languages, such as assembler, C / C++, Perl, Shell, PHP, and Java (registered trademark).

[0086] Furthermore, the program code for the software that implements the functions of the embodiment may be distributed via a network and stored in a storage means such as a computer's hard disk or memory, or in a storage medium such as a CD-RW or CD-R, and the computer's processor may read and execute the program code stored in the storage means or storage medium.

[0087] The functions realized by the components described herein may be implemented in a circuit or processing circuitry, including general-purpose processors, application-specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), CPUs (a Central Processing Unit), conventional circuits, and / or combinations thereof, programmed to realize the functions described herein. A processor is considered to be a circuit or processing circuitry, including transistors and other circuits. A processor may be a programmed processor that executes a program stored in memory. In this specification, circuitry, unit, and means are hardware programmed to perform or execute the functions described herein. Such hardware may be any hardware disclosed herein, or any hardware known to be programmed to perform or execute the functions described herein. If the hardware is a processor that is considered to be a type of circuitry, then the circuitry, means, or unit is a combination of hardware and software used to constitute the hardware and / or processor.

[0088] While several embodiments of this disclosure have been described above, these embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications are permitted without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0089] (Note) The details described in each of the above embodiments are noted below.

[0090] (Note 1) (Note 1) In an RF-DC circuit for a wireless power receiving device, the RF-DC circuit comprises a capacitor located between the positive terminal of the antenna and the power supply voltage terminal, and a diode connected in parallel with the capacitor, capable of outputting an overvoltage input from the positive terminal of the antenna to the GND output, wherein the connection between the positive terminal of the antenna and the capacitor is not connected to an overvoltage protection element. This suppresses the adverse effects on the output voltage at the power supply terminal due to the parasitic capacitance of the overvoltage protection element (ESD protection element), while also preventing overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress) from being output from the power supply terminal. It allows for the protection of devices connected to the power supply terminal without requiring a complex circuit configuration.

[0091] (Note 2) (Note 2) The RF-DC circuit described in Appendix 1, wherein an overvoltage protection element is connected between the capacitor and the power supply voltage terminal, and the overvoltage protection element can output overvoltage to the GND output via the antenna positive terminal, diode, and the overvoltage protection element. This allows the overvoltage protection element to be placed between the capacitor and the power supply terminal, effectively diverting the overvoltage from the antenna to the GND output. This protects the device connected to the power supply terminal while suppressing performance degradation of the RF-DC circuit.

[0092] (Note 3) (Note 3) The RF-DC circuit is the RF-DC circuit described in Appendix 1, which is configured as a semiconductor circuit. This allows for miniaturization, higher integration, and improved mass production capabilities by configuring the RF-DC circuit as a semiconductor circuit. This enables overall miniaturization and cost reduction of the wireless power receiving device.

[0093] (Note 4) (Note 4) The RF-DC circuit includes a second diode and a third diode connected between the positive terminal of the antenna and the diode, the RF-DC circuit is formed of bulk CMOS, and the diode, the second diode and the third diode are formed in a channel region on a silicon substrate, as described in Appendix 1. This allows for the implementation of RF-DC circuits at a lower cost compared to SOI processes by using a bulk CMOS process. Furthermore, the addition of a second and third diode suppresses the adverse effects of parasitic diodes in bulk processes. This enables the provision of low-cost, high-performance RF-DC circuits.

[0094] (Note 5) (Note 5) The RF-DC circuit described in Appendix 4 has outputs for the second and third diodes connected to an overvoltage protection element and a power supply terminal. This allows for more efficient overvoltage protection by connecting the outputs of the second and third diodes to the overvoltage protection element and the power supply voltage terminal, while suppressing the effects of parasitic capacitance. As a result, high rectification efficiency can be achieved in the CMOS structure while suppressing the effects of parasitic elements.

[0095] (Note 6) (Note 6) The RF-DC circuit is the RF-DC circuit described in Appendix 4, comprising a fourth diode provided between the capacitor and the power supply voltage terminal, and a fifth diode provided between the capacitor and the GND output, wherein the fourth and fifth diodes are configured as NMOS transistors. This allows the rectification efficiency of the circuit to be improved by configuring the fourth and fifth diodes as NMOS transistors. NMOS transistors have a lower forward voltage drop compared to conventional diodes, enabling efficient power conversion, especially in low-power wireless power receiving systems. This improves the overall power efficiency of the system, allowing for longer-range wireless power transfer and smaller receiving antennas.

[0096] (Note 7) (Note 7) The RF-DC circuit is formed by an SOI process, and the diode is formed in a silicon layer on an insulating layer, as described in Appendix 1. This allows for a reduction in parasitic capacitance compared to bulk CMOS by forming the RF-DC circuit with SOI CMOS. Forming a silicon layer on top of the insulating layer reduces capacitive coupling with the substrate, improving high-frequency characteristics. This enables efficient operation in higher frequency bands, leading to improved performance and miniaturization of wireless power receiving systems. [Explanation of Symbols]

[0097] RF-DC circuit 501, ANTP511 (antenna positive terminal), ANTN512 (antenna negative terminal), VCC513 (power supply voltage terminal), GND514 (ground terminal), C521 (capacitor), C_storage522 (storage capacitor), D_ESD531 (ESD protection diode), D532A, D532B (rectifier diodes), DA_ISO534A, DSub_ISO534B (isolation diodes), Voltage Clamp ESD541 (voltage clamp ESD protection element), Q551A, Q551B (NMOS transistors), Gate Ctrl552 (gate voltage control circuit), DBG_ISO561 (back gate isolation diode), DBG_ISO_Q561A (back gate isolation diode for Q551A), DSub_ISO_Q561B (back gate isolation diode for Q551B), DBG_ISO=Q561C (drain-back gate connection diode for Q551B), Gate565 (gate electrode of NMOS transistor) 565, BOX566 (buried oxide layer) 566

Claims

1. In the RF-DC circuit of a wireless power receiving device, The RF-DC circuit described above is A capacitor is provided between the positive terminal of the antenna and the power supply voltage terminal, A diode connected in parallel with the capacitor and capable of outputting an overvoltage input from the positive terminal of the antenna to the GND output, Equipped with, The connection between the positive terminal of the antenna and the capacitor is not connected to an overvoltage protection element. RF-DC circuit.

2. The overvoltage protection element is connected between the capacitor and the power supply voltage terminal. The overvoltage protection element is capable of outputting the overvoltage to the GND output via the antenna positive terminal, the diode, and the overvoltage protection element. The RF-DC circuit according to claim 1.

3. The RF-DC circuit is configured as a semiconductor circuit. The RF-DC circuit according to claim 1.

4. The RF-DC circuit described above is The antenna positive terminal and the diode are connected to a second diode and a third diode, The RF-DC circuit is formed using bulk CMOS, The diode, the second diode, and the third diode are formed in a channel region on a silicon substrate. The RF-DC circuit according to claim 1.

5. The outputs of the second diode and the third diode are connected to the overvoltage protection element and the power supply voltage terminal. The RF-DC circuit according to claim 4.

6. The RF-DC circuit described above is A fourth diode is provided between the capacitor and the power supply voltage terminal, A fifth diode is provided between the capacitor and the GND output, Equipped with, The fourth diode and the fifth diode are configured as NMOS transistors. The RF-DC circuit according to claim 4.

7. The RF-DC circuit is formed using an SOI process. The diode is formed on the silicon layer on the insulating layer, The RF-DC circuit according to claim 1.

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