Semiconductor equipment

Abstract

To provide a semiconductor device that enables high integration of transistors including an oxide semiconductor layer. [Solution] The semiconductor device includes a first transistor comprising a first oxide semiconductor layer, a first gate electrode layer on the first oxide semiconductor layer, and an insulating layer on the first gate electrode layer, and a second transistor comprising a second oxide semiconductor layer located above the first oxide semiconductor layer, a source electrode layer, and a drain electrode layer superimposed on the source electrode layer with the second oxide semiconductor layer in between, wherein one of the source electrode layer and drain electrode layer of the second transistor is provided as the same layer as the first gate electrode layer of the first transistor, and the other of the source electrode layer and drain electrode layer of the second transistor is provided on an insulating layer, the insulating layer includes an opening that exposes one of the source electrode layer and drain electrode layer of the second transistor, and the second oxide semiconductor layer is provided within the opening.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor. [Background technology]

[0002] In recent years, the development of semiconductor devices using oxide semiconductors has progressed as an alternative to silicon semiconductors using amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Documents 1 to 6). For example, transistors that utilize an oxide semiconductor layer containing an oxide semiconductor as a channel can be manufactured with a simple structure and low-temperature process, similar to transistors containing an amorphous silicon layer. Transistors containing an oxide semiconductor layer are known to have higher field-effect mobility than transistors containing an amorphous silicon layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Publication No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Publication No. 2018-006730 [Patent Document 5] Japanese Patent Publication No. 2016-184771 [Patent Document 6] Japanese Patent Publication No. 2021-108405 [Overview of the project] [Problems that the invention aims to solve]

[0004] With the miniaturization of semiconductor devices, there is a demand for high-density integration of transistors, even those containing oxide semiconductor layers. One known method for high-density integration of transistors is stacking them. However, in transistors containing oxide semiconductor layers, there is a problem in that the characteristics of the lower transistors are affected by the manufacturing process of the upper transistors.

[0005] One embodiment of the present invention aims to provide a semiconductor device that enables high integration of transistors including an oxide semiconductor layer. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first transistor including a first oxide semiconductor layer and a second transistor including a second oxide semiconductor layer located above the first oxide semiconductor layer, wherein the first transistor further includes a first gate electrode layer on the first oxide semiconductor layer and an insulating layer on the first gate electrode layer, and the second transistor further includes a source electrode layer and a drain electrode layer superimposed on the source electrode layer with a second oxide semiconductor layer in between, wherein one of the source electrode layer and the drain electrode layer of the second transistor is provided as the same layer as the first gate electrode layer of the first transistor, and the other of the source electrode layer and the drain electrode layer of the second transistor is provided on an insulating layer, the insulating layer includes an opening that exposes one of the source electrode layer and the drain electrode layer of the second transistor, and the second oxide semiconductor layer is provided within the opening. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing the configuration of a semiconductor device relating to one embodiment of the present invention. [Figure 2] This is a schematic plan view showing the configuration of the first transistor of a semiconductor device according to one embodiment of the present invention. [Figure 3] This is a schematic plan view showing the configuration of a second transistor in a semiconductor device according to one embodiment of the present invention. [Figure 4] It is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19]It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 29] It is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 30] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 31] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0008] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, and shape of the components compared to the actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with respect to previously shown figures are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" or "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Also, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be placed between the substrate and the oxide semiconductor layer. "Up" or "downward" refers to the stacking order in a structure in which multiple layers are stacked, and when referring to "pixel electrodes above the semiconductor device," the semiconductor device and the pixel electrodes may not overlap in a plan view. On the other hand, when referring to "pixel electrodes vertically above the semiconductor device," it means that the semiconductor device and the pixel electrodes overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0010] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0011] In this specification, "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are included as forms of semiconductor devices. The semiconductor devices of the embodiments shown below may be, for example, integrated circuits (ICs) such as display devices and microprocessors (MPUs), or transistors used in memory circuits.

[0012] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in the embodiments, liquid crystal display devices including a liquid crystal layer and organic EL display devices including an organic EL layer are described as examples. However, the structures described in the embodiments can be applied to other display devices including electro-optical layers as described above.

[0013] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0014] The source and drain electrodes of a transistor may have their functions reversed depending on the voltage supplied to each electrode. Therefore, in this specification, the terms "source electrode layer" and "drain electrode layer" may be interchangeable depending on the context. Similarly, in this specification, the terms "source region" and "drain region" may be interchangeable depending on the context.

[0015] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0016] <First Embodiment> A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 16.

[0017] [1. Configuration of semiconductor device 10] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention. As shown in Figure 1, the semiconductor device 10 includes two transistors (a first transistor Tr1 and a second transistor Tr2) provided on a substrate 100. The structure of the second transistor Tr2 is different from the structure of the first transistor Tr1.

[0018] [1-1. Configuration of the first transistor Tr1] The first transistor Tr1 includes a light-shielding layer 110, a first insulating layer 120, a first oxide semiconductor layer 130, a second insulating layer 140, a gate electrode layer 150-1, a third insulating layer 160, a source electrode layer 180-1, a drain electrode layer 180-2, a fourth insulating layer 190, and a fifth insulating layer 210. The light-shielding layer 110 is provided on the substrate 100. The first insulating layer 120 covers the light-shielding layer 110 and is provided on the substrate 100. The first oxide semiconductor layer 130 is provided on the first insulating layer 120. The second insulating layer 140 covers the first oxide semiconductor layer 130 and is provided on the first insulating layer 120. The gate electrode layer 150-1 is superimposed on the first oxide semiconductor layer 130 and is provided on the second insulating layer 140. The third insulating layer 160 covers the gate electrode layer 150-1 and is provided on top of the second insulating layer 140. The second insulating layer 140 and the third insulating layer 160 are provided with a first opening OP1 and a second opening OP2. The first oxide semiconductor layer 130 is exposed at the first opening OP1 and the second opening OP2. The source electrode layer 180-1 is provided inside the first opening OP1 and on top of the third insulating layer 160. The drain electrode layer 180-2 is provided inside the second opening OP2 and on top of the third insulating layer 160. The fourth insulating layer 190 covers the source electrode layer 180-1 and the drain electrode layer 180-2 and is provided on top of the third insulating layer 160. The fifth insulating layer 210 is provided on top of the fourth insulating layer 190.

[0019] The source electrode layer 180-1 and the drain electrode layer 180-2 are in contact with the first oxide semiconductor layer 130 through a first opening OP1 and a second opening OP2, respectively. That is, the source electrode layer 180-1 and the drain electrode layer 180-2 are electrically connected to the first oxide semiconductor layer 130. A second insulating layer 140 is provided between the first oxide semiconductor layer 130 and the gate electrode layer 150-1. In the first transistor Tr1, a portion of the second insulating layer 140 functions as a gate insulating layer.

[0020] The gate electrode layer 150-1 is located on the first oxide semiconductor layer 130. The first transistor Tr1 is a so-called top-gate transistor, but is not limited to this. If the light-shielding layer 110 is conductive, the light-shielding layer 110 and the first insulating layer 120 can be used as the gate electrode layer and the gate insulating layer, respectively. In this case, the first transistor Tr1 is a so-called dual-gate transistor. In a dual-gate transistor, the light-shielding layer 110 may be a floating electrode layer and may be electrically connected to the source electrode layer 180-1.

[0021] Figure 2 is a schematic plan view showing the configuration of the first transistor Tr1 of a semiconductor device 10 according to one embodiment of the present invention. As shown in Figure 2, the first oxide semiconductor layer 130 is divided into a source region SR, a drain region DR, and a channel region CR based on the gate electrode layer 150-1. The channel region CR is a region that overlaps with the gate electrode layer 150-1, while the source region SR and the drain region DR are regions that do not overlap with the gate electrode layer 150-1. The edges of the channel region CR substantially coincide with the edges of the gate electrode layer 150-1. The source region SR and the drain region DR have greater electrical conductivity than the channel region CR. The source region SR and the drain region DR have conductor properties, while the channel region has semiconductor properties. The source electrode layer 180-1 and the drain electrode layer 180-2 are in contact with the source region SR and the drain region DR, respectively.

[0022] The first channel length L1 of the first transistor Tr1 corresponds to the distance between the source region SR and the drain region DR. The first channel width W1 of the first transistor Tr1 corresponds to the width in a direction perpendicular to the direction of the first channel length L1. In other words, the first channel length L1 and the first channel width W1 of the first transistor Tr1 correspond to the length and width of the channel region CR, respectively.

[0023] [1-2. Configuration of the second transistor Tr2] The second transistor Tr2 includes a first insulating layer 120, a second insulating layer 140, a source electrode layer 150-2, a third insulating layer 160, a second oxide semiconductor layer 170, a drain electrode layer 180-3, a fourth insulating layer 190, a gate electrode layer 200, and a fifth insulating layer 210. The first insulating layer 120 and the second insulating layer 140 are provided in order on the substrate 100. The source electrode layer 150-2 is provided on the second insulating layer 140. The third insulating layer 160 covers the edge of the source electrode layer 150-2 and is provided on the second insulating layer 140. The third insulating layer 160 is provided with a third opening OP3. The source electrode layer 150-2 is exposed at the third opening OP3. The second oxide semiconductor layer 170 covers the bottom and sides of the third opening OP3 and is provided inside the third opening OP3 and on the third insulating layer 160. The drain electrode layer 180-3 is provided on the second oxide semiconductor layer 170 without overlapping with the third opening OP3. The fourth insulating layer 190 covers the second oxide semiconductor layer 170 and the drain electrode layer 180-3 and is provided inside the third opening OP3 and on the third insulating layer 160. The gate electrode layer 200 overlaps with the second oxide semiconductor layer 170 and is provided inside the third opening OP3 and on the fourth insulating layer 190. The fifth insulating layer 210 covers the gate electrode layer 200 and is provided on the fourth insulating layer 190.

[0024] The source electrode layer 150-2 is in contact with the second oxide semiconductor layer 170, located beneath it. The drain electrode layer 180-3 is in contact with the second oxide semiconductor layer 170, located on top of it. That is, the source electrode layer 150-2 and the drain electrode layer 180-3 are electrically connected to the second oxide semiconductor layer 170. A fourth insulating layer 190 is provided between the second oxide semiconductor layer 170 and the gate electrode layer 200. In the second transistor Tr2, a portion of the fourth insulating layer 190 functions as a gate insulating layer.

[0025] The source electrode layer 150-2 and the drain electrode layer 180-3 are arranged in the thickness direction of the second oxide semiconductor layer 170. The second transistor Tr2 is a so-called vertical transistor. In the second transistor Tr2, a channel is formed in a region provided on the side surface of the third opening OP3 in the second oxide semiconductor layer 170. Therefore, the second channel length L2 of the second transistor Tr2 roughly corresponds to the distance between the source electrode layer 150-2 and the drain electrode layer 180-3 in the thickness direction of the second oxide semiconductor layer 170 (see Figure 1).

[0026] The second channel length L2 may be smaller than the first channel length L1. Also, the second channel width W2 may be larger than the first channel width W1. Generally, vertical transistors can occupy a smaller area compared to top-gate and bottom-gate transistors. Therefore, by making a second vertical transistor Tr2 a part of the transistors in the semiconductor device 10, the transistors in the semiconductor device 10 can be highly integrated.

[0027] Figure 3 is a schematic plan view showing the configuration of a second transistor Tr2 of a semiconductor device 10 according to one embodiment of the present invention. In Figure 3, for the sake of explanation, the gate electrode layer 200 superimposed on the third opening OP3 on the drain electrode layer 180-3 is omitted. As shown in Figure 3, the second oxide semiconductor layer 170 is provided not only on the bottom surface of the third opening OP3 but also along the side surface of the third opening OP3. Therefore, the channel width W2 of the second transistor Tr2 generally corresponds to the inner circumference of the third opening OP3.

[0028] The planar shape of the third opening OP3 shown in Figure 3 is circular, but is not limited to this. The planar shape of the third opening OP3 may be elliptical or polygonal. Furthermore, the second oxide semiconductor layer 170 may be provided not on the entire side surface of the third opening OP3, but on a part of the side surface of the third opening OP3.

[0029] [1-3. Components of the semiconductor device 10] The first transistor Tr1 and the second transistor Tr2 share some common components. Furthermore, some of these components are formed by patterning a single deposited film and are provided as the same layer. The details of each component of the semiconductor device 10 will be described below.

[0030] [1-3-1. Circuit board 100] The substrate 100 is a support substrate for the first transistor Tr1 and the second transistor Tr2. For example, a translucent rigid substrate such as a glass substrate, quartz substrate, or sapphire substrate can be used as the substrate 100. Alternatively, a non-translucent rigid substrate such as a silicon substrate can be used as the substrate 100. Furthermore, a translucent flexible substrate such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate can be used as the substrate 100. To improve the heat resistance of the substrate 100, impurities may be introduced into the flexible substrate as described above. In addition, a substrate on which a silicon oxide film or silicon nitride film is deposited can also be used as the substrate 100.

[0031] [1-3-2. Light shielding layer 110] The light-shielding layer 110 can reflect or absorb ambient light. The light-shielding layer 110 can prevent ambient light from entering the channel region CR of the first oxide semiconductor layer 130. Therefore, it is preferable that the light-shielding layer 110 has a larger area than the channel region CR. A metallic material can be used as the light-shielding layer 110. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys thereof can be used as the light-shielding layer 110. Specifically, the alloy used for the light-shielding layer 110 is molybdenum tungsten (MoW), but is not limited to this. Furthermore, the light-shielding layer 110 only needs to be able to prevent the incidence of ambient light, and its thickness is not particularly limited.

[0032] [1-3-3. First Insulating Layer 120] The first insulating layer 120 can prevent impurities contained in the substrate 100 from diffusing into the first oxide semiconductor layer 130 and the second oxide semiconductor layer 170. In each of the first transistor Tr1 and the second transistor Tr2, the first insulating layer 120 is an underlying layer. As the first insulating layer 120, insulating oxides such as silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ), or insulating nitrides such as silicon nitride (SiN x ) or silicon oxynitride (SiN x O y ) can be used.

[0033] Here, silicon oxynitride (SiN x O y ) is a silicon oxide containing oxygen in a ratio less than that of nitrogen (x>y). Also, silicon oxynitride (SiO x N y ) is a silicon nitride containing nitrogen in a ratio less than that of oxygen (x>y).

[0034] The first insulating layer 120 may have a single-layer structure or a stacked structure. In the first transistor Tr1, the first oxide semiconductor layer 130 is in contact with the first insulating layer 120. When the first oxide semiconductor layer 130 is in contact with an insulating nitride layer, oxygen in the first oxide semiconductor layer 130 is extracted, and oxygen defects are likely to be generated in the first oxide semiconductor layer 130. Therefore, the layer in contact with the first oxide semiconductor layer 130 is preferably an insulating oxide layer. For example, the first insulating layer 120 may have a stacked structure in which an insulating oxide layer is provided on an insulating nitride layer.

[0035] [1-3-4. First Oxide Semiconductor Layer 130] The first oxide semiconductor layer 130 may have a single-layer structure or a stacked structure. Also, the first oxide semiconductor layer 130 may have an amorphous property or a crystalline property.

[0036] The first oxide semiconductor layer 130 can be fabricated using a sputtering method. The composition of the first oxide semiconductor layer 130 fabricated using a sputtering method depends on the composition of the sputtering target. In this case, the composition of the metallic elements in the first oxide semiconductor layer 130 can be determined based on the composition of the metallic elements in the sputtering target. Alternatively, the composition of the metallic elements in the first oxide semiconductor layer 130 may be determined using X-ray diffraction (XRD). Specifically, the composition of the metallic elements in the first oxide semiconductor layer 130 can be determined based on the crystal structure and lattice constants of the first oxide semiconductor layer 130 obtained from the XRD method. Furthermore, the composition of the metallic elements in the first oxide semiconductor layer 130 can also be determined using X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis. However, this does not apply to the oxygen contained in the first oxide semiconductor layer 130, as it changes depending on the sputtering process conditions.

[0037] The thickness of the first oxide semiconductor layer 130 is 10 nm or more and 100 nm or less, preferably 15 nm or more and 70 nm or less, and more preferably 15 nm or more and 40 nm or less.

[0038] [1-3-5. Second insulating layer 140] In the second transistor Tr2, the second insulating layer 140 is the underlayer, but in the first transistor Tr1, a portion of the second insulating layer 140 is in contact with the first oxide semiconductor layer 130 and functions as a gate insulating layer. Therefore, an insulating oxide can be used as the second insulating layer 140. The second insulating layer 140, which functions as a gate electrode layer, preferably has few defects and a composition close to the stoichiometric ratio. Specifically, it is preferable that no defects are observed in the second insulating layer 140 when evaluated by electron spin resonance (ESR) spectroscopy.

[0039] The thickness of the second insulating layer 140 is not particularly limited, but is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0040] [1-3-6. Gate electrode layer 150-1 and source electrode layer 150-2] The gate electrode layer 150-1 of the first transistor Tr1 and the source electrode layer 150-2 of the second transistor Tr2 are provided as the same layer. That is, the gate electrode layer 150-1 and the source electrode layer 150-2 are formed simultaneously by patterning a single conductive film. The same metallic material as the light-shielding layer 110 can be used for the gate electrode layer 150-1 and the source electrode layer 150-2.

[0041] [1-3-7. Third insulating layer 160] In the first transistor Tr1, the third insulating layer 160 is an interlayer insulating layer, while in the second transistor Tr2, it forms the side surface of the third opening OP3. As the third insulating layer 160, an insulating oxide or insulating nitride similar to that of the first insulating layer 120 can be used. The third insulating layer 160 may have a single-layer structure or a multilayer structure. For example, the third insulating layer 160 may have a multilayer structure in which an insulating oxide layer is provided on top of an insulating nitride layer. In this case, since the second oxide semiconductor layer 170 will be in contact with the insulating nitride layer, it is preferable that the thickness of the insulating nitride layer be smaller than the thickness of the insulating oxide layer.

[0042] [1-3-8. Second oxide semiconductor layer 170] The second oxide semiconductor layer 170 may have a single-layer structure or a multilayer structure. Furthermore, the second oxide semiconductor layer 170 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. Also, the same oxide semiconductor as the first oxide semiconductor layer 130 may be used for the second oxide semiconductor layer 170, or a different oxide semiconductor may be used.

[0043] The thickness of the second oxide semiconductor layer 170 is 10 nm to 150 nm, preferably 10 nm to 100 nm, and more preferably 10 nm to 50 nm.

[0044] [1-3-9. Source electrode layer 180-1, drain electrode layer 180-2, and drain electrode layer 180-3] The source electrode layer 180-1 and drain electrode layer 180-2 of the first transistor Tr1, and the drain electrode layer 180-3 of the second transistor Tr2, are provided as the same layer. That is, the source electrode layer 180-1, the drain electrode layer 180-2, and the drain electrode layer 180-3 are formed simultaneously by patterning a single conductive film. The same metallic material as the light-shielding layer 110 can be used for the source electrode layer 180-1, the drain electrode layer 180-2, and the drain electrode layer 180-3.

[0045] [1-3-10. Fourth insulating layer 190] In the first transistor Tr1, the fourth insulating layer 190 is a protective layer, but in the second transistor Tr2, a portion of the fourth insulating layer 190 is in contact with the second oxide semiconductor layer 170 and functions as a gate insulating layer. Therefore, an insulating oxide can be used as the fourth insulating layer 190. The fourth insulating layer 190, which functions as a gate insulating layer, preferably has few defects and a composition close to the stoichiometric ratio. Specifically, it is preferable that no defects are observed in the fourth insulating layer 190 when evaluated by the ESR method.

[0046] The thickness of the fourth insulating layer 190 is not particularly limited, but is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0047] [1-3-11. Guard electrode layer 200] At the bottom and sides of the third opening OP3, the gate electrode layer 200 is superimposed on the second oxide semiconductor layer 170 with the fourth insulating layer 190 in between. The gate electrode layer 200 may be provided so as to fill the third opening OP3. A metallic material similar to that used for the light-shielding layer 110 can be used for the gate electrode layer 200.

[0048] [1-3-12. Fifth insulating layer 210] The fifth insulating layer 210 is a protective layer. The fifth insulating layer 210 can be made of the same insulating nitride or insulating oxide as the first insulating layer 120. The fifth insulating layer 210 may have a single-layer structure or a laminated structure. For example, the fifth insulating layer 210 may have a laminated structure in which an insulating oxide layer is provided on top of an insulating nitride layer.

[0049] [2. Method for manufacturing the semiconductor device 10] Figure 4 is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 5 to 14 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. The method for manufacturing a semiconductor device 10 will be described below, but the method for manufacturing a semiconductor device 10 is not limited to this.

[0050] As shown in Figure 4, the method for manufacturing the semiconductor device 10 includes steps S1010 to S1130. Steps S1010 to S1130 will be described in order below, but the order of the steps in the method for manufacturing the semiconductor device 10 may be changed. Furthermore, the method for manufacturing the semiconductor device 10 may include further steps. For the sake of explanation below, the region in which the first transistor Tr1 is formed will be referred to as the first transistor formation region TFR1, and the region in which the second transistor is formed will be referred to as the second transistor formation region TFR2.

[0051] In step S1010, a light-shielding layer 110 having a predetermined pattern shape is formed on the substrate 100 within the first transistor formation region TFR1 (see Figure 5). The patterning of the light-shielding layer 110 is performed using photolithography.

[0052] In step S1020, a first insulating layer 120 is formed so as to cover the light-shielding layer 110, and then a first oxide semiconductor film 135 having a predetermined pattern shape is formed on the first insulating layer 120 within the first transistor formation region TFR1 (see Figure 6). The first insulating layer 120 is formed using chemical vapor deposition (CVD). On the other hand, the first oxide semiconductor film 135 is formed using sputtering. The first oxide semiconductor film 135 formed using sputtering has an amorphous structure. When forming the first oxide semiconductor film 135 using sputtering, the temperature of the object to be filmed (substrate 100 and the layer formed on the substrate 100) is controlled to 100°C or less, preferably 80°C or less, and more preferably 50°C or less while forming the first oxide semiconductor film 135. Furthermore, the first oxide semiconductor film 135 is formed under conditions of low oxygen partial pressure. For example, the oxygen partial pressure is 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and less than 10%. The first oxide semiconductor film 135 having an amorphous structure can be easily patterned using photolithography. For etching the first oxide semiconductor film 135, wet etching or dry etching may be used. In wet etching, the first oxide semiconductor film 135 can be etched using an acidic etching solution. For example, oxalic acid, PAN, sulfuric acid, or hydrogen peroxide can be used as the etching solution.

[0053] In step S1030, a heat treatment is performed on the first oxide semiconductor film 135 having a predetermined pattern shape (see Figure 7). Hereinafter, the heat treatment performed in step S1030 will be referred to as "OS annealing". In OS annealing, the first oxide semiconductor film 135 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300°C to 500°C, preferably 350°C to 450°C. The holding time at the target temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes.

[0054] In step S1040, a second insulating layer 140 is formed so as to cover the first oxide semiconductor layer 130, and then the first oxide semiconductor layer 130 is subjected to heat treatment (see Figure 8). Hereinafter, the heat treatment performed in step S1040 will be referred to as "oxidation annealing". The second insulating layer 140 is deposited using the CVD method. Due to the formation of the first oxide semiconductor layer 130 (i.e., patterning of the first oxide semiconductor film 135) and the formation of the second insulating layer 140 on the first oxide semiconductor layer 130, many oxygen vacancies are generated in the first oxide semiconductor layer 130. When oxidation annealing is performed, oxygen is supplied from the second insulating layer 140 to the first oxide semiconductor layer 130, and the oxygen vacancies in the first oxide semiconductor layer 130 are repaired. Alternatively, after the second insulating layer 140 is deposited, a process to introduce oxygen into the second insulating layer 140 may be performed. In this case, the amount of oxygen in the second insulating layer 140 increases, so that sufficient oxygen can be supplied to the first oxide semiconductor layer 130 by oxide annealing.

[0055] In step S1050, a conductive film 155 is deposited on the second insulating layer 140 (see Figure 9). The conductive film 155 is deposited using the sputtering method.

[0056] In step S1060, the conductive film 155 is patterned, forming a gate electrode layer 150-1 with a predetermined pattern shape within the first transistor formation region TFR1, and a source electrode layer 150-2 with a predetermined pattern shape within the second transistor formation region TFR2 (see Figure 10). That is, the gate electrode layer 150-1 and the source electrode layer 150-2 are the same layer formed from the conductive film 155. The patterning of the conductive film 155 is performed using photolithography.

[0057] In step S1070, impurities are implanted into the first oxide semiconductor layer 130 via the second insulating layer 140. For example, ion implantation can be used to implant impurities into the first oxide semiconductor layer 130. Examples of impurities that can be used include argon (Ar), phosphorus (P), or boron (B). If a gate electrode layer 150-1 is formed on the first oxide semiconductor layer 130, the gate electrode layer 150-1 acts as a mask, inhibiting the implantation of impurities into the first oxide semiconductor layer 130. Therefore, in the first oxide semiconductor layer 130, impurities are not implanted in the region overlapping with the gate electrode layer 150-1, and a channel region CR is formed in that region. On the other hand, in the first oxide semiconductor layer 130, a source region SR and a drain region DR are formed in the region where impurities have been implanted. In the source region SR and drain region DR, oxygen vacancies are generated by the implantation of impurities, and hydrogen is trapped in these oxygen vacancies. As a result, the source region SR and drain region DR are conductive and have higher electrical conductivity than the channel region CR. In step S1070, impurities are also injected into the second insulating layer 140 or the first insulating layer 120 within the second transistor formation region TFR2, using the source electrode layer 150-2 as a mask.

[0058] In step S1080, a third insulating layer 160 is formed to cover the gate electrode layer 150-1 and the source electrode layer 150-2. Subsequently, a first opening OP1 and a second opening OP2 are formed within the first transistor formation region TFR1 so as to expose the first oxide semiconductor layer 130, and a third opening OP3 is formed within the second transistor formation region TFR2 so as to expose the source electrode layer 150-2 (see Figure 12). The source region SR is exposed through the first opening OP1, and the drain region DR is exposed through the second opening OP2.

[0059] In step S1090, a second oxide semiconductor layer 170 having a predetermined pattern shape is formed within the second transistor formation region TFR2 so as to cover the bottom surface (i.e., the exposed source electrode layer 150-2) and sides of the third opening OP3 (see Figure 13). The second oxide semiconductor layer 170 is deposited using a sputtering method, and the patterning of the second oxide semiconductor layer 170 is performed using a photolithography method. Immediately after deposition, the second oxide semiconductor layer 170 is in contact with the first oxide semiconductor layer 130 at the bottom surfaces of the first opening OP1 and the second opening OP2.

[0060] Furthermore, the second oxide semiconductor layer 170 having a predetermined pattern shape may be subjected to heat treatment (so-called OS annealing).

[0061] In step S1100, a conductive film 185 is deposited on the third insulating layer 160 so as to cover the second oxide semiconductor layer 170 having a predetermined pattern shape (see Figure 14). The conductive film 185 is deposited using a sputtering method.

[0062] In step S1110, the conductive film 185 is patterned, and a source electrode layer 180-1 and a drain electrode layer 180-2 having a predetermined pattern shape are formed in the first transistor formation region TFR1, and a drain electrode layer 180-3 having a predetermined pattern shape is formed in the second transistor formation region TFR2 (see Figure 15). That is, the source electrode layer 180-1 and the drain electrode layer 180-2 in the first transistor formation region TFR1, and the drain electrode layer 180-3 in the second transistor formation region TFR2 are the same layer formed from the conductive film 185. The patterning of the conductive film 185 is performed using photolithography.

[0063] In step S1120, a fourth insulating layer 190 is formed on the third insulating layer 160 so as to cover the source electrode layer 180-1 and drain electrode layer 180-2 in the first transistor formation region TFR1, and the drain electrode layer 180-3 and the second oxide semiconductor layer 170 in the second transistor formation region TFR2. Subsequently, a gate electrode layer 200 having a predetermined pattern shape is formed on the fourth insulating layer 190 within the second transistor formation region TFR2 (see Figure 16). The fourth insulating layer 190 is deposited using the CVD method. The gate electrode layer 200 is deposited using the sputtering method, and the patterning of the gate electrode layer 200 is performed using the photolithography method. The gate electrode layer 200 is patterned to have a pattern shape that overlaps with the second oxide semiconductor layer 170 via the fourth insulating layer 190 on the bottom and side surfaces of the third opening OP3.

[0064] Furthermore, the second oxide semiconductor layer 170 may be subjected to heat treatment (so-called oxide annealing) after the formation of the fourth insulating layer 190 but before the formation of the gate electrode layer 200. Oxidation annealing can repair oxygen vacancies in the second oxide semiconductor layer 170.

[0065] In step S1130, a fifth insulating layer 210 is formed on the fourth insulating layer 190 so as to cover the gate electrode layer 200 having a predetermined pattern shape. This manufactures the semiconductor device 10 shown in Figure 1.

[0066] The semiconductor device 10 according to this embodiment includes a first transistor Tr1 including a first oxide semiconductor layer 130 and a second transistor Tr2 including a second oxide semiconductor layer 170 formed above the first oxide semiconductor layer 130. The first transistor Tr1 and the second transistor Tr2 share some components, and the second transistor Tr2 is fabricated on top of the first transistor Tr1. Even if the second transistor Tr2 is fabricated after the formation of the first oxide semiconductor layer 130 of the first transistor Tr1, the first transistor Tr1 is hardly affected by the fabrication process of the second transistor Tr2, and fluctuations in the characteristics of the first transistor Tr1 can be suppressed. Furthermore, by making the second transistor Tr2 a vertical transistor, the area occupied by the second transistor Tr2 can be further reduced. Therefore, the semiconductor device 10 can achieve high integration of transistors.

[0067] <Second Embodiment> Referring to Figures 17 to 27, a semiconductor device 20 according to one embodiment of the present invention will be described. Note that if the configuration of the semiconductor device 20 is the same as that of the semiconductor device 10, the description of the configuration of the semiconductor device 20 may be omitted.

[0068] [1. Configuration of the semiconductor device 20] Figure 17 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 according to one embodiment of the present invention. As shown in Figure 17, the semiconductor device 20 includes three transistors (a first transistor Tr1, a second transistor Tr2, and a third transistor Tr3) provided on a substrate 100. The structure of the third transistor Tr3 differs from the structures of the first transistor Tr1 and the second transistor Tr2.

[0069] Here, the configuration of the first transistor Tr1 according to this embodiment is the same as the configuration of the first transistor Tr1 described in the first embodiment, so its description is omitted. Similarly, the configuration of the second transistor Tr2 according to this embodiment is the same as the configuration of the second transistor Tr2 described in the first embodiment, so its description is omitted. However, in this embodiment, for the sake of explanation, the second oxide semiconductor layer 170 and the gate electrode layer 200 of the first embodiment will be described as the second oxide semiconductor layer 170-1 and the gate electrode layer 200-1, respectively.

[0070] [1-1. Configuration of the third transistor Tr3] The third transistor Tr3 includes a third insulating layer 160, a third oxide semiconductor layer 170-2, a fourth insulating layer 190, a gate electrode layer 200-2, a fifth insulating layer 210, a source electrode layer 220-1, a drain electrode layer 220-2, and a sixth insulating layer 230. The third oxide semiconductor layer 170-2 is provided on the third insulating layer 160. The fourth insulating layer 190 covers the third oxide semiconductor layer 170-2 and is provided on the third insulating layer 160. The gate electrode layer 200-2 is superimposed on the third oxide semiconductor layer 170-2 and is provided on the fourth insulating layer 190. The fifth insulating layer 210 covers the gate electrode layer 200-2 and is provided on the fourth insulating layer 190. The fourth insulating layer 190 and the fifth insulating layer 210 are provided with a fourth opening OP4 and a fifth opening OP5. The third oxide semiconductor layer 170-2 is exposed at the fourth opening OP4 and the fifth opening OP5. The source electrode layer 220-1 is provided inside the fourth opening OP4 and on the fifth insulating layer 210. The drain electrode layer 220-2 is provided inside the fifth opening OP5 and on the fifth insulating layer 210. The sixth insulating layer 230 covers the source electrode layer 220-1 and the drain electrode layer 220-2 and is provided on the fifth insulating layer 210.

[0071] The source electrode layer 220-1 and the drain electrode layer 220-2 are in contact with the third oxide semiconductor layer 170-2 via the fourth opening OP4 and the fifth opening OP5, respectively. In other words, the source electrode layer 220-1 and the drain electrode layer 220-2 are electrically connected to the third oxide semiconductor layer 170-2. A fourth insulating layer 190 is provided between the third oxide semiconductor layer 170-2 and the gate electrode layer 200-2. In the third transistor Tr3, a portion of the fourth insulating layer 190 functions as a gate insulating layer.

[0072] The gate electrode layer 200-2 is located on the third oxide semiconductor layer 170-2. The third transistor Tr3 is a so-called top-gate type transistor. Furthermore, the third transistor Tr3 is superimposed on the first transistor Tr1. In other words, the third transistor Tr3 is fabricated on top of the first transistor Tr1. Therefore, by including the third transistor Tr3 in the semiconductor device 20, the number of transistors can be increased, and the transistors of the semiconductor device 20 can be highly integrated. It is preferable that the channel region of the third transistor Tr3 (the region in the third oxide semiconductor layer 170-2 that is superimposed on the gate electrode layer 200-2) is superimposed on the light-shielding layer 110. With this configuration, it is possible to prevent ambient light from being incident on the channel region of the third oxide semiconductor layer 170-2.

[0073] [1-2. Components of the semiconductor device 20] The second transistor Tr2 and the third transistor Tr3 share some common components. Furthermore, some of these components are formed by patterning a single deposited film and are provided as the same layer. Below, we will focus on the second transistor Tr2 and the third transistor Tr3 and describe the details of each component of the semiconductor device 20.

[0074] [1-2-1. Second oxide semiconductor layer 170-1 and third oxide semiconductor layer 170-2] The second oxide semiconductor layer 170-1 and the third oxide semiconductor layer 170-2 of the second transistor Tr2 are provided as the same layer. That is, the second oxide semiconductor layer 170-1 and the third oxide semiconductor layer 170-2 are formed simultaneously by patterning a single oxide semiconductor film.

[0075] [1-2-2. Guard electrode layer 200-1 and guard electrode layer 200-2] The gate electrode layer 200-1 of the second transistor Tr2 and the gate electrode layer 200-2 of the third transistor Tr3 are provided as the same layer. That is, the gate electrode layer 200-1 and the gate electrode layer 200-2 are formed simultaneously by patterning a single conductive film. The same metallic material as the light-shielding layer 110 can be used for the gate electrode layer 200-1 and the gate electrode layer 200-2.

[0076] [1-2-3. Source electrode layer 220-1 and drain electrode layer 220-2] The source electrode layer 220-1 and drain electrode layer 220-2 of the third transistor Tr3 are provided as the same layer. That is, the source electrode layer 220-1 and the drain electrode layer 220-2 are formed simultaneously by patterning a single conductive film. The same metallic material as the light-shielding layer 110 can be used for the source electrode layer 220-1 and the drain electrode layer 220-2.

[0077] [1-2-4. Sixth insulating layer 230] The sixth insulating layer 230 is a protective layer. The sixth insulating layer 230 can be made of the same insulating nitride or insulating oxide as the first insulating layer 120. The sixth insulating layer 230 may have a single-layer structure or a laminated structure. For example, the sixth insulating layer 230 may have a laminated structure in which an insulating oxide layer is provided on top of an insulating nitride layer.

[0078] [2. Method for manufacturing the semiconductor device 20] Figure 18 is a flowchart illustrating a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention. Figures 19 to 27 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention.

[0079] The method for manufacturing the semiconductor device 20 includes steps S1010 to S1080 of the method for manufacturing the semiconductor device 10, so its explanation is omitted here. As shown in Figure 18, the method for manufacturing the semiconductor device 20 includes steps S1210 to S1300 instead of steps S1090 to S1130. Steps S1210 to S1300 will be explained in order below, but the order of steps in the method for manufacturing the semiconductor device 20 may be changed. Furthermore, the method for manufacturing the semiconductor device 20 may include further steps. For the sake of explanation below, it will be assumed that the third transistor Tr3 is superimposed on the first transistor Tr1 and fabricated within the first transistor formation region TFR1.

[0080] In step S1210, a second oxide semiconductor film 175 is deposited on the third insulating layer 160 so as to cover the bottom surface (i.e., the exposed source electrode layer 150-2) and sides of the third opening OP3 (see Figure 19). The second oxide semiconductor film 175 is deposited using a sputtering method.

[0081] In step S1220, the second oxide semiconductor film 175 is patterned, forming a second oxide semiconductor layer 170-1 with a predetermined pattern shape within the second transistor formation region TFR2, and forming a third oxide semiconductor layer 170-2 with a predetermined pattern shape within the first transistor formation region TFR1 (see Figure 20). That is, the second oxide semiconductor layer 170-1 and the third oxide semiconductor layer 170-2 are the same layer formed from the second oxide semiconductor film 175. The patterning of the second oxide semiconductor film 175 is performed using photolithography.

[0082] Furthermore, the second oxide semiconductor layer 170-1 and the third oxide semiconductor layer 170-2, which have a predetermined pattern shape, may be subjected to heat treatment (so-called OS annealing).

[0083] In step S1230, a conductive film 185 is deposited on the third insulating layer 160 so as to cover the second oxide semiconductor layer 170-1 and the third oxide semiconductor layer 170-2 (see Figure 21). The conductive film 185 is deposited using the sputtering method.

[0084] In step S1240, the conductive film 185 is patterned, and a source electrode layer 180-1 and a drain electrode layer 180-2 having a predetermined pattern shape are formed in the first transistor formation region TFR1, and a drain electrode layer 180-3 having a predetermined pattern shape is formed in the second transistor formation region TFR2 (see Figure 22). That is, the source electrode layer 180-1 and the drain electrode layer 180-2 in the first transistor formation region TFR1, and the drain electrode layer 180-3 in the second transistor formation region TFR2 are the same layer formed from the conductive film 185. The patterning of the conductive film 185 is performed using photolithography.

[0085] In step S1250, a fourth insulating layer 190 is formed on the third insulating layer 160 so as to cover the source electrode layer 180-1, the drain electrode layer 180-2, and the third oxide semiconductor layer 170-2 in the first transistor formation region TFR1, as well as the drain electrode layer 180-3 and the third oxide semiconductor layer 170-2 in the second transistor formation region TFR2. Subsequently, a conductive film 205 is deposited on the fourth insulating layer 190 (see Figure 23). The fourth insulating layer 190 is deposited using the CVD method. The conductive film 205 is deposited using the sputtering method.

[0086] In step S1260, the conductive film 205 is patterned, and a gate electrode layer 200-1 having a predetermined pattern shape is formed in the second transistor formation region TFR2, and a gate electrode layer 200-2 having a predetermined pattern shape is formed in the first transistor formation region TFR1 (see Figure 24).

[0087] In step S1270, a fifth insulating layer 210 is formed on the fourth insulating layer 190 so as to cover the gate electrode layer 200-1 and the gate electrode layer 200-2, and then a fourth opening OP4 and a fifth opening OP5 are formed so as to expose the third oxide semiconductor layer 170-2 (see Figure 25).

[0088] In step S1280, a conductive film 225 is deposited on the fifth insulating layer 210 (see Figure 26). The conductive film 225 is deposited using a sputtering method.

[0089] In step S1290, the conductive film 225 is patterned, and a source electrode layer 220-1 and a drain electrode layer 220-2 having a predetermined pattern shape are formed within the first transistor formation region TFR1 (see Figure 27). That is, the source electrode layer 220-1 and the drain electrode layer 220-2 are the same layer formed from the conductive film 225. The patterning of the conductive film 225 is performed using photolithography.

[0090] In step S1300, a sixth insulating layer 230 is formed on the fifth insulating layer 210 so as to cover the source electrode layer 220-1 and the drain electrode layer 220-2 having a predetermined pattern shape. This manufactures the semiconductor device 20 shown in Figure 17.

[0091] The semiconductor device 20 according to this embodiment includes a first transistor Tr1 including a first oxide semiconductor layer 130, a second transistor Tr2 including a second oxide semiconductor layer 170-1 formed above the first oxide semiconductor layer 130, and a third transistor Tr3 including a third oxide semiconductor layer 170-2. The second transistor Tr2 and the third transistor Tr3 share some components, and the third transistor Tr3 is fabricated by superimposing it on the first transistor Tr1. Even when the second transistor Tr2 and the third transistor Tr3 are fabricated after the formation of the first oxide semiconductor layer 130 of the first transistor Tr1, the first transistor Tr1 is hardly affected by the fabrication process of the second transistor Tr2 and the third transistor Tr3, and fluctuations in the characteristics of the first transistor Tr1 can be suppressed. Furthermore, by making the second transistor Tr2 a vertical transistor, the area occupied by the second transistor Tr2 can be reduced. Therefore, the semiconductor device 20 can achieve high integration of transistors.

[0092] <Third Embodiment> Referring to Figures 28 to 31, a semiconductor device 30 according to one embodiment of the present invention will be described. Note that if the configuration of the semiconductor device 30 is the same as that of the semiconductor device 10 or the semiconductor device 20, the description of the configuration of the semiconductor device 30 may be omitted.

[0093] [1. Configuration of semiconductor device 30] Figure 28 is a schematic cross-sectional view showing the configuration of a semiconductor device 30 according to one embodiment of the present invention. As shown in Figure 28, the semiconductor device 30 includes three transistors (a first transistor Tr1, a second transistor Tr2, and a fourth transistor Tr4) provided on a substrate 100. The structure of the fourth transistor Tr4 is different from the structure of the first transistors Tr1 to the third transistors Tr3.

[0094] Here, the configuration of the first transistor Tr1 according to this embodiment is the same as the configuration of the first transistor Tr1 described in the first embodiment, so its description is omitted. Similarly, the configuration of the second transistor Tr2 according to this embodiment is the same as the configuration of the second transistor Tr2 described in the second embodiment, so its description is omitted.

[0095] [1-1. Configuration of the fourth transistor Tr4] The fourth transistor Tr4 includes a second insulating layer 140, a gate electrode layer 150-1, a third insulating layer 160, a third oxide semiconductor layer 170-2, a source electrode layer 180-4, a drain electrode layer 180-5, a fourth insulating layer 190, and a fifth insulating layer 210. The third insulating layer 160 covers the gate electrode layer 150-1 and is provided on top of the second insulating layer 140. The third oxide semiconductor layer 170-2 is provided on top of the third insulating layer 160. The source electrode layer 180-4 and the drain electrode layer 180-5 each cover a portion of the third oxide semiconductor layer 170-2 and are provided on top of the third insulating layer 160. The fourth insulating layer 190 covers the source electrode layer 180-1, the drain electrode layer 180-2, the drain electrode layer 180-3, the third oxide semiconductor layer 170-2, the source electrode layer 180-4, and the drain electrode layer 180-5, and is provided on top of the third insulating layer 160.

[0096] The source electrode layer 180-4 and the drain electrode layer 180-5 are in contact with the third oxide semiconductor layer 170-2. That is, the source electrode layer 180-4 and the drain electrode layer 180-5 are electrically connected to the third oxide semiconductor layer 170-2. A third insulating layer 160 is provided between the gate electrode layer 150-1 and the third oxide semiconductor layer 170-2. In the fourth transistor Tr4, a portion of the third insulating layer 160 functions as a gate insulating layer.

[0097] The gate electrode layer 150-1 is located beneath the third oxide semiconductor layer 170-2. The fourth transistor Tr4 is a so-called bottom-gate type transistor, and the gate electrode layer 150-1 is provided in common with both the first transistor Tr1 and the fourth transistor Tr4. Therefore, in the semiconductor device 30, the first transistor Tr1 and the fourth transistor Tr4 operate in conjunction. Furthermore, the fourth transistor Tr4 is superimposed on the first transistor Tr1. In other words, the fourth transistor Tr4 is fabricated on top of the first transistor Tr1. Therefore, by including the fourth transistor Tr4 in the semiconductor device 30, the number of transistors can be increased, and the transistors in the semiconductor device 30 can be highly integrated.

[0098] [1-2. Components of the semiconductor device 30] The second transistor Tr2 and the fourth transistor Tr4 share some common components. Furthermore, some of these components are formed by patterning a single deposited film and are provided as the same layer. Below, we will focus on the second transistor Tr2 and the fourth transistor Tr4 and describe the details of each component of the semiconductor device 30.

[0099] [1-2-1. Source electrode layer 180-1, drain electrode layer 180-2, drain electrode layer 180-3, source electrode layer 180-4, and drain electrode layer 180-5] The source electrode layer 180-1 and drain electrode layer 180-2 of the first transistor Tr1, the drain electrode layer 180-3 of the second transistor Tr2, and the source electrode layer 180-4 and drain electrode layer 180-5 of the third transistor Tr3 are provided as the same layer. That is, the source electrode layer 180-1, drain electrode layer 180-2, drain electrode layer 180-3, source electrode layer 180-4, and drain electrode layer 180-5 are formed simultaneously by patterning a single conductive film. The same metallic material as the light-shielding layer 110 can be used for the source electrode layer 180-1, drain electrode layer 180-2, drain electrode layer 180-3, source electrode layer 180-4, and drain electrode layer 180-5.

[0100] [1-2-2. Fourth insulating layer 190] In the fourth transistor Tr4, the fourth insulating layer 190 is a protective layer. However, the fourth insulating layer 190 is in contact with the third oxide semiconductor layer 170-2. Therefore, an insulating oxide can be used as the fourth insulating layer 190. Furthermore, in the second transistor Tr2, a portion of the fourth insulating layer 190 functions as a gate insulating layer, so it is preferable that the fourth insulating layer 190 has few defects and a composition close to the stoichiometric ratio. Specifically, it is preferable that no defects are observed in the fourth insulating layer 190 when evaluated by the ESR method.

[0101] [2. Method for manufacturing semiconductor device 30] Figure 29 is a flowchart illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention. Figures 30 and 31 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention.

[0102] The method for manufacturing the semiconductor device 30 includes steps S1010 to S1080 and S1210 to S1230 of the method for manufacturing the semiconductor device 20, so its explanation is omitted here. As shown in Figure 29, the method for manufacturing the semiconductor device 30 includes steps S1510 to S1530 instead of steps S1240 to S1300. Steps S1510 to S1530 will be explained in order below, but the order of steps in the method for manufacturing the semiconductor device 30 may be changed. Furthermore, the method for manufacturing the semiconductor device 30 may include further steps. For the sake of explanation below, it will be assumed that the fourth transistor Tr4 is superimposed on the first transistor Tr1 and fabricated within the first transistor formation region TFR1.

[0103] In step S1510, the conductive film 185 is patterned, and a source electrode layer 180-1, a drain electrode layer 180-2, a source electrode layer 180-4, and a drain electrode layer 180-5 having a predetermined pattern shape are formed in the first transistor formation region TFR1, and a drain electrode layer 180-3 having a predetermined pattern shape is formed in the second transistor formation region TFR2 (see Figure 30). That is, the source electrode layer 180-1, the drain electrode layer 180-2, the drain electrode layer 180-3, the source electrode layer 180-4, and the drain electrode layer 180-5 are the same layer formed from the conductive film 185. The patterning of the conductive film 185 is performed using photolithography.

[0104] In step S1520, a fourth insulating layer 190 is formed on the third insulating layer 160 so as to cover the source electrode layer 180-1, drain electrode layer 180-2, source electrode layer 180-4, drain electrode layer 180-5, and the third oxide semiconductor layer 170-2 in the first transistor formation region TFR1, as well as the drain electrode layer 180-3 and the second oxide semiconductor layer 170-1 in the second transistor formation region TFR2. Subsequently, a gate electrode layer 200 having a predetermined pattern shape is formed on the fourth insulating layer 190 within the second transistor formation region TFR2 (see Figure 31). The fourth insulating layer 190 is deposited using the CVD method. The gate electrode layer 200 is deposited using the sputtering method, and the patterning of the gate electrode layer 200 is performed using the photolithography method. The gate electrode layer 200 is patterned to have a pattern shape that overlaps with the second oxide semiconductor layer 170 via the fourth insulating layer 190 at the bottom and side surfaces of the third opening OP3.

[0105] In step S1530, a fifth insulating layer 210 is formed on the fourth insulating layer 190 so as to cover the gate electrode layer 200 having a predetermined pattern shape. This manufactures the semiconductor device 30 shown in Figure 28.

[0106] The semiconductor device 30 according to this embodiment includes a first transistor Tr1 including a first oxide semiconductor layer 130, a second transistor Tr2 including a second oxide semiconductor layer 170-1 formed above the first oxide semiconductor layer 130, and a fourth transistor Tr4 including a third oxide semiconductor layer 170-2. The second transistor Tr2 and the fourth transistor Tr4 share some components, and the fourth transistor Tr4 is fabricated by superimposing it on the first transistor Tr1. Even when the second transistor Tr2 and the fourth transistor Tr4 are fabricated after the formation of the first oxide semiconductor layer 130 of the first transistor Tr1, the first transistor Tr1 is hardly affected by the fabrication process of the second transistor Tr2 and the fourth transistor Tr4, and fluctuations in the characteristics of the first transistor Tr1 can be suppressed. Furthermore, by making the second transistor Tr2 a vertical transistor, the area occupied by the second transistor Tr2 can be reduced. Therefore, the semiconductor device 30 can achieve high integration of transistors.

[0107] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0108] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0109] 10, 20, 30: Semiconductor device, 100: Substrate, 110: Light-shielding layer, 120: First insulating layer, 130: First oxide semiconductor layer, 135: First oxide semiconductor film, 140: Second insulating layer, 150-1: Gate electrode layer, 150-2: Source electrode layer, 155: Conductive film, 160: Third insulating layer, 170, 170-1: Second oxide semiconductor layer, 170-2: Third oxide semiconductor layer, 175: Second oxide semiconductor film, 180-1: Source electrode layer, 180-2: Drain electrode layer, 180-3: Drain electrode layer, 180-4: Source electrode layer, 180-5: Drain electrode layer, 185: Conductive film, 190: Fourth insulating layer, 200: Gate electrode layer, 200-1: Gate electrode layer, 200-2: Gate electrode layer, 205: Conductive film, 210: Fifth insulating layer, 220-1: Source electrode layer, 220-2: Drain electrode layer, 225: Conductive film, 230: Sixth insulating layer, OP1: First opening, OP2: Second opening, OP3: Third opening, OP4: Fourth opening, OP5: Fifth opening, Tr1: First transistor, Tr2: Second transistor, Tr3: Third transistor, Tr4: Fourth transistor, SR: Source region, DR: Drain region, CR: Channel region, TFR1: First transistor formation region, TFR2: Second transistor formation region

Claims

1. A first transistor comprising a first oxide semiconductor layer, A second transistor comprising a second oxide semiconductor layer located above the first oxide semiconductor layer, The first transistor described above is A first gate electrode layer on the first oxide semiconductor layer, The device further includes an insulating layer on the first gate electrode layer, The second transistor described above is Source electrode layer, The present invention further includes a drain electrode layer superimposed on the source electrode layer with the second oxide semiconductor layer in between, One of the source electrode layer and the drain electrode layer of the second transistor is provided as the same layer as the first gate electrode layer of the first transistor. The source electrode layer and the drain electrode layer of the second transistor are provided on the insulating layer, The insulating layer includes an opening that exposes one of the source electrode layer and the drain electrode layer of the second transistor. The second oxide semiconductor layer is provided within the opening, and the semiconductor device is provided within the opening.

2. The semiconductor device according to claim 1, wherein the second transistor further includes a second gate electrode superimposed on the other of the source electrode layer and the drain electrode layer with the opening.

3. The semiconductor device according to claim 1, wherein the channel length of the second transistor is smaller than the channel length of the first transistor.

4. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer comprises the same oxide semiconductor as the first oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer comprises an oxide semiconductor different from that of the first oxide semiconductor layer.

6. The semiconductor device according to claim 5, wherein the second oxide semiconductor layer has an amorphous structure.

7. Furthermore, the device includes a third transistor comprising a third oxide semiconductor layer located above the first oxide semiconductor layer. The semiconductor device according to claim 1, wherein the third oxide semiconductor layer is provided as the same layer as the second oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein the third transistor further comprises a third gate electrode layer on the third oxide semiconductor layer.

9. The semiconductor device according to claim 7, wherein the third transistor includes the first gate electrode layer.

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