Manufacturing method for semiconductor devices

Abstract

In a semiconductor device having a lower electrode on the underside of a semiconductor substrate, the contact between the lower electrode and the semiconductor substrate is improved. [Solution] The method for manufacturing a semiconductor device includes the steps of forming a diffusion source on the lower surface of a semiconductor substrate for diffusing conductive impurities into the semiconductor substrate, and irradiating the lower surface of the semiconductor substrate with laser light via the diffusion source.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device. For example, this disclosure relates to a method for manufacturing a semiconductor device including an insulated gate bipolar transistor (IGBT) or a diode. [Background technology]

[0002] Japanese Patent Publication No. 2023-173191 (Patent Document 1) describes a technique for reducing the leakage current of semiconductor devices including IGBTs or diodes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-173191 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] For example, consider a semiconductor device having a lower electrode on the underside of a semiconductor substrate. In such a semiconductor device, it is important to ensure low-resistance contact between the lower electrode and the semiconductor substrate in order to improve the performance of the device. In other words, in the aforementioned semiconductor device, it is desirable to improve the contact between the lower electrode and the semiconductor substrate.

[0005] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0006] In one embodiment, the method for manufacturing a semiconductor device includes the steps of forming a diffusion source on the lower surface of a semiconductor substrate for diffusing conductive impurities into the semiconductor substrate, and irradiating the lower surface of the semiconductor substrate with laser light through the diffusion source. [Effects of the Invention]

[0007] According to one embodiment, in a semiconductor device having a lower electrode on the lower surface of a semiconductor substrate, the contact between the lower electrode and the semiconductor substrate can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing the configuration of a semiconductor device including an IGBT. [Figure 2] This is a flowchart explaining the basic concept. [Figure 3] This is a flowchart illustrating Embodiment 1. [Figure 4] This figure shows the manufacturing process of a semiconductor device in Embodiment 1. [Figure 5] This figure shows the manufacturing process of semiconductor devices, following Figure 4. [Figure 6] This figure shows the manufacturing process of semiconductor devices, following Figure 5. [Figure 7] This figure shows the manufacturing process of semiconductor devices, following Figure 6. [Figure 8] This figure shows the manufacturing process of semiconductor devices, following Figure 7. [Figure 9] This diagram schematically shows the results of microscopic observation of the underside of a semiconductor substrate when laser annealing is performed without forming a film. [Figure 10] This diagram schematically shows the results of observing the underside of a semiconductor substrate under a microscope after removing the film when laser annealing is performed with the film already formed on it. [Figure 11] This is a flowchart illustrating Embodiment 2. [Figure 12] This is a flowchart illustrating Embodiment 3. [Figure 13] This figure shows the manufacturing process of a semiconductor device in Embodiment 3. [Figure 14] This figure shows the manufacturing process of semiconductor devices, following Figure 13. [Figure 15] This is a circuit diagram of the arm. [Figure 16] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 5. [Figure 17] It is a plan view showing the configuration of the semiconductor device in Embodiment 6. [Figure 18] It is a diagram showing a study example. [Figure 19] It is a cross-sectional view of the semiconductor device along the line A-A of FIG. 17. [Figure 20] It is a cross-sectional view showing the configuration of the semiconductor device in Embodiment 7.

Embodiments for Carrying Out the Invention

[0009] In all the drawings for explaining the embodiments, the same members are basically denoted by the same reference numerals, and the repeated description thereof is omitted. Note that, in order to make the drawings easy to understand, hatching may be added even to a plan view.

[0010] <Configuration of a Semiconductor Device Including an IGBT> FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device 100 including an IGBT.

[0011] In FIG. 1, the semiconductor device 100 has a semiconductor substrate SUB, a buffer layer BL, a drift layer DFL, a p-type well PW1, a p-type well PW2, a body contact region BC1, a body contact region BC2, a gate insulating film GOX, a gate electrode GE, an interlayer insulating film IL, a collector electrode CE, an emitter region ER1, an emitter region ER2, and an emitter electrode EE.

[0012] The semiconductor substrate SUB is a p-type silicon substrate. That is, for example, boron, a p-type impurity, is introduced into the semiconductor substrate SUB. An epitaxial layer EPI is formed on the upper surface of the semiconductor substrate SUB. The epitaxial layer EPI includes a buffer layer BL and a drift layer DFL. Since the epitaxial layer EPI is an n-type semiconductor layer, a pn junction is formed between the semiconductor substrate SUB and the epitaxial layer EPI. A collector electrode CE is formed on the lower surface of the semiconductor substrate SUB. The collector electrode CE is the lower electrode.

[0013] Within the epitaxial layer EPI, p-type wells PW1 and PW2 are formed. Within p-type well PW1, an emitter region ER1 and a body contact region BC1 are formed. The emitter region ER1 is an n-type semiconductor region, while the body contact region BC1 is a p-type semiconductor region. The emitter region ER1 and the body contact region BC1 are in contact with each other. Within p-type well PW2, an emitter region ER2 and a body contact region BC2 are formed. The emitter region ER2 is an n-type semiconductor region, while the body contact region BC2 is a p-type semiconductor region. The emitter region ER2 and the body contact region BC2 are in contact with each other.

[0014] A gate insulating film GOX is formed on the epitaxial layer EPI. A gate electrode GE is formed on the gate insulating film GOX. An interlayer insulating film IL is formed on the epitaxial layer EPI so as to cover the gate electrode GE. An emitter electrode EE is formed on the interlayer insulating film IL.

[0015] The emitter electrode EE is electrically connected to the emitter region ER1 and the body contact region BC1. Therefore, the emitter region ER1 and the body contact region BC1 are electrically connected via the emitter electrode EE.

[0016] Furthermore, the emitter electrode EE is electrically connected to the emitter region ER2 and the body contact region BC2. Therefore, the emitter region ER2 and the body contact region BC2 are electrically connected via the emitter electrode EE.

[0017] When 0V is applied to the emitter electrode EE and a positive voltage is applied to the collector electrode CE, the IGBT turns on when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode GE. Specifically, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, a channel is formed on the surface of the p-type well PW1, and the emitter region ER1 and the drift layer DFL are electrically connected to each other. Similarly, a channel is formed on the surface of the p-type well PW2, and the emitter region ER2 and the drift layer DFL are electrically connected to each other.

[0018] Since the emitter electrode EE, emitter region ER1, emitter region ER2, and drift layer DFL are electrically connected to each other, when 0V is applied to the emitter electrode EE, 0V is also applied to the drift layer DFL. On the other hand, since the semiconductor substrate SUB is electrically connected to the collector electrode CE, when a positive voltage is applied to the collector electrode CE, a positive voltage is also applied to the semiconductor substrate SUB. Therefore, a forward bias is applied to the pn junction formed by the semiconductor substrate SUB and the epitaxial layer EPI.

[0019] As a result, holes are injected from the collector electrode CE into the epitaxial layer EPI via the semiconductor substrate SUB. Then, electrons are injected from the emitter electrode EE into the epitaxial layer EPI via the emitter region ER1, emitter region ER2, channel, and drift layer DFL, as if attracted by the injected holes. This causes a conductivity modulation phenomenon, reducing the resistance within the epitaxial layer EPI. In other words, the on-resistance of the IGBT can be reduced by the conductivity modulation phenomenon.

[0020] Subsequently, applying a gate voltage lower than the threshold voltage to the gate electrode GE turns off the IGBT. More specifically, the IGBT turns off when the ejection of holes injected into the epitaxial layer EPI to the emitter electrode EE and the ejection of electrons injected into the epitaxial layer EPI to the collector electrode CE are complete. In other words, the IGBT turns off when the tail current, which flows due to the ejection of holes and electrons, stops flowing.

[0021] <Room for improvement> The technical concept of this disclosure aims to solve is to improve the contact between the lower electrode and the lower surface of the semiconductor substrate. Below, we will describe some areas for improvement as a specific example of this problem. In particular, the areas for improvement described here are specific problems that focus on semiconductor devices including IGBTs. For this reason, the technical concept of this disclosure aims to solve is not limited to the specific areas for improvement described here. The technical concept of this disclosure aims to solve is to improve the contact between the lower electrode and the lower surface of the semiconductor substrate in a semiconductor device having a lower electrode on the lower surface of a semiconductor substrate.

[0022] The following describes areas for improvement in semiconductor devices, including IGBTs.

[0023] To reduce the on-voltage of semiconductor devices including IGBTs, it is necessary to ensure sufficient contact between the underside of the semiconductor substrate (SUB) and the collector electrode (CE). For this purpose, for example, p-type impurities are introduced into the semiconductor substrate (SUB) from the underside using an ion implantation method. Subsequently, laser annealing is performed, irradiating the underside of the semiconductor substrate (SUB) with laser light. This activates the p-type impurities introduced into the semiconductor substrate (SUB). Afterward, a collector electrode (CE) consisting of a conductive film is formed on the underside of the semiconductor substrate (SUB). This creates ohmic contact between the underside of the semiconductor substrate (SUB) and the collector electrode (CE). As a result, sufficient contact between the underside of the semiconductor substrate (SUB) and the collector electrode (CE) can be ensured.

[0024] However, in the process described above, the impurity concentration of p-type impurities introduced near the bottom surface of the semiconductor substrate SUB is lower than the peak value. In other words, the peak value of the impurity concentration of p-type impurities introduced into the semiconductor substrate SUB is far from the bottom surface of the semiconductor substrate SUB. Therefore, the inventors have newly discovered that improvement is necessary from the standpoint of ensuring sufficient contact between the bottom surface of the semiconductor substrate SUB and the collector electrode CE. In particular, in IGBTs in which the impurity concentration of p-type impurities introduced from the bottom surface of the semiconductor substrate SUB is low, the decrease in contact between the bottom surface of the semiconductor substrate SUB and the collector electrode CE becomes apparent.

[0025] For example, in IGBTs used for high-speed switching, the number of switching cycles increases. As a result, switching losses increase in IGBTs used for high-speed switching applications.

[0026] Therefore, reducing switching losses is crucial for IGBTs used in high-speed switching applications. Reducing the tail current that flows during turn-off is an effective way to reduce switching losses. This is because reducing the tail current means shortening the time during which the tail current flows. In other words, shortening the time the tail current flows shortens the turn-off period during which switching losses occur. Therefore, reducing the tail current is desirable for IGBTs used in high-speed switching applications in order to reduce switching losses.

[0027] The tail current is caused by the discharge of holes and electrons injected into the epitaxial layer (EPI). Therefore, to reduce the tail current, it is effective to reduce the number of holes injected into the epitaxial layer (EPI) during the ON phase. Reducing the number of holes injected into the epitaxial layer (EPI) can be achieved by reducing the impurity concentration of p-type impurities introduced into the semiconductor substrate (SUB), which is the source of the holes. Therefore, in IGBTs for high-speed switching applications, the impurity concentration of p-type impurities introduced from the underside of the semiconductor substrate (SUB) is reduced. However, in this case, as mentioned above, a decrease in contact between the underside of the semiconductor substrate (SUB) and the collector electrode (CE) becomes apparent. For these reasons, it is desirable to improve the contact between the underside of the semiconductor substrate (SUB) and the collector electrode (CE).

[0028] <Basic philosophy> Figure 2 is a flowchart that explains the basic concept.

[0029] In Figure 2, the basic concept includes the steps of forming a diffusion source on the lower surface of the semiconductor substrate SUB (S10) for diffusing conductive impurities into the semiconductor substrate SUB, and irradiating the lower surface of the semiconductor substrate SUB with laser light via the diffusion source (S20). The basic concept also includes the steps of removing the diffusion source (S30) and forming a lower electrode on the lower surface of the semiconductor substrate SUB (S40). However, the step of removing the diffusion source is optional. That is, the step of removing the diffusion source is performed as needed. The step of irradiating with laser light is performed at a temperature that melts the semiconductor material near the lower surface of the semiconductor substrate SUB by laser annealing.

[0030] As a result, conductive impurities contained in the diffusion source are introduced from the diffusion source into the vicinity of the underside of the semiconductor substrate (SUB) and diffuse into the molten semiconductor material. In other words, conductive impurities are replenished from the diffusion source in the vicinity of the underside of the semiconductor substrate (SUB) where the impurity concentration of conductive impurities is lower than the peak value. As a result, according to the basic concept, the decrease in the impurity concentration of conductive impurities in the vicinity of the underside of the semiconductor substrate (SUB) can be suppressed. Furthermore, the conductive impurities diffuse almost uniformly within the molten semiconductor material. By replenishing the vicinity of the underside of the semiconductor substrate (SUB) with conductive impurities from the diffusion source and by diffusing the replenished conductive impurities almost uniformly into the molten semiconductor material through laser annealing, the decrease in the impurity concentration of conductive impurities in the vicinity of the underside of the semiconductor substrate (SUB) is suppressed. Therefore, by adopting the basic concept, the contact between the underside of the semiconductor substrate and the lower electrode can be improved.

[0031] The following describes embodiments that embody the basic concept.

[0032] <Embodiment 1> Embodiment 1 describes an example of applying the basic concept to a semiconductor device including an IGBT.

[0033] In Embodiment 1, the "conductive impurity" in the basic concept is "boron." "Boron" functions as a p-type impurity (acceptor). The "diffusion source" in the basic concept is a "boron-containing film." The "lower electrode" in the basic concept is a "collector electrode."

[0034] In Embodiment 1, the basic configuration of the semiconductor device including the IGBT is the same as that of the semiconductor device 100 shown in Figure 1. The semiconductor substrate SUB is a p-type semiconductor substrate. The semiconductor substrate SUB has an upper surface. An n-type epitaxial layer EPI is formed on the upper surface of the semiconductor substrate SUB. An n-type emitter region (emitter region ER1, emitter region ER2) is formed within the epitaxial layer EPI. A gate insulating film GOX is formed so as to be in partial contact with the emitter region. A gate electrode GE is formed on the gate insulating film GOX. The semiconductor substrate SUB is the collector region.

[0035] The IGBT assumed in Embodiment 1 is a planar type IGBT as shown in Figure 1. However, the technical concept of this disclosure is not limited to semiconductor devices including planar type IGBTs. The technical concept of this disclosure can also be applied to semiconductor devices including trench gate type IGBTs.

[0036] Figure 3 is a flowchart illustrating Embodiment 1.

[0037] First, as shown in Figure 4, the semiconductor substrate SUB has an upper surface FS and a lower surface BS. The semiconductor substrate SUB is made of a semiconductor material, for example, silicon (Si). Boron 10 (first conductive impurity) is introduced into the semiconductor substrate SUB from the lower surface BS using an ion implantation method (S101). In this state, the impurity concentration of boron introduced near the lower surface BS of the semiconductor substrate SUB is lower than the peak value. In other words, the peak value of the boron impurity concentration introduced into the semiconductor substrate SUB is far from the lower surface BS of the semiconductor substrate SUB. Therefore, if a collector electrode is formed on the lower surface BS of the semiconductor substrate SUB immediately after this process, there is a risk that the ohmic contact between the lower surface BS and the collector electrode will be insufficient. In particular, when manufacturing IGBTs with a low boron impurity concentration, the contact between the lower surface BS and the collector electrode is likely to decrease.

[0038] Therefore, in Embodiment 1, the following steps are performed.

[0039] First, a semiconductor substrate SUB having a bottom surface BS is prepared. Next, as shown in Figure 5, a film DF is formed on the bottom surface BS of the semiconductor substrate SUB (S102). The film DF contains boron (second conductive impurity). The film DF is, for example, a BPSG (Boro-Phospho Silicate Glass) film or a B2O3 film. The thickness of the film DF is approximately 1 nm or more and 100 nm or less.

[0040] Next, as shown in Figure 6, laser light is irradiated onto the bottom surface BS through the film DF (S103). The laser light irradiation step is performed at a temperature that melts the silicon near the bottom surface BS of the semiconductor substrate SUB by laser annealing. Specifically, in the laser light irradiation step, for example, the semiconductor material in the portion of the semiconductor substrate SUB that is more than 0 μm and less than or equal to 0.25 μm from the bottom surface BS in a direction perpendicular to the bottom surface BS (Z direction) is melted.

[0041] For example, the irradiation energy of the laser light is 1.8 J / cm². 2 This is the extent of the problem. In this case, the temperature of the silicon instantaneously exceeds 1400 degrees Celsius in the portion with a depth of 0.25 μm or less. As a result, the silicon melts. In addition, the boron contained in the film DF is introduced into the semiconductor substrate SUB. Therefore, by irradiating the underside of the semiconductor substrate SUB with laser light, boron is introduced into the semiconductor substrate SUB from the film DF (diffusion source). As a result, after the process of irradiating the underside of the semiconductor substrate SUB with laser light, the semiconductor substrate SUB contains boron introduced from the film DF.

[0042] Boron introduced from the film DF into the vicinity of the bottom surface BS of the semiconductor substrate SUB diffuses into the molten silicon. Within the molten silicon, the boron diffuses almost uniformly. This suppresses the decrease in the boron impurity concentration near the bottom surface BS of the semiconductor substrate SUB. Figure 6 schematically shows that the boron impurity concentration distribution 10A is almost uniform.

[0043] Next, as shown in Figure 7, the film DF is removed (S104). Then, as shown in Figure 8, a collector electrode CE is formed on the lower surface BS of the semiconductor substrate SUB (S105). The collector electrode CE is a conductive film. Conductive films include, for example, aluminum films (Al films), aluminum silicide films (AlSi films), and nickel silicide films (NiSi films). Conductive films can be formed, for example, by sputtering.

[0044] As described above, according to Embodiment 1, the decrease in boron impurity concentration near the lower surface BS of the semiconductor substrate SUB can be suppressed. Therefore, according to Embodiment 1, the contact between the lower surface BS of the semiconductor substrate SUB and the collector electrode CE can be improved. As a result, the on-voltage of the IGBT can be reduced. In other words, the on-resistance of the IGBT can be reduced.

[0045] The process described in Embodiment 1 includes a step of performing laser annealing to melt silicon while a boron-containing film DF is formed on the lower surface BS of the semiconductor substrate SUB. In this case, traces indicating that the process described in Embodiment 1 has been performed remain on the lower surface BS of the semiconductor substrate SUB. This point will be explained below.

[0046] Figure 9 schematically shows the results of microscopic observation of the underside BS of the semiconductor substrate SUB when laser annealing is performed without forming a film DF. As shown in Figure 9, no wrinkles are observed on the underside BS of the semiconductor substrate SUB.

[0047] In contrast, Figure 10 schematically shows the results of microscopic observation of the underside BS of the semiconductor substrate SUB after removing the film DF, following laser annealing, which melts the silicon with the film DF formed on it. As shown in Figure 10, a wrinkled pattern is observed on the underside BS of the semiconductor substrate SUB. This can be understood as follows: Laser annealing is performed to melt the silicon with the film DF formed on it. In this case, non-uniform stress is applied from the film DF during the solidification process of the molten silicon. As a result, a relatively random wrinkled pattern is formed on the underside BS of the semiconductor substrate SUB due to this non-uniform stress.

[0048] Therefore, when the process described in Embodiment 1 is performed, a wrinkle pattern is observed on the lower surface BS of the semiconductor substrate SUB. On the other hand, when laser annealing is performed without forming the film DF, no wrinkle pattern is observed. From this, it is possible to determine whether the process described in Embodiment 1 has been performed or not by observing the presence or absence of the wrinkle pattern.

[0049] <Embodiment 2> In Embodiment 1, for example, as shown in Figure 3, a step (S101) is performed in which boron is introduced into the semiconductor substrate SUB by ion implantation. In Embodiment 1, a step (S102) is then performed in which a film DF containing boron is formed on the lower surface BS of the semiconductor substrate SUB. In Embodiment 2, a step of forming a film DF containing boron on the lower surface BS of the semiconductor substrate SUB is performed before the step of introducing boron into the semiconductor substrate SUB by ion implantation.

[0050] Figure 11 is a flowchart illustrating Embodiment 2.

[0051] As shown in Figure 11, in Embodiment 2, first, a boron-containing film is formed on the lower surface BS of the semiconductor substrate SUB (S201). Then, a boron introduction step into the semiconductor substrate SUB by ion implantation is performed (S202). The subsequent steps are the same as in Embodiment 1.

[0052] In Embodiment 2, a boron-containing film DF is formed before the boron introduction step into the semiconductor substrate SUB by ion implantation. Therefore, the boron-containing film DF also functions as a "through-film" in the ion implantation step. In other words, in Embodiment 2, the boron-containing film DF is used not only as a boron diffusion source but also as a "through-film" in the ion implantation step. Therefore, according to Embodiment 2, the step of forming a "through-film" can be omitted. As a result, according to Embodiment 2, the manufacturing cost of semiconductor devices can be reduced.

[0053] <Embodiment 3> In Embodiment 3, the "conductive impurity" in the basic concept is "boron." The "boron" functions as a p-type impurity (acceptor). The "diffusion source" in the basic concept is "boron deposited on the underside of the semiconductor substrate." The "lower electrode" in the basic concept is the "collector electrode."

[0054] Figure 12 is a flowchart illustrating Embodiment 3.

[0055] First, as shown in Figure 4, the semiconductor substrate SUB has an upper surface FS and a lower surface BS. The semiconductor substrate SUB is made of a semiconductor material, for example, silicon (Si). Boron 10 is introduced into the semiconductor substrate SUB from the lower surface BS using an ion implantation method (S301). In this state, the impurity concentration of boron introduced near the lower surface BS of the semiconductor substrate SUB becomes lower than the peak value. As a result, if a collector electrode is formed on the lower surface BS immediately after this step, there is a risk that the ohmic contact between the lower surface BS and the collector electrode will be insufficient. In particular, when manufacturing IGBTs with a low boron impurity concentration, the contact between the lower surface BS and the collector electrode tends to decrease. Therefore, in Embodiment 3, the following steps are performed.

[0056] As shown in Figure 13, boron 20 is deposited onto the bottom surface BS of the semiconductor substrate SUB (S302). Specifically, in Embodiment 3, the semiconductor substrate SUB is transported with its bottom surface BS facing upwards in a cleanroom equipped with an air filter containing boron 20. As a result, boron 20 scattered from the air filter adheres to the bottom surface BS of the semiconductor substrate SUB.

[0057] To maintain clean air within the cleanroom, an air filter is installed in the air supply path to the cleanroom. The material of the air filter is glass fiber. However, from the viewpoint of reducing the cost and ease of manufacturing of the air filter, glass fiber material containing boron 20 may be used as the material for the air filter. Therefore, the air in a cleanroom equipped with an air filter containing boron 20 contains boron 20. In Embodiment 3, the boron 20 contained in the air within the cleanroom is used as a diffusion source.

[0058] Next, as shown in Figure 14, the bottom surface BS to which boron 20 is attached is irradiated with laser light (S303). The laser irradiation step is performed at a temperature that melts the silicon near the bottom surface BS of the semiconductor substrate SUB by laser annealing. Specifically, in the laser irradiation step, for example, the semiconductor material in the portion of the semiconductor substrate SUB that is more than 0 μm and less than or equal to 0.25 μm from the bottom surface BS in a direction perpendicular to the bottom surface BS (Z direction) is melted.

[0059] For example, the irradiation energy of the laser light is 1.8 J / cm². 2 This is the extent of the problem. In this case, the temperature of the silicon instantaneously exceeds 1400 degrees Celsius in the portion with a depth of 0.25 μm or less. As a result, the silicon melts. In addition, the boron 20 adhering to the lower surface BS is introduced into the semiconductor substrate SUB.

[0060] Boron 20 introduced near the bottom surface BS of the semiconductor substrate SUB diffuses into the molten silicon. Within the molten silicon, the boron 20 diffuses almost uniformly. This suppresses the decrease in the impurity concentration of boron 10 near the bottom surface BS of the semiconductor substrate SUB. Figure 14 schematically shows that the combined impurity concentration distribution 10A of boron 10 and boron 20 is almost uniform.

[0061] Next, as shown in Figure 8, a collector electrode CE is formed on the lower surface BS of the semiconductor substrate SUB (S304). The collector electrode CE is a conductive film. Conductive films include, for example, aluminum films (Al films), aluminum silicide films (AlSi films), and nickel silicide films (NiSi films). Conductive films can be formed, for example, by sputtering.

[0062] As described above, according to Embodiment 3, the decrease in the impurity concentration of boron 10 near the lower surface BS of the semiconductor substrate SUB can be suppressed. Therefore, according to Embodiment 3, the contact between the lower surface BS of the semiconductor substrate SUB and the collector electrode CE can be improved. As a result, the on-voltage of the IGBT can be reduced. In other words, the on-resistance of the IGBT can be reduced.

[0063] <Embodiment 4> Embodiment 4 describes an example in which, instead of performing the ion implantation process to introduce boron into the semiconductor substrate from the bottom surface using an ion implantation method, a process of depositing boron onto the bottom surface is performed. In other words, Embodiment 4 is a form for minimizing the boron impurity concentration in the semiconductor substrate. In Embodiment 4, in Figure 12, S101 is not performed, and S102 to S104 are performed.

[0064] The inventors analyzed the boron impurity concentration in the examples and comparative examples using SIMS (Secondary Ion Mass Spectrometry). In the examples, laser annealing was performed after depositing boron on the underside of the semiconductor substrate. In the comparative examples, laser annealing was performed without depositing boron on the underside of the semiconductor substrate.

[0065] As a result of the analysis, in the comparative example, in the range from a depth of 0 μm (lower surface) to a depth of 0.3 μm, the impurity concentration of boron is 1×10 15 ( / cm 3 ) or more and 1×10 16 ( / cm 3 ) or less. On the other hand, in the example, in the range from a depth of 0 μm (lower surface) to a depth of 0.3 μm, the impurity concentration of boron is 2×10 16 ( / cm 3 ) or more and 1×10 17 ( / cm 3 ) or less.

[0066] From this result, the boron introduced into the semiconductor substrate according to Embodiment 4 has, for example, the minimum impurity concentration necessary to meet the design specifications of an IGBT for high-speed switching applications.

[0067] Also, in Embodiment 4, it is possible to suppress a decrease in the impurity concentration of boron in the vicinity of the lower surface BS of the semiconductor substrate SUB. From this, according to Embodiment 4, the contact property between the lower surface BS of the semiconductor substrate SUB and the collector electrode CE can be improved. As a result, the on-voltage of the IGBT can be reduced. In other words, the on-resistance of the IGBT can be reduced.

[0068] Therefore, in Embodiment 4, in an IGBT for high-speed switching applications, it is possible to improve the contact property between the lower surface of the semiconductor substrate and the collector electrode while satisfying the design specifications regarding the impurity concentration of boron.

[0069] <Embodiment 5> In Embodiment 5, an example of applying the basic idea to a semiconductor device including a diode will be described.

[0070] The "conductive impurity" of the basic idea is "phosphorus". "Phosphorus" functions as an n-type impurity (donor). The "diffusion source" of the basic idea is a "film containing phosphorus" or "phosphorus attached to the lower surface of the semiconductor substrate". The "lower electrode" of the basic idea is the "cathode electrode".

[0071] An inverter, a power conversion device, is used, for example, to drive a motor. An inverter has an upper arm and a lower arm. Specifically, the upper and lower arms are connected in series between the power supply wiring and the grounding wiring. The upper and lower arms have similar configurations. Therefore, in the following, the upper and lower arms will not be distinguished and will simply be referred to as "arms."

[0072] Figure 15 is a circuit diagram of the arm.

[0073] As shown in Figure 15, the arm has an IGBT50 and a diode FRD. The IGBT50 is a switching element. The IGBT50 has a gate terminal GT, a collector terminal CT, and an emitter terminal ET.

[0074] In the IGBT50, a positive potential is applied to the collector terminal CT, while the emitter terminal ET is grounded. A gate voltage equal to or greater than the threshold voltage is then applied to the gate terminal GT. This turns the IGBT50 on, and current flows from the collector terminal CT to the emitter terminal ET. In this state, if a gate voltage lower than the threshold voltage is applied to the gate terminal GT, the IGBT50 turns off, and the current is cut off. By repeatedly switching the IGBT50 on and off as described above, the motor is driven.

[0075] Motors contain inductance. Therefore, a back electromotive force (EMF) may be generated due to this inductance. When a back EMF is generated, a positive potential is applied to the emitter terminal ET as shown in Figure 15, while a lower potential is applied to the collector terminal CT than the potential applied to the emitter terminal ET. That is, the potential of the emitter terminal ET becomes higher than the potential of the collector terminal CT. In this case, a reverse current attempts to flow from the emitter terminal ET to the collector terminal CT. However, the IGBT50 does not have the function to allow a reverse current to flow from the emitter terminal ET to the collector terminal CT.

[0076] Therefore, in order to allow the reverse current caused by the inductance to flow, a diode FRD is provided, as shown in Figure 15, to be connected in antiparallel to the IGBT50. As a result, the reverse current flows from the emitter terminal ET to the collector terminal CT through the diode FRD.

[0077] A freewheel diode (FRD) is also called a "freewheel diode." An FRD is, for example, a Schottky barrier diode or a pn junction diode. The following describes the case where the FRD is a pn junction diode.

[0078] Figure 16 is a cross-sectional view showing the configuration of a semiconductor device 200 including a diode.

[0079] The semiconductor device 200 includes a semiconductor substrate SUB1, a buffer layer BL, a drift layer DFL, an anode region AR, an interlayer insulating film IF1, a cathode electrode KE, and an anode electrode AE.

[0080] The semiconductor substrate SUB1 is an n-type silicon substrate. That is, for example, phosphorus, an n-type impurity, is introduced into the semiconductor substrate SUB1. An epitaxial layer EPI is formed on the upper surface of the semiconductor substrate SUB1. The epitaxial layer EPI includes a buffer layer BL and a drift layer DFL. A cathode electrode KE is formed on the lower surface of the semiconductor substrate SUB1. The cathode electrode KE is the lower electrode.

[0081] Within the epitaxial layer EPI, the anode region AR of the diode is formed. The anode region AR is a p-type semiconductor region. For example, boron, a p-type impurity, is introduced into the anode region AR. The epitaxial layer EPI is an n-type semiconductor layer. On the other hand, the anode region AR is a p-type semiconductor region. Therefore, a pn junction is formed at the interface between the epitaxial layer EPI and the anode region AR. The semiconductor substrate SUB1 and the epitaxial layer EPI constitute the cathode region of the diode.

[0082] An interlayer insulating film IL1 is formed on an epitaxial layer EPI having an anode region AR. An opening OP is formed in the interlayer insulating film IL1. A portion of the upper surface of the anode region AR is exposed through the opening OP. An anode electrode AE ​​is formed on the interlayer insulating film IL1, including the area within the opening OP. Ohmic contact is formed between the anode electrode AE ​​and the anode region AR.

[0083] Reducing the on-voltage is also important in semiconductor devices 200 that include diodes. Therefore, it is necessary to ensure sufficient contact between the underside of the semiconductor substrate SUB1 and the cathode electrode KE. For example, the following steps are performed to ensure sufficient contact between the underside of the semiconductor substrate SUB1 and the cathode electrode KE.

[0084] Specifically, phosphorus is introduced into the semiconductor substrate SUB1 from its underside using an ion implantation method. Subsequently, laser annealing is performed by irradiating the underside with laser light. This activates the phosphorus introduced into the semiconductor substrate SUB1. After that, a cathode electrode KE made of a conductive film is formed on the underside of the semiconductor substrate SUB1. This creates an ohmic contact between the underside of the semiconductor substrate SUB1 and the cathode electrode KE. As a result, contact between the underside of the semiconductor substrate SUB1 and the cathode electrode KE can be ensured.

[0085] The phosphorus impurity concentration introduced near the bottom surface is lower than the peak value, meaning that the peak value of the phosphorus impurity concentration introduced near the bottom surface is away from the bottom surface. Therefore, there is a risk that the contact between the bottom surface and the cathode electrode KE will be reduced. Accordingly, the technical ideas described in each of the embodiments from 1 to 4 can also be applied to Embodiment 5. In other words, the technical ideas of Embodiments 1 to 4 concerning the semiconductor device 100 including an IGBT are also valid when applied to the semiconductor device 200 including a diode.

[0086] In this case, phosphorus is introduced into the semiconductor substrate SUB1 from the diffusion source by the process of irradiating the underside of the semiconductor substrate SUB1 with laser light. As a result, after the process of irradiating the underside of the semiconductor substrate SUB1 with laser light, the semiconductor substrate SUB1 contains phosphorus introduced from the diffusion source.

[0087] <Embodiment 6> Embodiment 6 is an example of applying the basic concept to a semiconductor device including a diode.

[0088] Figure 17 is a plan view showing the configuration of a semiconductor device 200 including a diode.

[0089] In Figure 17, the semiconductor device 200 has a semiconductor chip CHP. The planar shape of the semiconductor chip CHP is, for example, rectangular. The semiconductor chip CHP has a cell portion R1 having a diode and a peripheral portion R2 that surrounds the cell portion R1 in a planar manner.

[0090] The following describes Embodiment 6 in comparison with the example considered.

[0091] Figure 18 shows an example of the study. In this example, an n-type semiconductor region NR is formed on the underside of the semiconductor substrate SUB1. This n-type semiconductor region NR is formed using the technical concept of this disclosure. Specifically, after forming an n-type impurity diffusion source on the underside of the semiconductor substrate SUB1, laser light is irradiated into the underside of the semiconductor substrate SUB1 through the diffusion source. This melts the silicon near the underside of the semiconductor substrate SUB1, and diffuses the n-type impurity into the semiconductor substrate SUB1. As a result, an n-type semiconductor region NR with a nearly uniform impurity concentration is formed.

[0092] In the example examined, the n-type semiconductor region NR is formed not only in the cell portion R1 but also in the peripheral portion R2. In this case, the inventors have made the following novel discoveries.

[0093] In other words, in the example considered, an n-type semiconductor region NR is also formed in the peripheral region R2. Therefore, when a forward bias is applied to the diode, electrons are injected into the epitaxial layer EPI not only from the n-type semiconductor region NR of the cell region R1, but also from the n-type semiconductor region NR of the peripheral region R2. On the other hand, holes are injected into the epitaxial layer EPI from the anode region AR, which is a p-type semiconductor region. In this example, since electrons are also injected into the epitaxial layer EPI from the peripheral region R2, the amount of electrons injected increases. Therefore, the amount of holes injected into the epitaxial layer EPI from the anode region AR also increases.

[0094] In this state, when a reverse bias is applied to the diode, electrons and holes injected into the epitaxial layer EPI are discharged (recovery operation). In this example, the amount of electrons and holes injected is large. Focusing on the discharge of holes, the holes are discharged from the anode electrode AE ​​through the anode region AR. However, the anode electrode AE ​​is formed only in the cell portion R1. Therefore, the large amount of holes discharged from the epitaxial layer EPI concentrates at the edge of the anode electrode AE. As a result, there is a risk that the anode electrode AE ​​may be destroyed. Therefore, in Embodiment 6, the following configuration is adopted.

[0095] Figure 19 is a cross-sectional view of a semiconductor device along line AA in Figure 17, and shows Embodiment 6. In Figure 19, a feature of Embodiment 6 is that the n-type semiconductor region NR is formed only in the cell portion R1. In other words, unlike the study example, the n-type semiconductor region NR is not formed in the peripheral portion R2. In this case, when a forward bias is applied to the diode, it becomes more difficult for electrons to be injected into the epitaxial layer EPI from the peripheral portion R2. Therefore, the amount of electrons injected into the epitaxial layer EPI is less than in the study example. As a result, the amount of holes injected from the anode region AR into the epitaxial layer EPI is also less than in the study example. Therefore, in Embodiment 6, when a reverse bias is applied to the diode and recovery operation is performed, the concentration of holes at the end of the anode electrode AE ​​can be suppressed more than in the study example. That is, according to Embodiment 6, the destruction of the anode electrode AE ​​can be suppressed.

[0096] For example, to form an n-type semiconductor region NR in the cell portion R1 while preventing its formation in the peripheral portion R2 using ion implantation, the following steps are required. Specifically, ion implantation must be performed through a mask patterned using photolithography. In this case, the number of steps increases, thus increasing the manufacturing cost of semiconductor devices including diodes.

[0097] In contrast, Embodiment 6 applies the basic concept. That is, in Embodiment 6, an n-type semiconductor region NR is formed by irradiating with laser light through laser annealing. In this case, the irradiation position of the laser light can be set. Therefore, the irradiation position of the laser light can be set so that the cell portion R1 is irradiated with laser light, while the peripheral portion R2 is not irradiated with laser light. That is, the lower surface of the semiconductor substrate SUB1 has the lower surface of the cell portion R1 and the lower surface of the peripheral portion R2. In the process of irradiating with laser light, the lower surface of the cell portion R1 is irradiated with laser light, while the lower surface of the peripheral portion R2 is not irradiated with laser light. As a result, an n-type semiconductor region NR can be formed only in the cell portion R1.

[0098] According to Embodiment 6, photolithography technology is not used. In other words, in Embodiment 6, the number of steps does not increase as in the example under consideration. Therefore, according to Embodiment 6, the increase in manufacturing costs of semiconductor devices including diodes can be suppressed.

[0099] <Embodiment 7> Embodiment 7 is an example of applying the basic concept to a semiconductor device including a diode.

[0100] In the semiconductor device 200 including the diode shown in Figure 16, during recovery operation, electrons may be rapidly discharged from the epitaxial layer EPI to the cathode electrode KE via the semiconductor substrate SUB1. In particular, if the thickness of the semiconductor substrate SUB1 and the epitaxial layer EPI is reduced in order to improve the characteristics of the diode, the rapid discharge of electrons becomes apparent. This rapid discharge of electrons leads to a rapid change in the recovery current.

[0101] The diode included in the semiconductor device 200 is used, for example, as a "freewheeling diode," which is a component of an inverter. An inverter is, for example, a circuit that drives a motor. A motor contains inductance. Therefore, when the aforementioned rapid change in recovery current flows through the motor, a large back electromotive force is generated. As a result, "ringing" occurs in the waveform of the recovery current.

[0102] Therefore, semiconductor devices containing diodes that can suppress "ringing" are being considered.

[0103] Figure 20 is a cross-sectional view showing the configuration of a semiconductor device 300 including a diode.

[0104] In Figure 20, the semiconductor substrate SUB1 is an n-type semiconductor substrate. In the first portion P1 of the semiconductor substrate SUB1, a p-type semiconductor region PR is formed, for example, in which boron is introduced. During the recovery operation, electrons are ejected along a path from the epitaxial layer EPI through the semiconductor substrate SUB1 to the cathode electrode KE.

[0105] However, a p-type semiconductor region PR is formed in the semiconductor device 300. Electrons cannot pass through the inside of the p-type semiconductor region PR. Therefore, during recovery operation, electrons discharged from the epitaxial layer EPI detour through the path indicated by the arrow in Figure 20. As a result, it takes time for electrons to be discharged. This means that the change in recovery current is mitigated. Therefore, since abrupt changes in the recovery current are suppressed, the back electromotive force generated when the recovery current flows through the motor can be reduced. Thus, according to the semiconductor device 300, "ringing" can be suppressed. In this way, from the viewpoint of suppressing "ringing," forming a p-type semiconductor region PR in the semiconductor substrate SUB1 is useful.

[0106] For example, a p-type semiconductor region (PR) can be formed using ion implantation. In this case, ion implantation must be performed via a mask patterned using photolithography techniques. However, this method increases the manufacturing cost of the semiconductor device 300, including the diode, due to the increased number of steps involved.

[0107] In contrast, Embodiment 7 applies the basic concept. Specifically, in Embodiment 7, p-type (second conductivity type) boron (third conductivity impurity), which is different from n-type (first conductivity type), is introduced into the first portion P1 of the semiconductor substrate SUB1. Subsequently, a p-type semiconductor region PR is formed by irradiating it with laser light through laser annealing. In this case, the irradiation position of the laser light can be set. Therefore, in Embodiment 7, a p-type semiconductor region PR can be formed in the first portion P1 of the semiconductor substrate SUB1 by performing the following steps.

[0108] Specifically, in Embodiment 7, a step is performed to form a diffusion source on the bottom surface BS of the semiconductor substrate SUB1 for diffusing boron into the first portion P1 of the semiconductor substrate SUB1. Subsequently, a step is performed to irradiate the bottom surface BS of the semiconductor substrate SUB1 with laser light via the diffusion source. In the laser light irradiation step, the laser light is irradiated to the first region BR1 of the bottom surface BS included in the first portion P1, while the laser light is not irradiated to any other region of the bottom surface BS. As a result, boron is replenished from the diffusion source near the first region BR1 of the bottom surface BS of the semiconductor substrate SUB1 where the boron impurity concentration is lower than the peak value. Then, by laser annealing, the replenished boron can be diffused almost uniformly into the molten silicon. Therefore, according to Embodiment 7, a p-type semiconductor region PR can be formed near the first region BR1 of the bottom surface BS with suppressed reduction in boron impurity concentration.

[0109] According to Embodiment 7, photolithography technology is not used. Therefore, according to Embodiment 7, the increase in manufacturing costs of the semiconductor device 300 including the diode can be suppressed.

[0110] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0111] 10 Boron 10A impurity concentration distribution 20 Boron 50 IGBT 100 Semiconductor Equipment 200 Semiconductor Equipment 300 semiconductor equipment AE anode electrode AR Anode Region BC1 Body Contact Area BC2 Body Contact Area BL buffer layer BR1 1st area BS bottom side CE collector electrode CHP semiconductor chip CT collector terminal DF membrane DFL Drift Layer EE emitter electrode EPI (Epitaxial Layer) ER1 Emitter region ER2 Emitter Region ET emitter terminal FRD diode FS top surface GE Terminal GOX gate insulating film GT gate terminal IF1 Interlayer Insulation IL interlayer film KE cathode electrode NR n-type semiconductor region OP opening P1 Part 1 PR p-type semiconductor region PW1 p-type well PW2 p-type well R1 Cell section R2 surrounding area SUB Semiconductor Substrate SUB1 Semiconductor substrate

Claims

1. (a) A step of preparing a semiconductor substrate having a bottom surface, (b) A step of introducing a first conductive impurity of a first conductivity type into the semiconductor substrate from the lower surface of the semiconductor substrate by using an ion implantation method. (c) A step of forming a film containing the second conductive impurity of the first conductivity type on the lower surface, (d) After step (c), a step of irradiating the lower surface with laser light through the film, (e) A step of removing the film after step (d), (f) After step (e), a step of forming a conductive film on the lower surface, A method for manufacturing a semiconductor device, comprising:

2. In the method for manufacturing a semiconductor device according to claim 1, Step (c) is performed after step (b).

3. In the method for manufacturing a semiconductor device according to claim 1, Step (c) is performed before step (b).

4. In the method for manufacturing a semiconductor device according to claim 1, The aforementioned semiconductor substrate is composed of semiconductor material, In step (d) above, the semiconductor material located in a portion of the semiconductor substrate that is 0 μm or more and 0.25 μm or less from the lower surface in a direction perpendicular to the lower surface is melted.

5. In the method for manufacturing a semiconductor device according to claim 1, The aforementioned semiconductor substrate is A cell section having a pn junction diode, A peripheral portion that surrounds the cell portion in a planar manner, Includes, The lower surface of the semiconductor substrate has the lower surface of the cell portion and the lower surface of the peripheral portion. In step (d) above, the laser light is irradiated onto the lower surface of the cell portion, while the laser light is not irradiated onto the lower surface of the peripheral portion.

6. In the method for manufacturing a semiconductor device according to claim 1, The semiconductor substrate is of the first conductivity type, In step (b) above, a third conductive impurity of a second conductivity type different from the first conductivity type is introduced into the first portion of the semiconductor substrate. In step (d) above, the laser light is irradiated onto the first region of the lower surface included in the first portion, while the laser light is not irradiated onto any region of the lower surface other than the first region.

7. In the method for manufacturing a semiconductor device according to claim 1, The semiconductor substrate is of the first conductivity type, The semiconductor substrate has an upper surface, The first conductivity type epitaxial layer is formed on the upper surface of the semiconductor substrate. Within the epitaxial layer, an anode region constituting a diode is formed, which is an anode region of a second conductivity type different from the first conductivity type. The semiconductor substrate and the epitaxial layer constitute the cathode region of the diode. After step (d), the semiconductor substrate contains the second conductive impurity.

8. In the method for manufacturing a semiconductor device according to claim 7, The aforementioned first conductive impurity is an n-type impurity, The aforementioned second conductive impurity is an n-type impurity.

9. In the method for manufacturing a semiconductor device according to claim 8, The first conductive impurity is phosphorus, The second conductive impurity is phosphorus.

10. In the method for manufacturing a semiconductor device according to claim 1, The semiconductor substrate is of the first conductivity type, The semiconductor substrate has an upper surface, An epitaxial layer of a second conductivity type, different from the first conductivity type, is formed on the upper surface of the semiconductor substrate. Within the epitaxial layer, the emitter region of the second conductivity type constituting the IGBT is formed. The gate electrode of the IGBT is formed on a gate insulating film that is in partial contact with the emitter region. The semiconductor substrate is the collector region of the IGBT, After step (d), the semiconductor substrate contains the second conductive impurity.

11. In the method for manufacturing a semiconductor device according to claim 10, The first conductive impurity is a p-type impurity, The second conductive impurity is a p-type impurity.

12. In the method for manufacturing a semiconductor device according to claim 11, The first conductive impurity is boron, The second conductive impurity is boron.

13. (a) A step of preparing a semiconductor substrate having a bottom surface, (b) A step of depositing a first conductive impurity of the first conductivity type onto the lower surface, (c) After step (b), a step of irradiating the lower surface with laser light, (d) After step (c), a step of forming a conductive film on the lower surface, A method for manufacturing a semiconductor device, comprising:

14. In the method for manufacturing a semiconductor device according to claim 13, The first conductive impurity is boron, In step (b) above, the semiconductor substrate is transported in a cleanroom equipped with a boron-containing air filter, with its lower surface facing upwards.

15. In the method for manufacturing a semiconductor device according to claim 13, The aforementioned semiconductor substrate is composed of semiconductor material, In step (c), the semiconductor material located in a portion of the semiconductor substrate that is 0 μm or more and 0.25 μm or less from the lower surface in a direction perpendicular to the lower surface is melted.

16. In the method for manufacturing a semiconductor device according to claim 13, The aforementioned semiconductor substrate is A cell section having a pn junction diode, A peripheral portion that surrounds the cell portion in a planar manner, Includes, The lower surface of the semiconductor substrate has the lower surface of the cell portion and the lower surface of the peripheral portion. In step (c) above, the laser light is irradiated onto the lower surface of the cell portion, while the laser light is not irradiated onto the lower surface of the peripheral portion.

17. In the method for manufacturing a semiconductor device according to claim 13, The semiconductor substrate is a second conductivity type different from the first conductivity type, In step (c) above, the laser light is irradiated onto the first region of the lower surface, while the laser light is not irradiated onto any region of the lower surface other than the first region.

18. In the method for manufacturing a semiconductor device according to claim 13, The semiconductor substrate is of the first conductivity type, The semiconductor substrate has an upper surface, The first conductivity type epitaxial layer is formed on the upper surface of the semiconductor substrate. Within the epitaxial layer, an anode region constituting a diode is formed, which is an anode region of a second conductivity type different from the first conductivity type. The semiconductor substrate and the epitaxial layer constitute the cathode region of the diode. The first conductive impurity is phosphorus, After step (c), the semiconductor substrate contains the first conductive impurity.

19. In the method for manufacturing a semiconductor device according to claim 13, The semiconductor substrate is of the first conductivity type, The semiconductor substrate has an upper surface, An epitaxial layer of a second conductivity type, different from the first conductivity type, is formed on the upper surface of the semiconductor substrate. Within the epitaxial layer, the emitter region of the second conductivity type constituting the IGBT is formed. The gate electrode of the IGBT is formed on a gate insulating film that is in partial contact with the emitter region. The semiconductor substrate is the collector region of the IGBT, The first conductive impurity is boron, After step (c), the semiconductor substrate contains the first conductive impurity.

Images