Protection circuits and hazards

Abstract

To provide a protection circuit and semiconductor device that can prevent internal circuits from becoming floating while keeping current consumption low. [Solution] The protection circuit 1A is a circuit having a first end connected to a first power supply terminal to which a first power supply voltage is applied, and a second end connected to a second power supply terminal, via a current path P1 formed by parasitic diodes 6_1 to 6_n of semiconductor elements included in the internal circuit 6. The circuit is configured to be switchable between a first conduction state in which the first end and the second end conduct with a first resistance value in a steady state when a first power supply voltage of the correct polarity is applied, and a second conduction state in which the first end and the second end conduct with a second resistance value higher than the first resistance value while limiting the reverse current in a reverse connection state when a first power supply voltage of the opposite polarity to the correct polarity is applied.

Description

Technical Field

[0001] The present invention relates to a protection circuit and a semiconductor device.

Background Art

[0002] A power supply device (for example, a secondary battery, etc.) that supplies power to a semiconductor device may apply a power supply voltage of a polarity opposite to the polarity applied in the steady state (hereinafter simply referred to as "reverse polarity") due to reverse connection of a connector, noise, etc. A general semiconductor device is configured to include a parasitic diode that is forward-biased with respect to the reverse-polarity power supply voltage. Therefore, when a reverse-polarity power supply voltage is applied to a semiconductor device that does not consider the application of a reverse-polarity power supply voltage, an excessive forward current flows through the parasitic diode, and the elements constituting the semiconductor device may be damaged. From the viewpoint of preventing damage to elements caused by the application of such a reverse-polarity power supply voltage, a technique for protecting an integrated circuit has been disclosed (for example, see Patent Document 1).

[0003] The protection circuit to which the technique disclosed in Patent Document 1 is applied has an NPN bipolar transistor including a base connected via a resistor to a VCC terminal that supplies a power supply voltage VCC (≠0V), a collector connected to an internal circuit to be protected (hereinafter referred to as "protection target" or "protected circuit"), and an emitter connected to a GND terminal that supplies a power supply voltage of 0V.

[0004] In a state where a reverse-polarity power supply voltage is not applied, that is, in a steady state where the power supply voltage VCC is a positive voltage (VCC>0), if the power supply voltage VCC is sufficiently higher than the forward voltage Vf of the base-emitter junction diode of the NPN bipolar transistor, the current driving force increases and the collector-emitter voltage can be regarded as substantially 0V. Therefore, in the steady state, the internal circuit can be regarded as being directly connected to the GND terminal.

[0005] On the other hand, when a reverse polarity power supply voltage is applied, that is, when the power supply voltage VCC is a negative voltage (VCC < 0), the base voltage follows the power supply voltage VCC and the base current stops flowing. As a result, the NPN bipolar transistor in the protection circuit is cut off, and the collector current is interrupted. By interrupting the collector current, it is possible to interrupt the excessive forward current that would cause damage to the element if the internal circuit were directly connected to the GND terminal, and consequently, the protected object can be protected from damage to the element caused by the application of a reverse polarity power supply voltage. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-289956 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] However, in the case of conventional protection circuits and semiconductor devices equipped with the technology disclosed in Patent Document 1, the internal circuit becomes floating when the NPN bipolar transistor in the protection circuit is in the cutoff state. The internal circuit becoming floating can have undesirable effects and therefore needs improvement. More specifically, when the internal circuit becomes floating, it increases the possibility of electrostatic discharge damage due to charge accumulation or discharge in the protected object, and also increases the possibility of malfunction due to electromagnetic noise interference.

[0008] On the other hand, if a base current is passed through the NPN bipolar transistor in the protection circuit, it is possible to prevent the NPN bipolar transistor from entering a cutoff state and thus avoid the internal circuit becoming floating. However, passing a base current through the NPN bipolar transistor is undesirable because it hinders the reduction of current consumption.

[0009] This invention has been made in consideration of the circumstances described above, and aims to provide a protection circuit and semiconductor device that can prevent the internal circuit from becoming floating while keeping the current consumption low. [Means for solving the problem]

[0010] A protection circuit according to an embodiment of the present invention is a protection circuit having a first end connected to a first power supply terminal to which a first power supply voltage is applied, and a second end connected to a second power supply terminal, via a current path formed by a parasitic diode of a semiconductor element included in the internal circuit, wherein the protection circuit is configured to be switchable between a first conduction state in which the first end and the second end conduct with a first resistance value in a steady state in which the first power supply voltage of the correct polarity is applied from the first power supply terminal, and a second conduction state in which the first end and the second end conduct with a second resistance value higher than the first resistance value while limiting the reverse current in a reverse connection state in which the first power supply voltage of the opposite polarity to the correct polarity is applied from the first power supply terminal. [Effects of the Invention]

[0011] According to the present invention, it is possible to prevent the internal circuit from becoming floating while keeping the current consumption low. [Brief explanation of the drawing]

[0012] [Figure 1] This is a circuit diagram showing an example of the configuration (first configuration example) of a protection circuit and semiconductor device according to the first embodiment of the present invention. [Figure 2] (A) is a circuit diagram showing a first configuration example of a step-down circuit in a semiconductor device according to the first embodiment, which includes a load containing a constant current source; (B) is a circuit diagram showing a first configuration example of a constant current source as a load; and (C) is a circuit diagram showing a second configuration example of a constant current source as a load. [Figure 3] This is a circuit diagram showing an example of the configuration of a protection circuit and semiconductor device according to the first embodiment (second configuration example). [Figure 4](A), (B), and (C) are circuit diagrams showing second, third, and fourth configuration examples of the load of the step-down circuit in the semiconductor device according to the first embodiment, respectively. [Figure 5] This is a circuit diagram showing a modified example (third configuration example) of the protection circuit and semiconductor device according to the second embodiment. [Figure 6] This is a circuit diagram showing a modified example (fourth configuration example) of the protection circuit and semiconductor device according to the second embodiment. [Figure 7] (A), (B), and (C) are circuit diagrams showing the first, second, and third configuration examples of the current / voltage conversion circuit included in the step-down circuit of the semiconductor device according to the second embodiment. [Figure 8] (A) and (B) are circuit diagrams showing a first and second configuration example of a constant current source provided in a step-down circuit in a semiconductor device according to the second embodiment, respectively. [Figure 9] This is a circuit diagram showing a modified example (second configuration example) of the step-down circuit in the protection circuit according to the second embodiment. [Modes for carrying out the invention]

[0013] Hereinafter, a protection circuit and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings.

[0014] [First Embodiment] Figure 1 is a circuit diagram of a protection circuit 1A, which is an example of a protection circuit according to the first embodiment, and a semiconductor device 10A, which is an example of a semiconductor device according to the first embodiment.

[0015] The semiconductor device 10A includes a protection circuit 1A and a protected circuit 2A which is the object to be protected by the protection circuit 1A. The protection circuit 1A and the protected circuit 2A are configured as semiconductor integrated circuits. The semiconductor device 10A includes a first end connected to a VDD terminal 3 that supplies a voltage VDD which is an example of a power supply voltage, and a second end connected to a GND terminal 4 which is a ground terminal that supplies a ground voltage GND which is an example of a power supply voltage different from the voltage VDD. Here, the connection point between the first end of the semiconductor device 10A and the VDD terminal 3 is called node N1, and the connection point between the second end of the semiconductor device 10A and the GND terminal 4 is called node N2.

[0016] The protected circuit 2A is connected to node N1, includes a first end corresponding to the first end of the semiconductor device 10A, a second end that would be connected to the GND terminal 4 if there were no protection circuit 1A, and an output end that supplies a gate voltage Vg to the protection circuit 1A. The protection circuit 1A includes a first end connected to the second end of the protected circuit 2A, a second end connected to the GND terminal 4, and an input end that receives the supply of the gate voltage Vg from the protected circuit 2A. Here, the connection point between the protection circuit 1A (first end) and the protected circuit 2A (second end) is called node N3.

[0017] The protection circuit 1A includes an NMOS transistor 11 which is an example of an N-type field effect transistor (FET), and a current limiting circuit 5A connected in parallel with the NMOS transistor 11 as a protection transistor.

[0018] The NMOS transistor 11 includes a source as the first end, a drain as the second end, and a gate as the input end. The source of the NMOS transistor 11 corresponds to the first end of the protection circuit 1A and is connected to the second end of the protected circuit 2A. The drain of the NMOS transistor 11 corresponds to the second end of the protection circuit 1A and is connected to the GND terminal 4. The gate of the NMOS transistor 11 is connected to the output end of the protected circuit 2A.

[0019] The current limiting circuit 5A includes, for example, a depletion-type NMOS transistor 51 with its gate and source connected. In the depletion-type NMOS transistor 51, the drain is connected to the drain of the NMOS transistor 11. The source is connected to the source of the NMOS transistor 11 and the gate of the depletion-type NMOS transistor 51. The gate is connected to the source of the NMOS transistor 11. In other words, the depletion-type NMOS transistor 51 includes a drain as a first terminal connected to the drain of the NMOS transistor 11, a source as a second terminal connected to the source of the NMOS transistor 11, and a gate as a control terminal connected to its own source (the depletion-type NMOS transistor 51).

[0020] The protected circuit 2A comprises an internal circuit 6 that uses semiconductor elements such as FETs, and a source follower 7 that acts as a step-down circuit connected in parallel with the internal circuit 6.

[0021] Since semiconductor elements contain parasitic diodes, an internal circuit 6 to which a semiconductor element is applied has a current path P1 formed by one parasitic diode 6_1 or a plurality of n (where n is an integer of 2 or more) parasitic diodes 6_1 to 6_n, which connect nodes N3 and N1 in a conductive manner. In other words, both ends of the current path P1 correspond to both ends of the internal circuit 6. Here, of the ends of the current path P1 and the internal circuit 6, the end connected to node N1 is referred to as the first end, and the end connected to node N3 is referred to as the second end.

[0022] The source follower 7 includes a depletion-type NMOS transistor 70 and a load 71, a control terminal 73, and an output terminal 74. The depletion-type NMOS transistor 70 and the load 71 are connected in series between node N1 and node N3.

[0023] The depletion-type NMOS transistor 70, acting as a step-down transistor, includes a drain as the first terminal, a source as the second terminal, and a gate as the control terminal. The load 71 includes a first terminal connected to the second terminal of the current path P1, i.e., node N3, and a second terminal connected to the source of the depletion-type NMOS transistor 70. Here, the connection point between the depletion-type NMOS transistor 70 (source) and the load 71 (second terminal) is referred to as node N4.

[0024] In the depletion-type NMOS transistor 70, the drain is connected to the first end of the current path P1, i.e., node N1. The source is connected to the second end of the load 71 and the output terminal 74. The gate is connected to the control terminal 73.

[0025] The control terminal 73 is connected to any node outside the source follower 7 that can supply a predetermined bias voltage Vbias, such as a node in the internal circuit 6. Connecting the control terminal 73 to a node in the internal circuit 6 is preferable because it allows the bias voltage Vbias to be supplied without adding any new circuitry. The output terminal 74 is connected outside the source follower 7 to the gate of the NMOS transistor 11 corresponding to the input terminal of the protection circuit 1A.

[0026] Next, we will describe the constant current source 711, which is the first configuration example of the load 71. Figure 2(A) is a circuit diagram showing a first configuration example of the load 71 including the constant current source 711. Figure 2(B) is a circuit diagram showing a first configuration example of the constant current source 711, and Figure 2(C) is a circuit diagram showing a second configuration example of the constant current source 711.

[0027] The constant current source 711 includes a first end connected to node N4 and a second end connected to node N3, and is configured to supply a constant current I1 (see Figure 2(A)). The constant current source 711 has, for example, a depletion-type NMOS transistor 31 as a depletion-type FET with its source and gate connected, and is configured to supply a constant current I1 to the drain of the depletion-type NMOS transistor 31 (see Figure 2(B)).

[0028] The constant current source 711 may be configured with a current mirror circuit 32 formed by connecting two NMOS transistors 321 and 322, and a constant current source 33 that supplies a constant current I2 to the drain of the NMOS transistor 322. The current mirror circuit 32 is configured such that the gate of the NMOS transistor 322 is connected to its own drain and to the gate of the NMOS transistor 321. In the constant current source 711 having the current mirror circuit 32 and the constant current source 33, a constant current I1 (=m1 × I2) obtained by copying the constant current I2 flowing to the drain of the NMOS transistor 322 with a predetermined mirror ratio m1 (m1 is any positive number) can be supplied to the drain of the NMOS transistor 321.

[0029] Next, the circuit operation of the protection circuit 1A and the semiconductor device 10A will be explained sequentially, divided into the following states: (1) when the power supply is correctly connected and a positive power supply voltage VDD (>0V) is supplied from the VDD terminal 3 (hereinafter referred to as the "steady state"), (2) when the power supply is reversed and a negative power supply voltage VDD (<0V) is supplied from the VDD terminal 3 (hereinafter referred to as the "reverse connection state"), (3) when the internal circuit 6 is in standby mode (hereinafter simply referred to as the "standby state"), and (4) when no voltage VDD is supplied from the VDD terminal 3 (hereinafter referred to as the "VDD terminal open state").

[0030] (1) Steady state The current flowing through the internal circuit 6 flows from the VDD terminal 3 to the GND terminal 4, that is, from node N1 to node N3. When controlling the NMOS transistor 11 by supplying a gate voltage Vg from the source follower 7, the bias voltage Vbias, which is the gate voltage of the depletion-type NMOS transistor 70, is set so that the gate voltage Vg of the NMOS transistor 11 is higher than its threshold voltage Vth. When this set bias voltage Vbias is applied to the gate of the depletion-type NMOS transistor 70, the NMOS transistor 11 turns on and current flows from the source (node ​​N3) to the drain (node ​​N2) of the NMOS transistor 11.

[0031] The gate voltage Vg can be approximated by the following equation (1), using the bias voltage Vbias, the gate-source voltage Vgs of the depletion-type NMOS transistor 70, and the threshold voltage Vth_sf of the depletion-type NMOS transistor 70. Vg=Vbias-Vgs≒Vbias-Vth_sf>Vth ---(1)

[0032] Here, if a depletion-type NMOS transistor 70, which is a depletion-type FET with a negative threshold voltage, is used as the step-down transistor of the source follower 7, the gate voltage Vg must be greater than the bias voltage Vbias, that is, the following equation (2) Vg≧Vbias ---(2) The source follower 7 can be configured to satisfy the above equation (2). By configuring the source follower 7 to satisfy equation (2) above, it is possible to make it easier to turn on the NMOS transistor 11.

[0033] On the other hand, the depletion-type NMOS transistor 51, whose gate and source are connected (short-circuited), can be considered as a diode-connected FET in a steady state, and therefore, when it is ON, current flows from the source to the drain. Here, in order to operate the internal circuit 6 stably, it is preferable to operate the reference node, node N3, at a voltage close to the ground voltage GND, which is the voltage at the GND terminal 4. When the voltage at node N3 is close to the ground voltage GND, both the NMOS transistor 11 and the depletion-type NMOS transistor 51 operate in a resistance region where the drain-source voltage is close to 0V. Therefore, the current flowing from node N1, which is connected to the VDD terminal 3, to node N3 flows to the GND terminal 4 through the on-resistances of the NMOS transistor 11 and the depletion-type NMOS transistor 51.

[0034] Here, if we denote the voltage at node N3, the on-resistance of NMOS transistor 11, the on-resistance of depletion-type NMOS transistor 51, the equivalent resistance obtained by connecting the on-resistance of NMOS transistor 11 and the on-resistance of depletion-type NMOS transistor 51 in parallel, and the current flowing from node N3 to node N2 as voltage VN3, resistance Ron_prt, resistance Ron_dep, resistance Ron (=Ron_prt / / Ron_dep), and current Iope_gnd, respectively, then these can be expressed by the following equation (3). VN3=(Ron_prt / / Ron_dep)×Iope_gnd =Ron×Iope_gnd ---(3)

[0035] Here, from equation (3) above, by increasing the aspect ratio of the NMOS transistor 11 and the depletion-type NMOS transistor 51, or by setting the gate voltage Vg supplied to the gate of the NMOS transistor 11 to a higher value, the combined resistance value Ron can be made sufficiently small, thereby bringing the internal circuit 6 closer to a state connected to the GND terminal 4, i.e., a grounded state. By bringing the internal circuit 6 closer to a grounded state, floating of the internal circuit 6 can be prevented.

[0036] (2) Reverse connection state When a negative voltage is applied to the VDD terminal 3, the forward bias of the parasitic diodes 6_1 to 6_n in the internal circuit 6 causes the gate voltage Vg of the NMOS transistor 11 and the voltage VN3 at node N3 to decrease in accordance with the voltage VDD. When the gate voltage Vg of the NMOS transistor 11 and the voltage VN3 at node N3 decrease and the gate-source voltage Vgs11 of the NMOS transistor 11 falls below the threshold voltage Vth, the NMOS transistor 11 turns off.

[0037] On the other hand, the depletion-type NMOS transistor 51, with its gate and source connected (short-circuited), can be considered a constant current source, and therefore the current can be limited from the drain connected to node N2 to the source connected to node N3. Here, the threshold voltage VTND of the depletion-type NMOS transistor 51 is negative (VTND < 0V) and the gate-source voltage Vgs51 is 0V (Vgs51 = 0V), so when the drain-source voltage is greater than or equal to the absolute value of the threshold voltage |VTND|, it operates in the saturation region based on equation (4), which is a general equation for transistors. VDS ≥ VGS - VTH --- (4) VDS: Drain-Source Voltage VGS: Gate-Source Voltage VTH: Threshold Voltage

[0038] Here, if we denote the current flowing from the drain to the source of the depletion-type NMOS transistor 51 as the reverse current Irev, and the transconductance coefficient Kdep of the depletion-type NMOS transistor 51 as a constant, then the reverse current Irev is the drain current of the depletion-type NMOS transistor 51, and can be expressed by the following equation (5). Irev=Kdep×|VTND| 2 ---(5)

[0039] The reverse current Irev is a reverse current that flows to the VDD terminal 3 via the protected circuit 2A (more specifically, the internal circuit 6 or source follower 7), and is generally undesirable. However, the transconductance coefficient Kdep can be reduced by reducing the aspect ratio of the depletion-type NMOS transistor 51. By setting the transconductance coefficient Kdep to a small value, the depletion-type NMOS transistor 51 can be made capable of limiting the reverse current Irev to an acceptable current value.

[0040] (3) Standby state In standby mode, the current flowing through the source follower 7 is cut off to reduce current consumption. With the current flowing through the source follower 7 cut off, the gate voltage Vg of the NMOS transistor 11 falls below the threshold voltage Vth of the NMOS transistor 11, and the NMOS transistor 11 turns off. On the other hand, the depletion-type NMOS transistor 51, with its gate and source connected (short-circuited), can be considered as a diode-connected FET, similar to the steady state, and operates in the resistance region of its on-resistance, resistance Ron_dep.

[0041] Here, (3) If the current that flows through the internal circuit 6 in the standby state is denoted as the standby current Istb, then the voltage VN3 at node N3 can be expressed by the following equation (6). VN3 = Ron_dep × Istb --- (6) From equation (6), if the aspect ratio of the depletion-type NMOS transistor 51 is increased, and the design is such that the combined resistance value Rdep is sufficiently small, then even in the standby state where current consumption is suppressed, the internal circuit 6 can be brought close to the state where it is connected to the GND terminal 4, i.e., the ground state, similar to the steady state (1). By bringing the internal circuit 6 closer to the ground state, floating of the internal circuit 6 can be prevented.

[0042] (4) VDD terminal open When the VDD terminal is open, no voltage VDD is supplied from the VDD terminal 3 to node N1, so the NMOS transistor 11 turns off. On the other hand, the depletion-type NMOS transistor 51, with its gate and source connected (short-circuited), can be considered as a diode-connected FET, similar to (1) the steady state and (3) the standby state, and operates in the resistance region of its on-resistance, resistor Ron_dep. Therefore, similar to (1) the steady state and (3) the standby state, the internal circuit 6 can be brought closer to ground. By bringing the internal circuit 6 closer to ground, floating of the internal circuit 6 can be prevented.

[0043] Here, we will describe an example of a design procedure that allows the internal circuit 6 to be brought close to ground in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and (2) the reverse connection state to limit the reverse current Irev to an acceptable current value.

[0044] First, using equations (5) and (6) described above, the aspect ratio of the depletion-type NMOS transistor 51 is determined so that the reverse current Irev and the voltage VN3 (=Ron_dep × Istb) at node N3 in the standby state are set to the desired values. When determining the aspect ratio of the depletion-type NMOS transistor 51, if the reverse current Irev is to be reduced, the aspect ratio of the depletion-type NMOS transistor 51 is set to a small value. After determining the aspect ratio of the depletion-type NMOS transistor 51, the aspect ratio and gate voltage Vg of the NMOS transistor 11 are then determined using equation (3) described above so that (1) the voltage VN3 at node N3 in the steady state is set to the desired value.

[0045] By designing in this manner, the protection circuit and semiconductor device according to this embodiment can be configured to bring the internal circuit 6 closer to the ground state in (1) the steady state, (3) the standby state and (4) the VDD terminal open state, and (2) the reverse current Irev in the reverse connection state can be limited to an acceptable current value.

[0046] As described above, with the protection circuit 1A and semiconductor device 10A, the protection circuit 1A is configured to include a current limiting circuit 5A connected in parallel with the NMOS transistor 11, so that a current path can be secured between the internal circuit 6 and the GND terminal 4 even when the NMOS transistor 11 is in the off state. Therefore, a current path can be secured between the internal circuit 6 and the GND terminal 4, and the floating of the internal circuit 6 can be prevented.

[0047] Furthermore, the configuration in which the protection circuit 1A is connected in parallel with the NMOS transistor 11 and includes a current limiting circuit 5A allows the protection circuit 1A and the semiconductor device 10A to bring the internal circuit 6 closer to ground in (1) the steady state, (3) the standby state and (4) the VDD terminal open state, and (2) the reverse current Irev to be limited to an acceptable current value in the reverse connection state.

[0048] It should be noted that the protection circuit and semiconductor device according to the first embodiment are not limited to the protection circuit 1A and semiconductor device 10A described above. Next, other configuration examples (modified versions) of the protection circuit 1A and semiconductor device 10A will be described.

[0049] Figure 3 is a circuit diagram showing a modified example (second configuration example) of the protection circuit and semiconductor device according to the first embodiment, namely protection circuit 1B and semiconductor device 10B.

[0050] The semiconductor device 10B differs from the semiconductor device 10A in that it includes a protection circuit 1B instead of a protection circuit 1A, but otherwise it is substantially the same. The protection circuit 1B differs from the protection circuit 1A in that it includes a current limiting circuit 5B instead of a current limiting circuit 5A, but otherwise it is substantially the same. The current limiting circuit 5B differs from the current limiting circuit 5A in that it further includes a resistor 52 connected between the source of the depletion-type NMOS transistor 51 and node N3.

[0051] In the current limiting circuit 5B, the depletion-type NMOS transistor 51 includes a drain connected to the drain of the NMOS transistor 11, a source as a second terminal, and a gate as a control terminal. The resistor 52 includes a first terminal connected to the source of the depletion-type NMOS transistor 51, and a second terminal connected to the source of the NMOS transistor 11 and the gate of the depletion-type NMOS transistor 51. In other words, the resistor 52 conducts between the source of the depletion-type NMOS transistor 51 and the source of the NMOS transistor 11 connected to the gate of the depletion-type NMOS transistor 51.

[0052] With the protection circuit 1B and semiconductor device 10B configured in this way, although the resistance value between the ends of the current limiting circuit 5B, i.e., between node N2 and node N3, is different from the resistance value between the ends of the current limiting circuit 5A, it operates in the same manner as the protection circuit 1A and semiconductor device 10A.

[0053] In the protection circuit 1B and semiconductor device 10B, the resistor 52 and the depletion-type NMOS transistor 51 appear to be in series, so equations (3) and (6) above are obtained by substituting "Ron_dep" with "Ron_dep+R52" in equations (3) and (6) above. Here, "R52" is the resistance value of resistor 52. Also, in the reverse connection state (2), the voltage drop across resistor 52 is approximately the absolute value |VTND| of the threshold voltage of the depletion-type NMOS transistor 51, so the reverse current Irev is the value obtained by dividing the absolute value |VTND| of the threshold voltage of the depletion-type NMOS transistor 51, which corresponds to the voltage drop across resistor 52, by its resistance value "R52", as shown in equation (7) below. Irev=|VTND| / R52 ---(7)

[0054] With the protection circuit 1B and semiconductor device 10B, the protection circuit 1B includes a current limiting circuit 5B connected in parallel with the NMOS transistor 11, which ensures a current path between the internal circuit 6 and the GND terminal 4 even when the NMOS transistor 11 is in the off state. Therefore, a current path can be ensured between the internal circuit 6 and the GND terminal 4, preventing the internal circuit 6 from floating.

[0055] Furthermore, the configuration in which the protection circuit 1B is connected in parallel with the NMOS transistor 11 and includes a current limiting circuit 5B allows the protection circuit 1B and the semiconductor device 10B to bring the internal circuit 6 closer to ground in (1) the steady state, (3) the standby state and (4) the VDD terminal open state, and (2) the reverse current Irev to be limited to an acceptable current value in the reverse connection state.

[0056] In the first embodiment, an example of a load 71 which is a constant current source 711 (first configuration example: see Figures 2(A) to 2(C)) has been described so far, but the load 71 is not limited to the case of the constant current source 711 described above. For example, the load 71 may be configured as shown in Figures 4(A), (B) and (C) described later.

[0057] Figures 4(A), (B), and (C) are circuit diagrams showing a second configuration example of the load 71, namely a resistor 712; a third configuration example of the load 71, namely a Zener diode 713; and a fourth configuration example of the load 71, namely a transistor circuit 714, respectively.

[0058] In this embodiment, the load 71 may be, for example, a resistor 712 (see second configuration example: Figure 4(A)), a Zener diode 713 (see third configuration example: Figure 4(B)), or a transistor circuit 714 including at least one diode-connected MOS transistor 714_1 (see fourth configuration example: Figure 4(C)). Note that the transistor circuit 714 is not limited to including one diode-connected MOS transistor 714_1, but may be configured by connecting multiple diode-connected MOS transistors, each including a MOS transistor 714_1, in series.

[0059] [Second Embodiment] Figures 5 and 6 are examples of semiconductor devices according to the second embodiment, and are circuit diagrams showing a semiconductor device 10C equipped with a protection circuit 1A and a semiconductor device 10D equipped with a protection circuit 1B, respectively.

[0060] Semiconductor devices 10C and 10D differ from semiconductor devices 10A (see Figure 1) and 10B (see Figure 3) in that they are equipped with a protected circuit 2B instead of the protected circuit 2A (see Figures 1 and 3), and more specifically, they are equipped with a step-down circuit 9 instead of the source follower 7 as a step-down circuit, but otherwise they are substantially the same. Therefore, in this description of the embodiment, we will focus on the differences from the above-described embodiment and omit redundant explanations. Note that the differences between semiconductor device 10C and semiconductor device 10D are substantially the same as the differences between semiconductor device 10A and semiconductor device 10B. Therefore, in this embodiment, semiconductor device 10C will be described, and semiconductor device 10D will be omitted in the description of semiconductor device 10C later, by substituting protection circuit 1A, current limiting circuit 5A, and semiconductor device 10C with protection circuit 1B, current limiting circuit 5B, and semiconductor device 10D, respectively.

[0061] The semiconductor device 10C includes a protection circuit 1A and a protected circuit 2B that is protected by the protection circuit 1A. The protection circuit 1A and the protected circuit 2B are configured as a semiconductor integrated circuit.

[0062] The protected circuit 2B comprises an internal circuit 6 and a step-down circuit 9 connected in parallel with the internal circuit 6. The protected circuit 2B also includes a first terminal connected to node N1 and corresponding to the first terminal of semiconductor device 10C, a second terminal connected to GND terminal 4 if the protection circuit 1A is not present, and an output terminal that supplies the gate voltage Vg to the protection circuit 1A.

[0063] The step-down circuit 9 according to the first configuration example includes a current-voltage conversion circuit (hereinafter referred to as "I / V conversion circuit") 90, a constant current source 91, and an output terminal 94. Here, the connection point between the constant current source 91 and the I / V conversion circuit 90 is referred to as node N5.

[0064] The constant current source 91 includes a first terminal connected to node N1 and a second terminal connected to node N5, and is configured to supply a constant current I3. The I / V conversion circuit 90 includes a first terminal connected to node N3 and a second terminal connected to node N5, and is configured to convert the constant current I3 supplied from the constant current source 91 into a gate voltage Vg and output it to node N5. The output terminal 94 is connected to node N5 within the step-down circuit 9. On the other hand, the output terminal 94 is connected to the gate of the NMOS transistor 11 outside the step-down circuit 9.

[0065] Next, we will explain an example configuration of the I / V conversion circuit 90. Figures 7(A), 7(B), and 7(C) are circuit diagrams showing a first configuration example of the I / V conversion circuit 90 having a resistor 901, a second configuration example having a Zener diode 902, and a third configuration example having a transistor circuit 903, respectively.

[0066] The I / V conversion circuit 90 is composed of, for example, a resistor 901 (first configuration example: see Figure 7(A)), a Zener diode 902 (second configuration example: see Figure 7(B)), or a transistor circuit 903 (third configuration example: see Figure 7(C)) including at least one diode-connected MOS transistor 903_1. Note that the transistor circuit 903 is not limited to including one diode-connected MOS transistor 903_1, but may also be composed of multiple diode-connected MOS transistors including MOS transistor 903_1 connected in series.

[0067] Next, we will describe an example configuration of the constant current source 91. Figures 8(A) and 8(B) are circuit diagrams showing a first configuration example in which the constant current source 91 has a depletion-type NMOS transistor 912 with its gate and source connected, and a second configuration example in which the constant current source 35 and a current mirror circuit 36 ​​are connected, respectively.

[0068] The constant current source 91 has, for example, a depletion-type NMOS transistor 912 as a depletion-type FET with its source and gate connected, and is configured to flow a constant current I3 through the drain of the depletion-type NMOS transistor 912 (see Figure 8(A)).

[0069] The constant current source 91 is configured with a current mirror circuit 36 ​​formed by connecting two NMOS transistors 361 and 362, and a constant current source 35 that supplies a constant current I4 to the drain of NMOS transistor 362. The current mirror circuit 36 ​​is configured such that the gate of NMOS transistor 362 is connected to its own drain and to the gate of NMOS transistor 361. In the constant current source 91, which has the current mirror circuit 36 ​​and the constant current source 35, a constant current I3 (= m2 × I4) obtained by copying the constant current I4 flowing to the drain of NMOS transistor 362 with a predetermined mirror ratio m2 (m2 is any positive number) can be supplied to the drain of NMOS transistor 361.

[0070] Next, the circuit operation of the protection circuit 1A and the semiconductor device 10C will be explained sequentially, divided into (1) steady state, (2) reverse connection state, (3) standby state, and (4) VDD terminal open state. In explaining the circuit operation of the semiconductor device 10C, explanations that overlap with those of the semiconductor device 10A will be simplified or omitted as appropriate.

[0071] (1) Steady state The current flowing through the internal circuit 6 flows from node N1 to node N3. The constant current I3 of the constant current source 91 is set so that the gate voltage Vg of the NMOS transistor 11 from the step-down circuit 9 is higher than its threshold voltage Vth. The constant current I3 set in this way is supplied to the I / V conversion circuit 90, which generates a gate voltage Vg that makes it easy to turn on the NMOS transistor 11 and supplies it to the gate of the NMOS transistor 11. In other respects, the circuit operation is the same as that of the protection circuit 1A and the semiconductor device 10A.

[0072] (2) Reverse connection state The reverse current Irev in the protection circuit 1A and semiconductor device 10C differs from the reverse current Irev in the protection circuit 1A and semiconductor device 10A in that it is the current that flows to the VDD terminal 3 via the protected circuit 2B (more specifically, the internal circuit 6 or the step-down circuit 9), but the circuit operation of the protection circuit 1A and semiconductor device 10C is the same as the circuit operation of the protection circuit 1A and semiconductor device 10A.

[0073] (3) Standby state The semiconductor device 10C is equipped with a switch (not shown) that cuts off the current flowing through the step-down circuit 9 in order to transition to a standby state. In the standby state, the current flowing through the step-down circuit 9 is cut off by turning off the switch in order to reduce current consumption. When the current flowing through the step-down circuit 9 is cut off, the gate voltage Vg of the NMOS transistor 11 falls below the threshold voltage Vth of the NMOS transistor 11, and the NMOS transistor 11 turns off. In other respects, the circuit operation is the same as that of the protection circuit 1A and the semiconductor device 10A.

[0074] (4) VDD terminal open When the VDD terminal is open, the circuit operation of the protection circuit 1A and the semiconductor device 10C is the same as the circuit operation of the protection circuit 1A and the semiconductor device 10A.

[0075] As described above, the protection circuit 1A and semiconductor device 10C provide the same effects as the protection circuit 1A and semiconductor device 10A. Specifically, the protection circuit 1A and semiconductor device 10C ensure a current path between the internal circuit 6 and the GND terminal 4, preventing the internal circuit 6 from floating. Furthermore, the internal circuit 6 can be brought closer to ground in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and the reverse current Irev can be limited to an acceptable current value in (2) the reverse connection state.

[0076] Furthermore, the same effects as those of the protection circuit 1B and semiconductor device 10D can be obtained. Specifically, the protection circuit 1B and semiconductor device 10D can secure a current path between the internal circuit 6 and the GND terminal 4, thereby preventing the internal circuit 6 from floating. In addition, the internal circuit 6 can be brought closer to the ground state in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and in (2) the reverse connection state, the reverse current Irev can be limited to an acceptable current value.

[0077] In the second embodiment, an example of a step-down circuit 9 having a constant current source 91 and an I / V conversion circuit 90 has been described so far, but the step-down circuit 9 is not limited to this example. For example, the step-down circuit 9 may be configured as shown in Figure 9, which will be described later.

[0078] Figure 9 is a circuit diagram showing a part of the second configuration example of a step-down circuit 9 having a resistor 92 and an I / V conversion circuit 90, specifically the resistor 92.

[0079] The step-down circuit 9 in the second configuration differs from the step-down circuit 9 in the first configuration in that it has a resistor 92 instead of a constant current source 91, but otherwise is substantially the same. The step-down circuit 9 in the second configuration generates a gate voltage Vg from the output terminal 94, similar to the step-down circuit 9 in the first configuration. The gate voltage Vg is supplied to the protection circuit 1A. The operation of the protection circuit 1A is as described above.

[0080] It should be noted that the present invention is not limited to the embodiments described above, and in practice, it can be implemented in various forms other than those described above, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, although the protection circuits 1A and 1B described above are examples that do not include a source follower 7 or a step-down circuit 9, the protection circuits 1A and 1B may be configured to further include a source follower 7 or a step-down circuit 9.

[0081] In the embodiments described above, a depletion-type NMOS transistor 70 was described as an example of a step-down transistor, but the invention is not limited to this. The step-down transistor may also be an enhancement-type transistor.

[0082] The protection circuit and semiconductor device according to this embodiment are described using the case where the voltage VDD is a positive voltage in a steady state as an example. However, the protection circuit and semiconductor device according to this embodiment may also be constructed by reversing the polarity of polarized elements such as the depletion-type NMOS transistor 11 (P-type and N-type) and the polarity of the power supply voltage (positive and negative).

[0083] The MOS transistors in the protection circuit and semiconductor device according to this embodiment are examples of field-effect transistors (FETs), and any type of FET is acceptable. In other words, in addition to MOSFETs, other field-effect transistors such as junction FETs (JFETs) and metal-insulated semiconductor FETs (MISFETs) may be appropriately selected.

[0084] These embodiments and their variations are included within the scope and essence of the invention, as well as within the scope of the invention and its equivalents as described in the claims. [Explanation of symbols]

[0085] 10A, 10B, 10C, 10D Semiconductor equipment 1A,1B protection circuit 2A,2B Protected circuit 3 VDD terminal 4 GND terminal 5A, 5B current limiting circuit 6 Internal circuit 6_1~6_n Parasitic diodes 7. Source Follower (Step-Down Circuit) 9 Step-down circuit 11 NMOS transistor (protection transistor) 70 Depletion-type NMOS transistor (step-down transistor) 71 load 73 (Control terminal of the step-down circuit) 74,94 (Output terminals of the step-down circuit) 90 I / V conversion circuit 91 Constant current source 92 resistors P1 Current Path

Claims

1. A protection circuit having a first end connected to a first power supply terminal to which a first power supply voltage is applied, and a second end connected to a second power supply terminal, via a current path formed by a parasitic diode of a semiconductor element included in the internal circuit, A protection circuit characterized by being configured to be switchable between a first conducting state in which the first terminal and the second terminal conduct with a first resistance value in a steady state in which the first power supply voltage of the correct polarity is applied from the first power supply terminal, and a second conducting state in which the first terminal and the second terminal conduct with a second resistance value higher than the first resistance value while limiting the reverse current in a reverse connection state in which the first power supply voltage of the opposite polarity to the correct polarity is applied from the first power supply terminal.

2. The protection circuit has a first current path and a second current path connected in parallel with each other. In the steady state, the first resistance value is formed by both the first current path and the second current path. The protection circuit according to claim 1, wherein in the reverse connection state, the second resistance value is formed by the second current path.

3. The first current path includes a protection transistor, The protection circuit according to claim 2, wherein the second current path includes a depletion-type transistor.

4. The protection circuit according to any one of claims 1 to 3, further comprising a step-down circuit connected in parallel with the internal circuit to generate a voltage for switching and controlling the conduction state of the protection circuit.

5. The protection circuit according to claim 4, A semiconductor device comprising a protected circuit having the aforementioned internal circuit.

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