Flip-flop circuit

Abstract

The present invention provides a flip-flop circuit and a drive circuit. [Solution] A flip-flop circuit having first to fifth input terminals and first to third output terminals, wherein the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulated signal, and the fifth input terminal is supplied with a second pulse width modulated signal. The first output terminal supplies a first selection signal based on the first pulse width modulated signal during the period from when the first trigger signal is supplied until the second trigger signal is supplied, the first output terminal supplies a first selection signal during the period when the batch selection signal is supplied, the second output terminal supplies a second selection signal based on the second pulse width modulated signal during the period from when the first trigger signal is supplied until the second trigger signal is supplied, and the third output terminal supplies a third trigger signal.

Claims

[Claim 1] Having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first output terminal, a second output terminal, a third output terminal, a first transistor, a second transistor, a third transistor, a node, a first wiring, a fourth transistor, and a second wiring, The first input terminal is supplied with a first trigger signal. The second input terminal is supplied with a second trigger signal, The third input terminal is supplied with a collective selection signal, The fourth input terminal is supplied with the first pulse width modulated signal, The fifth input terminal is supplied with a second pulse width modulated signal, The first output terminal has the function of supplying a first selection signal based on the first pulse width modulation signal during the period from when the first trigger signal is supplied until when the second trigger signal is supplied. The first output terminal has the function of supplying the first selection signal during the period in which the collective selection signal is supplied. The second output terminal supplies a second selection signal based on the second pulse width modulation signal during the period from when the first trigger signal is supplied until when the second trigger signal is supplied. The third output terminal supplies a third trigger signal. The first transistor comprises a gate electrode electrically connected to the node, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the third input terminal. The first transistor is in a non-conducting state during the period from when the first trigger signal is supplied until when the second trigger signal is supplied. The second transistor comprises a gate electrode electrically connected to the node, a first electrode electrically connected to the second output terminal, and a second electrode electrically connected to the first wiring. The second transistor is in a non-conducting state during the period from when the first trigger signal is supplied until when the second trigger signal is supplied. The third transistor comprises a gate electrode electrically connected to the node, a first electrode electrically connected to the third output terminal, and a second electrode electrically connected to the first wiring. The third transistor is in a non-conducting state during the period from when the first trigger signal is supplied until when the second trigger signal is supplied. The fourth transistor is a flip-flop circuit comprising a gate electrode electrically connected to the second wiring, a first electrode electrically connected to the node, and a second electrode electrically connected to the gate electrode of the first transistor.

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