Indication device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SEMICON ENERGY LAB CO LTD
- Filing Date
- 2026-02-25
- Publication Date
- 2026-06-17
Smart Images

Figure 00000000_0000_ABST
Abstract
Claims
1. A first to fourth wiring having regions extended in the row direction, A fifth wiring having a region extended in the direction of the row, The first to fourth transistors, The first EL element, It has a second EL element, The first transistor, the second transistor, and the first EL element are arranged in the first pixel. The third transistor, the fourth transistor, and the second EL element are arranged in the second pixel. In the row direction, the first pixel and the second pixel are adjacent to each other. The first image signal supplied from the first wiring is transmitted from the first wiring to the second transistor, at least through the channel formation region of the first transistor. The current corresponding to the first image signal transmitted to the second transistor flows from the second wiring to the first EL element, at least through the channel formation region of the second transistor. The second image signal supplied from the third wiring is transmitted from the third wiring to the fourth transistor, at least through the channel formation region of the third transistor. The current corresponding to the second image signal transmitted to the fourth transistor flows from the fourth wiring to the second EL element, at least through the channel formation region of the fourth transistor. The fifth wiring is electrically connected to the gate electrode of the first transistor and electrically connected to the gate electrode of the third transistor. In a plan view, the channel formation region of the second transistor has a region in which current flows in a direction intersecting the channel length direction of the first transistor. In a plan view, the channel formation region of the fourth transistor has a region in which current flows in a direction intersecting the channel length direction of the third transistor. The semiconductor layer having the channel formation region of the first transistor has the channel formation region of the second transistor, the channel formation region of the third transistor, the channel formation region of the fourth transistor, and an opening. The fifth wiring has a region that overlaps with the opening, The opening has a shape that extends in the row direction, In a plan view, the second wiring has a first region that overlaps with a conductive layer that functions as the gate electrode of the second transistor. A display device wherein the length of the opening in the column direction is greater than the length of the first region in the column direction.
2. A first to fourth wiring having regions extended in the row direction, A fifth wiring having a region extended in the direction of the row, The first to fourth transistors, The first EL element, It has a second EL element, The first transistor, the second transistor, and the first EL element are arranged in the first pixel. The third transistor, the fourth transistor, and the second EL element are arranged in the second pixel. In the row direction, the first pixel and the second pixel are adjacent to each other. The first image signal supplied from the first wiring is transmitted from the first wiring to the second transistor, at least through the channel formation region of the first transistor. The current corresponding to the first image signal transmitted to the second transistor flows from the second wiring to the first EL element, at least through the channel formation region of the second transistor. The second image signal supplied from the third wiring is transmitted from the third wiring to the fourth transistor, at least through the channel formation region of the third transistor. The current corresponding to the second image signal transmitted to the fourth transistor flows from the fourth wiring to the second EL element, at least through the channel formation region of the fourth transistor. The fifth wiring is electrically connected to the gate electrode of the first transistor and electrically connected to the gate electrode of the third transistor. In a plan view, the channel formation region of the second transistor has a region in which current flows in a direction intersecting the channel length direction of the first transistor. In a plan view, the channel formation region of the fourth transistor has a region in which current flows in a direction intersecting the channel length direction of the third transistor. The semiconductor layer having the channel formation region of the first transistor has the channel formation region of the second transistor, the channel formation region of the third transistor, the channel formation region of the fourth transistor, and an opening. The fifth wiring has a region that overlaps with the opening, The region overlapping the opening of the fifth wiring has one end and multiple ends in the wiring width direction of the fifth wiring. The opening has a shape that extends in the row direction, In a plan view, the second wiring has a first region that overlaps with a conductive layer that functions as the gate electrode of the second transistor. A display device wherein the length of the opening in the column direction is greater than the length of the first region in the column direction.
3. In claim 1 or 2, The semiconductor layer is a display device having silicon.