Method for manufacturing a semiconductor device and a semiconductor device.
The sintering process with controlled oxidizing gas introduction during heat treatment uniformizes etching characteristics, addressing gouging issues and ensuring reliable semiconductor devices with good step coverage and reduced stress on metal wiring.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- NISSHINBO MICRO DEVICES INC
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-10
AI Technical Summary
Conventional methods for wet etching of TEOS films in semiconductor devices result in gouging at the interface with the silicon substrate, leading to residual resist material and requiring additional dry etching, which can damage the substrate and complicate thickness control.
A sintering process involving an inert gas atmosphere with controlled introduction of oxidizing gas during heat treatment to uniformize the etching characteristics of CVD insulating films, followed by isotropic wet etching to create openings with continuous gradient sidewalls.
Eliminates gouging issues, eliminates the need for dry etching, and ensures good step coverage and reliability of wiring by maintaining uniform etching characteristics and reducing stress on metal wiring.
Smart Images
Figure 2026095079000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device having a process involving wet etching of an insulating film formed by CVD, and particularly to those having a good etching shape.
Background Art
[0002] As an insulating film used in a semiconductor device, there is a TEOS (tetra ethoxy silane) film. The TEOS film can be formed at a low temperature, and even when using a low-melting-point metal wiring such as aluminum, it does not cause damage due to heat and has excellent insulation properties because of its dense film quality. In addition, the TEOS film has good coverage on the structure and is uniformly formed on the wiring, so it improves the interlayer insulation performance. Furthermore, it can be easily formed by a general film-forming technique such as the plasma CVD method. As a method for forming an opening for contact of wiring or an electrode, since the side wall of the opening can be inclined, it is desirable to use isotropic wet etching.
[0003] FIG. 6 is a diagram showing a patterning process of an insulating film by wet etching. In this figure, 11 is a silicon substrate, 12 is an insulating film formed by using CVD such as a TEOS film, and 13 is a resist mask. First, a silicon substrate 11 is prepared (FIG. 6(a)), and an insulating film 12 is formed on the entire surface thereof (FIG. 6(b)). Next, a resist mask 13 is formed thereon by ordinary photolithography (FIG. 6(c)), and then the insulating film 12 is patterned by wet etching to form an opening 14 for exposing the silicon substrate 11 (FIG. 6(d)).
[0004] However, after patterning by wet etching, gouges 15 in the insulating film 12 sometimes occurred at the interface with the silicon substrate, as shown in Figure 7(a). In the space created by the gouges 15, a portion of the resist 16 remains as foreign matter 17 (Figure 7(c)) after subsequent processes (Figure 7(b)), which may affect even later processes. To prevent such problems, it is conceivable to perform dry etching after wet etching, as disclosed in the conventional example of Patent Document 1.
[0005] Figure 8 shows the process described in the conventional example of Patent Document 1. That is, the process is as follows: After forming a resist mask 13 on the insulating film 12 (Figure 8(a)), the insulating film 12 is removed to a predetermined depth by wet etching (Figure 8(b)), and the remaining insulating film 12 is removed by dry etching to expose the surface of the silicon substrate 11 (Figure 8(c)). With this process, the insulating film 12 near the interface with the silicon substrate 11 is removed by anisotropic dry etching, so no gouging occurs. [Prior art documents] [Patent Documents]
[0006] [Patent Document 1] Japanese Patent Publication No. 2004-266082 [Overview of the project] [Problems that the invention aims to solve]
[0007] In the conventional method described in Patent Document 1, a damaged layer is formed on the silicon substrate surface by dry etching, requiring a repair process. Furthermore, since the insulating film is opened by dry etching, if the thickness of the insulating film remaining after wet etching varies each time, problems may arise such as being unable to open the insulating film or, conversely, excessive damage to the silicon substrate surface. Therefore, controlling the thickness of the insulating film remaining after wet etching becomes important, but this process can easily become complicated.
[0008] Therefore, the invention described in Patent Document 1 involves stacking multiple insulating films with different etching rates, and after wet etching, creating stepped differences in the opening sidewalls by making the opening areas of each insulating film different, thereby improving the step coverage of the wiring formed later. However, this invention involves forming multiple insulating films, which unnecessarily increases the amount of work required.
[0009] The inventors diligently investigated the cause of gouging in insulating films after wet etching and found that gouging is particularly likely to occur in insulating films formed by CVD (hereinafter referred to as CVD insulating films). From this, they discovered that oxidizing gases cause the etching characteristics of CVD insulating films to be non-uniform, and that these oxidizing gases are incorporated into the CVD insulating film during the sintering process (so-called heat treatment) necessary to give the CVD insulating film a dense composition. The inventors then found that if the amount of oxidizing gas incorporated into the CVD insulating film during the sintering process is made uniform, the etching characteristics of the CVD insulating film can be made uniform, and gouging can be eliminated, thus completing the present invention. [Means for solving the problem]
[0010] Based on the spirit of the above invention, one embodiment of a method for manufacturing a semiconductor device includes a step of opening a CVD insulating film by wet etching to expose a semiconductor substrate, and after forming the CVD insulating film, a sintering step of heat-treating the CVD insulating film in an inert gas atmosphere consisting of a first gas, the sintering step comprising a first step of heating to a first temperature, a second step of raising the temperature from the first temperature to a second temperature, and a third step of heating at the second temperature, wherein the first step involves adding an oxidizing second gas for a predetermined time. The first gas may be nitrogen and the second gas may be oxygen.
[0011] Furthermore, in another embodiment of the semiconductor device manufacturing method, the oxidizing gas added in the first step is used to oxidize the surface of the semiconductor substrate beneath the CVD insulating film to form a thermal oxide film, and then wet etching of the CVD insulating film is performed to open up the thermal oxide film as well, so that the side walls of the openings in the CVD insulating film and the side walls of the openings in the thermal oxide film have different inclination angles.
[0012] Furthermore, in one embodiment relating to a semiconductor device, the sidewalls of the openings in the CVD insulating film formed on the semiconductor substrate have a continuous gradient over the entire range of the film thickness.
[0013] Furthermore, another embodiment of the semiconductor device further includes a thermal oxide film between the CVD insulating film and the semiconductor substrate, wherein the CVD insulating film and the thermal oxide film have different inclination angles at the side walls of the opening. [Effects of the Invention]
[0014] According to one aspect of the present invention, by adding a step of introducing an oxidizing gas to the sintering process, a method for manufacturing a semiconductor device that does not require dry etching or other additional steps can be provided. Furthermore, according to another aspect of the present invention, a semiconductor device with good step coverage of wiring and electrodes can be provided. [Brief explanation of the drawing]
[0015] [Figure 1] This diagram shows the manufacturing process of a semiconductor device according to the first embodiment. [Figure 2] This figure shows the heating profile in the sintering process according to the present invention. [Figure 3] This figure shows metal wiring formed on an insulating film with an opening formed in the manufacturing process of a semiconductor device according to the first embodiment. [Figure 4] This figure shows the manufacturing process of a semiconductor device according to the second embodiment. [Figure 5] This figure shows metal wiring formed on an insulating film with an opening formed in the manufacturing process of a semiconductor device according to the second embodiment. [Figure 6] It is a diagram showing the manufacturing process of a conventional semiconductor device. [Figure 7] It is a diagram showing peeling of a CVD insulating film generated in the manufacturing process of a conventional semiconductor device. [Figure 8] It is a diagram showing the manufacturing process of a semiconductor device shown in the conventional example of Patent Document 1.
Embodiments for Carrying Out the Invention
[0016] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 5. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals and described.
[0017] (First Embodiment) <Regarding the manufacturing process of a semiconductor device> FIG. 1 is a diagram showing the manufacturing process of a semiconductor device according to the first embodiment of the present invention. The process will be described along with this figure. First, an insulating film 2 is formed on a silicon substrate 1 by CVD (FIG. 1(a)). The CVD may be plasma CVD or LP-CVD (low-pressure chemical vapor deposition). The insulating film 2 is a silicon oxide film formed by CVD using TEOS gas as a reaction gas. Immediately after film formation, the grain size and density are non-uniform, so sintering is required to obtain a uniform composition.
[0018] However, in the conventional sintering process using a horizontal diffusion furnace, incomplete introduction of oxygen into the insulating film 2 occurs due to entrainment of air when the wafer is introduced into the diffusion furnace. As a result, since oxygen is only taken into the vicinity of the surface of the insulating film 2, the oxygen concentration taken in near the surface of the insulating film and near the silicon substrate at a position deeper than this is different, and the etching characteristics above and below the insulating film after sintering also differ. This is the cause of peeling, and this cause is eliminated by the sintering process of the present invention shown in FIG. 1(b).
[0019] Figure 1(b) schematically shows the sintering process of the present invention, and the temperature profile in the actual sintering process is as shown in Figure 2. In Figure 2, the vertical axis represents temperature, the horizontal axis represents time, the thin line represents the temperature change of nitrogen as an inert gas, and the thick line represents the temperature change of oxygen added as an oxidizing gas. That is, the temperature profile of the sintering process includes at least a first step of heating at a first temperature of 900°C, a second step of raising the temperature from 900°C to a second temperature of 1100°C, and a third step of maintaining and heating at 1100°C, as shown by the thin line in Figure 2. After the third step, a fourth step of lowering the temperature from 1100°C to the first temperature of 900°C and a fifth step of maintaining and continuing heating at 900°C are performed, and then the silicon substrate 1 is taken out of the furnace.
[0020] Generally, the sintering process has only the temperature profile of this thin line, but in this embodiment, the thick line part is added. As shown by the short thick line drawn during the first step of heating at a constant temperature of 900°C, oxygen is added into the furnace for a short time. By adjusting the amount and time of adding this oxygen, oxygen can be incorporated into the insulating film 2. This is because the first step of the sintering process is before the temperature rise, and the composition of the insulating film is still rough, and oxygen can spread through the voids.
[0021] As shown in Figure 2, in the first step, after the silicon substrate 1 is put into the furnace, nitrogen is flowed at a predetermined flow rate for a while. Then oxygen is added. After a certain period of time, the addition of oxygen is stopped, and nitrogen is continuously flowed to replace the atmosphere in the furnace with nitrogen. Then, the second to fifth steps are performed in a nitrogen atmosphere. In this way, the insulating film 2 that has undergone the sintering process in Figure 1(b) changes to a dense composition, and the etching characteristics become uniform over the entire range of the film thickness.
[0022] Next, as shown in Figure 1(c), a resist mask 3 is formed on the insulating film 2 using a conventional photolithograph. Then, the silicon substrate 1 is exposed to a hydrofluoric acid-based etchant to perform wet etching, forming an opening in the insulating film 2 as shown in Figure 1(d). During this process, the etching proceeds isotropically, and the side walls 4 of the openings have a continuous gradient across the entire film thickness.
[0023] <About semiconductor devices> Figure 3 shows the formation of metal wiring 5 on the insulating film 2, which has an opening formed in the manufacturing process of the semiconductor device according to the first embodiment described above. As described above, the side walls 4 of the opening have a continuous slope over the entire thickness of the film. This opening formed by wet etching alone can alleviate stress on the wiring, and even if the metal wiring 5 is, for example, aluminum wiring which is relatively prone to step breakage, step coverage is good. As a result, a semiconductor device equipped with an insulating film 2 having such an opening is highly reliable.
[0024] (Second Embodiment) <Regarding the manufacturing process of semiconductor devices> Figure 4 shows the manufacturing process of a semiconductor device according to the second embodiment of the present invention. The process will be explained in accordance with this figure. First, the insulating film 2 is deposited on the silicon substrate 1 by CVD, which is the same as in the first embodiment (Figure 4(a)). Next, the process moves to the sintering process shown in Figure 4(b), and the temperature profile at this time is the same as that of Figure 2, which was explained earlier. However, the difference in this process from the first embodiment is the amount of oxygen added. That is, by increasing the amount of oxygen added, the surface of the silicon substrate 1 is oxidized and a thin thermal oxide film 6 is formed.
[0025] Subsequently, a resist mask 3 is formed on the insulating film 2 using a conventional photolithograph (Figure 4(c)), and then the silicon substrate 1 is exposed to a hydrofluoric acid-based etchant to perform wet etching, forming openings in the insulating film 2 as shown in Figure 4(d). Because the etching proceeds isotropically, the side walls 4 of the openings in the insulating film 2 have a continuous gradient across the entire thickness, and the side walls 7 of the openings in the thermal oxide film 6 also have a continuous gradient across the entire thickness.
[0026] In other words, in the second embodiment, the opening sidewall has two different inclination angles. Since the insulating film 2 is a TEOS film and the thermal oxide film 6 is a thermal oxide film, their reactivity to hydrofluoric acid-based etchants is different. In this case, the thermal oxide film has a slower etching rate than the TEOS film, so the inclination of the opening sidewall formed by sidewall 7 is gentler than that of sidewall 4. Therefore, the opening sidewall as a whole is gentler than in the case of embodiment 1.
[0027] <About semiconductor devices> Figure 5 shows the formation of metal wiring 5 on the insulating film 2, which has an opening formed in the manufacturing process of the semiconductor device according to the second embodiment described above. As described above, both the side walls 4 and 7 of the opening have a continuous slope across the entire thickness of the film, resulting in a gentler overall slope. This opening formed by wet etching alone reduces the stress on the wiring, and even if the metal wiring 5 is, for example, aluminum wiring which is relatively prone to step breakage, step coverage is good. As a result, a semiconductor device equipped with an insulating film 2 having such an opening is highly reliable.
[0028] While embodiments of the present invention have been described above, various modifications are possible based on the spirit of the invention. For example, in the above embodiments, nitrogen was used as the inert gas, but other inert gases such as helium, neon, or argon may also be used, and oxygen was used as the oxidizing gas, but other oxidizing gases such as water vapor may also be used.
[0029] Furthermore, although a TEOS film was exemplified as the CVD insulating film in the above embodiment, a PSG film containing phosphorus as an impurity or a BSG film containing boron may also be used. In addition, a porous insulating film formed by atmospheric pressure CVD, LPCVD, or plasma CVD may also be used. [Explanation of symbols]
[0030] 1.11 Silicon substrate 2, 12 insulating film 3.13 Resist Mask 14 Aperture 15. Gouge 16 Resist 17 Foreign object 4, 7 side wall 5 Metal wiring 6. Thermal oxide film
Claims
1. A method for manufacturing a semiconductor device, comprising a step of opening a CVD insulating film by wet etching to expose a semiconductor substrate, The process includes a sintering step in which the CVD insulating film is formed and then heat-treated in an inert gas atmosphere consisting of a first gas. The sintering process includes a first step of heating at a first temperature, A second step of raising the temperature from the first temperature to the second temperature, The process comprises a third step of heating at the second temperature, The first step is characterized by adding an oxidizing gas consisting of a second gas for a predetermined time, in a method for manufacturing a semiconductor device.
2. A method for manufacturing a semiconductor device according to claim 1, characterized in that the first gas is nitrogen and the second gas is oxygen.
3. The oxidizing gas added in the first step oxidizes the surface of the semiconductor substrate to form a thermal oxide film. The aforementioned wet etching also opens up the thermal oxide film, A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the inclination angle of the side wall of the opening is different for the CVD insulating film and the thermal oxide film.
4. A semiconductor device comprising a CVD insulating film having an aperture formed on a semiconductor substrate, A semiconductor device characterized in that the side wall of the opening has a continuous slope over the entire range of the film thickness of the CVD insulating film.
5. A thermal oxide film is further provided between the semiconductor substrate and the CVD insulating film, The semiconductor device according to claim 4, characterized in that the CVD insulating film and the thermal oxide film have different inclination angles at the side wall of the opening.