Optical phased array element and method for manufacturing the same

Abstract

This invention provides an optical phased array element that enables narrowing of the waveguide pitch while controlling the phase using high-EO-effect materials that are difficult to microfabricate. [Solution] The optical phased array element 1 comprises a first substrate 10 having a drive circuit on one side, a cladding layer 20 disposed on one side of the first substrate 10, a waveguide 30 disposed within the cladding layer 20 and having an optical branching section 32 for branching incident light L1, a phase control section 34 for phase-controlling the branched light, and an optical emission section 36 for outputting phase-controlled light, an electro-optical layer 50 disposed within the cladding layer 20 and in contact with the side of the waveguide of the phase control section 34 opposite to the first substrate 10, and formed of a material having an electro-optical effect, and a pair of application electrodes 60 disposed between the electro-optical layer 50 in the cladding layer 20 and the first substrate 10 so as to sandwich each of the waveguides of the phase control section 34, the application electrodes 60 being connected to the drive circuit by wiring disposed within the cladding layer 20.

Description

Technical Field

[0001] The present invention relates to an optical phased array element and a method for manufacturing the same.

Background Art

[0002] Lithium niobate (LiNbO3, hereinafter sometimes referred to as "LN") has optical transmission characteristics in a wide wavelength range and has a high electro-optic effect (hereinafter sometimes referred to as "EO effect", and "electro-optic" sometimes referred to as "EO"). Because the phase of light traveling in the waveguide can be controlled by this high EO effect, the application of LN to ring resonators and optical phased arrays has been studied. However, since LN is chemically very stable, it is difficult to microfabricate it into a desired shape using a dry etching method or the like. In Non-Patent Document 1, it has been reported that this difficulty was avoided and a ring resonator was fabricated by directly laminating a Si3N4 film on an LN layer and processing only the Si3N4 by photolithography to form a waveguide. Further, in Non-Patent Document 2, an optical phased array having a phase control section using the technique of Non-Patent Document 1 has been reported.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Non-Patent Document 2

[0004] An optical phased array is an element that controls the direction of light emitted from an optical emission section by splitting the incident waveguide into multiple waveguides using a splitter, controlling the phase with a phase control unit, and controlling the direction of light emitted from the optical emission section. Multiple waveguides are arranged in the optical emission section, and the deflection angle of the emitted light can be increased by narrowing the waveguide pitch. The deflection angle is the angle corresponding to the change in the direction of the emitted light. However, when waveguides are formed on an LN layer, crosstalk occurs as the distance between waveguides decreases because LN has a weak light confinement effect, making it impossible to narrow the waveguide pitch. For this reason, in Non-Patent Literature 2, an optical emission section is fabricated on a separate substrate from the phase control unit, using waveguides made of a material with a high light confinement effect that allows for narrow pitch and a cladding layer. The substrate of the phase control unit and the substrate of the optical emission section are then attached to a common base substrate and the waveguides are connected. In this case, waveguide misalignment leads to optical loss, requiring high alignment accuracy, which presents difficulties separate from the microfabrication of LN.

[0005] This invention was made to solve the aforementioned problems, and aims to provide an optical phased array element that can narrow the waveguide pitch while controlling the phase using high EO-effect materials that are difficult to microfabricate. [Means for solving the problem]

[0006] To solve these problems, the optical phased array element according to the present invention comprises a first substrate having a drive circuit on one side, a cladding layer disposed on one side of the first substrate, a waveguide disposed within the cladding layer and having an optical branching section for branching incident light, a phase control section for phase-controlling the branched light, and an optical emission section for outputting phase-controlled light, an electro-optical layer disposed within the cladding layer and in contact with the side of the waveguide of the phase control section opposite to the first substrate, and formed of a material having an electro-optical effect, and a pair of application electrodes disposed between the electro-optical layer within the cladding layer and the first substrate so as to sandwich each of the waveguides of the phase control section, wherein the application electrodes are connected to the drive circuit by wiring disposed within the cladding layer.

[0007] Furthermore, the method for manufacturing an optical phased array element according to the present invention includes: a first substrate formation step of forming a first substrate having a drive circuit on one side; a first cladding layer formation step of forming a first cladding layer on one side of the first substrate; a wiring formation step of forming wiring having one end connected to the drive circuit and penetrating the first cladding layer in the thickness direction of the first substrate; a waveguide formation step of forming a waveguide on the first cladding layer having an optical branching section for branching incident light, a phase control section for phase-controlling the branched light, and an optical emission section for outputting phase-controlled light; an application electrode formation step of forming a pair of application electrodes on the first cladding layer so as to sandwich each of the waveguides of the phase control section; and a method for manufacturing an optical phased array element continuous with the first cladding layer, The process includes: a second cladding layer formation step in which the surface of the waveguide opposite to the first substrate is exposed and a second cladding layer is formed on the same plane as the exposed surface of the waveguide; an electro-optic substrate preparation step in which an electro-optic substrate is prepared having an outermost electro-optic layer of a size corresponding to the phase control unit and made of a material having an electro-optic effect, and a third cladding layer in contact with the electro-optic layer; a bonding step in which the electro-optic substrate is bonded with the exposed surface of the waveguide of the phase control unit facing the electro-optic layer; and a fourth cladding layer formation step in which a fourth cladding layer is formed to cover the waveguide, continuous with the second cladding layer and the third cladding layer, wherein in the applied electrode formation step, the other end of the wiring is connected to the applied electrode. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide an optical phased array element that can narrow the waveguide pitch while controlling the phase using high EO effect materials that are difficult to microfabricate. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a plan view illustrating the schematic of an optical phased array element according to the embodiment. [Figure 1B] This is a side view illustrating the schematic of an optical phased array element according to the embodiment. [Figure 2A] Figure 1A is a cross-sectional view along the IIA-IIA line. [Figure 2B] Figure 1A is a cross-sectional view along the IIB-IIB line. [Figure 3A] This is a plan view illustrating the optical phased array element according to the embodiment, with some components omitted from the description. [Figure 3B] This is a plan view illustrating a portion of Figure 3A in an enlarged view. [Figure 4] This is a plan view illustrating the schematic of the first substrate. [Figure 5A] This is a side view illustrating the schematic of a modified optical phased array element. [Figure 5B] This is a perspective view illustrating the general structure of an electro-optical substrate. [Figure 5C] This is a cross-sectional view illustrating the schematic of a modified optical phased array element. [Figure 6] This is a flowchart illustrating a method for manufacturing an optically phased array element according to the embodiment. [Figure 7A] This is a cross-sectional view illustrating a first substrate on which a drive circuit is formed, in a method for manufacturing an optically phased array element according to an embodiment. [Figure 7B] This is a cross-sectional view illustrating a state in which a portion of the first cladding layer has been formed in a method for manufacturing an optically phased array element according to the embodiment. [Figure 7C] This is a cross-sectional view illustrating a state in which the formed first cladding layer has been planarized in a method for manufacturing an optically phased array element according to the embodiment. [Figure 7D] This is a cross-sectional view illustrating a state in which the remainder of the first cladding layer has been formed in a method for manufacturing an optically phased array element according to the embodiment. [Figure 7E] This is a cross-sectional view illustrating a state in which through holes are formed in the first cladding layer in a method for manufacturing an optical phased array element according to the embodiment. [Figure 7F] This is a cross-sectional view illustrating a state in which wiring has been formed in a method for manufacturing an optically phased array element according to the embodiment. [Figure 7G]In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which a layer serving as a waveguide is formed. [Figure 7H] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which a pattern of the waveguide is formed. [Figure 7I] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which an applied electrode is formed. [Figure 7J] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which an intermediate body of the second cladding layer is formed. [Figure 7K] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which a surface of the waveguide is exposed from the second cladding layer. [Figure 7L] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which an electro-optic substrate is bonded. [Figure 7M] In the method for manufacturing an optical phased array element according to the embodiment, it is a cross-sectional view illustrating a state in which a fourth cladding layer is formed. [Figure 8A] It is a side view that enlarges a part of FIG. 1B and illustrates the outline while omitting the description of some members. [Figure 8B] It is a side view that illustrates the outline of a modification example of the light emitting portion. [Embodiments for Carrying Out the Invention]

[0010] Embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiments and modification examples, and various design changes based on the description of the claims are possible. In the drawings, when some members are omitted, the sizes, shapes, and positional relationships of the members may be exaggerated. Expressions of directions including up, down, left, right, etc. are examples of relative positional relationships and do not limit the directions during use and manufacturing.

[0011] [Optical Phased Array Element] An optical phased array element 1 according to an embodiment will be described with reference to Figures 1A to 4. As illustrated in Figure 1A, the optical phased array element 1 is an element that controls the direction (deflection angle θ) of the emitted light L2 by splitting the incident light L1 and controlling its phase. The optical phased array element 1 comprises a first substrate 10, a cladding layer 20, a waveguide 30, an electro-optical layer 50, and an application electrode 60. The application electrode 60 is connected to the drive circuit 15 of the first substrate 10 by wiring 65. The various components of the optical phased array element 1 will be described below.

[0012] (first board) The first substrate 10 is a substrate having a drive circuit 15. As illustrated in Figure 1B, the first substrate 10 has a drive circuit 15 on one of its surfaces 10A. Here, the first substrate 10 is a silicon (Si) substrate, and the drive circuit 15 is formed on one of its surfaces 10A by known CMOS (complementary metal-oxide-semiconductor) manufacturing techniques.

[0013] (Cladding layer) The cladding layer 20 is a layer that confines light to the inside of the waveguide 30 (inside the waveguide 30) due to the difference in refractive index between it and the waveguide 30. The cladding layer 20 is placed on one surface 10A of the first substrate 10. The cladding layer 20 is formed from a material with a lower refractive index than the waveguide 30, and by surrounding the waveguide 30, light can be confined. Here, the material of the cladding layer 20 is silicon dioxide (SiO₂). X ) and its main component is SiO2 (X=2).

[0014] (Waveguide) Waveguide 30 is a component that serves as a path for light. As illustrated in Figures 2A and 2B, waveguide 30 is placed within the cladding layer 20. Waveguide 30 has a linear, curved, or a combination thereof shape. Waveguide 30 is, as a whole, an optical transmission path that takes incident light L1 as input and output light L2 as output. Waveguide 30 is continuous without seams from the input side to the output side. Waveguide 30 can have a width of, for example, 1 μm to 10 μm and a thickness of, for example, 0.1 μm to 2 μm, and is set according to the wavelength band of the light.

[0015] The material of the waveguide 30 can be selected according to the wavelength of light. For example, a silicon waveguide transmits infrared light but not visible light. Silicon nitride has a broad transmission band that transmits both infrared and visible light. Also, in order to enhance the light confinement effect, a high refractive index is preferable in relation to the cladding layer 20. Here, the material of the waveguide 30 is silicon nitride (SiN X ) and its main component is Si3N4 (X=1.33). As illustrated in Figure 3A, the waveguide 30 includes an optical branching section 32 that branches the incident light L1, a phase control section 34 that phase-controls the branched light, and an optical emission section 36 that outputs the phase-controlled light. Note that Figure 3A is a plan view in which the cladding layer 20 is omitted in order to explain the waveguide 30 and the applied electrode 60.

[0016] (Optical branching section) The optical splitter 32 is a section that splits the light into multiple waveguides. The optical splitter 32 takes the incident light L1 as input and outputs the split light to the phase control unit 34. In this case, the optical splitter 32 uses a multi-stage connection of 1-input, 2-output multimode interference (MMI) type splitters 31 to split the incident light L1 from one waveguide into eight waveguides of equal intensity.

[0017] (Phase control unit) The phase control unit 34 is the section that controls the phase of the light. The phase control unit 34 takes the light branched in the light branching unit 32 as input and outputs the phase-modulated light to the light output unit 36. Here, the light input through eight waveguides is output through the same eight waveguides. In the phase control unit 34, the waveguide pitch is wide, and the application electrodes 60 are placed between the waveguides. The phase control unit 34 can independently modulate the phase of light from multiple waveguides. For example, by controlling the phase of the waveguide on the left in the direction of light propagation in a plan view to lag behind, the emitted light L2 can be deflected to the left.

[0018] (Light emission section) The light emission section 36 is a section where the waveguide pitch is adjusted to be narrower and light is emitted. The waveguide pitch is the distance between the centers of adjacent waveguides. The light emission section 36 receives light from the phase control section 34 as input and outputs emitted light L2 to the outside. Here, the light input through the eight waveguides is output from the output terminal 37, where the same eight waveguides are densely packed. At the output terminal 37, the waveguides are parallel to each other and arranged at equal intervals. The waveguides are separated by a cladding layer 20. The waveguide pitch may be wide at the input side, i.e., where the phase control unit 34 inputs. Widening the waveguide pitch can reduce crosstalk between adjacent waveguides. On the other hand, to increase the deflection angle, it is preferable to have a narrow pitch at the output terminal 37. The waveguide pitch at the output terminal 37 can be, for example, 1 μm to 8 μm, and here it is 4 μm.

[0019] (Electro-optical layer) The electro-optic layer 50 is a layer that produces an electro-optic effect in which the refractive index changes due to an electric field. As illustrated in Figure 2A, the electro-optic layer 50 is located within the cladding layer 20 and is in contact with the surface 30A of the waveguide of the phase control unit 34 that is opposite to the first substrate 10. That is, the electro-optic layer 50 is in contact with the upper surface of the waveguide 30 in the figure and is located within the cladding layer 20 together with the waveguide 30. Since there is no cladding layer between the electro-optic layer 50 and the waveguide of the phase control unit 34, light also spreads towards the electro-optic layer 50. Furthermore, the amount of spreading towards the electro-optic layer 50 can be changed by adjusting the width and thickness of the waveguide of the phase control unit 34. In addition, the refractive index of the electro-optic layer 50 changes due to the electric field applied by the applied electrode 60, thereby modulating the phase of the light.

[0020] The electro-optic layer 50 is arranged with a uniform thickness in the region covering the waveguide of the phase control unit 34 in a plan view. The thickness of the electro-optic layer 50 can be, for example, 0.1 μm to 2 μm, and in this case it is 0.4 μm. The electro-optic layer 50 is formed of a material that exhibits an electro-optic effect (EO effect). The material of the electro-optic layer 50 can be a known material, and lithium niobate (LiNbO3), which is known to have a high EO effect, is preferred. As illustrated in Figure 2B, the electro-optic layer 50 is not provided in the waveguide of the light emission section 36. By not providing the electro-optic layer 50 in the region of the light emission section 36, the waveguide pitch can be narrowed in the light emission section 36.

[0021] (applying electrode) The application electrodes 60 are electrodes that apply an electric field to the electro-optic layer 50. As illustrated in Figure 2A, the application electrodes 60 are arranged in pairs between the electro-optic layer 50 in the cladding layer 20 and the first substrate 10, with each of the waveguides of the phase control unit 34 in between. The application electrodes 60 are connected to the drive circuit 15 of the first substrate 10 by wiring 65. As illustrated in Figure 3B, the pair of applied electrodes 60 62 here consists of a reference electrode 60G that serves as the reference potential and a signal electrode 60S whose potential changes relative to the reference potential. The waveguide of the phase control unit 34 is linear, and along its extension direction, one pair of applied electrodes 60 are arranged on each side of the waveguide. Note that the symbols for the AC power supply and reference potential in Figure 3B schematically represent the signal electrode 60S or the reference electrode 60G. The material of the applied electrode 60 can be, for example, elemental metals such as Au, Ag, Cu, Al, Ti, and Cr, alloys such as Al alloys and Cu alloys, ZnO, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0022] (Drive circuit) The drive circuit 15 is a circuit that generates a signal to control the phase of the light. As illustrated in Figure 4, the drive circuit 15 is located on one side 10A of the first substrate 10. Here, the drive circuit 15 is a CMOS integrated circuit and can generate high-frequency control signals. The high-frequency control signals enable high-speed switching of the deflection of the emitted light L2. The drawing illustrates the region in which the drive circuit 15 is formed. The size of the drive circuit 15 relative to the surface 10A of the first substrate 10 is not particularly limited and can be adjusted as needed. Power supply terminals for supplying power to the drive circuit 15 from an external source, and setting terminals for externally setting how the phase of light is controlled, are omitted from the drawing. Power supply terminals and setting terminals can be placed, for example, in a portion of the surface 10A of the first substrate 10 that is not covered by the cladding layer 20 in a plan view.

[0023] The drive circuit 15 outputs the generated signal from the electrode 18. The electrode 18 is the output terminal of the drive circuit 15. Here, each electrode 18 corresponds to one applied electrode 60 and is positioned to overlap with the corresponding applied electrode 60 in a plan view. The electrode 18 has an electrode corresponding to the reference electrode 60G and an electrode corresponding to the signal electrode 60S, and these are arranged alternately. The electrode 18 is formed as part of the drive circuit 15 and is positioned in close proximity to the circuit elements of the drive circuit 15. The electrode 18 may be positioned at a distance from the circuit elements of the drive circuit 15, but it is preferable that it be positioned in close proximity to the circuit elements in order to suppress the effects of noise and the like.

[0024] Electrode 18 is connected to the application electrode 60 by wiring 65 provided within the cladding layer 20. The wiring 65 is a component that connects the electrode 18 of the drive circuit 15 to the application electrode 60. As illustrated in Figure 2A, the wiring 65 is provided in the thickness direction of the first substrate 10 from the electrode 18 of the drive circuit 15. That is, the wiring 65 extends from the electrode 18 in a direction perpendicular to the surface 10A of the first substrate 10, and the application electrode 60 corresponding to the end of the extension is located there. In this way, the phase control unit 34 and the applied electrode 60 are positioned in a location that overlaps with the drive circuit 15 on the first substrate 10 in a plan view, and the electrodes 18 of the drive circuit 15 and the applied electrode 60 are connected by wiring 65 perpendicular to the first substrate 10, thereby minimizing the wiring length.

[0025] Furthermore, the shape of the wiring 65 is wider in the direction perpendicular to Figure 2A, as exemplified in Figure 1B, than in the width exemplified in Figure 2A, thus achieving both dense arrangement and low resistance. The materials for the electrodes 18 and wiring 65 can be, for example, elemental metals such as Au, Ag, Cu, Al, Ti, and Cr, or alloys such as Al alloys and Cu alloys.

[0026] In the optical phased array element 1 having the above configuration, a cladding layer 20 is placed on the surface 10A of the first substrate 10 having the drive circuit 15, and a waveguide 30 is placed within the cladding layer 20, thereby allowing the drive circuit 15 and the waveguide 30 to be arranged to overlap, and thus enabling miniaturization of the element. The optical phased array element 1 eliminates the need for microfabrication of the EO layer 50 by placing the EO layer 50 on the waveguide 30 in contact with the waveguide 30. Furthermore, by selectively placing the EO layer 50 in the region of the phase control unit 34, crosstalk due to the spreading of light in the light emission unit 36 ​​is reduced. As a result, the optical phased array element 1 can achieve a narrower waveguide pitch while controlling the phase with a high EO effect material that is difficult to microfabricate.

[0027] Non-patent document 2 describes forming waveguides on an LN substrate. In this case, since the LN substrate is made of an x-cut type, two application electrodes are required for each waveguide, i.e., a pair. If the wiring for supplying signals to the application electrodes is provided from the side of the waveguide, the wiring becomes complicated. Note that LN substrates are classified as x-cut and z-cut depending on the direction of their crystal axis. The optical phased array element 1 has a Si3N4 waveguide positioned on a silicon substrate made using CMOS technology, overlapping with the drive circuit, and a LiNbO3 layer in contact with the waveguide that serves as the phase control unit. This allows LiNbO3 to be used for phase control without microfabrication, and it has a seamless Si3N4 waveguide structure and incorporates the drive circuit. In this way, by combining a waveguide with high transmission characteristics for visible light and a material with high electro-optical effect, an optical phased array element for visible light and low voltage drive can be created.

[0028] (modified version) Next, a modified example of the optical phased array element will be described with reference to Figures 5A to 5C. As illustrated in Figure 5A, the modified optical phased array element 2 further comprises a second substrate 70 disposed on a cladding layer 20 covering the electro-optic layer 50, which has the same shape and size as the electro-optic layer 50 in a plan view. A silicon oxide layer 25 may be provided on the second substrate 70. Except for the presence of the second substrate 70 and the silicon oxide layer 25, it is common to the optical phased array element 1 according to the embodiment.

[0029] The second substrate 70 is the substrate on which the electro-optic layer 50 was fixed. As described in the manufacturing method, the electro-optic layer 50 may be a separately formed layer. As illustrated in Figure 5B, as the separately formed electro-optic layer 50, for example, an electro-optic substrate 80 can be used which has the electro-optic layer 50 as the outermost layer and a third cladding layer 23 in contact with the electro-optic layer 50. The electro-optic substrate 80 is a substrate on which the electro-optic layer 50 is formed on the second substrate 70 via the third cladding layer 23. As illustrated in Figures 5A and 5C, the cladding layer of the electro-optic substrate 80 is part of a continuous cladding layer 20 in the optical phased array element 2.

[0030] The second substrate 70 in the optical phased array element 2 originates from this electro-optic substrate 80. The silicon oxide layer 25 may also be present depending on the manufacturing method. Note that the second substrate 70 and the silicon oxide layer 25 can be removed. The height of the cladding layer 20 relative to the surface 10A of the first substrate 10 is not particularly limited in relation to the second substrate 70. The cladding layer 20 may expose part or all of the second substrate 70, or it may cover the entire second substrate 70.

[0031] [Manufacturing method for optically phased array elements] Next, the manufacturing method of the optical phased array element will be described with reference to Figures 6 to 7M. ​​As illustrated in Figure 6, the manufacturing method S1 of the optical phased array element includes a first substrate formation step S10, a first cladding layer formation step S20, a wiring formation step S30, a waveguide formation step S40, an application electrode formation step S50, a second cladding layer formation step S60, an electro-optical substrate preparation step S70, a bonding step S80, and a fourth cladding layer formation step S90. In the application electrode formation step S50, the wiring 65 is connected to the application electrode 60. The various components of the manufacturing method S1 will be described below.

[0032] (First substrate formation process) The first substrate formation step S10 is a step of forming a first substrate 10 having a drive circuit 15 on one side 10A. The drive circuit 15 may be formed on the first substrate 10, a part of it may be formed on the first substrate 10 and the rest may be separately created and attached, or a semiconductor chip with the entire drive circuit 15 formed on it may be attached to the first substrate 10. As illustrated in Figure 7A, in this case, a drive circuit 15 having electrodes 18 is formed on one side 10A of the first substrate 10, and the first substrate 10 is a semiconductor chip made by fractionating a silicon wafer on which the drive circuit 15 has been formed using CMOS manufacturing technology. The material of electrode 18 can be, for example, elemental metals such as Au, Ag, Cu, Al, Ti, and Cr, or alloys such as Al alloys and Cu alloys. Note that in the cross-sectional view, the drive circuit 15 is omitted from the description, and only the electrode 18, which is part of the drive circuit 15, is shown. Also, Figures 7A to 7M illustrate side by side the cross-section at the position of line VII-1 in Figure 1A and the cross-section at the position of line VII-2.

[0033] (First cladding layer formation process) The first cladding layer formation step S20 is a step of forming a first cladding layer 21 on one surface 10A of the first substrate 10. Here, the first cladding layer 21 is a silicon oxide layer and can be formed by known methods such as sputtering. The second to fourth cladding layers are formed in the same manner. The formation of the first cladding layer 21 can be carried out in three steps. First, as illustrated in Figure 7B, an intermediate body 210 of the first cladding layer is formed on the surface 10A of the first substrate 10, to a thickness greater than that of the electrode 18. The upper surface of the intermediate body 210 has irregularities that reflect the electrode 18.

[0034] Next, as illustrated in Figure 7C, the upper surface of the intermediate 210 is flattened to form the intermediate 211 of the first cladding layer 21. Flattening can be performed, for example, by chemical mechanical polishing (CMP). Then, as illustrated in Figure 7D, a silicon oxide layer is further formed on the intermediate 211 to complete the first cladding layer 21. The silicon oxide film formed around the corners of the stepped portion of electrode 18 may have inferior quality in terms of uniformity, etc. By planarizing the cladding layer, the effect of the stepped portion of electrode 18 can be suppressed. Note that the first cladding layer 21 may be planarized after it has been formed to the desired thickness, without performing planarization as an intermediate.

[0035] (Wiring formation process) The wiring formation process S30 is a process in which wiring 65 is formed, with one end 65A connected to the drive circuit 15, and which penetrates the first cladding layer 21 in the thickness direction of the first substrate 10. The wiring 65 can be formed by the damascene method. In the damascene method, a groove is formed first, and the wiring is formed by embedding it in the groove. First, as illustrated in Figure 7E, through holes are formed in the first cladding layer 21 at the positions of each electrode 18. These through holes in the first cladding layer 21 become bottomed holes 64 with the electrode 18 as the bottom surface. That is, the electrode 18 is exposed at the bottom surface of the bottomed hole 64. The bottomed holes 64 can be formed, for example, by etching.

[0036] The bottomed hole 64 is formed in the shape of the wiring 65. Here, the bottomed hole 64 is narrow in the direction in which the electrodes 18 are aligned and wider in the direction perpendicular to that direction. In addition, the inner wall of the bottomed hole 64 is formed to be perpendicular to the first substrate 10. Next, as illustrated in Figure 7F, wiring 65 is formed in the bottomed hole 64, for example, by a plating method. This connects one end 65A of the wiring 65 to the electrode 18. The material of the wiring 65 can be selected from the same material as that of the electrode 18. In Figure 7F, the wiring 65 is exposed on the upper surface of the first cladding layer 21. Then, for example, the entire upper surface of the first cladding layer 21 and the wiring 65 in Figure 7F is flattened using the CMP method. After flattening, the upper surface of the first cladding layer 21 forms the same plane as the upper surface of the wiring 65.

[0037] (Waveguide formation process) Waveguide formation step S40 is a step of forming a waveguide 30 on the first cladding layer 21, which has an optical branching section for branching incident light, a phase control section for controlling the phase of the branched light, and an optical emission section for outputting the phase-controlled light. Here, the waveguide 30 is a layer of silicon nitride. First, as illustrated in Figure 7G, a silicon nitride layer 300 is uniformly formed on the first cladding layer 21 and the wiring 65 using known methods such as sputtering or chemical vapor deposition (CVD).

[0038] Then, as illustrated in Figure 7H, the silicon nitride layer 300 is microfabricated, for example, by photolithography and dry etching, to form the waveguide pattern 30. The waveguide pattern 30 has an optical branching section 32, a phase control section 34, and an optical emission section 36, as illustrated in Figure 3A. The formation of the waveguide 30 includes the formation of the splitter 31 of the optical branching section 32.

[0039] (Applying electrode formation process) The application electrode formation step S50 is a step of forming a pair of application electrodes 60 on the first cladding layer 21 so as to sandwich each of the waveguides of the phase control unit 34. The application electrodes 60 can be formed by, for example, sputtering, photolithography, and dry etching. The material of the application electrodes 60 can be a metal similar to that of the electrodes 18 and wiring 65, as well as ZnO, ITO, IZO, etc. In the application electrode formation step S50, the other end 65B of the wiring 65 is connected to the application electrode 60. As a result, the application electrode 60 is connected to the electrode 18 by the wiring 65. Figure 7I illustrates the state in which the application electrode 60 has been formed. The application electrode 60 may be formed so that its height from the top surface of the first cladding layer 21 is the same as that of the waveguide 30.

[0040] (Second cladding layer formation process) The second cladding layer formation step S60 is a step in which the second cladding layer 22 is formed in a continuous manner with the first cladding layer 21, exposing the surface 30A of the waveguide 30 opposite to the first substrate 10, and forming a second cladding layer 22 that is in the same plane as the exposed surface 30A of the waveguide 30. The formation of the second cladding layer 22 can be carried out in two steps. First, as illustrated in Figure 7J, an intermediate body 220 of the second cladding layer 22, which is continuous with the first cladding layer 21, is formed, and the waveguide 30 and the applied electrode 60 are embedded in it. Here, using the upper surface of the first cladding layer 21 as a reference, the waveguide 30 is taller than the applied electrode 60, so the waveguide 30 and the applied electrode 60 can be embedded by forming the intermediate body 220 thicker than the waveguide 30.

[0041] Then, for example, the upper surface of the intermediate 220 is flattened by the CMP method to complete the second cladding layer 22. As illustrated in Figure 7K, the waveguide 30 and the second cladding layer 22 are at the same height from the upper surface of the first cladding layer 21. That is, the upper surface of the waveguide 30 is exposed from the second cladding layer 22, and the surfaces are flattened so that the upper surface of the waveguide 30 and the upper surface of the second cladding layer 22 form the same plane.

[0042] (Electro-optical substrate preparation process) The electro-optic substrate preparation step S70 is a step of preparing an electro-optic substrate 80 having an electro-optic layer 50 on its outermost surface. The electro-optic layer 50 is sized to correspond to the phase control unit 34 and is formed of a material that has an electro-optic effect. The electro-optic substrate 80 also has a third cladding layer 23 in contact with the electro-optic layer 50. As illustrated in Figure 5B, the electro-optic substrate 80 is a substrate in which the third cladding layer 23 is formed on a second substrate 70 which is a support substrate, and the electro-optic layer 50 is formed on the third cladding layer 23. The preparation of the electro-optic substrate 80 includes obtaining such a substrate and processing the obtained substrate to the size corresponding to the phase control unit 34. The electro-optic substrate 80 may be manufactured or obtained by purchase, etc. Here, we will describe the case where a commercially available substrate is used. For example, a thin-film LN substrate is commercially available in which a silicon oxide film is laid on a silicon substrate, and an LN thin film is laid on top of that. That is, a substrate can be obtained in which the second substrate 70 is a silicon substrate, the third cladding layer 23 is a silicon oxide layer, and the electro-optic layer 50 is an LN layer.

[0043] Next, the obtained substrate is processed by cutting or other means to match the size of the area of ​​the phase control unit 34. In this processing, the electro-optic substrate 80 is cut so that, in a plan view, it covers the area of ​​the phase control unit 34, particularly the area where the applied electrodes 60 are located, and does not overlap with the area where the waveguide 30 bends. For example, it can be cut to match the shape and size of the electro-optic layer 50 as illustrated in Figure 3A. The electro-optic substrate preparation process S70 can be performed before the bonding process S80 and can be carried out in parallel with processes S10 to S60.

[0044] (Joining process) The bonding step S80 is a step in which the electro-optic substrate 80 is bonded to the surface 30A of the waveguide of the phase control unit 34 and the electro-optic layer 50 by facing each other. In bonding step S80, the prepared electro-optic substrate 80 is bonded to the surface formed by the waveguide 30 and the second cladding layer 22, which were flattened in the second cladding layer formation step S60. As illustrated in Figure 7L, the electro-optic substrate 80 is bonded so that the electro-optic layer 50 faces the surface 30A where the waveguide is exposed. Furthermore, in a plan view, the electro-optic layer 50 is positioned and bonded so that it covers the area of ​​the phase control unit 34. This ensures that the electro-optic layer 50 is in contact with the waveguide of the phase control unit 34. The bonding can be performed, for example, by surface activation bonding, which involves cleaning the surfaces in a vacuum using an ion beam or the like before bonding.

[0045] (Fourth cladding layer formation process) The fourth cladding layer formation step S90 is a step of forming the fourth cladding layer 24 on the waveguides of the optical branching section 32 and the optical emission section 36. After the bonding step S80 is completed, the waveguides of the optical branching section 32 and the optical emission section 36 are exposed from the second cladding layer 22. The fourth cladding layer formation step S90 forms the fourth cladding layer 24 which is continuous with the second cladding layer 22, and provides a cladding layer on the exposed waveguides. The fourth cladding layer 24 is also formed to be continuous with the third cladding layer 23. The fourth cladding layer 24 covers the waveguide 30, continuous with the second cladding layer 22 and the third cladding layer 23. As illustrated in Figure 7M, a silicon oxide layer is formed on the entire upper surface of the waveguide 30 and the second cladding layer 22. As a result, a silicon oxide layer 25 is also formed on the second substrate 70. The first cladding layer 21 to the fourth cladding layer 24 form a continuous cladding layer 20. Note that in Figures 7J to 7M, boundary lines are drawn where the cladding layers 21 to the fourth cladding layer 24 meet, but these boundary lines are for illustrative purposes only.

[0046] The manufacturing method S1 for the optical phased array element, which includes the above configuration, eliminates the need for microfabrication of the EO layer by forming a second cladding layer that is coplanar with the exposed surface of the waveguide and joining the exposed surface of the cladding layer to the electro-optic layer of the electro-optic substrate. Furthermore, by processing the electro-optic layer to a size corresponding to the phase control section, in the optical branching and optical emission sections, light propagates through the silicon nitride waveguide, and in the phase control section, light also leaks and propagates through the EO layer along the silicon nitride waveguide, allowing for phase control of the light by the EO effect caused by the electric field from the applied electrode. Moreover, since the optical emission section consists only of the silicon nitride waveguide and the cladding layer, the optical confinement effect in this section of the waveguide is strong, reducing optical crosstalk, and allowing for a narrower pitch arrangement than waveguides fabricated by miniaturizing the EO layer. In addition, the manufacturing process can be simplified by using a commercially available thin-film LN substrate as the electro-optic substrate.

[0047] The manufacturing method S1 for the optical phased array element involves fabricating a silicon nitride waveguide on a silicon substrate made with CMOS technology, and bonding an EO layer from a separate substrate to the waveguide that will serve as the phase control unit. This allows for the use of EO material for phase control without microfabrication, and enables the manufacture of an optical phased array element with a seamless silicon nitride waveguide structure and an integrated drive circuit. Furthermore, the CMOS drive circuit can be integrated into the optical phased array element chip, eliminating the complexity of the wiring for the phase control unit.

[0048] By following the steps up to the fourth cladding layer formation step S90 of manufacturing method S1, a modified optical phased array element 2 can be manufactured. After the fourth cladding layer formation step S90, a step to remove the silicon oxide layer 25 and the second substrate 70 may be provided. Furthermore, a step to planarize the removed cladding layer 20 may be provided. By performing these steps, the optical phased array element 1 according to the embodiment can be manufactured.

[0049] In addition, in the electro-optic substrate preparation step S70, a substrate consisting solely of LN may be prepared instead of the electro-optic substrate 80. Even when using a substrate consisting solely of LN, the bonding step S80 and the fourth cladding layer formation step S90 can be performed by processing it to the size of the area of ​​the phase control unit 34, similar to the case of the electro-optic substrate 80. In this case, the fourth cladding layer 24 is also formed on the substrate consisting solely of LN. Alternatively, in bonding step S80, bonding may be performed after forming an adhesive layer, for example, a silicon layer of several nanometers in thickness, on each of the surfaces to be bonded, i.e., the upper surface of the waveguide 30 and the second cladding layer 22 in the figure, and the lower surface of the electro-optical layer 50. Alternatively, the electro-optical substrate preparation step S70 may be omitted, and a step for forming the LN layer may be added after the second cladding layer formation step S60. The LN layer is formed in the region of the phase control unit 34. In this case, the bonding step S80 becomes unnecessary, and the fourth cladding layer 24 can be formed on the formed LN layer in the fourth cladding layer formation step S90.

[0050] (Modified light emission section) In the optical phased array element 1, the light emission section was described as an end-face emission structure, but a grating may be engraved in the waveguide to cause the light to be emitted upwards. Figure 8A is a schematic side view illustrating the emission end 37 of the optical phased array element 1. In the end-face emission structure, the emitted light L2 is emitted from the end face of the waveguide of the optical emission section 36 into the plane in which the waveguide is located. Note that the cladding layer 20 is omitted from Figures 8A and 8B for illustrative purposes. In contrast, in the modified optical emission section 36G, a grating is provided in the waveguide to emit the light L2 to the outside of the plane on which the waveguide is located. Figure 8B is a schematic side view illustrating the emission end 37G with a grating. The emitted light L2 is emitted upward in the figure, and the deflection angle φ can be controlled by phase control. [Explanation of symbols]

[0051] 1 Optical phased array element 10 First board 15 Drive Circuit 18 electrodes (drive circuit) 20 Clad layer 30 Waveguides 31 Splitter 32 Optical branching section 34 Phase Control Unit 36 Light Emitting Section 37 Output end 50 Electro-optic layer 60 Applied electrode 65 Wiring 70 Second board 80 Electro-optic substrate

Claims

1. A first substrate having a drive circuit on one side, A cladding layer disposed on one surface of the first substrate, A waveguide is provided within the cladding layer and includes an optical branching section for branching incident light, a phase control section for phase-controlling the branched light, and an optical output section for outputting phase-controlled light. An electro-optic layer is disposed within the cladding layer, in contact with the surface of the waveguide of the phase control unit opposite to the first substrate, and is formed of a material having an electro-optic effect. The cladding layer comprises a pair of application electrodes arranged between the electro-optic layer and the first substrate so as to sandwich each of the waveguides of the phase control unit, The applied electrode is an optical phased array element connected to the drive circuit by wiring arranged within the cladding layer.

2. The optical phased array element according to claim 1, further comprising a second substrate disposed on the cladding layer covering the electro-optic layer, having the same shape and size as the electro-optic layer in a plan view.

3. The optical phased array element according to claim 1, wherein the wiring is provided in the thickness direction of the first substrate from the electrodes of the drive circuit.

4. The optical phased array element according to any one of claims 1 to 3, wherein the material of the electro-optic layer is lithium niobate.

5. The optical phased array element according to claim 4, wherein the material of the waveguide is silicon nitride.

6. A first substrate forming step in which a first substrate having a drive circuit on one side is formed, A first cladding layer formation step, in which a first cladding layer is formed on one surface of the first substrate, A wiring formation step involves connecting one end to the drive circuit and forming wiring that penetrates the first cladding layer in the thickness direction of the first substrate, A waveguide formation step is to form a waveguide on the first cladding layer having an optical branching section for branching incident light, a phase control section for phase-controlling the branched light, and an optical emission section for outputting phase-controlled light. An application electrode formation step involves forming a pair of application electrodes on the first cladding layer so as to sandwich each of the waveguides of the phase control unit, A second cladding layer formation step is to form a second cladding layer that is continuous with the first cladding layer, exposing the surface of the waveguide opposite to the first substrate, and forming a second cladding layer that is in the same plane as the exposed surface of the waveguide. An electro-optic substrate preparation step involves preparing an electro-optic substrate having an outermost electro-optic layer formed of a material having an electro-optic effect and corresponding to the size of the phase control unit, and a third cladding layer in contact with the electro-optic layer. A bonding step of bonding the electro-optic substrate by bringing the exposed surface of the waveguide of the phase control unit and the electro-optic layer facing each other, The process includes a fourth cladding layer formation step, in which a fourth cladding layer is formed to cover the waveguide, continuous with the second cladding layer and the third cladding layer, A method for manufacturing an optical phased array element, wherein in the application electrode formation step, the other end of the wiring is connected to the application electrode.

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