Efficient and secure data processing using domain-oriented masking

Abstract

This invention provides methods, apparatus, and systems for efficient and secure data processing using domain-oriented masking. [Solution] In an integrated circuit (IC) using multiple Advanced Encryption Standard (AES) substitution boxes (S-Boxes) 118-1, each having multiple GF multipliers that provide random numbers each time the input is updated, in order to limit the need for an entropy generation circuit, the output from the previous stage of the first S-Box is provided as a random number to the subsequent stage of the second S-Box, and the input registers of the Galois field (GF) multiplier and the pipeline registers in the stages of the Advanced Encryption Standard substitution boxes (S-Boxes) share a single flip-flop.

Claims

1. An integrated circuit equipped with a replacement box for advanced encryption standards, A masked Galois field multiplier, The masked Galois multiplier has at least two input registers, The above-mentioned advanced encryption standard includes at least two pipeline registers from the first stage to the second stage of the replacement box, A first flip-flop configured to operate with a first pair of registers, including a first input register of the at least two input registers to the masked Galois multiplier and a first pipeline register of the at least two pipeline registers from the first stage to the second stage, An integrated circuit comprising a first stage which includes a second input register from among the at least two input registers and a second flip-flop configured to operate with a second pair of registers, the second pipeline register from among the at least two pipeline registers.

2. The at least two input registers to the masked Galois multiplier include four input registers, The integrated circuit according to claim 1, wherein the at least two pipeline registers from the first stage to the second stage of the replacement box for the advanced encryption standard include four pipeline registers.

3. The first stage is, A third flip-flop configured to operate with a third pair of registers, including a third input register of the at least two input registers to the masked Galois multiplier and a third pipeline register of the at least two pipeline registers from the first stage to the second stage, The integrated circuit according to claim 2, further comprising a fourth input register of the at least two input registers to the masked Galois multiplier and a fourth flip-flop configured to operate with a fourth pair of registers, the fourth pipeline register of the at least two pipeline registers from the first stage to the second stage.

4. The masked Galois multiplier is a masked first Galois multiplier, The replacement box for the aforementioned advanced encryption standard is: A masked second Galois field multiplier, At least two input registers to the masked second Galois multiplier, The replacement box of the aforementioned advanced encryption standard includes at least two pipeline registers from the second stage to the third stage, A third flip-flop configured to operate with a third pair of registers, including a third input register of the at least two input registers to the masked second Galois multiplier and a third pipeline register of the at least two pipeline registers from the second stage to the third stage, The integrated circuit according to claim 1, further comprising a second stage which includes a fourth input register of the at least two input registers to the masked second Galois multiplier and a fourth flip-flop configured to operate with a fourth pair of registers, the fourth pipeline register of the at least two pipeline registers from the second stage to the third stage.

5. The at least two input registers to the masked second Galois multiplier include four input registers, The integrated circuit according to claim 4, wherein the at least two pipeline registers from the second stage to the third stage of the replacement box for the advanced encryption standard include four pipeline registers.

6. The replacement box for the aforementioned advanced encryption standard is: A fifth flip-flop configured to operate with a fifth pair of registers, including a fifth input register among the at least two input registers to the masked second Galois multiplier and a fifth pipeline register among the at least two pipeline registers from the second stage to the third stage, The integrated circuit according to claim 4, further comprising the second stage, which includes a sixth input register from the at least two input registers to the masked second Galois multiplier, and a sixth flip-flop configured to operate with a sixth pair of registers, the sixth pipeline register from the at least two pipeline registers from the second stage to the third stage.

7. The integrated circuit according to claim 1, wherein the first pair of registers and the second pair of registers store a mask or mask data.

8. The integrated circuit according to claim 1, wherein the circuit synthesis tool is disabled for at least a portion of the substitution boxes of the advanced encryption standard.

9. It is an integrated circuit, It comprises at least two replacement boxes for advanced cryptographic standards, the first replacement box for advanced cryptographic standards is: An integrated circuit comprising a prestage including a first Galois field multiplier, wherein the output of the first Galois field multiplier is coupled to the random input of a second Galois field multiplier in a subsequent stage of an additional highly cryptographic standard substitution box among the at least two highly cryptographic standard substitution boxes.

10. The output of the first Galois field multiplier is, The random number input to the third Galois field multiplier in the subsequent stage of the substitution box for the additional advanced encryption standard, or The integrated circuit according to claim 9, wherein the random number input of a fourth Galois field multiplier in the subsequent stage of another substitution box of the at least two substitution boxes of advanced cryptographic standards is further coupled, and the other substitution box of advanced cryptographic standards is different from the additional substitution box of advanced cryptographic standards.

11. The first portion of the output of the first Galois field multiplier is coupled to the random number input of the second Galois field multiplier, and the first portion of the output has fewer bits than the output. The integrated circuit according to claim 10, wherein the second portion of the output of the first Galois field multiplier is coupled to the random number input of the third Galois field multiplier, and the second portion of the output has fewer bits than the output.

12. The output of the first Galois multiplier is the first output, The preceding stage of the substitution box of the first advanced cryptographic standard further includes a fifth Galois field multiplier having a second output, The third portion of the second output of the fifth Galois field multiplier is coupled to the random number input of the second Galois field multiplier, and the third portion of the second output has fewer bits than the second output. The fourth portion of the second output of the fifth Galois field multiplier is coupled to the random number input of the third Galois field multiplier, and the fourth portion of the second output has fewer bits than the second output. The integrated circuit according to claim 11, having a number.

13. The integrated circuit according to claim 9, wherein the output from the first Galois field multiplier includes a partial result of the first Galois field multiplier, the partial result includes at least a portion of a mask or mask data.

14. The aforementioned replacement boxes for at least two advanced encryption standards constitute the first set of replacement boxes for advanced encryption standards, The aforementioned integrated circuit is Further comprising a second set of replacement boxes for advanced encryption standards, the replacement box for the second advanced encryption standard among the replacement boxes for at least two different advanced encryption standards, The integrated circuit according to claim 9, comprising a prestage including a masked sixth Galois field multiplier, wherein the output of the sixth Galois field multiplier is coupled to the random input of a seventh Galois field multiplier in a subsequent stage of an additional high-level cryptographic standard substitution box among the substitution boxes of at least two different high-level cryptographic standards.

15. The integrated circuit according to claim 14, wherein the first set of replacement boxes for the advanced encryption standard and the second set of replacement boxes for the advanced encryption standard include a different number of replacement boxes for the advanced encryption standard.

16. A method for performing a secure encryption operation using any one of the integrated circuits described in claims 1 to 15.

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