Electro-optical devices and electronic equipment

Abstract

To provide an electro-optical device and electronic equipment that facilitate the formation of a first contact. [Solution] The electro-optical device comprises a substrate, a semiconductor layer including source and drain regions, and a first transistor having a gate electrode, a first insulating layer disposed between the substrate and the first transistor, a conductive portion electrically connected to the source and drain regions, a second insulating layer disposed between the semiconductor layer and the conductive portion, a first contact disposed in a hole provided in the second insulating layer and connecting the source and drain regions and the conductive portion, and a first light-shielding portion disposed between the substrate and the first insulating layer, wherein the first light-shielding portion is provided at a different position from the first contact in a plan view in the thickness direction of the substrate.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In an electronic device such as a projector, for example, an electro-optical device such as a liquid crystal display device capable of changing optical characteristics for each pixel is used.

[0003] The electro-optical device described in Patent Document 1 includes a substrate, a pixel switching element having a semiconductor layer, and a film-shaped light-shielding portion that suppresses the incidence of light on the semiconductor layer. The light-shielding portion is provided so as to overlap the semiconductor layer in a plan view. By providing such a light-shielding portion, it is possible to suppress the incidence of light on the semiconductor layer, and thus it is possible to prevent malfunction due to the photocurrent of the pixel switching element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] For example, in the formation of the light-shielding portion, the surface of the light-shielding portion may be flattened. In this case, a phenomenon called dishing may occur, in which a dish-shaped depression is formed on the surface of the light-shielding portion. Conventionally, when the light-shielding portion overlaps the entire area of the semiconductor layer in a plan view, the shape of the semiconductor layer becomes a shape along the surface shape of the light-shielding portion. Therefore, the shape of the semiconductor layer may affect the formation of the contact on the upper layer of the semiconductor layer. Specifically, when forming a contact that connects the semiconductor layer and the wiring, the etching time for contact formation may increase excessively.

Means for Solving the Problems

[0006] One embodiment of the electro-optical apparatus of the present invention comprises a substrate, a semiconductor layer including source and drain regions, and a first transistor having a gate electrode, a first insulating layer disposed between the substrate and the first transistor, a conductive portion electrically connected to the source and drain regions, a second insulating layer disposed between the semiconductor layer and the conductive portion, a first contact disposed in a hole provided in the second insulating layer and connecting the source and drain regions and the conductive portion, and a first light-shielding portion disposed between the substrate and the first insulating layer, wherein the first light-shielding portion is provided at a position different from the first contact in a plan view in the thickness direction of the substrate.

[0007] One embodiment of the electronic device of the present invention comprises an electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of an electro-optical apparatus according to an embodiment. [Figure 2] This is a cross-sectional view of the AA line of the electro-optical apparatus shown in 1. [Figure 3] This figure schematically shows the peripheral circuits of the electro-optical device shown in Figure 1. [Figure 4] Figure 1 is an equivalent circuit diagram showing the electrical configuration of the element substrate. [Figure 5] Figure 2 shows a portion of the element substrate in the pixel region. [Figure 6] This is a cross-sectional view along the line A1-A1 in Figure 4. [Figure 7] This is a cross-sectional view along the line A2-A2 in Figure 4. [Figure 8] This figure shows the planar arrangement of the second light-shielding section and the second transistor shown in Figure 6. [Figure 9] A portion of the scan line drive circuit in the peripheral region of Figure 3 is shown. [Figure 10] This figure shows the planar arrangement of the first transistor and the first light-shielding section in Figure 9. [Figure 11]This is a diagram for explaining the first light-shielding portion of the comparative example. [Figure 12] This is a diagram showing the first light-shielding portion of the comparative example when dishing does not occur. [Figure 13] This is a diagram for explaining the first light-shielding portion of the present embodiment. [Figure 14] This is a cross-sectional view showing the first light-shielding portion of the first modification example. [Figure 15] This is a plan view of the first light-shielding portion shown in FIG. 14. [Figure 16] This is a diagram showing a part of the pixel region of the element substrate of the second modification example. [Figure 17] This is a diagram showing a part of the peripheral region of the element substrate of the second modification example. [Figure 18] This is a perspective view showing a personal computer which is an example of an electronic device. [Figure 19] This is a plan view showing a smartphone which is an example of an electronic device. [Figure 20] This is a schematic diagram showing a projector which is an example of an electronic device.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the dimensions or scales of each part are appropriately different from the actual ones, and there are also parts schematically shown for easy understanding. Further, the scope of the present invention is not limited to these embodiments unless there is a description to particularly limit the present invention in the following description.

[0010] A. Electro-optical device 1. Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A of the electro-optical device 100 shown in FIG. 1. Hereinafter, for convenience of explanation, the X-axis, Y-axis, and Z-axis that are orthogonal to each other will be appropriately used for explanation. Also, one direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction. Also, the Z-axis is typically a vertical axis. The Z1 direction is the upper side, and the Z2 direction is the lower side. However, the Z-axis does not have to be a vertical axis.

[0011] Also, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α but also the case where element α and element β are separated. Also, the "electrical connection" between element α and element β includes not only a configuration in which element α and element β are directly joined to conduct, but also a configuration in which element α and element β are indirectly conducted through another conductor.

[0012] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device of an active matrix driving method. The electro-optical device 100 includes a device substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. As shown in FIG. 2, the device substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Note that viewing from the Z1 direction or Z2 direction, which is the direction in which these overlap, is referred to as "plan view". Also, the shape of the electro-optical device 100 in plan view shown in FIG. 1 is a quadrangle, but it may be a polygon other than a quadrangle or a circle.

[0013] The element substrate 2 shown in Figure 2 comprises a light-transmitting first substrate 21, a light-transmitting laminate 22, a plurality of light-transmitting pixel electrodes 25, and a light-transmitting first alignment film 29. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are stacked in this order in the Z1 direction. "Light-transmitting" refers to the ability to transmit visible light, preferably with a visible light transmittance of 50% or more.

[0014] The first substrate 21 corresponds to the "substrate". The first substrate 21 is a translucent and insulating flat plate, and is composed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of translucent insulating films. Various wirings and the like are provided on the laminate 22. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, transparent conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown in the figures, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in a plan view. The first alignment film 29 is translucent and insulating. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. The first alignment film 29 is arranged to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0015] The opposing substrate 3 is positioned opposite the element substrate 2. The opposing substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second orientation film 34. Although not shown in the figures, the opposing substrate 3 also has a light-shielding border that surrounds a plurality of pixel electrodes 25 in a plan view. "Light-shielding" refers to light-shielding properties to visible light, preferably with a visible light transmittance of less than 50%, and more preferably 10% or less.

[0016] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a translucent and insulating plate, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 is translucent and insulating and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode placed on a plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes, for example, transparent conductive materials such as ITO, IZO, and FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide.

[0017] The sealing member 4 is placed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins, such as epoxy resin. The sealing member 4 may also include a gap material made of an inorganic material such as glass.

[0018] The liquid crystal layer 5 is located within a region enclosed by the element substrate 2, the opposing substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optic layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0019] The electro-optical device 100 has a pixel region A10 and a peripheral region A20 located outside the pixel region A10 in a plan view. The pixel region A10 is an area for displaying an image and is provided with a plurality of pixels P arranged in a matrix. A plurality of pixel electrodes 25 are arranged one-to-one for the plurality of pixels P. The aforementioned common electrode 33 is provided in common for the plurality of pixels P. The peripheral region A20 surrounds the pixel region A10 in a plan view.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Figure 2, an image is displayed by modulating the light LL between the time it is incident on the opposing substrate 3 and the time it is emitted from the element substrate 2. Alternatively, an image may be displayed by modulating the light incident on the element substrate 2 while it is emitted from the opposing substrate 3.

[0021] Furthermore, the electro-optical device 100 is applied to, for example, a color display device such as a personal computer and a smartphone, which will be described later. When applied to such a display device, a color filter is appropriately used for the electro-optical device 100. Also, the electro-optical device 100 is applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light bulb. In this case, a color filter is omitted for the electro-optical device 100.

[0022] 2. Peripheral Circuits Figure 3 is a schematic diagram showing the peripheral circuit 10 in the electro-optical device 100 shown in Figure 1. As shown in Figure 3, the peripheral region A20 of the electro-optical device 100 is provided with the peripheral circuit 10 and a plurality of external terminals 13. The plurality of external terminals 13 are connected to wiring (not shown) that is routed from the peripheral circuit 10.

[0023] Furthermore, the pixel region A10 has n scan lines 241 and m data lines 242, where n and m are integers greater than or equal to 2. The n scan lines 241 extend along the X-axis and are spaced equally along the Y-axis. The m data lines 242 extend along the Y-axis and are spaced equally along the X-axis. The n scan lines 241 and m data lines 242 are electrically insulated from each other and are arranged in a grid pattern in a planar view. The region enclosed by two adjacent scan lines 241 and two adjacent data lines 242 corresponds to pixel P.

[0024] Furthermore, the peripheral circuitry 10 includes two scan line drive circuits 11, a data line drive circuit 12, a test circuit 14, and a sampling circuit 15.

[0025] In the illustrated example, the two scan line drive circuits 11 are arranged on either side of the pixel area A10. Each scan line drive circuit 11 includes multiple transistors. For example, the scan line drive circuit 11 located on the left side of the pixel area A10 drives the odd-numbered scan lines 241, and the scan line drive circuit 11 located on the right side of the pixel area A10 drives the even-numbered scan lines 241. Alternatively, the same scan line 241 may be driven by scan line drive circuits 11 located on both the left and right sides.

[0026] The inspection circuit 14 is located, for example, on the opposite side of the multiple external terminals 13 of the pixel area A10. Data lines 242 are connected to the inspection circuit 14. The inspection circuit 14 is used to inspect the electro-optical device 100 for operational defects, etc., by detecting the image signal during the manufacturing or shipment of the electro-optical device 100. The inspection circuit 14 has, for example, a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to an inspection line (not shown). In addition, the gate of each transistor is electrically connected to a control signal line (not shown).

[0027] The data line drive circuit 12 and the sampling circuit 15 are arranged, for example, on the opposite side of the pixel region A10 from the inspection circuit 14. The data line drive circuit 12 is electrically connected to m data lines 242 via the sampling circuit 15. Based on the sampling signal output from the data line drive circuit 12, the sampling circuit 15 samples the image signal and supplies it to the data lines 242.

[0028] The sampling circuit 15 has a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to a constant potential line (not shown). In addition, the gate of each transistor is electrically connected to a signal line (not shown) to which the sampling signal is supplied.

[0029] 3. Electrical configuration of the element substrate 2 Figure 4 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 in Figure 1. As shown in Figure 4, each pixel P in the pixel region A10 of the element substrate 2 is provided with a second transistor 23, a pixel electrode 25, and a capacitive element 24. The second transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each second transistor 23 includes a gate, source, and drain. The pixel electrode 25 is electrically connected to the drain of the corresponding second transistor 23. In addition, as mentioned above, n scan lines 241 and m data lines 242, as well as n constant potential lines 243, are arranged in the pixel region A10.

[0030] Each of the n scan lines 241 is electrically connected to the gate of a corresponding number of second transistors 23. Scan signals G1, G2, ..., and Gn are supplied to the 1 to n scan lines 241 sequentially from the scan line drive circuit 11.

[0031] Each of the m data lines 242 is electrically connected to the source of a corresponding number of second transistors 23. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m data lines 242 from the aforementioned data line driving circuit 12 via the sampling circuit 15.

[0032] n constant potential lines 243 extend in the X1 direction and are arranged at equal intervals in the Y2 direction. Furthermore, the n constant potential lines 243 are electrically insulated from the n scan lines 241 and m data lines 242, and are spaced apart from them. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitive element 24. The other electrode of each capacitive element 24 is electrically connected to the corresponding pixel electrode 25. Each capacitive element 24 is a holding capacitor for maintaining the potential of the pixel electrode 25. A constant potential Vcom is applied to one electrode of the capacitive element 24, and the other electrode is electrically connected to the drain of the second transistor 23.

[0033] As scanning signals G1, G2, ..., and Gn become sequentially active and n scanning lines 241 are selected sequentially, the second transistor 23 connected to the selected scanning line 241 turns ON. Then, image signals S1, S2, ..., and Sm, whose magnitudes correspond to the grayscale to be displayed, are taken up via m data lines 242 to the pixel P corresponding to the selected scanning line 241 and applied to the pixel electrode 25. As a result, a voltage corresponding to the grayscale to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in Figure 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. Furthermore, the applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates the light, enabling grayscale display.

[0034] 4. Pixel area A10 Figure 5 shows a portion of the element substrate 2 in the pixel region A10 of Figure 2. As shown in Figure 5, the pixel region A10 has a plurality of aperture regions A11 and a light-shielding region A12. The plurality of aperture regions A11 are arranged in a matrix in plan view. The shape of the light-shielding region A12 in plan view is a frame shape located between the plurality of aperture regions A11. Each aperture region A11 is the region where the pixel electrode 25 is placed and is a region through which light is transmitted. On the other hand, the second transistor 23 is placed in the light-shielding region A12 and is a region that has light-shielding properties. In addition, although not shown in Figure 5, various wirings such as the scan line 241, data line 242, and constant potential line 243 shown in Figure 4, and the capacitive element 24 are placed in the light-shielding region A12.

[0035] 5. Configuration of the light-shielding region A12 of the element substrate 2 Figure 6 is a cross-sectional view of the line A1-A1 in Figure 2. Figure 7 is a cross-sectional view of the line A2-A2 in Figure 5.

[0036] As shown in Figures 6 and 7, the element substrate 2 has a first substrate 21, which is a "substrate," and a laminate 22. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. In addition, insulating layer 221 is the "first insulating layer," and insulating layers 222 and 223 are the "second insulating layers." Furthermore, insulating layers 221 to 229 have light-transmitting and insulating properties. The materials of insulating layers 221 to 229 are, for example, inorganic materials containing silicon, such as silicon oxide and silicon oxynitride.

[0037] The light-shielding region A12 of the laminate 22 contains the aforementioned second transistor 23, capacitive element 24, scan line 241, and data line 242. Furthermore, the laminate 22 is provided with a fourth light-shielding section 244 and a third light-shielding section 240. In addition, relay electrodes 245, 246, 247, 248, and 249 are arranged in the laminate 22. Moreover, the first substrate 21 has multiple second light-shielding sections 210.

[0038] As described above, the first substrate 21 is made of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess H1.

[0039] A second light-shielding portion 210 is positioned within the recess H1. Therefore, the second light-shielding portion 210 is positioned between the first substrate 21 and the insulating layer 221, which is the "first insulating layer". The second light-shielding portion 210 is formed, for example, using the damascene method. The second light-shielding portion 210 is provided to suppress the incidence of light onto the semiconductor layer 231 of the second transistor 23. Note that the first substrate 21 does not necessarily have to have the recess H1. In this case, the second light-shielding portion 210 is positioned on a flat surface of the first substrate 21 facing the Z1 direction.

[0040] A second transistor 23 is placed on the insulating layer 221. The second transistor 23 has a semiconductor layer 231, a gate insulating film 233, and a gate electrode 232, all arranged in a direction away from the first substrate 21. The semiconductor layer 231 is placed on the insulating layer 221. The gate electrode 232 is placed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. The region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0041] The second transistor 23 has, for example, an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the direction along the Y axis. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The regions excluding the channel region 231c are doped with impurities to enhance conductivity. The impurity concentration in the low-concentration drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the low-concentration source region 231e is lower than the impurity concentration in the source region 231b. For example, the second transistor 23 does not necessarily have an LDD structure, and the low-concentration source region 231e may be omitted.

[0042] The gate electrode 232 is formed, for example, by doping polysilicon with impurities that enhance conductivity. Alternatively, the gate electrode 232 may be formed using conductive materials such as metals, metal oxides, and metal compounds. In a plan view, the gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231. The gate insulating film 233 is composed of a silicon oxide film formed, for example, by thermal oxidation or CVD (chemical vapor deposition). A portion of this second transistor 23 overlaps the second light-shielding portion 210 in a plan view.

[0043] As shown in Figure 6, a third light-shielding portion 240 and a fourth light-shielding portion 244 are arranged on the insulating layer 223. The third light-shielding portion 240 covers the low-concentration drain region 231d of the semiconductor layer 231 in a plan view. The third light-shielding portion 240 is connected to the drain region 231a of the semiconductor layer 231 via a contact 270. Therefore, the third light-shielding portion 240 is the pixel potential. For example, the contact 270 is a contact plug that fills holes penetrating the insulating layers 222 and 223. The contact 270 also has a portion that covers the low-concentration drain region 231d in a plan view. The third light-shielding portion 240 and the contact 270 are, for example, a single unit and are formed by the damascene method.

[0044] The fourth light-shielding portion 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills holes penetrating the insulating layers 222 and 223. The fourth light-shielding portion 244 and the contact 271 are, for example, a single unit and are formed by the damascene method.

[0045] Contacts 7 are placed in the insulating layers 221-224. The contacts 7 are formed, for example, using the damascene method.

[0046] As shown in Figure 7, the contact 7 is positioned to surround the gate electrode 232 from both the Z-axis and Y-axis directions. The contact 7 is electrically connected to the gate electrode 232. A portion of the contact 7 also penetrates the insulating layer 221 and is electrically connected to the second light-shielding portion 210. The second light-shielding portion 210 functions as a back gate.

[0047] Although not shown in detail, the low-concentration drain region 231d is surrounded by contact 7, the third light-shielding portion 240, and contact 270. Therefore, the incidence of light into the low-concentration drain region 231d can be suppressed. Consequently, it is possible to suppress the operation of the second transistor 23 becoming unstable due to the incidence of such light. As a result, the risk of display defects such as brightness unevenness can be suppressed. Thus, a decrease in display quality can be suppressed.

[0048] As shown in Figure 6, a scan line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scan line 241 is electrically connected to the gate electrode 232 via a contact 7 that penetrates the insulating layers 223 and 224. The relay electrode 245 is electrically connected to the third light-shielding portion 240 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the fourth light-shielding portion 244 via a contact 273 that penetrates the insulating layer 224.

[0049] Relay electrodes 247 and 248 are placed on the insulating layer 225. Relay electrode 247 is electrically connected to relay electrode 246 via a contact 275 that penetrates the insulating layer 225. Relay electrode 248 is electrically connected to relay electrode 245 via a contact 274 that penetrates the insulating layer 225.

[0050] A data line 242 is placed on the insulating layer 226. The data line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the data line 242 is electrically connected to the source region 231b via contact 276, relay electrode 247, contact 275, relay electrode 246, contact 273, fourth light shield 244, and contact 271.

[0051] As shown in Figure 7, a relay electrode 249 is placed on the insulating layer 226. The relay electrode 249 is electrically connected to a relay electrode 248 via a contact 277 that penetrates the insulating layer.

[0052] A capacitive element 24 is placed on the insulating layer 227. The capacitive element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. Electrode 2401 is placed on the insulating layer 227. Electrode 2402 is placed on the insulating layer 228. The dielectric layer 2403 is placed between electrodes 2401 and 2402. Electrode 2401 also serves as the constant potential line 243 in Figure 4. Furthermore, as shown in Figure 7, electrode 2402 is electrically connected to the intermediate electrode 249 via contact 278 that penetrates the insulating layers 227 and 228. Therefore, as shown in Figure 6 or Figure 7, electrode 2402 is electrically connected to the drain region 231a via contact 278, intermediate electrode 249, contact 277, intermediate electrode 248, contact 274, intermediate electrode 245, contact 272, third light shield 240, and contact 270.

[0053] As shown in Figure 6, the pixel electrode 25 is placed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229.

[0054] Each of the aforementioned scanning lines 241, data lines 242, electrodes 2401, 2402, fourth light-shielding sections 244 and 240, and relay electrodes 245, 246, 247, 248, and 249 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or multi-layer. For example, they may be composed of a laminate of an aluminum film and a titanium nitride film.

[0055] Furthermore, each of the aforementioned contacts 7, 270, 271-279 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), as well as metal nitrides and metal silicides. Each of the contacts 7, 270, 271-279 may be single-layer or multi-layer. In addition, each of the contacts 7, 270, 271-279 may be integrally formed with the connected electrode or wiring, or may be formed separately.

[0056] Note that the arrangement of wiring and electrodes in the light-shielding region A12 shown in Figures 6 and 7 is just an example. For example, other capacitive elements besides the capacitive element 24 may be provided in the light-shielding region A12. The scan line 241, data line 242, and capacitive element 24 are arranged in this order in the Z1 direction, but they do not have to be arranged in this order.

[0057] Figure 8 shows the planar arrangement of the second light-shielding portion 210 and the second transistor 23 shown in Figure 6. As shown in Figure 8, the second light-shielding portion 210 overlaps the semiconductor layer 231 of the second transistor 23 in a planar view. In particular, the overlap of the second light-shielding portion 210 with the low-concentration drain region 231d in a planar view suppresses display defects caused by light incident on the low-concentration drain region 231d.

[0058] Furthermore, the second light-shielding portion 210 overlaps with the entire semiconductor layer 231 in a plan view. Therefore, compared to the case where the second light-shielding portion 210 overlaps with a part of the semiconductor layer 231, display defects caused by light incident on the semiconductor layer 231 can be suppressed. In addition, display defects caused by light LL and reflected light incident on the semiconductor layer 231 located in the pixel region A10 can be avoided.

[0059] The first light-shielding portion 200 is provided with a slit, and the first light-shielding portion 200 may be divided into multiple parts.

[0060] 6. Peripheral area A20 Figure 9 shows a portion of the scanning line driving circuit 11 within the peripheral region A20 of Figure 3. As shown in Figure 9, the laminate 22 is provided with unit circuits 22a. A unit circuit 22a is provided, for example, for each scanning line 241. The unit circuit 22a includes a first transistor 26. Conductive parts 281 and 282 are also provided in the laminate 22. Relay electrodes 283, 284, 285, and 286 are also provided in the laminate 22. Peripheral electrodes 250 are also arranged on the laminate 22. The peripheral electrodes 250 are, for example, ion trap electrodes. A first light-shielding portion 200 is provided in the first substrate 21 for each first transistor 26. The first light-shielding portion 200 has a plurality of light-shielding films 211.

[0061] The first substrate 21 has a plurality of recesses H0 spaced apart from each other. A first light-shielding portion 200 is placed in each recess H0. Therefore, the first light-shielding portion 200 is placed between the first substrate 21 and the insulating layer 221, which is the "first insulating layer". The first light-shielding portion 200 has a plurality of light-shielding films 211 spaced apart from each other. Each of the plurality of light-shielding films 211 is formed, for example, using the damascene method. The first light-shielding portion 200 is provided to prevent light from entering the semiconductor layer 261 of the first transistor 26. The first light-shielding portion 200 is also provided in the same layer as the second light-shielding portion 210. That is, the first light-shielding portion 200 and the second light-shielding portion 210 are provided between the first substrate 21 and the insulating layer 221. Note that the first substrate 21 does not necessarily have to have recesses H0. In this case, the first light-shielding portion 200 is positioned on a flat surface of the first substrate 21 facing the Z1 direction.

[0062] The first transistor 26 is placed on the insulating layer 221. The insulating layer 221 is the "first insulating layer" placed between the first substrate 21 and the first transistor 26. The first transistor 26 is also provided on the same layer as the second transistor 23 mentioned above. In other words, the first transistor 26 and the second transistor 23 are placed on the insulating layer 221.

[0063] The first transistor 26 has a semiconductor layer 261, a gate insulating film 263, and a gate electrode 262, all arranged in a direction away from the first substrate 21. The semiconductor layer 261 is placed on the insulating layer 221. The semiconductor layer 261 is placed in the same layer as the semiconductor layer 231 provided in the light-shielding region A12. The gate electrode 262 is placed on the insulating layer 222. The gate electrode 262 is placed in the same layer as the gate electrode 232 provided in the light-shielding region A12. The gate insulating film 263 is interposed between the gate electrode 232 and the semiconductor layer 231. The gate insulating film 263 is placed in the same layer as the gate insulating film 233 provided in the light-shielding region A12. The region of the insulating layer 222 that corresponds to the gate electrode 262 in a plan view corresponds to the gate insulating film 263. In addition, insulating layers 223 and 224 are the "second insulating layer" that covers the first transistor 26.

[0064] The first transistor 26 has, for example, an LDD structure. The semiconductor layer 261 has a source-source-drain region 261a, a source-drain region 261b, a channel region 261c, a low-concentration region 261d, and a low-concentration region 261e. The channel region 261c is located between the source-drain region 261a and the source-drain region 261b. The low-concentration region 261d is located between the channel region 261c and the source-drain region 261a. The low-concentration region 261e is located between the channel region 261c and the source-drain region 261b. The semiconductor layer 261 is formed of, for example, polysilicon. The regions excluding the channel region 261c are doped with impurities to enhance conductivity. The impurity concentration in the low-concentration region 261d is lower than the impurity concentration in the source-drain region 261a. The impurity concentration in the low-concentration region 261e is lower than the impurity concentration in the source-drain region 261b.

[0065] For example, the first transistor 26 does not necessarily have an LDD structure, and the low-concentration region 261e may be omitted. Also, the "source-drain region" functions as either a source region or a drain region. Either the source-source-drain region 261a or 261b functions as a source region, and the other functions as a drain region.

[0066] The gate electrode 262 is formed, for example, by doping polysilicon with impurities that enhance conductivity. Alternatively, the gate electrode 262 may be formed using conductive materials such as metals, metal oxides, and metal compounds. In a plan view, the gate electrode 262 overlaps the channel region 261c of the semiconductor layer 261. The gate insulating film 263 is composed of a silicon oxide film deposited, for example, by thermal oxidation or CVD.

[0067] Although not shown in detail, the gate electrode 262 may also be electrically connected to the first light-shielding portion 200. In other words, the first light-shielding portion 200 may be at the same potential as the gate electrode. When the first light-shielding portion 200 and the gate electrode 262 are at the same potential, electric field concentration due to the potential difference is less likely to occur, thus making it less likely for the gate insulating film 263 to break down. Also, when the first light-shielding portion 200 and the gate electrode 262 are at the same potential, the first light-shielding portion 200 can function as a back gate.

[0068] Furthermore, conductive parts 281 and 282 are arranged in the insulating layer 223. The insulating layers 222 and 223 are a "second insulating layer" arranged between the semiconductor layer 261 and the conductive parts 281 and 282. The conductive parts 281 and 282 are arranged in the same layer as the third light-shielding part 240 and the fourth light-shielding part 244. The conductive part 281 is electrically connected to the source / drain region 261a of the semiconductor layer 261 via the first contact 291. The first contact 291 is located in a hole provided in the insulating layers 222 and 223, which are the "second insulating layer," and connects the source / drain region 261a and the conductive part 281. The conductive part 282 is electrically connected to the source / drain region 261b of the semiconductor layer 261 via the first contact 292. The first contact 292 is positioned in holes provided in the insulating layers 222 and 223, which are the "second insulating layer," and connects the source / drain region 261b to the conductive portion 282.

[0069] Intermediate electrodes 280, 283, and 284 are arranged on the insulating layer 224. Intermediate electrode 280 is electrically connected to gate electrode 262 via a contact 290 that fills a contact hole H2, which is a hole that penetrates the insulating layers 223 and 224. Intermediate electrode 283 is electrically connected to conductive part 281 via a contact 293 that penetrates the insulating layer 224. Intermediate electrode 284 is electrically connected to conductive part 282 via a contact 294 that penetrates the insulating layer 224.

[0070] Relay electrodes 285 and 286 are arranged on the insulating layer 225. Relay electrode 285 is electrically connected to relay electrode 283 via a contact 295 that penetrates the insulating layer 225. Relay electrode 286 is electrically connected to relay electrode 284 via a contact 296 that penetrates the insulating layer 225. Each of relay electrodes 285 and 286 is electrically connected to other transistors or other elements adjacent to the first transistor 26. Therefore, each of the conductive parts 281 and 282 is electrically connected to other transistors or other elements adjacent to the first transistor 26.

[0071] Various wirings, electrodes, or light-shielding layers, not shown in the illustration, may be placed on the insulating layer 226. Furthermore, peripheral electrodes 250 are placed on the insulating layer 229. The peripheral electrodes 250 are placed on the same layer as the pixel electrodes 25.

[0072] Furthermore, from the viewpoint of ease of manufacturing, it is preferable that the various wirings or electrodes arranged in the light-shielding region A12 and the various wirings or electrodes arranged in the surrounding region A20 be formed from the same material in each layer.

[0073] 7. Unit circuit 22a Figure 10 shows the planar arrangement of the first transistor 26 and the first light-shielding portion 200 in Figure 9. The cross-section along line B3-B3 in Figure 10 corresponds to Figure 9.

[0074] As shown in Figure 10, the unit circuit 22a has two first transistors 26. The unit circuit 22a includes, for example, a NOT gate. One of the two first transistors 26 is an n-channel MOS transistor and the other is a p-channel MOS transistor. In this embodiment, the two first transistors 26 share a common gate electrode 262.

[0075] Furthermore, the gate electrode 262 extends in the direction along the X-axis. A contact 290 is positioned at the X2 end of the gate electrode 262. In this embodiment, a plurality of light-shielding portions 212 are provided. The plurality of light-shielding portions 212 are spaced apart from each other. For example, the plurality of light-shielding portions 212 are positioned in the X2 direction relative to the first light-shielding portion 200.

[0076] A first light-shielding portion 200 is provided for each first transistor 26. The first light-shielding portion 200 has a plurality of gaps S10. Therefore, the first light-shielding portion 200 has a plurality of light-shielding films 211 spaced apart from each other. In this embodiment, the first light-shielding portion 200 has four light-shielding films 211. Four light-shielding films 211 are provided for one first transistor 26. The four light-shielding films 211 are spaced apart from each other along the Y-axis. In a plan view, a plurality of first contacts 291 are provided between two adjacent light-shielding films 211, aligned along the X-axis. The plurality of first contacts 291 do not overlap the gate electrode 262 in a plan view. The same applies to the first contacts 292. Also, the two first transistors 26 are aligned along the X-axis. The four light-shielding films 211 of the two first transistors 26 are provided at the same position along the X-axis.

[0077] Each gap S10 is a slit that extends along the X-axis and separates the first light-shielding portion 200. Each gap S10 is elongated in length and extends along the X-axis in a plan view. Each gap S10 extends along the direction in which multiple first contacts 291 or multiple first contacts 292 are aligned in a plan view. Furthermore, multiple gaps S10 are aligned along the Y-axis for each first transistor 26 and spaced apart from one another. Therefore, multiple light-shielding films 211 are aligned along the Y-axis for each first transistor 26. Multiple light-shielding films 211 do not overlap with the first contacts 291 and 292 in a plan view. The first contacts 291 and 292 overlap with the gaps S10 in a plan view. Furthermore, multiple light-shielding films 211 do not overlap with part of the gate electrode 262. Part of the gate electrode 262 overlaps with the gaps S10 in a plan view.

[0078] The first light-shielding portion 200 overlaps the source and drain regions 261a and 261b of the semiconductor layer 261 in a plan view. On the other hand, the first light-shielding portion 200 is provided at a different position from the first contacts 291 and 292 in a plan view in the thickness direction of the first substrate 21. That is, the first light-shielding portion 200 does not overlap the first contacts 291 and 292 in a plan view. None of the first contacts 291 and 292 overlap the first light-shielding portion 200 in a plan view. The first contacts 291 and 292 overlap the gap S10 in a plan view.

[0079] Since the first light-shielding portion 200 does not overlap with the first contacts 291 and 292 in a plan view, it is possible to avoid the shape of the first light-shielding portion 200 influencing the formation of the first contacts 291 and 292. Therefore, it is possible to avoid an excessive increase in the etching time for forming the first contacts 291 and 292.

[0080] Figure 11 is a diagram illustrating the first light-shielding portion 200x of a comparative example. Figure 12 is a diagram illustrating the first light-shielding portion 200x of a comparative example when dishing does not occur. Figure 13 is a diagram illustrating the first light-shielding portion 200 of this embodiment.

[0081] In the comparative examples shown in Figures 11 and 12, the first light-shielding portion 200x overlaps with the first contacts 291 and 292 and the first substrate 21 when viewed in the thickness direction. In contrast, in the present embodiment shown in Figure 13, the first light-shielding portion 200x does not overlap with the first contacts 291 and 292 and the first substrate 21 when viewed in the thickness direction.

[0082] In the formation of the first light-shielding portion 200x, a planarization treatment may be performed to flatten the upper surface of the first light-shielding portion 200x. For example, the planarization treatment may be performed by polishing such as CMP (Chemical Mechanical Polishing).

[0083] In this planarization process, as shown in Figure 11, there is a risk of a phenomenon called dishing occurring, in which dish-shaped depressions are formed on the upper surface of the multiple light-shielding films 211x of the first light-shielding section 200x. Similarly, as shown in Figure 13, the first light-shielding section 200 of this embodiment is also susceptible to dishing, in which dish-shaped depressions are formed on the upper surface of the multiple light-shielding films 211x. Figure 12 shows an example where the planarization process is not performed and dishing does not occur. In this case, no dish-shaped depressions are formed on the surface of the light-shielding films 211x.

[0084] If there is a recess on the upper surface of the light-shielding film 211x, the length L of each first contact 291 or 292 becomes longer compared to when there is no recess. Therefore, the lengths L of each first contact 291 and 2992 shown in Figure 11 are longer than the lengths L of each first contact 291 and 292 shown in Figure 12. As a result, the etching time for forming the contact holes for positioning the first contact 291 or 292 becomes longer.

[0085] In contrast, in this embodiment shown in Figure 13, the first light-shielding portion 200 does not overlap with the first contacts 291 and 292 in a plan view. Therefore, the lengths L of the first contacts 291 and 292 shown in Figure 13 are shorter than those of the comparative example shown in Figure 11. Thus, it is possible to avoid an excessive increase in the etching time for forming the first contacts 291 or 292.

[0086] As mentioned above, if the etching time for forming the contact holes becomes too long, there is a risk that the source-drain potential and the potential of the first light-shielding portion 200 will short-circuit. Also, due to the effects of dishing or erosion, the thickness of the insulating layers 221-223 may be thicker in the peripheral region A20 than in the pixel region A10. The first light-shielding portion 200 and the first contacts 291 and 292 are provided in the peripheral circuit 10. For this reason, for example, the length of the first contacts 291 and 292 in the peripheral circuit 10 may be longer in the Z-axis direction than the contacts 270 and 270 in the pixel P. Therefore, the etching time for the contact holes for arranging the first contacts 291 and 292 in the peripheral circuit 10 may be longer than the etching time for the contact holes for arranging the contacts 270 and 270 in the pixel P. Thus, if the etching time for the contact holes for arranging the first contacts 291 and 292 in the peripheral circuit 10 becomes long, the risk of the aforementioned short-circuit problem increases.

[0087] In this embodiment, as described above, the first light-shielding portion 200 does not overlap with the first contacts 291 and 292 in a plan view. Therefore, it is not necessary to consider the etching time issues in the peripheral circuit 10. As a result, conductivity can be stabilized in both the peripheral circuit 10 and the pixel P.

[0088] Furthermore, the first contacts 291 and 292 are contact plugs filled into holes formed in the insulating layers 222 and 223, which are the "second insulating layer." Contact holes in which contact plugs are placed tend to have a higher aspect ratio compared to contact holes in which so-called trench-type contacts are placed. As a result, the etching speed tends to be slower and the etching time tends to be longer. For this reason, when the first contacts 291 and 292 are contact plugs, a structure in which the first light-shielding portion 200 does not overlap with the first contacts 291 and 292 in a plan view is beneficial.

[0089] Furthermore, as mentioned above, the first light-shielding section 200 has a plurality of light-shielding films 211 that are spaced apart from each other. In other words, the first light-shielding section 200 is separated into a plurality of light-shielding films 211. Because the first light-shielding section 200 is separated into a plurality of light-shielding films 211, the planar area of ​​each light-shielding film 211 can be reduced, and dishing can be suppressed. For this reason, the effect of dishing is smaller in this embodiment in Figure 13 compared to the comparative example in Figure 11.

[0090] In a plan view, the multiple first contacts 291 overlap in the gap S10 between two adjacent light-shielding films 211. In a plan view, the two light-shielding films 211 are arranged so as to sandwich the multiple first contacts 291. In a plan view, the two light-shielding films 211 and the multiple first contacts 291 are spaced apart from each other. The same applies to the multiple first contacts 292.

[0091] Furthermore, as shown in Figure 10, the first light-shielding portion 200 overlaps with a part of the gate electrode 232 in a plan view. That is, the first light-shielding portion 200 has a gap S10 that overlaps with the gate electrode 232. By overlapping the first light-shielding portion 200 with the gate electrode 232 in a plan view, the light-shielding performance of the first light-shielding portion 200 can be improved compared to the case where there is no overlap. In addition, by overlapping a part of the gate electrode 232 in a plan view, the planar area of ​​the first light-shielding portion 200 increases compared to the case where it overlaps with the entire gate electrode 232 in a plan view, thereby reducing the risk of dishing occurring.

[0092] Furthermore, the planar area of ​​the first light-shielding portion 200, that is, the total planar area of ​​the multiple light-shielding films 211, is larger than the planar area of ​​the second light-shielding portion 210. This is a comparison between the first light-shielding portion 200 corresponding to one first transistor 26 and the second light-shielding portion 210 corresponding to one second transistor 23. Moreover, the planar area of ​​each of the multiple light-shielding films 211 is larger than the planar area of ​​the second light-shielding portion 210.

[0093] Since the planar area of ​​the first light-shielding portion 200 is larger than that of the second light-shielding portion 210, the first light-shielding portion 200 is more likely to experience dishing than the second light-shielding portion 210. Therefore, it is beneficial that the first light-shielding portion 200 does not overlap with the first contacts 291 and 292 in a plan view. On the other hand, it is preferable that the second light-shielding portion 210 overlaps with the contacts 270 and 271 in a plan view. By having the second light-shielding portion 210 overlap with the contacts 270 and 271 in a plan view, the light-shielding performance of the second light-shielding portion 210 can be improved. Thus, it is possible to prevent malfunctions caused by the photocurrent of the second transistor 23.

[0094] B. Variations The embodiments illustrated above can be modified in various ways. Specific examples of modifications that can be applied to the aforementioned embodiments are given below. Two or more embodiments arbitrarily selected from the following examples can be combined as appropriate, to the extent that they do not contradict each other.

[0095] B1. First variation Figure 14 is a cross-sectional view showing the first light-shielding portion 200A of the first modified example. Figure 15 is a plan view of the first light-shielding portion 200A shown in Figure 14.

[0096] As shown in Figures 14 and 15, the first light-shielding portion 200A is positioned differently from the gate electrode 262 in a plan view. That is, the first light-shielding portion 200A does not overlap with the gate electrode 262 in a plan view. By not overlapping the gate electrode 262 in a plan view, the risk of dishing occurring on the first light-shielding portion 200A can be reduced compared to the case where they overlap.

[0097] B2. Second variation Figure 16 shows a portion of the pixel region A10 of the element substrate 2D of the second modified example. Figure 17 shows a portion of the peripheral region A20 of the element substrate 2D of the second modified example. The laminate 22D of the element substrate 2D shown in Figures 16 and 17 further comprises a lens layer 213, insulating layers 214 and 215. The lens layer 213, insulating layers 214 and 215 are laminated in this order from the insulating layer 229. The materials of the lens layer 213, insulating layers 214 and 215 are, for example, silicon-containing inorganic materials such as silicon oxide and silicon oxynitride.

[0098] As shown in Figure 16, in the light-shielding region A12 of the pixel region A10, a relay electrode 234 is placed on the insulating layer 229. The relay electrode 234 is connected to a contact 297. A relay electrode 236 is placed on the insulating layer 214. The relay electrode 236 is connected to the relay electrode 234 via a contact 235 that penetrates the lens layer 213 and the insulating layer 214. In the light-shielding region A12, a pixel electrode 25 is placed on the insulating layer 215. The pixel electrode 25 is connected to the relay electrode 236 via a contact 237 that penetrates the insulating layer 215. Also, as shown in Figure 17, in the peripheral region A20, a peripheral electrode 250 is placed on the insulating layer 215.

[0099] Each of the relay electrodes 234 and 236 includes, for example, a metal such as aluminum, a metal nitride, and a metal silicide. Furthermore, each of the aforementioned contacts 235 and 237 includes, for example, tungsten, and a metal such as aluminum, a metal nitride, and a metal silicide.

[0100] Furthermore, the lens layer 213 has multiple lens surfaces 2130. In the pixel region A10, one lens surface 2130 is provided for each pixel electrode 25. Therefore, in the pixel region A10, one lens surface 2130 is provided for each second transistor 23. In contrast, in the peripheral region A20, multiple lens surfaces 2130 are provided for each first transistor 26. In the illustrated example, two lens surfaces 2130 are provided for one first transistor 26. Note that in the peripheral region A20, there may be any number of lens surfaces 2130 provided for each first transistor 26.

[0101] B3. Other variations

[0102] In the embodiments described above, an active-matrix electro-optical device 100 is exemplified, but the device is not limited thereto, and the driving method of the electro-optical device 100 may be, for example, a passive-matrix method.

[0103] The driving method for the "electro-optical device" is not limited to a longitudinal electric field method, but may also be a transverse electric field method. An example of a transverse electric field method is the IPS (In Plane Switching) mode. Examples of longitudinal electric field methods include the TN (Twisted Nematic) mode, VA (Vertical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode.

[0104] 2.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0105] Figure 18 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main unit 2010 in which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0106] Figure 19 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0107] Figure 20 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. Electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b, corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and memory, and controls the operation of the electro-optical devices 100.

[0108] The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is the light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator, such as a light bulb, that modulates the monochromatic light supplied from the illumination optical system 4001 according to the displayed image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0109] The above electronic device comprises the aforementioned electro-optical device 100 and control units 2003, 3002, or 4005. The aforementioned electro-optical device 100 makes malfunctions of the first transistor 26 and the second transistor 23 less likely. Therefore, the risk of display malfunctions is suppressed. Thus, by including the electro-optical device 100, the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000 can be improved.

[0110] Furthermore, the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices, but include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of Sale) terminals. In addition, electronic devices to which the present invention is applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0111] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added.

[0112] Furthermore, while the above description described a liquid crystal display device as an example of the electro-optical device of the present invention, the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to image sensors and the like. [Explanation of symbols]

[0113] 2...Element substrate, 3...Opposite substrate, 4...Sealing member, 5...Liquid crystal layer, 10...Peripheral circuit, 11...Scanning line driving circuit, 12...Data line driving circuit, 14...Inspection circuit, 15...Sampling circuit, 21...First substrate, 22...Laminate, 22a...Unit circuit, 23...Second transistor, 25...Pixel electrode, 26...First transistor, 100...Electro-optical device, 200...First light-shielding part, 210...Second light-shielding part, 212...Light-shielding part, 231...Semiconductor layer, 231a...Drain region, 231b...Source region, 231c...Chip Channel region, 231d...low-concentration drain region, 231e...low-concentration source region, 232...gate electrode, 233...gate insulating film, 261...semiconductor layer, 261a...drain region, 261b...drain region, 261c...channel region, 261d...low-concentration region, 261e...low-concentration region, 262...gate electrode, 263...gate insulating film, 281...conductive part, 282...conductive part, 291...first contact, 292...first contact, A10...pixel region, A20...peripheral region, P...pixel, S10...gap.

Claims

1. circuit board and A first transistor having a semiconductor layer including source and drain regions, and a gate electrode, A first insulating layer is disposed between the substrate and the first transistor, A conductive part electrically connected to the source and drain regions, A second insulating layer is disposed between the semiconductor layer and the conductive portion, A first contact is provided in a hole in the second insulating layer and connects the source / drain region and the conductive part, A first light-shielding portion is disposed between the substrate and the first insulating layer, Equipped with, The first light-shielding portion is provided at a position different from the first contact in a plan view in the thickness direction of the substrate. Electro-optical device.

2. The first light-shielding portion overlaps with a part of the gate electrode in the plan view. The electro-optical apparatus according to claim 1.

3. The first light-shielding portion is provided at a position different from the gate electrode in the plan view. The electro-optical apparatus according to claim 1.

4. It comprises a pixel area for displaying an image and a peripheral area provided outside the pixel area, The peripheral region is provided with the first transistor, the first contact, and the first light-shielding portion. The electro-optical apparatus according to claim 1.

5. The pixel region is provided with a second light-shielding portion located in the same layer as the first light-shielding portion, and a second transistor located in the same layer as the first transistor. The planar area of ​​the first light-shielding portion is larger than the planar area of ​​the second light-shielding portion. The electro-optical apparatus according to claim 4.

6. The first contact is a contact plug filled in a hole formed in the first insulating layer. The electro-optical apparatus according to claim 1.

7. The first light-shielding portion has a plurality of light-shielding films spaced apart from each other. The electro-optical apparatus according to claim 1.

8. An electro-optical apparatus according to any one of claims 1 to 7, An electronic device characterized by having a control unit that controls the operation of the electro-optical device.

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