Semiconductor equipment

Abstract

To provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate, even in a leadless package. [Solution] The semiconductor device 100 comprises a semiconductor chip 110, a plurality of leads 102 arranged spaced apart around the semiconductor chip 110 in a plan view, an insulating material layer 160 on which the semiconductor chip 110 and leads 102 are mounted on the upper side, a sealing resin 140 that seals the upper surface of the insulating material layer 160, the semiconductor chip 110 and leads 102, and a metal film 150 formed on a part of the lower surface of the leads 102. The leads 102 have a step portion 102a at the corners exposed from the lower surface 102b and the side surface 140s of the sealing resin.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] With the increasing functionality of electronic devices such as mobile phones and mobile devices, there is a growing demand for miniaturization and thinning of semiconductor devices used in such electronic devices.

[0003] A general package of a semiconductor device formed by molding an epoxy resin has a structure in which a semiconductor chip is mounted on a die pad that is a part of a lead frame, covered with an epoxy resin, and an outer shape is formed. As one form of such a small package structure, there is a non-lead type DFN (Dual Flat Nonleaded) package.

[0004] In general, the lower surface of the lead of the DFN package is substantially flush with the lower surface of the encapsulating resin, and is resin-sealed so that the lower surface of the lead is exposed. Then, a plating layer is formed on the lower surface of the lead, and the lead frame is diced into individual pieces by cutting with a dicing device. In the DFN package manufactured in this way, the lower surface of the lead on which the plating layer is formed functions as an outer lead.

[0005] As described above, when only the lower surface of the lead on which the plating layer is formed is joined to the mounting substrate with solder or the like, it is difficult to ensure the joining strength between the lead and the mounting substrate.

[0006] In order to suppress the decrease in the bonding strength between the lead and the mounting substrate, for example, in the invention described in Patent Document 1, a semiconductor device in which an elongated groove-shaped recess is formed on the lower surface of the lead is described.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

[0008] However, in the invention described in Patent Document 1, the lower surfaces of the leads and tabs are formed almost flush with the lower surface of the sealing resin, and the interface between the leads and tabs and the solder plating layer is flush with the lower surface of the sealing resin. Furthermore, when the leads and tabs are joined to the mounting substrate with solder or the like, solder will be formed at the edges of the interface of the metal film. As a result, stress may be concentrated at the interface between the leads and tabs and the solder plating layer.

[0009] Figure 13 is a schematic side view (perspective view) of a conventional semiconductor device. As shown in Figure 13, in a conventional DFN package semiconductor device 900, the electrodes on the surface of a semiconductor chip 910 fixed to a mounting portion 901 with a conductive adhesive 920 are electrically connected to a plurality of leads 902 by conductive wires 930. A stepped portion 902a is formed at the corner between the lower surface 902b and the end face 902s of the lead 902. The sealing resin 940 forms the outer shape of the semiconductor device 900 such that at least a portion of a plurality of leads 902 is exposed. The mounting portion 901 and the plurality of leads 902 are made of a metallic material such as a copper alloy.

[0010] Figure 14 is an enlarged (schematic) view of section B in Figure 13 when a conventional semiconductor device is bonded to a mounting substrate. The lower surface 902b of the lead 902 is formed on the same plane as the lower surface 940b of the sealing resin 940. The metal film 950 is formed on the lower surface 902b of the lead 902. This metal film 150 is made of a material with good solder wettability and is bonded to the mounting substrate 980 by solder 970.

[0011] In conventional DFN packages as shown in Figures 13 and 14, the lower surface 902b of the lead 902 is generally formed almost flush with the lower surface 940b of the encapsulating resin, and the interface between the lower surface 902b of the lead 902 and the metal film 950 is flush with the lower surface 940b of the encapsulating resin. Furthermore, the lower surface of the metal film 950 protrudes slightly beyond the lower surface 940b of the encapsulating resin 940. As a result, solder 970 is formed on the end face 950d of the metal film 950.

[0012] In such a structure, when reliability tests are performed involving repeated high and low temperature changes, stress caused by the difference in thermal expansion coefficients between the lead 902, the encapsulating resin 940, and the mounting substrate 980 concentrates at the interface between the lower surface 902b of the lead 902 and the metal film 950. This stress may cause cracks to form at the interface between the lower surface 902b of the lead 902 and the metal film 950. The same applies to other non-lead type packages if the lower surface of the lead and the lower surface of the encapsulating resin are formed on approximately the same plane.

[0013] The present invention has been made in view of the circumstances described above, and one aspect of the present invention aims to provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate even in a leadless package. [Means for solving the problem]

[0014] The semiconductor device in one embodiment of the present invention is Semiconductor chips and In a plan view, a plurality of leads are arranged spaced apart around the semiconductor chip, An insulating material layer on which the semiconductor chip and the leads are mounted on the upper side, The upper surface of the insulating material layer, the semiconductor chip and the lead are sealed with a sealing resin, A metal film formed on a part of the lower surface of the lead, Equipped with, The lead has a part of its lower surface exposed from the lower surface of the insulating material layer, its side surface exposed from the side surface of the encapsulating resin, and has a stepped portion at the corner exposed from the lower surface of the insulating material layer and the side surface of the encapsulating resin. The metal film is formed on the lower surface of the lead and the stepped portion, which are exposed from the lower surface of the insulating material layer.

[0015] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: a step of mounting a semiconductor chip and a plurality of leads on the upper surface side of an insulating material layer; a step of electrically connecting the semiconductor chip and the leads respectively; a step of encapsulating the plurality of semiconductor chips and the leads with an encapsulating resin; a step of performing a half cut on the lead from the lower surface of the insulating material layer; a step of removing a part of the lower surface of the insulating material layer; a step of forming a metal film on the lead exposed from the lower surface of the insulating material layer; a step of fully cutting and separating the encapsulating resin and the lead along the locus of the half cut with a blade having a width narrower than the blade that performed the half cut; and includes the above steps.

Advantages of the Invention

[0016] According to one aspect of the present invention, it is possible to provide a semiconductor device having a lead that can ensure the bonding reliability with a mounting substrate even in a non-lead type package.

Brief Description of the Drawings

[0017] [Figure 1] It is a schematic top view (perspective view) of a semiconductor device according to the first embodiment of the present invention. [Figure 2] It is a schematic cross-sectional view taken along line II-II shown in FIG. 1. [Figure 3] It is a schematic cross-sectional view taken along line III-III shown in FIG. 1. [Figure 4]It is an enlarged view (schematic view) of part A in FIG. 2 when the semiconductor device in the first embodiment of the present invention is joined to a mounting substrate. [Figure 5] It is a diagram showing the manufacturing process of the semiconductor device in the first embodiment of the present invention. [Figure 6] Following FIG. 5, it is a diagram showing the manufacturing process of the semiconductor device in the first embodiment of the present invention. [Figure 7] Following FIG. 6, it is a diagram showing the manufacturing process of the semiconductor device in the first embodiment of the present invention. [Figure 8] It is a schematic cross-sectional view of the semiconductor device of Modification 1 in the first embodiment of the present invention. [Figure 9] It is a schematic cross-sectional view of the semiconductor device of Modification 2 in the first embodiment of the present invention. [Figure 10] It is a schematic top view (perspective view) of the semiconductor device in the second embodiment of the present invention. [Figure 11] It is a schematic cross-sectional view of line XI-XI shown in FIG. 10. [Figure 12] It is a schematic cross-sectional view of the semiconductor device in the third embodiment of the present invention. [Figure 13] It is a schematic side view (perspective view) of a conventional semiconductor device. [Figure 14] It is an enlarged view (schematic view) of part B in FIG. 13 when a conventional semiconductor device is joined to a mounting substrate.

Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals are given to the same constituent parts, and redundant explanations may be omitted.

[0019] Furthermore, the X, Y, and Z axes shown in the drawings are assumed to be orthogonal to each other. The Z-axis direction may be referred to as the "height direction" or "thickness direction." The +Z-axis direction may be referred to as "upward," and the -Z-axis direction as "downward." The +Z-side surface of each component may be referred to as the "front surface" or "top surface," and the -Z-side surface may be referred to as the "back surface" or "bottom surface." "Plan view" refers to viewing each component from the +Z-side toward the -Z-side. "Side view" refers to viewing each component by looking through it from the +Y-side toward the -Y-side.

[0020] Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not necessarily as shown. The quantity, position, shape, structure, and size of each component are not limited to the embodiments shown below, and may be adjusted to suit the purpose of implementing the present invention.

[0021] (First embodiment) Figure 1 is a schematic top view (perspective view) of a semiconductor device in the first embodiment of the present invention. As shown in Figure 1, the semiconductor device 100 in the first embodiment of the present invention includes a semiconductor chip 110, a plurality of leads 102, an insulating material layer 160, and a sealing resin 140.

[0022] The semiconductor chip 110 is a semiconductor chip that enables the semiconductor device 100 to function, and is mounted on the upper surface of the insulating material layer 160. The insulating material layer 160 is, for example, an insulating resin or an insulating substrate. When an insulating resin is used for the insulating material layer 160, a resin film may be used, or it may be formed by transfer.

[0023] The multiple leads 102 are arranged at a fixed distance apart on two opposing sides of the semiconductor chip 110 in the +X and -X directions, in a plan view. A portion of the multiple leads 102 on the semiconductor chip 110 side is mounted on the upper surface of the insulating material layer 160. In this embodiment, the multiple leads 102 are formed of a copper alloy and have an integrated lead frame structure. Figure 1 shows one semiconductor device that has been finally divided into individual pieces.

[0024] Multiple electrode pads (not shown) formed on the upper surface of a semiconductor chip 110 and the upper surfaces of multiple leads 102 are electrically connected by conductive wires 130. The upper surfaces of the leads 102 are formed as smooth surfaces. Therefore, the upper surfaces of the leads 102 can have a large area for forming second bonds with the conductive wires 130. This ensures a sufficient bonding area for wire bonding and suppresses a decrease in connection strength. The conductive wires 130 are, for example, gold wires or copper wires.

[0025] Figure 2 is a schematic cross-sectional view taken along line II-II shown in Figure 1. As shown in Figure 2, the lower surface 102b of the lead 102 is formed flush with the lower surface of the sealing resin 140. A portion of the lower surface 102b of the lead 102 is exposed from the lower surface of the insulating material layer 160, and the side surface 102s is exposed from the side surface 140s of the sealing resin 140. The lead 102 has a stepped portion 102a at the corner exposed from the lower surface of the insulating material layer 160 and the side surface 140s of the sealing resin 140. The lead 102 has a thickness t1, and the stepped portion 102a is formed to a depth t2 from the lower surface 102b of the lead 102.

[0026] The metal film 150 is continuously formed on a portion of the lower surface 102b and the stepped portion 102a of the lead 102 that is exposed from the lower surface of the insulating material layer 160. This metal film 150 functions as an external terminal. The thickness of the metal film 150 may be changed as appropriate. The material of the metal film 150 can be any material with good solder wettability, such as lead, bismuth, tin, copper, silver, palladium, gold, or alloys thereof.

[0027] Figure 3 is a schematic cross-sectional view taken along line III-III in Figure 1. As shown in Figure 3, the +Y and -Y sides of the lead 102 have a thin lower surface. This allows the sealing resin to fill the thin lower surface of the lead, preventing the lead 102 from falling out of the sealing resin 140.

[0028] Figure 4 is an enlarged (schematic) view of part A in Figure 2 when the semiconductor device according to the first embodiment of the present invention is bonded to a mounting substrate. The metal film 150 formed on the lower surface 102b of the lead 102 is bonded to the mounting substrate 180 by solder 170. At this time, since the end face 150d of the metal film 150 is formed adjacent to the insulating material layer 160, solder 170 is not formed on the end face 150d of the metal film 150.

[0029] As a result, stress caused by the difference in thermal expansion coefficients between the sealing resin 140 and the mounting substrate does not concentrate at the interface between the lower surface 102b of the lead 102 and the metal film 150. Therefore, this semiconductor device 100 can suppress the occurrence of cracks at the interface between the lead 102 and the metal film 150, and ensure the reliability of the bond with the mounting substrate.

[0030] The manufacturing method of the semiconductor device 100 will now be explained with reference to Figures 5 to 7.

[0031] As shown in Figure 5, a plurality of leads 102 and a semiconductor chip 110 are fixed to the upper surface of an insulating material layer 160. Then, a plurality of electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 and the upper surfaces of the plurality of leads 102 are electrically connected with conductive wires 130. In this embodiment, the plurality of leads 102 are formed of a copper alloy and have an integrated lead frame structure.

[0032] Subsequently, the lead frame is sandwiched between two molds (not shown), and sealing resin is injected into the molds and allowed to solidify to seal it.

[0033] Next, as shown in Figure 6, a stepped portion 102a is formed to a predetermined depth t2 from the lower surface 102b of the lead 102 by a first cutting using a dicing device. The first cutting cuts the stepped portion 102a to a depth t2 ranging from 20% to 95% of the thickness t1 of the lead 102. After that, a portion of the insulating material layer 160 is removed, exposing a portion of the lower surface 102b of the lead 102.

[0034] Next, as shown in Figure 7, a metal film 150 is formed on the lower surface 102b and the stepped portion 102a of the lead 102 exposed from the sealing resin 140 by electroplating. At this time, the end face 150d of the metal film 150 is formed adjacent to the insulating material layer 160.

[0035] Subsequently, the semiconductor device 100 is manufactured by cutting the lead 102 and the sealing resin 140 at predetermined positions using a dicing device in a second cutting process, thereby separating them into individual pieces. At this time, the blade width of the dicing device used in the second cutting process is narrower than the blade width used in the first cutting process. This forms the side surface 140s of the sealing resin 140 and the side surface 102s of the lead 102.

[0036] As described above, in this embodiment, the semiconductor device 100 has an end face 150d of the metal film 150 formed adjacent to the insulating material layer 160. Therefore, when the lead 102 is joined to the mounting substrate with solder, solder 170 is not formed on the end face 150d of the metal film 150. As a result, stress caused by the difference in thermal expansion coefficients between the lead 102, the sealing resin 140, and the mounting substrate does not concentrate at the interface between the lead 102 and the metal film 150. Therefore, the occurrence of cracks at the interface between the lead 102 and the metal film 150 can be suppressed, and the reliability of the joint with the mounting substrate can be ensured even in a leadless type package.

[0037] (Modification 1 of the first embodiment) Figure 8 is a schematic cross-sectional view of a semiconductor device in a modified example 1 of the first embodiment of the present invention. As shown in Figure 8, in Modification 1 of the First Embodiment of the present invention, the semiconductor device 200 has leads 202 of the semiconductor chip 110 in the -X direction with a length L1, and leads 202 of the semiconductor chip 110 in the +X direction with a length L2 which is longer than length L1. A portion of the multiple leads 202 on the semiconductor chip 110 side is mounted on the upper surface of the insulating material layer 160. The metal film 250 is formed to be identical on a portion of the lower surface 202b of the leads 202 in the +X direction of the semiconductor chip 110 and on a portion of the lower surface 202b of the leads 202 in the -Y direction of the semiconductor chip 110. Otherwise, it is the same as the semiconductor device 100.

[0038] Thus, in this embodiment, because the lead 202 is mounted on the upper surface of the insulating material layer 260, even if the length of the lead is increased, the lead will not detach from the sealing resin, and the length of the lead can be increased while maintaining the same thickness.

[0039] (Modification 2 of the first embodiment) Figure 9 is a schematic cross-sectional view of a semiconductor device in a modified example 2 of the first embodiment of the present invention. As shown in Figure 9, the semiconductor device 300 of Modification 2 of the first embodiment of the present invention is the same as Modification 1 of the first embodiment, except that a recess 302r is formed on a part of the lower surface of the lead 302. The recess 302r is structured in such a way that the sealing resin 340 fits inside.

[0040] Thus, in this embodiment, the semiconductor device 300 allows for free design of the shape of the lead 202 because the lead 202 is mounted on the upper surface of the insulating material layer 160 and the sealing resin 340 fills the recess 302r on the lower surface of the lead 302.

[0041] (Second embodiment) Figure 10 is a schematic top view (perspective view) of a semiconductor device in a second embodiment of the present invention. As shown in Figure 10, the semiconductor device 400 in the second embodiment of the present invention has a semiconductor chip mounting portion 401 on the upper surface of an insulating material layer 460. The suspension portion 403 extends from two sides of the mounting portion 401 in the +Y direction and the -Y direction.

[0042] Figure 11 is a schematic cross-sectional view along the line XI-XI shown in Figure 10. As shown in Figure 11, the semiconductor chip 110 is mounted on the upper surface of the mounting section 401, fixed with conductive adhesive 420. A portion of the lower surface of the mounting section 401 is exposed from the lower surface of the insulating material layer 460, improving its function as a heat sink. In this embodiment, the mounting section 401, the multiple leads 402, and the suspension section 403 are formed from the same copper alloy material and have an integrated lead frame structure.

[0043] The metal film 450 is formed on a portion of the lower surface of the mounting portion 401 that is exposed from the lower surface of the insulating material layer 460, and on a portion of the lower surface 402b and the stepped portion 402a of the lead 402. In this way, because the end face 450d of the metal film 450 is formed adjacent to the insulating material layer 460, when the lead 402 and the mounting portion 401 are joined to the mounting substrate with solder or the like, no solder is formed on the end face 450d of the metal film 450.

[0044] In the configurations shown in Figures 10 and 11, stress concentration at the interface between the lower surface 402b of the lead 402 and the metal film 450 can be suppressed. In addition, when connecting the mounting portion 201 to the mounting substrate, stress concentration at the interface between the lower surface of the mounting portion 201 and the metal film 450 can be suppressed. Therefore, this semiconductor device 400 can suppress the occurrence of cracks at the interface between the lead 402 and the metal film 450, and at the interface between the lower surface of the mounting portion 401 and the metal film 450.

[0045] Therefore, the semiconductor device 400 in the second embodiment of the present invention can ensure reliable bonding with the mounting substrate even if it is in a leadless package.

[0046] (Third embodiment) Figure 12 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. As shown in Figure 12, the semiconductor device 500 in the third embodiment of the present invention is the same as in the first embodiment of the present invention, except that a groove 590 is provided on the lower surface of the sealing resin 540 adjacent to the semiconductor chip end face 102d of the lead 102, and a metal film 550 is formed on a part of the end face 102d.

[0047] In the configuration shown in Figure 12, since the end face 550d of the metal film 550 is formed adjacent to the encapsulating resin 540, when the lead 102 is joined to the mounting substrate with solder, no solder is formed on the end face 550d of the metal film 550. As a result, stress caused by the difference in thermal expansion coefficients between the lead 102, the encapsulating resin 540, and the mounting substrate does not concentrate at the interface between the lead 102 and the metal film 550. Therefore, the occurrence of cracks at the interface between the lead 102 and the metal film 550 can be suppressed, and the reliability of the bond with the mounting substrate can be ensured even in a leadless type package.

[0048] Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment and also includes designs and the like that do not depart from the spirit of the invention.

[0049] For example, in this embodiment, the semiconductor device is packaged as a DFN package, but it is not limited to this, and other packages may be used. Also, although conductive wires are used for the electrical connection between the leads and the semiconductor chip, a flip-chip configuration using bumps formed on the upper surface of the semiconductor chip for the electrical connection between the leads and the semiconductor chip may also be used.

[0050] Furthermore, while the lead frame is made of a copper alloy, it is not limited to this material and may be made of other materials. Although the metal film is formed using electroplating, electroless plating may also be used. [Explanation of Symbols]

[0051] 100, 200, 300, 400, 500, 900 fighter jets 401, 901 mounting section (semiconductor chip mounting section) 102, 202, 302, 402, 902 leads 102a, 402a, 902a Stepped section 102b, 202b, 302b, 902b Underside (Underside of the reed) 102s, 402s, 902s Side view (side of the reed) 102d End face (end face of the lead) 302r recess 403 Suspension section 110, 910 semiconductor chips 420, 920 conductive adhesive 130, 930 conductive wire 140, 240, 340, 540, 940 Sealing resin 140s Side view (side view of the sealing resin) 940b Bottom surface (bottom surface of the sealing resin) 150, 250, 350, 450, 550, 950 Metal film 150d, 450d, 550d, 950d end faces (end faces of metal films) 160, 260, 360, 460, 560 insulating material layer 170, 970 solder 180, 980 mounted circuit board 590 Groove t1 Lead thickness t2 Depth (depth of the step from the bottom surface of the reed) L1, L2 Length (Lead length)

Claims

1. Semiconductor chips and In a plan view, a plurality of leads are arranged spaced apart around the semiconductor chip, An insulating material layer on which the semiconductor chip and the leads are mounted on the upper side, The upper surface of the insulating material layer, the semiconductor chip and the lead are sealed with a sealing resin, A metal film formed on a part of the lower surface of the lead, Equipped with, The lead has a portion of its lower surface exposed from the lower surface of the insulating material layer, a side surface exposed from the side surface of the sealing resin, and a stepped portion at the corner exposed from the lower surface of the insulating material layer and the side surface of the sealing resin. The semiconductor device is characterized in that the metal film is formed on the lower surface of the lead exposed from the lower surface of the insulating material layer and on the stepped portion.

2. The semiconductor device according to claim 1, wherein the semiconductor chip and the lead are connected by a conductive wire.

3. The sealing resin has a groove formed in a part of its lower surface adjacent to the end face of the lead on the semiconductor chip side. A portion of the end face of the lead is exposed from the sealing resin. The semiconductor device according to claim 1, wherein the metal film is further formed on the end face of the lead exposed from the sealing resin.

4. The semiconductor chip and the insulating material layer have a mounting portion, A portion of the lower surface of the mounting portion is exposed from the lower surface of the insulating material layer, The semiconductor device according to any one of claims 1 to 3, wherein the metal film is further formed on the lower surface of the mounting portion that is exposed from the lower surface of the insulating material layer.

5. A process of mounting a semiconductor chip and multiple leads on the upper surface of an insulating material layer, A step of electrically connecting the semiconductor chip and the lead, A step of sealing the plurality of semiconductor chips and the leads with a sealing resin, A step of performing a half-cut of the lead from the lower surface of the insulating material layer, A step of removing a portion of the lower surface of the insulating material layer, A step of forming a metal film on the lead exposed from the lower surface of the insulating material layer, A step of fully cutting the sealing resin and the lead along the trajectory of the half-cut using a blade narrower than the blade used for the half-cut, thereby separating them into individual pieces. A method for manufacturing a semiconductor device, characterized by comprising the above.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of forming a groove in a part of the lower surface of the sealing resin after the step of removing a part of the lower surface of the insulating material layer.

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