Etching method, method for manufacturing semiconductor device, and etching apparatus

Abstract

This invention provides an etching method using HF gas as a catalyst. [Solution] According to the embodiment, the etching method includes the steps of: providing a catalyst layer 2 on a substrate 1 mainly composed of silicon; exposing the substrate 1 on which the catalyst layer 2 is provided to an HF gas atmosphere; and etching the substrate 1 in contact with the catalyst layer 2 by irradiating the substrate 1 in the HF gas atmosphere with light.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to an etching method, a method for manufacturing a semiconductor device, and an etching apparatus. [Background technology]

[0002] One method for etching silicon is reactive ion etching (RIE). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-118849 [Patent Document 2] Japanese Patent Publication No. 2024-118858 [Non-patent literature]

[0004] [Non-Patent Document 1] Ko-hei Sano. at el, “Atmospheric Gas-Phase Catalyst Etching of SiO2 for Deep Microfabrication Using HF Gas and Patterned Photoresist”, ACS Appl. Mater. Interfaces 2024, 16, p. 22657 - 22664. [Non-Patent Document 2] V. Lehmann, “The Physics of Macropore Formation in Low Doped n-Type Silicon”, J. Electrochem. Soc., Vol. 140, No. 10, October 1993, p. 2836 - 2843. [Non-Patent Document 3] Jeung Ku Kang, at el, “The mechanism of HF / H2O chemical etching of SiO2”, JOURNAL OF CHEMICAL PHYSICS, VOLUME 116, NUMBER 1, 1 JANUARY 2002, p. 275 - 280. [Non-Patent Document 4] V. Lehmann, “POROUS SILICON - A NEW MATERIAL FOR MEMS”, IEEE ISBN: 0-7803-2985-6 / 96, 1996, p. 1 - 6. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] One embodiment of the present invention provides an etching method using HF gas as a catalyst. [Means for solving the problem]

[0006] The etching method according to the embodiment includes the steps of: providing a catalyst layer on a substrate mainly composed of silicon; exposing the substrate on which the catalyst layer is provided to an HF gas atmosphere; and etching the substrate in contact with the catalyst layer by irradiating the substrate in the HF gas atmosphere with light. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic diagram illustrating the etching method for silicon oxide and silicon according to the first embodiment. [Figure 2] Flowchart of catalytic etching of silicon oxide and silicon according to the first embodiment. [Figure 3] A schematic diagram showing each step of the catalytic etching of silicon oxide and silicon in the etching method according to the first embodiment. [Figure 4] This figure schematically shows each step of pattern formation of the catalyst layer in the etching method according to the first embodiment, when the resist does not contain a catalyst. [Figure 5] A block diagram showing an example of the overall configuration of a semiconductor device manufactured using the etching method according to the first embodiment. [Figure 6] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor device manufactured using the etching method according to the first embodiment. [Figure 7] A cross-sectional view showing an example of the cross-sectional structure of a semiconductor device manufactured using the etching method according to the first embodiment. [Figure 8] A cross-sectional view of the region RA in FIG. 7. [Figure 9] A cross-sectional view showing an example of the cross-sectional structure of a cell region of a memory cell array included in a semiconductor device manufactured using the etching method according to the first embodiment. [Figure 10] A cross-sectional view taken along the line X-X of FIG. 9. [Figure 11] A flowchart showing an example of a method for manufacturing a semiconductor device using the etching method according to the first embodiment. [Figure 12] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 13] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 14] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 15] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 16] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 17] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 18] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 19] A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 20]A cross-sectional view showing the manufacturing process of a semiconductor device using the etching method according to the first embodiment. [Figure 21] A diagram showing an example of the configuration of an etching apparatus used for catalyst etching according to the second embodiment. [Modes for carrying out the invention]

[0008] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be given a common reference numeral. When multiple components having a common reference numeral need to be distinguished, a subscript will be added to the common reference numeral to distinguish them. When there is no particular need to distinguish between multiple components, only the common reference numeral will be assigned to those components, and no subscript will be added. Here, the subscript is not limited to subscripts or superscripts, but also includes, for example, lowercase alphabet letters added to the end of the reference numeral, and indices indicating arrangement.

[0009] 1. First Embodiment 1.1 Etching methods for silicon oxide and silicon First, referring to Figure 1, we will explain the etching methods for silicon oxide (SiO) and silicon (Si) as examples. Figure 1 is a schematic diagram showing the etching methods for silicon oxide and silicon.

[0010] In this embodiment, a catalyst-based etching method (hereinafter also referred to as "catalytic etching") is described as one method for etching silicon oxide and silicon. Note that the materials to be etched using catalysts are not limited to silicon oxide and silicon. For example, catalyst etching can also be applied to silicon nitride (SiN).

[0011] As shown in the upper part of Figure 1, for example, when catalytic etching silicon oxide 3 formed on a silicon substrate 1, a pattern of catalyst layer 2 is formed on the upper surface of silicon oxide 3. The silicon substrate 1 is a substrate mainly composed of silicon, for example, a silicon wafer. The silicon substrate 1 may contain impurities. The silicon oxide 3 is a layer containing silicon and oxygen. For catalyst layer 2, a material that hydrogen bonds with hydrogen fluoride (HF) gas is used as a catalytic reaction. For example, the hydroxyl group (-OH) of phenol hydrogen bonds with HF. In the following description, we will describe the case where catalyst layer 2 is a novolac resin containing phenol. For example, in photolithography using g-line or i-line, a resist containing novolac resin may be used. For example, when a resist containing novolac resin is used as catalyst layer 2, a pattern of catalyst layer 2 can be formed by photolithography. Note that the functional group that hydrogen bonds with HF is not limited to the hydroxyl group (-OH). Furthermore, the catalyst layer 2 is not limited to novolac resin. Details of materials other than novolac resin for the catalyst layer 2 will be described later.

[0012] When a silicon substrate 1, on which a catalyst layer 2 is formed and silicon oxide 3 is provided, is exposed to an HF gas atmosphere, the catalyst layer 2 forms hydrogen bonds with HF in the HF gas. In hydrogen-bonded HF molecules, the interatomic distance between H and F is wider than in the normal state. HF molecules with a wider interatomic distance between H and F are more reactive than HF molecules in the normal state. Therefore, the silicon oxide 3 in contact with the catalyst layer 2 is preferentially etched by HF. As the catalyst layer 2 settles through the etched silicon oxide 3, the silicon oxide 3 is anisotropically etched. The reaction equation between silicon oxide (SiO2) and HF in this case is shown in equation (1). SiO2 + 4HF → SiF4 + 2H2O (1)

[0013] As shown in the lower part of Figure 1, for example, when catalytic etching a silicon substrate 1, a pattern of catalyst layer 2 is formed on the upper surface of the silicon substrate 1. The material of catalyst layer 2 is the same as when catalytic etching silicon oxide 3. Note that silicon oxide 3 and silicon substrate 1 may be etched continuously. Also, a layer different from silicon oxide 3 and silicon substrate 1 may be formed between silicon oxide 3 and silicon substrate 1.

[0014] When silicon is etched with HF gas, etching proceeds relatively easily when holes (positive pores) are supplied, as shown in the reaction equation (2). Si + 4(h + ) + 4HF → SiF4 + 4H + (2)

[0015] Here, h + H indicates a hole. + This represents a hydrogen ion.

[0016] The SiF4 produced by equation (2) proceeds to the reaction shown in equation (3). SiF4 + 2HF → H2SiF6(3)

[0017] As a result of the reactions shown in equations (2) and (3), silicon in contact with the catalyst layer 2 is etched preferentially over silicon not in contact with the catalyst layer 2.

[0018] In this embodiment, ultraviolet (UV) light is irradiated from the back surface of the silicon substrate 1 to create holes h in the silicon substrate 1. + This generates [something]. Note that the light (electromagnetic wave) irradiated onto the silicon substrate 1 is not limited to UV light. The light irradiated onto the silicon substrate 1 can have a wavelength of 1100 nm or less. Therefore, the light that can be irradiated onto the silicon substrate 1 includes visible light. If the light has a wavelength of 1100 nm or less, the holes h + It can generate holes h generated by UV light irradiation. + It diffuses within the silicon substrate 1 and reaches the interface between the catalyst layer 2 and the silicon substrate 1.

[0019] In this state, when the silicon substrate 1 on which the catalyst layer 2 is formed is exposed to an HF gas atmosphere, the catalyst layer 2 forms hydrogen bonds with HF. The HF molecules, with their increased interatomic distance between H and F, preferentially etch the silicon in contact with the catalyst layer 2. As the catalyst layer 2 settles within the etched silicon substrate 1, the silicon substrate 1 undergoes anisotropic etching.

[0020] Catalyst layer 2 can be any material whose functional group forms hydrogen bonds with HF as a catalytic reaction. Catalyst layer 2 has at least one of the following functional groups that form hydrogen bonds with HF: a hydroxyl group (-OH), a carboxyl group (-COOH), an amino group (-NH2), an amide group (-CONH2), a nitro group (-NO2), or an ether group (-O-).

[0021] The catalyst layer 2, which has hydroxyl groups (-OH) excluding phenol, includes at least one of the following: polyvinyl alcohol (PVA:Poly(vinyl alcohol)), polyhydroxyethyl methacrylate (PHEMA:Poly(hydroxyethyl methacrylate)), polyhydroxystyrene (PHS:Poly(hydroxystyrene)), vinyl acetate-vinyl alcohol copolymer (PVAc-Vac:Poly(vinyl acetate-co-vinyl alcohol)), and 4-hydroxystyrene-methyl methacrylate copolymer (PHS-MMA:Poly(4-hydroxystyrene-co-methyl methacrylate)).

[0022] The catalyst layer 2 having a carboxyl group (-COOH) is made of polymethacrylic acid (PMAA), polyacrylic acid (PAA), polyitaconic acid (PIA), styrene-maleic acid copolymer (PSMA), poly-vinylbenzoic acid (PVBA), poly-acryloylbenzoic acid (PABA), poly-carboxystyrene (PCS), ethylene glycol monomethacrylate-co-methacrylic acid copolymer (PEGMA-MAA), and ethylene glycol monomethacrylate-co-acrylic acid copolymer (PEGMA-AA). It comprises at least one of the following: (a) and ethylene glycol monomethacrylate-itaconic acid copolymer (PEGMA-IA:Poly(ethylene glycol monomethacrylate-co-itaconic acid)).

[0023] The catalyst layer 2 having an amino group (-NH2) is composed of poly(4-aminostyrene) (PAS), polyallylamine (PAA), polyethyleneimine (PEI), poly(2-aminoethyl methacrylate) (PAEMA), polyvinylamine (PVAm), poly(3-aminophenylboronic acid) (PAPBA), poly(2-aminoethyl acrylate) (PAEA), poly(4-vinylbenzylamine) (PVBA), poly(N,N-dimethylaminoethyl methacrylate) (PDMAEMA), and allylamine-acrylic acid copolymer (PAA-AA). It contains at least one of the following:

[0024] The catalyst layer 2 having an amide group (-CONH2) is made of polyacrylamide (PAM), poly(N-isopropylacrylamide) (PNIPAM), N-vinylpyrrolidone-acrylamide copolymer (PVP-AAm), poly(N,N-dimethylacrylamide) (PDMA), acrylamide-methacrylic acid copolymer (PAM-MAA), poly(acrylamide-co-methacrylic acid) (PPAM), and acrylamide-acrylic acid copolymer (PAM-AA). It comprises at least one of the following: acid), poly(N-(2-hydroxyethyl)acrylamide (PHEA), poly(N-acryloyl glycine) (PAG), and poly(N-methacryloyl glycine) (PMAG).

[0025] The catalyst layer 2 having a nitro group (-NO2) is made of poly(2-nitrobenzyl methacrylate) (PNBMA), poly(2-nitrobenzyl acrylate) (PNBA), poly(4-nitrobenzyl methacrylate) (PNBMA), poly(4-nitrobenzyl acrylate) (PNBA), poly(2-nitrobenzyl methacrylamide) (PNBMAm), poly(2-nitrobenzyl acrylamide) (PNBAm), and poly(4-nitrobenzyl methacrylamide) (PNBMAm). It comprises at least one of methacrylamide, poly(4-nitrobenzyl acrylamide) (PNBAm), poly(2-nitrobenzyl vinyl ether) (PNBVE), and poly(4-nitrobenzyl vinyl ether) (PNBVE).

[0026] The catalyst layer 2 having an ether group (-O-) contains at least one of the following: polyethylene glycol (PEG:Poly(ethylene glycol)), polypropylene glycol (PPG:Poly(propylene glycol)), polyethylene oxide (PEO:Poly(ethylene oxide)), polypropylene oxide (PPO:Poly(propylene oxide)), polyethylene glycol dimethacrylate (PEGDMA:Poly(ethylene glycol dimethacrylate)), polypropylene dimethacrylate (PPGDMA:Poly(propylene glycol dimethacrylate)), polyethylene glycol methacrylate (PEGMA:Poly(ethylene glycol methacrylate)), polypropylene glycol methacrylate (PPGMA:Poly(propylene glycol methacrylate)), ethylene oxide-propylene oxide copolymer (PEO-PPO:Poly(ethylene oxide-co-propylene oxide)), and polyethylene glycol vinyl ether (PEGVE:Poly(ethylene glycol vinyl ether)).

[0027] Furthermore, catalyst layer 2 may contain polyvinylphenol (PVP) or naphthol novolac. In addition, catalyst layer 2 may contain diazonaphthoquinone-diazido (NQD).

[0028] 1.2 Catalytic etching process when etching silicon oxide and silicon Next, the catalytic etching process for silicon oxide and silicon will be explained with reference to Figures 2 and 3. Figure 2 is a flowchart of the catalytic etching of silicon oxide and silicon. Figure 3 is a schematic diagram showing each step of the catalytic etching of silicon oxide and silicon.

[0029] In the catalytic etching of silicon oxide and silicon, steps S1 to S6 shown in Figure 2 are executed sequentially. Each step will be explained in turn.

[0030] <Step S1> As shown in Figure 3(a), first, a pattern for the catalyst layer 2 is formed on the silicon oxide 3. For example, the catalyst layer 2 is a g-line (or i-line) resist containing a novolac resin. In this case, the resist mask formed by photolithography functions as the catalyst layer 2.

[0031] <Step S2> Next, the supply of HF gas to silicon oxide 3 and silicon substrate 1 is started. That is, silicon oxide 3 is exposed to an HF gas atmosphere.

[0032] <Step S3> As shown in Figure 3(b), the silicon oxide 3 in contact with the catalyst layer 2 is etched in an HF atmosphere. After etching of the silicon oxide 3, the bottom surface of the catalyst layer 2 is in contact with the silicon substrate 1. That is, at this stage, the catalyst layer 2 is provided on the silicon substrate 1.

[0033] <Step S4> As shown in Figure 3(c), UV light irradiation of the silicon substrate 1 is started in an HF atmosphere with the catalyst layer 2 placed on the silicon substrate 1. This creates holes h in the silicon substrate 1. + This is generated.

[0034] <Step S5> As shown in Figure 3(d), the silicon substrate 1 in contact with the catalyst layer 2 is etched in an HF atmosphere.

[0035] <Step S6> Finally, catalyst layer 2 is removed, and the catalyst etching process is complete.

[0036] In the flowchart shown in Figure 2, the case where UV light irradiation in step S4 is started after etching of silicon oxide 3 in step S3 is explained. However, the timing of starting UV light irradiation may be simultaneous with the start of HF supply in step S2, or it may be during the etching of silicon oxide 3.

[0037] 1.3 Patterning of the catalyst layer when the resist does not contain the catalyst layer material Next, with reference to Figure 4, an example of pattern formation of catalyst layer 2 when the resist does not contain the material for catalyst layer 2 will be described. Figure 4 is a schematic diagram showing each step of pattern formation of the catalyst layer when the resist does not contain the catalyst.

[0038] In step S1, as explained using Figure 2, the actions (a1) to (a3) ​​in Figure 4 are performed in order.

[0039] As shown in Figure 4(a1), first, a catalyst layer 2 is deposited on silicon oxide 3. For example, catalyst layer 2 is SOC (Spin on Carbon). Next, SOG (Spin on Glass) 4 is deposited on catalyst layer 2. SOG 4 functions as a mask when etching catalyst layer 2. Then, a resist 5 is applied and a pattern of resist 5 is formed by photolithography using an ArF excimer laser.

[0040] As shown in Figure 4(a2), the SOG4 and catalyst layer 2 are then etched using the resist 5 as a mask.

[0041] As shown in Figure 4(a3), when the resist 5 and SOG4 are removed, the pattern of the catalyst layer 2 is formed. The subsequent operations are the same as steps S2 to S6 described using Figure 2. With this method, a finer pattern of the catalyst layer 2 can be formed than when, for example, a g-line or i-line resist containing novolac resin is used.

[0042] 1.4 Examples of application to the manufacturing method of semiconductor devices Next, an example of applying catalytic etching to a semiconductor device manufacturing method will be described. In this example, the semiconductor device is a three-dimensional stacked NAND flash memory. The following describes the case where catalytic etching of this embodiment is applied to the dicing process of a NAND flash memory. Note that the semiconductor device is not limited to a NAND flash memory. Furthermore, catalytic etching can be applied to processes other than dicing.

[0043] 1.4.1 Overall configuration of semiconductor device First, an example of the overall configuration of the semiconductor device 50 will be described with reference to Figure 5. Figure 5 is a block diagram showing an example of the overall configuration of the semiconductor device 50. Note that in Figure 5, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0044] As shown in Figure 5, the semiconductor device 50 includes an array chip 10 and a circuit chip 20. The semiconductor device 50 has a structure in which the array chip 10 and the circuit chip 20 are bonded together (hereinafter referred to as the "bonded structure"). However, the semiconductor device 50 does not have to have a bonded structure. The semiconductor device 50 may also have a structure in which the circuit and memory cell array are formed on a semiconductor substrate.

[0045] The array chip 10 is a chip on which an array of non-volatile memory cell transistors is provided. The circuit chip 20 is a chip on which a circuit for controlling the array chip 10 is provided. Note that multiple array chips 10 may be provided. In this case, multiple array chips 10 may be bonded together so as to be stacked on the circuit chip 20.

[0046] The array chip 10 includes one or more memory cell arrays 11. The memory cell array 11 is a region in which non-volatile memory cell transistors are arranged in three dimensions. In the example shown in Figure 5, the array chip 10 includes one memory cell array 11.

[0047] The circuit chip 20 includes a sequencer 21, a voltage generation circuit 22, a low decoder 23, and a sense amplifier 24.

[0048] The sequencer 21 is the control circuit for the semiconductor device 50. For example, the sequencer 21 is connected to the voltage generation circuit 22, the row decoder 23, and the sense amplifier 24. The sequencer 21 controls the voltage generation circuit 22, the row decoder 23, and the sense amplifier 24. The sequencer 21 also controls the overall operation of the semiconductor device 50 based on the control of an external controller. More specifically, the sequencer 21 performs write operations, read operations, erase operations, etc.

[0049] The voltage generation circuit 22 is a circuit that generates voltages used for writing, reading, and erasing operations. For example, the voltage generation circuit 22 is connected to the row decoder 23 and the sense amplifier 24. The voltage generation circuit 22 supplies the generated voltage to the row decoder 23 and the sense amplifier 24, etc.

[0050] The row decoder 23 is a circuit that decodes row addresses. A row address is an address signal that specifies the row-direction wiring (word lines and selection gate lines, described later) of the memory cell array 11. Based on the decoding result of the row address, the row decoder 23 supplies the voltage applied from the voltage generation circuit 22 to the memory cell array 11.

[0051] The sense amplifier 24 is a circuit that performs data writing and reading. During a read operation, the sense amplifier 24 senses the data read from the memory cell array 11. During a write operation, the sense amplifier 24 supplies a voltage to the memory cell array 11 corresponding to the data to be written.

[0052] Next, the internal structure of the memory cell array 11 will be described. The memory cell array 11 has multiple block BLKs. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased all at once. The multiple memory cell transistors within a block BLK are mapped to rows and columns. In the example shown in Figure 5, the memory cell array 11 includes four blocks BLK0, BLK1, BLK2, and BLK3.

[0053] Each block BLK contains multiple string units SU. A string unit SU is a collection of multiple NAND strings that are selected together, for example, during a write or read operation. A NAND string contains multiple memory cell transistors connected in series. In the example shown in Figure 5, each block BLK contains four string units SU0, SU1, SU2, and SU3. The number of block BLKs and the number of string units SUs contained in each block BLK are arbitrary.

[0054] 1.4.2 Circuit configuration of memory cell array Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to Figure 6. Figure 6 is a circuit diagram showing an example of the circuit configuration of the memory cell array 11. The example shown in Figure 6 shows the circuit diagram of one block BLK.

[0055] As shown in Figure 6, the string unit SU contains multiple NAND strings NS. Each of the multiple NAND strings NS within the string unit SU is connected to one of the bit lines BL0 to BLm (where m is an integer greater than or equal to 1).

[0056] The NAND string NS includes multiple memory cell transistors MC and selection transistors ST1 and ST2. In the example shown in Figure 6, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0057] A memory cell transistor (MC) is a memory element that stores data non-volatilely. The MC includes a control gate and a charge storage film. The MC may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage film. The FG type uses a conductor for the charge storage film. The following description will focus on the case where the memory cell transistor (MC) is of the MONOS type.

[0058] The selection transistors ST1 and ST2 are switching elements. They are used to select the string unit SU during various operations.

[0059] The current paths of the selection transistor ST2, memory cell transistors MC0~MC7, and selection transistor ST1 within the NAND string NS are connected in series. The drain of selection transistor ST1 is connected to the bit line BL. The source of selection transistor ST2 is connected to the source line SL.

[0060] The control gates of memory cell transistors MC0 to MC7 within the same block BLK are connected in common to word lines WL0 to WL7. More specifically, for example, block BLK contains four string units SU0 to SU3, and each string unit SU contains multiple memory cell transistors MC0. The control gates of multiple memory cell transistors MC0 within block BLK are connected in common to a single word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0061] The gates of multiple selection transistors ST1 within a string unit SU are connected in common to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within a string unit SU0 are connected in common to selection gate line SGD0. The gates of multiple selection transistors ST1 within a string unit SU1 are connected in common to selection gate line SGD1. The gates of multiple selection transistors ST1 within a string unit SU2 are connected in common to selection gate line SGD2. The gates of multiple selection transistors ST1 within a string unit SU3 are connected in common to selection gate line SGD3.

[0062] The gates of multiple selection transistors ST2 within block BLK are connected in common to the selection gate line SGS.

[0063] Word lines WL0 to WL7, selection gate lines SGD0 to SGD3, and selection gate line SGS are connected to the row decoder 23, respectively.

[0064] The bit lines BL are connected in common to one NAND string NS within each string unit SU of each block BLK. Each bit line BL is connected to the sense amplifier 24.

[0065] Source lines SL are shared, for example, between multiple block lines BLK.

[0066] 1.4.3 Cross-sectional structure of semiconductor device Next, an example of the cross-sectional structure of the semiconductor device 50 will be described with reference to Figure 7. Figure 7 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 50.

[0067] In the following explanation, the plane on which the circuit chip 20 and the array chip 10 are bonded together is referred to as the XY plane. The directions that are orthogonal to each other on the XY plane are referred to as the X direction and the Y direction. The direction that is approximately perpendicular to the XY plane and moves from the array chip 10 toward the circuit chip 20 is referred to as the Z1 direction. The direction that is approximately perpendicular to the XY plane and moves from the circuit chip 20 toward the array chip 10 is referred to as the Z direction. If neither the Z1 direction nor the Z2 direction is specified, it will be referred to as the Z direction.

[0068] As shown in Figure 7, the semiconductor device 50 includes an array chip 10, a circuit chip 20, and a spacer 301.

[0069] The semiconductor device 50 of this embodiment has a bonded structure in which an array chip 10 and a circuit chip 20 are bonded together. Hereinafter, the surface on which the array chip 10 and the circuit chip 20 are bonded together will be referred to as the "bonded surface BS".

[0070] For example, the area of ​​the array chip 10 on the bonding surface BS is smaller than the area of ​​the circuit chip 20. In such a case, the surface of the circuit chip 20 facing the Z2 direction is provided with a region R1 to which the array chip 10 is bonded and a region R2 to which the spacer 301 is formed.

[0071] The circuit chip 20 includes a semiconductor substrate 201, an insulating layer 211, a transistor region TRR, a wiring layer region IR, a plurality of bonding pads BP2, and a bonding pad WP.

[0072] The semiconductor substrate 201 is, for example, a silicon substrate or a silicon wafer.

[0073] The transistor region TRR is provided on the surface of the semiconductor substrate 201 facing the Z2 direction. Multiple transistors constituting multiple circuits are provided in the transistor region TRR. In other words, multiple transistors are provided on the semiconductor substrate 201.

[0074] The wiring layer region IR is a region in which multiple wiring layers are provided, connecting the transistor region TRR to the bonding pad BP2 or the bonding pad WP. The wiring layer region IR is provided between the transistor region TRR and the bonding pad BP2 and the bonding pad WP.

[0075] The bonding pad BP2 is provided such that the surface facing the Z2 direction is exposed to the bonding surface BS. In other words, the surface of the bonding pad BP2 facing the Z2 direction is exposed from the insulating layer 211. The bonding pad BP2 is bonded to the bonding pad BP1 provided on the array chip 10. The bonding pad BP2 contains, for example, copper (Cu).

[0076] The bonding pad WP is provided inside the insulating layer 211. An opening region of the bonding pad WP is provided in region R2. In the opening region, a portion of the surface of the bonding pad WP facing the Z2 direction is exposed. The bonding pad WP functions as an external connection terminal that is electrically connected to other chips or substrates. For example, a bonding wire BW is connected to the bonding pad WP. The bonding pad WP contains a conductive metal such as aluminum (Al).

[0077] The insulating layer 211 is provided on the surface of the semiconductor substrate 201 facing the Z2 direction. For example, the insulating layer 211 covers the transistor region TRR and the wiring layer region IR. The insulating layer 211 contains silicon oxide.

[0078] The array chip 10 includes a laminate SB, an insulating layer 110, and a plurality of adhesive pads BP1.

[0079] The stacked SB has a structure in which multiple wiring layers and multiple insulating layers are stacked alternately, one layer at a time. The stacked SB corresponds to one memory cell array 11. In the example shown in Figure 7, the array chip 10 includes two stacked SBs, i.e., two memory cell arrays 11. Details of the structure of the stacked SB (memory cell array 11) will be described later.

[0080] The bonding pad BP1 is provided such that its surface facing the Z1 direction is exposed to the bonding surface BS. In other words, the surface of the bonding pad BP2 facing the Z1 direction is exposed from the insulating layer 110. For example, the bonding pad BP1 is electrically connected to the memory cell array 11 provided on the laminate SB. The bonding pad BP1 is bonded to the bonding pad BP2 provided on the circuit chip 20. The bonding pad BP1 contains, for example, copper. The array chip 10 and the circuit chip 20 are electrically connected via the bonding pads BP1 and BP2.

[0081] The insulating layer 110 is provided so as to cover the laminate SB. The insulating layer 110 contains silicon oxide.

[0082] The spacer 301 is provided in region R2 of the circuit chip 20. The spacer 301 flattens the step portion caused by the area difference between the circuit chip 20 and the array chip 10. The surface of the spacer 301 facing in the Z2 direction is approximately parallel to the surface of the array chip 10 facing in the Z2 direction. The spacer 301 is provided with an opening 302 for exposing the bonding pad WP of the circuit chip 20. For example, the bonding wire BW passes through the opening 302 and is connected to the bonding pad WP.

[0083] 1.4.3.1 Cross-sectional structure of array chip Next, with reference to Figure 8, an example of the cross-sectional structure of the array chip 10 will be described. Figure 8 is a cross-sectional view of region RA in Figure 7. In the following description, we will focus on the cross-section of the region in the array chip 10 where the memory cell array 11 is provided (hereinafter also referred to as the "memory cell array region").

[0084] As shown in Figure 8, the array chip 10 includes a semiconductor layer 101, wiring layers 102, 105, and 107, conductors 103, 104, 106, and 109, electrodes 108, insulating layers 110-112, and memory pillars MP.

[0085] The memory cell array 11 includes a cell region CR and a WL connection region WR. The cell region CR is the region where the memory cell transistor MC is located. The WL connection region WR is the connection region between the word line WL and the selection gate lines SGD and SGS, and the corresponding number of contact plugs.

[0086] A semiconductor layer 101 is provided on the surface of the insulating layer 111 facing the Z1 direction. The semiconductor layer 101 extends in the X and Y directions. The semiconductor layer 101 in the memory cell array region functions as a source line SL. For example, the insulating layer 111 contains silicon oxide (SiO) as an insulating material. For example, the semiconductor layer 101 contains silicon.

[0087] In the cell region CR, multiple insulating layers 112 and multiple wiring layers 102 are alternately stacked one layer at a time on the Z1-oriented surface of the semiconductor layer 101. In the example shown in Figure 8, 10 insulating layers 112 and 10 wiring layers 102 are alternately stacked one layer at a time. The stacked structure of 10 insulating layers 112 and 10 wiring layers 102 corresponds to the laminate SB. The insulating layers 112 and wiring layers 102 extend in the X direction. The insulating layer 112 contains, for example, silicon oxide. The wiring layer 102 contains, for example, tungsten (W) as a conductive material. In the example shown in Figure 8, the 10 wiring layers 102 function, in order from the side closest to the semiconductor layer 101, as a selectable gate line SGS, word lines WL0 to WL7, and a selectable gate line SGD.

[0088] In the WL connection region WR, the ends of the multiple wiring layers 102 and multiple insulating layers 112 are drawn out in a stepped manner. The length of the multiple wiring layers 102 in the X direction gradually decreases from the semiconductor layer 101 side toward the circuit chip 20 side.

[0089] Multiple memory pillars MP are provided in the cell region CR. Each memory pillar MP corresponds to one NAND string NS. The memory pillar MP has, for example, a cylindrical shape extending in the Z direction. The memory pillar MP penetrates (passes through) multiple insulating layers 112 and multiple wiring layers 102. The Z2 end (bottom surface) of the memory pillar MP reaches into the semiconductor layer 101. Details of the structure of the memory pillar MP will be described later.

[0090] The insulating layer 110 is provided so as to cover the insulating layer 112, the wiring layer 102, and the memory pillar MP.

[0091] Multiple conductors 109 are provided in the WL connection region WR. The conductors 109 have, for example, a cylindrical shape extending in the Z direction. The conductors 109 function as contact plugs. The conductors 109 contain, for example, tungsten as a conductive material. The conductors 109 are connected to one of the wiring layers 102, but are not electrically connected to the other wiring layers 102. The length of the conductors 109 in the Z direction varies depending on the wiring layer 102 to which they are connected.

[0092] A conductor 103 is provided on the surface of the memory pillar MP facing the Z1 direction. The conductor 103 has, for example, a cylindrical shape extending in the Z direction. The conductor 103 functions as a contact plug. The conductor 103 contains, for example, tungsten as a conductive material.

[0093] A conductor 104 is provided on the Z1-oriented surfaces of the conductor 103 in the cell region CR and the conductor 109 in the WL connection region WR. The conductor 104 has, for example, a cylindrical shape extending in the Z direction. The conductor 104 functions as a contact plug. The conductor 104 contains, for example, tungsten as a conductive material.

[0094] A wiring layer 105 is provided on the surface of the conductor 104 facing the Z1 direction. For example, multiple wiring layers 105 of a cell region CR each extend in the Y direction and are arranged side by side in the X direction. Each of the multiple memory pillars MP is electrically connected to one of the multiple wiring layers 105 via conductors 103 and 104. The wiring layer 105 to which the memory pillar MP is connected functions as a bit line BL. The wiring layer 105 contains, for example, copper as a conductive material.

[0095] A conductor 106 is provided on the surface of the wiring layer 105 facing the Z1 direction. The conductor 106 has, for example, a cylindrical shape extending in the Z direction. The conductor 106 functions as a contact plug. The conductor 106 contains, for example, tungsten as a conductive material.

[0096] A wiring layer 107 is provided on the surface of the conductor 106 facing the Z1 direction. The wiring layer 107 contains, for example, tungsten as a conductive material. The conductor 106 and the wiring layer 107 may be formed by the dual damascene method. In the case of the dual damascene method, the patterns of the conductor 106 and the wiring layer 107 are processed together. The conductor 106 and the wiring layer 107 are then embedded together with a conductive material (for example, tungsten).

[0097] The side of the insulating layer 110 facing the Z1 direction is in contact with the insulating layer 211 of the circuit chip 20. In other words, the surface where the insulating layer 110 and the insulating layer 211 are in contact is the bonding surface BS.

[0098] An electrode 108 is provided on the surface of the wiring layer 107 facing the Z1 direction. The electrode 108 contains, for example, copper as a conductive material. The electrode 108 is formed, for example, by a dual damascene method. The electrode 108 includes a bonding pad BP1 and a contact plug that connects the bonding pad BP1 and the wiring layer 107. The electrode 108 functions as the bonding pad BP1.

[0099] The bonding pad BP1 is in contact with the bonding pad BP2 provided on the circuit chip 20 on the bonding surface BS.

[0100] Furthermore, the number of wiring layers 102 provided on the array chip 10 and the number of layers in the multilayer wiring structure on the wiring layers 102 can be designed arbitrarily.

[0101] 1.4.3.2 Cross-sectional structure of a circuit chip Next, we will describe the cross-sectional structure of the circuit chip 20 with reference to Figure 8.

[0102] The circuit chip 20 includes a semiconductor substrate 201, a transistor TR, a gate insulating film 202, a gate electrode 203, a conductor 204, wiring layers 205, 207, and 209, conductors 206 and 208, an electrode 210, and an insulating layer 211.

[0103] As shown in Figure 8, a plurality of transistors TR are provided on the surface of the semiconductor substrate 201 facing the Z2 direction. The region where the plurality of transistors TR are provided corresponds to the transistor region TRR. Each transistor TR includes a gate insulating film 202, a gate electrode 203, and a source and drain (not shown) formed on the semiconductor substrate 201. The gate insulating film 202 is provided on the surface of the semiconductor substrate 201 facing the Z2 direction. The gate electrode 203 is provided on the surface of the gate insulating film 202 facing the Z2 direction.

[0104] A conductor 204 is provided on the gate electrode 203 and on the surface of the semiconductor substrate 201 facing the Z2 direction. The conductor 204 has, for example, a cylindrical shape extending in the Z direction. The conductor 204 functions as a contact plug. The conductor 204 contains, for example, tungsten.

[0105] A wiring layer 205 is provided on the surface of the conductor 204 facing the Z2 direction. The wiring layer 205 contains, for example, tungsten as a conductive material.

[0106] A conductor 206 is provided on the surface of the wiring layer 205 facing the Z2 direction. The conductor 206 has, for example, a cylindrical shape extending in the Z direction. The conductor 206 functions as a contact plug. The conductor 206 contains, for example, tungsten or copper as a conductive material.

[0107] A wiring layer 207 is provided on the surface of the conductor 206 facing the Z2 direction. The wiring layer 207 contains, for example, tungsten or copper as a conductive material. The wiring layer 207 and the conductor 206 may be formed together by a dual damascene method.

[0108] A conductor 208 is provided on the surface of the wiring layer 207 facing the Z2 direction. The conductor 208 has, for example, a cylindrical shape extending in the Z direction. The conductor 208 functions as a contact plug. The conductor 208 contains, for example, copper as a conductive material.

[0109] A wiring layer 209 is provided on the surface of the conductor 208 facing the Z2 direction. The wiring layer 209 contains, for example, copper as a conductive material. The wiring layer 209 and the conductor 208 may be formed together by a dual damascene method.

[0110] An insulating layer 211 is provided on the surface of the semiconductor substrate 201 facing the Z2 direction. The insulating layer 211 covers the transistor TR, the conductor 204, the wiring layer 205, the conductor 206, the wiring layer 207, the conductor 208, and the wiring layer 209. The surface of the insulating layer 211 facing the Z2 direction is in contact with the insulating layer 110 of the array chip 10.

[0111] An electrode 210 is provided on the surface of the wiring layer 209 facing the Z2 direction. The electrode 210 contains, for example, copper as a conductive material. The electrode 210 includes a bonding pad BP2 and a contact plug that connects the bonding pad BP2 and the wiring layer 209. The electrode 210 is formed, for example, by a dual damascene method.

[0112] The bonding pad BP2 is in contact with the bonding pad BP1 provided on the array chip 10 at the bonding surface.

[0113] Furthermore, the number of layers in the multilayer wiring structure provided on the circuit chip 20 can be designed arbitrarily.

[0114] 1.4.3.3 Cross-sectional structure of memory pillar Next, an example of the cross-sectional structure of a memory pillar MP will be described with reference to Figures 9 and 10. Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of the cell region CR of the memory cell array 11. Figure 9 shows two memory pillar MPs included in the cell region CR of the memory cell array 11. Figure 10 is a cross-sectional view along line XX in Figure 9. More specifically, Figure 10 shows the cross-sectional structure of the memory pillar MP along the XY plane in the layer containing the wiring layer 102. The following description will focus on the structure of the memory pillar MP.

[0115] As shown in Figure 9, the semiconductor layer 101 includes, for example, three semiconductor layers 101a, 101b, and 101c. Semiconductor layer 101b is provided on the Z1-oriented surface of semiconductor layer 101a. Semiconductor layer 101c is provided on the Z1-oriented surface of semiconductor layer 101b. Semiconductor layer 101b is formed, for example, by replacing the sacrificial layer provided between semiconductor layer 101a and semiconductor layer 101c. Semiconductor layers 101a to 101c include, for example, silicon. Semiconductor layers 101a to 101c also include, for example, phosphorus (P) as a semiconductor impurity.

[0116] On the surface of the semiconductor layer 101 facing the Z1 direction, 10 insulating layers 112 and 10 wiring layers 102 are alternately stacked one layer at a time. In other words, a laminated body SB is provided.

[0117] An insulating layer 110 is provided on the surface of the wiring layer 102, which functions as a selectable gate wire SGD, facing in the Z1 direction.

[0118] Multiple memory pillars MP are provided within the cell region CR of the memory cell array 11. The memory pillars MP penetrate the 10 wiring layers 102. The bottom surface of the memory pillars MP reaches the semiconductor layer 101. The memory pillars MP may also have a structure in which multiple pillars are connected in the Z direction.

[0119] Next, the internal structure of the memory pillar MP will be described. The memory pillar MP includes a block insulating film 140, a charge storage film 141, a tunnel insulating film 142, a semiconductor film 143, a core film 144, and a cap film 145.

[0120] A block insulating film 140, a charge storage film 141, and a tunnel insulating film 142 are stacked on a portion of the side surface of the memory pillar MP and on the bottom surface facing the Z2 direction, in order from the outside. More specifically, the block insulating film 140, charge storage film 141, and tunnel insulating film 142 on the side surface of the memory pillar MP are removed in the same layer as and near the semiconductor layer 101b. A semiconductor film 143 is provided so as to be in contact with the side surface and bottom surface of the tunnel insulating film 142 and the semiconductor layer 101b. The semiconductor film 143 is the region where the channels of the memory cell transistor MC and the selection transistors ST1 and ST2 are formed. The interior of the semiconductor film 143 is filled with a core film 144. At the top of the memory pillar MP in the Z1 direction, a cap film 145 is provided on the upper ends of the semiconductor film 143 and the core film 144. The side surface of the cap film 145 is in contact with the tunnel insulating film 142. The cap film 145 contains, for example, silicon. A conductor 103 is provided on the surface of the cap film 145 facing the Z1 direction. A conductor 104 is provided on the surface of the conductor 103 facing the Z1 direction. The conductor 104 is connected to a wiring layer 105 that functions as a bit line BL.

[0121] Memory cell transistors MC0 to MC7 are formed by combining memory pillar MP with wiring layer 102 that functions as word lines WL0 to WL7. Similarly, selection transistor ST1 is formed by combining memory pillar MP with wiring layer 102 that functions as a selection gate line SGD. Selection transistor ST2 is formed by combining memory pillar MP with wiring layer 102 that functions as a selection gate line SGS. Thus, each memory pillar MP can function as a single NAND string NS.

[0122] An example of a cross-sectional structure of a memory pillar MP along the XY plane is described below.

[0123] As shown in Figure 10, in a cross-section including the wiring layer 102, the core film 144 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 143 surrounds the sides of the core film 144. The tunnel insulating film 142 surrounds the sides of the semiconductor film 143. The charge storage film 141 surrounds the sides of the tunnel insulating film 142. The block insulating film 140 surrounds the sides of the charge storage film 141. The wiring layer 102 surrounds the sides of the block insulating film 140.

[0124] The semiconductor film 143 is used as the channel (current path) for the memory cell transistors MC0 to MC7 and the selection transistors ST1 and ST2. The tunnel insulating film 142 and the block insulating film 140 each contain, for example, silicon oxide. The charge storage film 141 has the function of storing charge. The charge storage film 141 contains, for example, silicon nitride (SiN).

[0125] 1.4.4 Method for Manufacturing Semiconductor Devices Next, an example of a manufacturing method for the semiconductor device 50 will be described with reference to Figures 11 to 20. Figure 11 is a flowchart showing an example of a manufacturing method for the semiconductor device 50. Figures 12 to 20 are cross-sectional views showing the manufacturing process of the semiconductor device 50. In the following description, we will focus on the manufacturing process and assembly process of the array chip.

[0126] As shown in Figure 11, the manufacturing process for the semiconductor device 50 broadly includes a manufacturing process for the array chip 10, a manufacturing process for the circuit chip 20, and an assembly process for bonding the array chip 10 and the circuit chip 20 together.

[0127] First, the manufacturing process of the array chip 10 will be explained. In the manufacturing process of the array chip 10, steps S11 to S14 shown in Figure 11 are executed sequentially.

[0128] <Step S11> As shown in Figure 12, first, a memory cell array including a stacked SB is formed on a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon substrate or a silicon wafer. That is, multiple array chips 10 are formed on the silicon substrate. In the example shown in Figure 12, three array chips 10 are arranged in the X direction. For example, a protective film 400 is provided on the insulating layer 110 and on the surface of the bonding pad BP1 facing the Z1 direction. The protective film 400 is preferably made of a material that suppresses oxidation of the bonding pad BP1 and can be removed by catalytic etching. Note that the protective film 400 may be omitted.

[0129] In this embodiment, instead of cutting the multiple array chips 10 formed on the semiconductor substrate 100 by dicing, catalytic etching, as described using steps S12 and S13, is performed.

[0130] <Step S12> As shown in Figure 13, a pattern of the catalyst layer 2 is formed on the protective film 400 in order to separate and individualize each chip. For example, if the catalyst layer 2 is a resist, the pattern is formed by photolithography, as explained using Figures 2 and 3(a). If the catalyst layer 2 is not a resist, the catalyst layer 2 is formed by etching, as explained using Figure 4, for example.

[0131] <Step S13> As shown in Figure 14, catalytic etching of the insulating layer 110 and the semiconductor substrate 100 is performed. More specifically, as explained using Figures 2 and 3, first the insulating layer 110 (and protective film 400) is etched in an HF gas atmosphere. Next, UV light is irradiated from the back surface of the semiconductor substrate 100, and the semiconductor substrate 100 is etched in the same HF gas atmosphere. At this stage, the semiconductor substrate 100 is not separated; that is, grooves are formed in the semiconductor substrate 100.

[0132] After catalytic etching, catalyst layer 2 is removed.

[0133] <Step S14> As shown in Figure 15, the array chip 10 is separated into individual pieces. More specifically, a BG (back grinding) protective tape 410 is attached to the insulating layer 110 (protective film 400), and the back surface of the semiconductor substrate 100 is ground to thin the semiconductor substrate 100. This separates the array chip 10 into individual pieces. After back surface grinding, a pickup tape is attached to the ground surface of the semiconductor substrate 100. At this stage, the BG protective tape 410 and protective film 400 are removed.

[0134] Next, we will briefly explain the manufacturing process of the circuit chip 20.

[0135] <Step S21> As shown in Figure 11, multiple circuit chips 20 are formed on a semiconductor substrate 201. The area of ​​the circuit chips 20 is larger than the area of ​​the array chip 10. The circuit chips 20 are not separated into individual pieces before bonding.

[0136] Next, the assembly process will be explained. In the assembly process, steps S31 to S36 shown in Figure 11 are executed sequentially.

[0137] <Step S31> As shown in Figure 16, individual array chips 10 are bonded onto a circuit chip 20 provided on a semiconductor substrate 201. The area of ​​the circuit chip 20 is larger than the area of ​​the array chip 10. Therefore, multiple array chips 10 are scattered on top of the semiconductor substrate 201.

[0138] <Step S32> As shown in Figure 17, a spacer 301 is deposited to fill the gap between the array chips 10. The spacer 301 covers the surface of the array chip 10 facing the Z2 direction.

[0139] <Step S33> As shown in Figure 18, the semiconductor substrate 100 of the array chip 10 and the spacer 301 on it are removed. The removal method may be grinding, dry etching, CMP (Chemical Mechanical Polishing), or a combination of these. As a result, the surface of the spacer 301 facing the Z2 direction is made approximately parallel to the surface of the array chip 10 facing the Z2 direction.

[0140] <Step S34> As shown in Figure 18, an opening 302 is formed, and the bonding pad WP is exposed. In this embodiment, instead of cutting the semiconductor substrate 201 by dicing, catalytic etching, as described in steps S35 and S36, is performed.

[0141] <Step S35> As shown in Figure 19, a pattern of the catalyst layer 2 is formed on the spacer 301, similar to step S12. For example, if the catalyst layer 2 is a resist, the pattern is formed by photolithography, as explained using Figures 2 and 3(a). If the catalyst layer 2 is not a resist, the catalyst layer 2 is formed by etching, as explained using Figure 4, for example.

[0142] <Step S36> As shown in Figure 20, catalytic etching is performed on the spacer 301, the insulating layer 211, and the semiconductor substrate 201. More specifically, as explained using Figures 2 and 3, first the spacer 301 and the insulating layer 211 are etched in an HF gas atmosphere. Next, UV light is irradiated from the back surface of the semiconductor substrate 201, and the semiconductor substrate 201 is etched in the same HF gas atmosphere. This separates the circuit chip 20.

[0143] After catalytic etching, catalyst layer 2 is removed.

[0144] 1.5 Effects of this embodiment In the configuration according to this embodiment, a material that forms hydrogen bonds with HF gas can be used in the catalyst layer. This allows the silicon oxide in contact with the catalyst layer to be preferentially etched by the HF gas. In other words, the catalyst layer enables anisotropic etching of silicon oxide.

[0145] Furthermore, with the configuration according to this embodiment, holes can be generated within the silicon substrate by irradiating it with light of a wavelength of 1100 nm or less (including UV light and visible light). This allows the silicon in contact with the catalyst layer to be preferentially etched by HF gas. In other words, anisotropic etching of silicon can be achieved by the catalyst layer.

[0146] Furthermore, with the configuration according to this embodiment, catalytic etching can be applied to the dicing process in the manufacturing method of semiconductor devices. For example, in the case of plasma dicing, carbon fluoride (CF) gas is used, resulting in an environmental burden due to the CF gas. In contrast, catalytic etching can reduce the environmental burden. Also, since a fine catalyst layer pattern can be formed, the spacing between chips on the semiconductor substrate can be narrowed. This allows for an increase in the number of chips per semiconductor substrate. Therefore, costs can be reduced.

[0147] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, an etching apparatus for catalyst etching will be described. The following description will focus on the differences from the first embodiment.

[0148] 2.1 Configuration of the etching apparatus Referring to Figure 21, an example of the configuration of the etching apparatus 1000 for catalytic etching will be described. Figure 21 is a diagram showing an example of the configuration of the etching apparatus 1000 used for catalytic etching. In the following description, the case in which the etching apparatus 1000 is a semiconductor device manufacturing apparatus will be described, but it is not limited to this case.

[0149] In the following description, with the etching apparatus 1000 installed, the direction of gravity is defined as "down," and the opposite direction is defined as "up." In the cross-sectional view of the etching apparatus 1000, the bottom of the drawing shows the bottom of the etching apparatus 1000, and the top of the drawing shows the top of the etching apparatus 1000.

[0150] As shown in Figure 21, the etching apparatus 1000 includes a chamber 1010, a stage 1020, a light source 1030, a heating window 1040, a heater 1050, an exhaust device 1060, a control unit 1070, a valve BV, and a throttle valve TV.

[0151] Chamber 1010 is a processing chamber used for catalytic etching. Chamber 1010 is made of, for example, stainless steel. However, other materials may be used for Chamber 1010. Chamber 1010 may have a configuration that allows the temperature of the inner wall of Chamber 1010 to be adjusted by a temperature control mechanism (not shown). For example, Chamber 1010 is provided with a gate valve (not shown). For example, the silicon substrate 1 is transported into Chamber 1010 from outside through the gate valve. In the example shown in Figure 21, a silicon substrate 1 is placed on which silicon oxide 3 is formed on the upper surface, and a catalyst layer 2 is provided on top of the silicon oxide 3. However, the substrate is not limited to silicon substrate 1. The substrate may be made of a material other than silicon. It is sufficient that a layer that can be etched by catalytic etching is formed on the substrate, and the catalyst layer 2 is provided on top of that. That is, it is sufficient that the substrate has the catalyst layer 2 as the uppermost layer.

[0152] The chamber 1010 is provided with a supply port (supply port) 1011 and an exhaust port (exhaust port) 1012. The supply port 1011 is used when supplying HF gas into the chamber 1010. Note that a plurality of supply ports 1011 may be provided. For example, a supply port 1011 for supplying a purge gas or the like may be provided separately. The supply port 1011 is connected to a valve BV. The valve BV controls the on / off of gas supply into the chamber 1010. The exhaust port 1012 is used when exhausting the gas in the chamber 1010. The exhaust port 1012 is connected to an exhaust device 1060 via a throttle valve TV. The gas in the chamber 1010 is exhausted from the exhaust port 1012 to the exhaust device 1060. For example, the inside of the chamber 1010 is maintained at a reduced pressure (a pressure lower than atmospheric pressure). Note that the pressure inside the chamber 1010 may be atmospheric pressure (normal pressure).

[0153] The stage (susceptor) 1020 is provided below the chamber 1010. The silicon substrate 1 is placed on the stage 1020. A recess (counter bore) for placing the silicon substrate 1 may be provided on the upper surface of the stage 1020. For example, the stage 1020 has a function as a transmission window for transmitting the irradiation light of a light source 1030 provided below. The stage 1020 is, for example, made of quartz. Note that the stage 1020 may be made of a material that can transmit the irradiation light from the light source 1030.

[0154] The light source 1030 is provided below the stage 1020. The light source 1030 irradiates light on the back surface of the silicon substrate 1. The silicon substrate 1 generates holes h + by the irradiation light of the light source 1030. The irradiation light of the light source 1030 may be UV light or visible light. As long as it is irradiation light with a wavelength of 1100 nm or less, holes h are generated in the silicon substrate 1 +This can generate [unclear]. For example, the light source 1030 is turned off during silicon oxide etching and turned on during silicon etching. The light source 1030 may be provided on the top or side surface of the chamber 1010. In this case, a window for transmitting the irradiation light is provided on the top or side surface of the chamber 1010. The stage 1020 does not need to have the function of transmitting the irradiation light.

[0155] A heating window 1040 is provided on at least a portion of the upper surface of the chamber 1010. The heating window 1040 has the function of transmitting infrared light (thermal radiation) emitted from the heater 1050 located above it. For example, quartz is used for the heating window 1040. However, any material that can transmit infrared light is acceptable for the heating window 1040.

[0156] A heater 1050 is provided above the chamber 1010. The heater 1050 heats the silicon substrate 1 through the heating window 1040. For example, the heater 1050 is an IR (Infrared) heater that emits infrared light. The configuration of the heater 1050 is arbitrary. The heater 1050 may be lamp-heated, resistance-heated, or induction-heated. For example, in catalytic etching, the silicon substrate 1 and silicon oxide 3 are heated to 100°C or higher and 400°C or lower. For example, if water remains on the surface of the silicon substrate 1 and silicon oxide 3 during catalytic etching, the reaction between HF and Si (SiO) is promoted, and the etching selectivity of the catalyst layer 2 decreases. To remove the water, it is preferable to heat the silicon substrate 1 and silicon oxide 3 to 100°C or higher. Also, for example, considering suitability to the semiconductor device manufacturing process and the suppression of etching of the stage 1020 and heating window 1040 by HF gas, it is preferable to heat the silicon substrate 1 and silicon oxide 3 to 400°C or lower. The heater 1050 may be provided on the bottom or side of the chamber 1010. If the heater 1050 is provided below the chamber 1010, the stage 1020 functions as a heating window 1040.

[0157] The exhaust system 1060 exhausts the gas from the chamber 1010. The configuration of the exhaust system 1060 is arbitrary. For example, the exhaust system 1060 may include at least one of a turbomolecular pump, a mechanical booster pump, and a dry pump.

[0158] The control unit 1070 controls the entire etching apparatus 1000. More specifically, for example, the control unit 1070 controls the light source 1030, heater 1050, exhaust system 1060, valve BV, and throttle valve TV.

[0159] 2.2 Effects according to this embodiment In the configuration according to this embodiment, the etching apparatus 1000 irradiates the silicon substrate 1 with light of a wavelength of 1100 nm or less to create holes in the silicon substrate 1. + This can generate [the specified phenomenon]. Furthermore, HF gas can be supplied into the chamber 1010. This makes it possible to provide an etching apparatus capable of performing the catalytic etching described in the first embodiment.

[0160] 3. Variations, etc. The etching method according to the above embodiment includes the steps of: providing a catalyst layer (2) on a substrate (1) mainly composed of silicon; exposing the substrate (1) on which the catalyst layer (2) is provided to an HF gas atmosphere; and etching the substrate (1) in contact with the catalyst layer (2) by irradiating the substrate (1) in the HF gas atmosphere with light.

[0161] With the configuration according to the above embodiment, an etching method using HF gas as a catalyst can be provided.

[0162] Furthermore, various modifications are applicable, not limited to the embodiments described above.

[0163] For example, the catalytic etching described in the above embodiment can also be applied to the manufacturing process of optical elements such as X-ray sensors and two-dimensional photonic crystals. Furthermore, catalytic etching can be applied to the manufacturing process of electrical circuit elements, optical elements, MEMS (Micro Electro Mechanical Systems), recording elements, sensors, or molds. Examples of electrical circuit elements include volatile or non-volatile semiconductor memories such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and MRAM (Magnetoresistive Random Access Memory), as well as semiconductor elements such as LSI (Large Scale Integration), CCD (Charge Coupled Device), image sensors, and FPGA (Field Programmable Gate Array). Examples of molds include molds for imprinting.

[0164] Furthermore, the term "connection" in the above embodiment also includes a state in which the devices are indirectly connected by interposing something else, such as a transistor or a resistor.

[0165] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0166] 1...Silicon substrate, 2...Catalyst layer, 3...Silicon oxide, 4...SOG, 5...Resist, 10...Array chip, 11...Memory cell array, 20...Circuit chip, 21...Sequencer, 22...Voltage generation circuit, 23...Raw decoder, 24...Sense amplifier, 50...Semiconductor device, 100...Semiconductor substrate, 101, 101a~101c...Semiconductor layer, 102, 105, 107, 205, 207, 209...Wiring layer, 103, 104, 106, 109, 204, 206, 208...Conductor, 108, 210...Electrode, 110~112, 211...Insulating layer, 140...Block insulating film, 141...Charge storage film, 142...Tunnel insulating film, 143...Semiconductor film, 144...Core film, 145...Cap film, 201...Semiconductor substrate, 202...Gate insulating film, 2 03…Gate electrode, 301…Spacer, 302…Opening, 400…Protective film, 410…BG protective tape, 1000…Etching device, 1010…Chamber, 1011…Supply port, 1012…Exhaust port, 1020…Stage, 1030…Light source, 1040…Heating window, 1050…Heater, 1060…Exhaust device, 1070…Control unit, BL, BL0~BLm…Bit lines, BLK, BLK0~BLK3…Block, BP1, BP2…Bonding pads, MC, MC0~MC7…Memory cell transistors, SGD, SGD0~SGD3, SGS…Selection gate lines, ST1, ST2…Selection transistors, SU, SU0~SU3…String units, TR…Transistors, WL, WL0~WL7…Word lines, WP…Bonding pads

Claims

1. A process of forming a catalyst layer on a substrate mainly composed of silicon, A step of exposing the substrate on which the catalyst layer is provided to an HF gas atmosphere, A step of etching the substrate in contact with the catalyst layer by irradiating the substrate in the HF gas atmosphere with light. Equipped with, Etching method.

2. A step of forming a first layer containing oxygen or nitrogen and silicon on the substrate, A step of forming the catalyst layer on the aforementioned layer, A step of exposing the first layer on which the catalyst layer is formed and the substrate to an HF gas atmosphere to etch the first layer in contact with the catalyst layer. It also has, The etching method according to claim 1.

3. The catalyst layer forms hydrogen bonds with the HF gas. The etching method according to claim 1.

4. The catalyst layer contains phenol, The etching method according to claim 3.

5. The catalyst layer comprises a hydroxyl group (-OH), a carboxyl group (-COOH), and an amino group (-NH). ２ ), amide group (-CONH ２ ), nitro group (-NO ２ ), having at least one ether bond (-O-), The etching method according to claim 3.

6. The catalyst layer comprises at least one of the following: novolac resin, polyvinylphenol (PVP), naphthol novolac, and diazonaphthoquinone-diazido (NQD). The etching method according to claim 4.

7. The wavelength of the aforementioned light is 1100 nm or less. The etching method according to claim 1.

8. The process of etching the substrate is carried out in an atmosphere of 100°C to 400°C. The etching method according to claim 1.

9. A step of forming a first layer containing oxygen or nitrogen and silicon on a silicon-based substrate, The steps include providing a catalyst layer on the first layer, A step of exposing the first layer on which the catalyst layer is formed and the substrate to an HF gas atmosphere to etch the first layer in contact with the catalyst layer, After etching the first layer, the substrate in the HF gas atmosphere is irradiated with light to etch the substrate in contact with the catalyst layer. Prepare A method for manufacturing a semiconductor device.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the substrate includes a silicon wafer and the first layer includes silicon oxide.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the step of etching the substrate includes a dicing step.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the first layer includes a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately stacked.

13. Multiple array chips are formed by etching the aforementioned substrate. The process further includes bonding a circuit chip with a wiring layer formed on it to the plurality of array chips. The method for manufacturing a semiconductor device according to claim 9.

14. The catalyst layer contains phenol, The method for manufacturing a semiconductor device according to claim 9.

15. The catalyst layer comprises at least one of the following: novolac resin, polyvinylphenol (PVP), naphthol novolac, and diazonaphthoquinone-diazido (NQD). The method for manufacturing a semiconductor device according to claim 14.

16. Chamber and A stage is provided within the chamber, with a catalyst layer on the uppermost layer, on which a workpiece containing silicon is placed. A light source that irradiates the workpiece with light, A heater for heating the workpiece, A supply port is provided in the chamber and used for supplying HF gas into the chamber, An exhaust port is provided in the chamber and is used for exhausting air from the chamber. An etching apparatus equipped with the following features.

17. The catalyst layer forms hydrogen bonds with the HF gas. The etching apparatus according to claim 16.

18. The heater heats the workpiece to a temperature of 100°C or higher and 400°C or lower. The etching apparatus according to claim 16.

19. The wavelength of the aforementioned light is 1100 nm or less. The etching apparatus according to claim 16.

20. The light source irradiates the workpiece with light when etching the silicon. The etching apparatus according to claim 16.

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