Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can effectively utilize regions formed on a semiconductor element. [Solution] According to one embodiment, the semiconductor device comprises at least one semiconductor chip having a first chip, a second chip, and a third chip. The second chip is bonded to the first chip on a first region on the upper surface of the first chip so as to be electrically connected to the first chip, and has an area smaller than the area of ​​the first chip. The third chip is bonded to the first chip on a second region on the upper surface of the first chip so as to be electrically connected to the first chip, has an area smaller than the area of ​​the first chip, and has an electrical function different from the electrical function of the second chip.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor conductor manufactured by bonding two wafers, when the sizes (i.e., areas) of semiconductor elements on each wafer are different, regions are formed on the semiconductor elements after bonding.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device and a method for manufacturing the same that can effectively utilize regions formed on semiconductor elements.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor device includes at least one semiconductor chip having a first chip, a second chip, and a third chip. The second chip is joined to the first chip on a first region on the upper surface of the first chip so as to be electrically connected to the first chip, and has an area smaller than the area of the first chip. The third chip is joined to the first chip on a second region on the upper surface of the first chip so as to be electrically connected to the first chip, has an area smaller than the area of the first chip, and has an electrical function different from the electrical function of the second chip. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view showing an example of the configuration of a semiconductor chip in a semiconductor device according to the first embodiment. [Figure 3A] Figure 3A is a cross-sectional view showing an example of the configuration around a metal pad in a semiconductor device according to the first embodiment. [Figure 3B] Figure 3B is a cross-sectional view showing the power supply path to a functional chip in a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing an example of the configuration of a memory cell array and transistors in a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view showing an example of the configuration of a columnar portion in a semiconductor device according to the first embodiment. [Figure 6A] Figure 6A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6B] Figure 6B is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6A. [Figure 6C] Figure 6C is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6B. [Figure 6D] Figure 6D is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6C. [Figure 6E] Figure 6E is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6D. [Figure 6F] Figure 6F is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6E. [Figure 6G] Figure 6G is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6F. [Figure 6H] Figure 6H is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 6G. [Figure 6I]FIG. 6I is a cross-sectional view showing an example of a method of manufacturing a semiconductor device, following FIG. 6H. [Figure 6J] FIG. 6J is a cross-sectional view showing an example of a method of manufacturing a semiconductor device, following FIG. 6I. [Figure 6K] FIG. 6K is a cross-sectional view showing an example of a method of manufacturing a semiconductor device, following FIG. 6J. [Figure 6L] FIG. 6L is a cross-sectional view showing an example of a method of manufacturing a semiconductor device, following FIG. 6K. [Figure 6M] FIG. 6M is a cross-sectional view showing an example of a method of manufacturing a semiconductor device, following FIG. 6L. [Figure 7] FIG. 7 is a diagram showing an example of the sizes of an array chip and a functional chip in the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing the sizes of an array chip and a functional chip in the semiconductor device according to the first modification of the first embodiment. [Figure 9] FIG. 9 is a diagram showing the sizes of an array chip and a functional chip in the semiconductor device according to the second modification of the first embodiment. [Figure 10] FIG. 10 is a diagram showing the sizes of an array chip and a functional chip in the semiconductor device according to the third modification of the first embodiment. [Figure 11] FIG. 11 is a diagram showing the sizes of an array chip and a functional chip in the semiconductor device according to the fourth modification of the first embodiment. [Figure 12] FIG. 12 is a diagram showing the sizes of an array chip and a functional chip in the semiconductor device according to the fifth modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing the semiconductor device according to the sixth modification of the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing the semiconductor device according to the seventh modification of the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing the semiconductor device according to the eighth modification of the first embodiment. [Figure 16]FIG. 16 is a side view showing a semiconductor device according to a ninth modification of the first embodiment. [Figure 17] FIG. 17 is a side view showing a semiconductor device according to a tenth modification of the first embodiment. [Figure 18] FIG. 18 is a side view showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 19A] FIG. 19A is a side view showing a semiconductor device according to a first modification of the second embodiment. [Figure 19B] FIG. 19B is a side view showing another example of a semiconductor device according to a first modification of the second embodiment. [Figure 20] FIG. 20 is a side view showing a semiconductor device according to a second modification of the second embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing an example of the configuration of a semiconductor chip in a semiconductor device according to a comparative example.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratios of the respective parts are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the already shown drawings, and the detailed description thereof will be omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the first embodiment. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the wiring substrate 10 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the wiring substrate 10. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0009] The semiconductor device 1 comprises a wiring board 10, semiconductor chips 20, 30-33, adhesive layers 40-43, a resin layer 80, bonding wires 90, and sealing resin 91. The wiring board 10 is an example of a substrate, a second substrate, or a third substrate. The semiconductor chip 30 is an example of a first semiconductor chip or a third semiconductor chip. The semiconductor chip 31 is an example of a second semiconductor chip or a fourth semiconductor chip. The bonding wires 90 are an example of a wire, a second wire, or a third wire. The semiconductor device 1 is, for example, a package for a NAND flash memory.

[0010] The wiring board 10 is, for example, a printed circuit board or interposer that includes a wiring layer 11 and an insulating layer 15. The wiring layer 11 is made of a low-resistance metal such as copper (Cu), nickel (Ni), or an alloy thereof. The insulating layer 15 is made of an insulating material such as glass epoxy resin. In the example shown in Figure 1, the wiring layer 11 is provided only on the front and back surfaces of the insulating layer 15. However, the wiring board 10 may have a multilayer wiring structure formed by laminating multiple wiring layers 11 and multiple insulating layers 15. The wiring board 10 may have through-electrodes (columnar electrodes) that penetrate its front and back surfaces, for example, as in an interposer.

[0011] A solder resist layer 14 is provided on the wiring layer 11 on the surface side of the insulating layer 15, forming the surface (surface F1) of the wiring substrate 10. The solder resist layer 14 is an insulating layer that protects the wiring layer 11 from metal materials (not shown) connecting the semiconductor chip 20 and the wiring layer 11, and suppresses short-circuit defects.

[0012] A solder resist layer 14, which constitutes the back surface of the wiring board 10, is provided on the wiring layer 11 on the back side of the insulating layer 15. Metal bumps 13 are provided on the wiring layer 11 exposed from the solder resist layer 14. The metal bumps 13 are provided to electrically connect the wiring board 10 to other components (not shown).

[0013] The semiconductor chip 20 is, for example, a controller chip that controls a memory chip. A semiconductor element (not shown) is provided on the side of the semiconductor chip 20 facing the wiring board 10. The semiconductor element may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit that constitutes the controller. An electrode pillar (not shown) that is electrically connected to the semiconductor element is provided on the back (bottom) side of the semiconductor chip 20. For example, a low-resistance metal material such as copper, nickel, or an alloy thereof is used for the electrode pillar.

[0014] A metallic material is provided around the electrode pillars, which act as connecting bumps. The electrode pillars are electrically connected to the wiring layer 11 exposed at the openings in the solder resist layer 14 via the metallic material. Low-resistance metallic materials such as solder, silver, and copper are used as the metallic material. In this way, the metallic material electrically connects the electrode pillars of the semiconductor chip 20 to the wiring layer 11 of the wiring substrate 10.

[0015] A resin layer 80 is provided in the area surrounding the metal material and in the area between the semiconductor chip 20 and the wiring substrate 10. The resin layer 80 is, for example, a cured underfill resin, and covers and protects the area around the semiconductor chip 20.

[0016] The semiconductor chip 30 is, for example, a memory chip including a NAND flash memory. The semiconductor chip 30 has semiconductor elements (not shown) on its surface (top surface). The semiconductor elements may be a memory cell array and its peripheral circuits (CMOS circuits). The memory cell array may be a three-dimensional memory cell array in which multiple memory cells are arranged in three dimensions. The semiconductor chip 30 is bonded (i.e., placed) on the semiconductor chip 20 via an adhesive layer 40. Also, a semiconductor chip 31 is bonded to the semiconductor chip 30 via an adhesive layer 41. A semiconductor chip 32 is bonded to the semiconductor chip 31 via an adhesive layer 42. A semiconductor chip 33 is bonded to the semiconductor chip 32 via an adhesive layer 43. The semiconductor chips 31 to 33 are, for example, memory chips including a NAND flash memory, similar to semiconductor chip 30. The semiconductor chips 30 to 33 may be memory chips of the same type. In the figure, in addition to the semiconductor chip 20 as a controller chip, four semiconductor chips 30 to 33 as memory chips are stacked. However, the number of stacked semiconductor chips may be 3 or less, or 5 or more. As will be described later, semiconductor chips 30 to 33 further have a functional chip CH3 (see Figure 2) as a semiconductor element. The functional chip CH3 is a different chip from the array chip CH2. Furthermore, the functional chip CH3 is a semiconductor chip other than memory such as NAND or DRAM (Dynamic Random Access Memory). Moreover, the functional chip CH3 is a chip that can add functions (e.g., high-speed operation, high voltage resistance, power supply stabilization) to a semiconductor memory device that has only a CMOS circuit and the array chip CH2. The functional chip CH3 can also be called a chip component, an additional chip component, or an additional chip.

[0017] The bonding wire 90 is connected to any pad on the wiring board 10 and the semiconductor chips 30-33. In other words, the bonding wire 90 connects the wiring board 10 to the pads of the semiconductor chips 30-33. To connect with the bonding wire 90, the semiconductor chips 30-33 are stacked with an offset equal to the pads. Note that semiconductor chip 20 is flip-chip connected by electrode pillars and is therefore not wire-bonded. However, semiconductor chip 20 may also be wire-bonded in addition to being connected by electrode pillars.

[0018] Furthermore, the sealing resin 91 seals the semiconductor chips 20, 30-33, adhesive layers 40-43, spacers 50, bonding wires 90, etc. As a result, the semiconductor device 1 is configured as a single semiconductor package on the wiring board 10, comprising multiple semiconductor chips 20, 30-33.

[0019] Next, we will describe the details of semiconductor chips 30-33.

[0020] Figure 2 is a cross-sectional view showing an example of the configuration of semiconductor chips 30 and 31 in the semiconductor device 1 according to the first embodiment. Note that Figure 2 shows two semiconductor chips 30 and 31. The semiconductor chip 31 will be described below, but semiconductor chips 30, 32, and 33 have a similar configuration to semiconductor chip 31. In the example shown in Figure 2, the semiconductor chip 20 shown in Figure 1 is omitted in order to explain semiconductor chips 30 and 31 in detail.

[0021] The semiconductor chip 31 includes a circuit chip CH1, an array chip CH2, and a function chip CH3. The circuit chip CH1 is an example of a first chip. The array chip CH2 is an example of a second chip. As the second chip, a DRAM chip or an SRAM (Static Random Access Memory) chip may be provided instead of the array chip CH2. The function chip CH3 is an example of a third chip.

[0022] Circuit chip CH1 functions as a control circuit (i.e., a logic circuit) that controls the operation of array chip CH2. Circuit chip CH1 may also function as a control circuit that controls the operation of function chip CH3.

[0023] The circuit chip CH1 comprises a semiconductor substrate 111, an interlayer insulating film 112, a transistor (i.e., a semiconductor element) 113, and a metal pad BP1. The metal pad BP1 is an example of a lower pad.

[0024] The semiconductor substrate 111 is provided on the underside of the circuit chip CH1. The semiconductor substrate 111 is, for example, a silicon (Si) substrate.

[0025] The interlayer insulating film 112 is provided on the semiconductor substrate 111. The interlayer insulating film 112 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films.

[0026] Multiple transistors 113 are located above the semiconductor substrate 111. The transistors 113 constitute a peripheral circuit (CMOS circuit) as a control circuit for the memory cell array 123 of the array chip CH2. This control circuit is electrically connected to the metal pad BP1. The transistors 113 may further constitute a peripheral circuit as a control circuit for the functional chip CH3.

[0027] The metal pad BP1 is provided on the bonding surface (i.e., lamination surface) S between the array chip CH2 and the functional chip CH3. The bonding surface S is also the upper surface of the circuit chip CH1, the lower surface of the array chip CH2, and the lower surface of the functional chip CH3. Among the multiple metal pads BP1, the metal pad BP1 located below the array chip CH2 is bonded to the metal pad BP2 of the array chip CH2. Among the multiple metal pads BP1, the metal pad BP1 located below the functional chip CH3 is bonded to the metal pad BP3 of the functional chip CH3. Metal pad BP2 is an example of an upper pad. The metal pads BP1, BP2, and BP3 are, for example, Cu layers.

[0028] The array chip CH2 is bonded (i.e., laminated) to the circuit chip CH1 on a first region R1 on the upper surface of the circuit chip CH1 so as to be electrically connected to the circuit chip CH1. The area of ​​the array chip CH2 is smaller than the area of ​​the circuit chip CH1. Note that the areas of the circuit chip CH1 and the array chip CH2 are the areas viewed from the Z direction.

[0029] The array chip CH2 includes a semiconductor substrate 121, an interlayer insulating film 122, a memory cell array (i.e., semiconductor element) 123, a contact plug C1, a metal pad BP2, and a metal pad WP. The metal pad WP is an example of a pad, a second pad, a third pad, or a fourth pad.

[0030] The semiconductor substrate 121 is provided on the upper side of the array chip CH2. The semiconductor substrate 121 is, for example, a silicon (Si) substrate.

[0031] The interlayer insulating film 122 is provided beneath the semiconductor substrate 121. The interlayer insulating film 122 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films.

[0032] The memory cell array 123 is located beneath the semiconductor substrate 121. The memory cell array 123 is, for example, a non-volatile memory. The memory cell array 123 has a stepped structure. The memory cell array 123 is electrically connected to the metal pad BP2.

[0033] The contact plug C1 electrically connects the conductive layer (word line WL) of the memory cell array 123 to the metal pad BP2.

[0034] The metal pad BP2 is provided on the bonding surface S with the circuit chip CH1. The metal pad BP2 is bonded to the metal pad BP1 of the circuit chip CH1. The multiple metal pads BP2 are, for example, Cu layers.

[0035] The metal pad WP is provided on the upper surface of the array chip CH2. The metal pad WP functions as an external connection pad (bonding pad) for the semiconductor chips 30-33. That is, the metal pad WP is connected to the bonding wire 90. Therefore, the bonding wire 90 electrically connects the metal pad WP and the wiring board 10. The metal pad WP contains a conductive metal such as nickel (Ni).

[0036] The functional chip CH3 is bonded (i.e., laminated) to the circuit chip CH1 on a second region R2, which is different from the first region R1 on the upper surface of the circuit chip CH1, so as to be electrically connected to the circuit chip CH1. As described above, the functional chip CH3 has a metal pad BP3, similar to the array chip CH2. The functional chip CH3 is bonded (i.e., electrically connected) to the metal pad BP1 of the circuit chip CH1 via the metal pad BP3. The area of ​​the functional chip CH3 is smaller than the area of ​​the circuit chip CH1. Note that the area of ​​the functional chip CH3 is the area viewed from the Z direction.

[0037] By providing the functional chip CH3 on a second region R2, which is different from the first region R1 on which the array chip CH2 is provided, the step portion caused by the area difference (i.e., size difference) between the circuit chip CH1 and the array chip CH2 can be filled. More specifically, in the example shown in Figure 2, the upper surface of the functional chip CH3 is approximately parallel to the upper surface of the array chip CH2. In other words, the thickness (i.e., the dimension in the Z direction) of the functional chip CH3 is equal to the thickness of the array chip CH2. Because the thickness of the functional chip CH3 is equal to the thickness of the array chip CH2, the functional chip CH3 can fill the step portion caused by the area difference between the circuit chip CH1 and the array chip CH2 so that it becomes approximately flat. The functional chip CH3 of the semiconductor chip 30 supports the semiconductor chip 31 on top of the semiconductor chip 30. By the lower functional chip CH3 supporting the upper semiconductor chip 31, risks during assembly, such as chip tilting, can be suppressed. In other words, the upper surface area of ​​the lower semiconductor chips 30-32 can be increased, allowing for proper stacking (die bonding) of the semiconductor chips 30-33.

[0038] In the example shown in Figure 2, a member 115 is provided between the array chip CH2 and the functional chip CH3. Member 115 includes, for example, a resin such as epoxy resin. If member 115 is a resin, member 115 may also include a filler. The resin of member 115 may be a different material from the sealing resin 91. In this case, for example, the size of the filler will differ between member 115 and the sealing resin 91. On the other hand, the resin of member 115 may be the same material as the sealing resin 91. In this case, for example, the size of the filler will be the same between member 115 and the sealing resin 91. Member 115 is not limited to a resin and may be an insulating film such as SiO2.

[0039] The functional chip CH3 not only functions as a spacer to fill the step created by the area difference between the circuit chip CH1 and the array chip CH2, but also functions electrically in the semiconductor device 1 (i.e., semiconductor chips 30-33) as one of the semiconductor elements constituting the semiconductor device 1. In other words, the functional chip CH3 is an electrically functional spacer, not a spacer without electrical function, such as a resin. In this specification, “electrical function” of a chip means the function of transmitting, receiving, or both transmitting and receiving power (i.e., at least one of current and voltage), control signals, and data to and from other chips.

[0040] The area of ​​the functional chip CH3 differs from the area of ​​the array chip CH2. This difference in area between the functional chip CH3 and the array chip CH2 allows for a relaxation of the area constraints on the functional chip CH3. Furthermore, it is possible to select a functional chip CH3 with a suitable area based on the area difference between the circuit chip CH1 and the array chip CH2, and the application of the functional chip CH3.

[0041] The functional chip CH3 may also be a boost circuit. If the functional chip CH3 is a boost circuit, it can supply a large current to the semiconductor device 1, supply multiple voltages, and improve power conversion efficiency.

[0042] The functional chip CH3 may be a passive component such as a capacitor. If the functional chip CH3 is a passive component, it can stabilize the power supply to the semiconductor device 1.

[0043] The functional chip CH3 may also be a heater. If the functional chip CH3 is a heater, it can heat and regenerate the array chip CH2.

[0044] The functional chip CH3 may be a Peltier element. If the functional chip CH3 is a Peltier element, it can regenerate and cool the array chip CH2.

[0045] The functional chip CH3 may be RAM such as SRAM or DRAM. If the functional chip CH3 is RAM, it can enable high-speed operation of the semiconductor device 1.

[0046] The functional chip CH3 may be a controller that controls the array chip CH2. By placing the controller adjacent to the array chip CH2, the transmission path between the controller and the array chip CH2 can be shortened. In addition, the semiconductor device 1 can be miniaturized.

[0047] The functional chip CH3 may be made of a different material other than silicon (for example, GaN or SiC). This can improve the voltage resistance of the functional chip CH3, allowing it to be used in high-voltage power supplies.

[0048] The functional chip CH3 is not limited to having a single electrical function, but may be composed of a combination of elements having multiple electrical functions.

[0049] Figure 3A is a cross-sectional view showing an example of the configuration around the metal pad WP in the semiconductor device 1 according to the first embodiment. Figure 3A is an enlarged view of the dashed frame D shown in Figure 2.

[0050] As shown in Figure 3A, a component 115 may be provided on the right side of the array chip CH2.

[0051] The semiconductor substrate 121 is provided with a recess 1211. The recess 1211 is provided so as to penetrate from the top surface to the bottom surface of the semiconductor substrate 121.

[0052] The array chip CH2 further has an insulating film 124.

[0053] The insulating film 124 is a protective film (passivation film) and includes, for example, polyimide. The insulating film 124 is provided on the side surface of the recess 1211 and on the upper surface of the semiconductor substrate 121. In the example shown in Figure 3A, the insulating film 124 is not provided on the member 115. This is because a portion of the insulating film 124 is removed so that it does not remain in the dicing region when the semiconductor chips 30-33 are separated. However, as shown in Figure 6M, the insulating film 124 may be provided on the member 115, or it may be provided so as to cover a part of the member 115.

[0054] The metal pad WP is provided above the semiconductor substrate 121. More specifically, the metal pad WP is provided on the insulating film 124. The metal pad WP is provided so as to extend from the bottom surface of the recess 1211 in the lateral direction of the recess 1211. That is, the metal pad WP is integrally configured with the wiring that extends from the bottom surface of the recess 1211 to above the semiconductor substrate 121. Therefore, the metal pad WP extends so as to penetrate the semiconductor substrate 121.

[0055] The metal pad WP further comprises metal members 131 and 132.

[0056] The metal component 131 includes, for example, nickel (Ni).

[0057] The metal member 132 is provided so as to cover the metal member 131. The metal member 132 includes, for example, gold (Au).

[0058] The array chip CH2 further includes a contact plug C2.

[0059] The contact plug (columnar electrode) C2 is provided so as to penetrate the interlayer insulating film 122 and extend from the bottom surface of the recess 1211 (the lower surface of the metal pad WP) to the metal pad BP2. Therefore, the contact plug C2 electrically connects the metal pad WP and the circuit chip CH1. The contact plug C2 contains a conductive metal such as tungsten (W).

[0060] Figure 3B is a cross-sectional view showing the power supply path P to the functional chip CH3 in the semiconductor device 1 according to the first embodiment. Power is supplied from a power source (not shown) to the array chip CH2, which is provided with a metal pad WP, ​​via a bonding wire 90 (see Figure 2) with one end connected to the metal pad WP and a wiring board 10 connected to the other end of the bonding wire 90. As shown in Figure 3B, a power supply path P from the power source to the functional chip CH3 is formed between the metal pad WP and the functional chip CH3. The supply path P passes through a contact plug C2 included in the circuit chip CH1. Therefore, even if a metal pad WP is not provided on the functional chip CH3, power can be supplied to the functional chip CH3 via the circuit chip CH1.

[0061] Next, the configuration of the memory cell array 123 and the transistor 113 will be described.

[0062] Figure 4 is a cross-sectional view showing an example of the configuration of the memory cell array 123 and transistor 113 according to the first embodiment.

[0063] The array chip CH2 comprises multiple word lines WL and source lines SL as electrode layers within the memory cell array 123. Figure 4 shows the stepped structure 201 of the memory cell array 123. Each word line WL is electrically connected to the word wiring layer 202 via a contact plug C1. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 203 and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer and a second layer SL2 which is a metal layer.

[0064] The circuit chip CH1 comprises a plurality of transistors 113. Each transistor 113 comprises a gate electrode 301 provided on a semiconductor substrate 111 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the semiconductor substrate 111. The circuit chip CH1 also comprises a plurality of contact plugs 302 provided on the gate electrode 301, source diffusion layer, or drain diffusion layer of the transistors 113, a wiring layer 303 provided on the contact plugs 302 and containing a plurality of wires, and a wiring layer 304 provided on the wiring layer 303 and containing a plurality of wires.

[0065] The circuit chip CH1 further comprises a wiring layer 305 provided on the wiring layer 304 and containing a plurality of wirings, a plurality of via plugs 306 provided on the wiring layer 305, and a plurality of metal pads BP1 provided on the via plugs 306. The metal pads BP1 are, for example, a Cu (copper) layer or an Al (aluminum) layer.

[0066] The array chip CH2 comprises a plurality of metal pads BP2 provided on a metal pad BP1, and a plurality of via plugs 307 provided on the metal pads BP2. The array chip CH2 also comprises a wiring layer 308 provided on the via plugs 307, which includes a plurality of wirings. The metal pads BP2 are, for example, a Cu layer or an Al layer.

[0067] Figure 5 is a cross-sectional view showing an example of the configuration of the columnar portion CL according to the first embodiment.

[0068] As shown in Figure 5, the memory cell array 123 comprises a plurality of word lines WL and a plurality of insulating layers 401 alternately stacked on an interlayer insulating film 122 (see Figure 4). The word lines WL are, for example, W (tungsten) layers. The insulating layers 401 are, for example, silicon oxide films.

[0069] The columnar portion CL includes, in order, a block insulating film 402, a charge storage layer 403, a tunnel insulating film 404, a channel semiconductor layer 405, and a core insulating film 406. The charge storage layer 403 is, for example, a silicon nitride film and is formed on the side surfaces of the word line WL and the insulating layer 401 via the block insulating film 402. The charge storage layer 403 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 405 is, for example, a polysilicon layer and is formed on the side surfaces of the charge storage layer 403 via the tunnel insulating film 404. The block insulating film 402, the tunnel insulating film 404, and the core insulating film 406 are, for example, a silicon oxide film or a metal insulating film.

[0070] Next, we will describe the manufacturing method of the semiconductor device 1.

[0071] Figures 6A to 6M are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0072] First, as shown in Figure 6A, the array wafer W2 is prepared. The preparation of the array wafer W2 includes the steps of forming a memory cell array 123 on a semiconductor substrate 121 and applying a protective film 125 on an interlayer insulating film 122. The protective film 125 is, for example, an alkali-soluble film. The step of applying the protective film 125 may be omitted.

[0073] After preparing the array wafer W2, edge trimming of the array wafer W2 is performed as shown in Figure 6B. After edge trimming, protective tape BT is attached to the array wafer W2. Protective tape BT is used for backgrinding the array wafer W2. After attaching protective tape BT, backgrinding of the array wafer W2 is performed. Backgrinding thins the semiconductor substrate 121.

[0074] After backgrinding, a dicing tape DT1 is attached to the array wafer W2 as shown in Figure 6C. After attaching the dicing tape DT1, the protective tape BT is peeled off. After peeling off the protective tape BT, the peeled surface of the protective film 125 is cleaned. After cleaning the peeled surface of the protective film 125, the array wafer W2 is diced. By performing dicing, the array wafer W2 is divided into multiple array chips CH2. The dicing process does not necessarily have to be performed after cleaning the peeled surface of the protective film 125. The dicing process can be performed before bonding the multiple array chips CH2 and multiple functional chips CH3 onto the circuit wafer W1, which will be described later.

[0075] After dicing, the individual array chips CH2 are transferred to the dicing tape DT2, as shown in Figure 6D. The step of transferring to the dicing tape DT2 may be omitted. After transferring the array chips CH2 to the dicing tape DT2, the protective film 125 is replaced. The step of replacing the protective film 125 may be omitted. After replacing the protective film 125, a pre-bonding treatment is performed. The pre-bonding treatment is a pre-treatment for bonding the array chips CH2 to the circuit wafer W1. The pre-bonding treatment includes, for example, N2 plasma treatment and water washing.

[0076] For the functional chip CH3, preparations for bonding the individual functional chips CH3 to the circuit wafer W1 are carried out by, for example, the same process as for the array chip CH2 (Figures 6A to 6D). That is, first, a wafer (i.e., semiconductor substrate 121) on which the functional chips CH3 are formed before individualization is prepared. Next, the wafer edge trimming, protective tape BT application, and backgrinding are performed in order. Then, the functional chips CH3 are individualized by applying dicing tape DT1, peeling off protective tape BT, cleaning the peeled surface of the protective film 125, and dicing in order. Then, transfer to dicing tape DT2, replacement of protective film 125, and pre-bonding treatment are performed in order. The transfer to dicing tape DT2 and the replacement of protective film 125 may be omitted. The method for manufacturing the functional chip CH3 is not limited to the above method.

[0077] Furthermore, as shown in Figure 6E, a circuit wafer W1 is prepared. The preparation of the circuit wafer W1 includes the step of forming transistors 113 on a semiconductor substrate 111.

[0078] After preparing the circuit wafer W1, a protective film 114 is applied as shown in Figure 6F. The step of applying the protective film 114 may be omitted. After applying the protective film 114, the transistors 113 on the semiconductor substrate 111 are separated by laser grooving. The step of separating the transistors 113 may be omitted. For example, when the circuit wafer W1, to which multiple array chips CH2 and multiple functional chips CH3 described later are joined, is separated into multiple circuit chips CH1, the transistors 113 may be separated together. Laser grooving is performed according to the size of the circuit chip CH1. Separation of the transistors 113 may be performed by other methods such as blade dicing or laser stealth dicing.

[0079] After the transistor 113 is separated into individual components, the protective film 114 is removed as shown in Figure 6G. After removing the protective film 114, the circuit wafer W1 is subjected to pre-bonding treatment. After the pre-bonding treatment of the circuit wafer W1, multiple array chips CH2 and multiple functional chips CH3 are bonded onto the circuit wafer W1. When bonding the array chips CH2 and functional chips CH3 onto the circuit wafer W1, the circuit wafer W1, array chips CH2, and functional chips CH3 are annealed. By bonding the array chips CH2 and functional chips CH3 onto the circuit wafer W1, the metal pads BP1 and BP2 are bonded to each other as shown in Figures 3A and 4. The array chips CH2 are bonded to the circuit wafer W1 so that the circuit wafer W1 (i.e., the circuit chip CH1) and the array chip CH2 are electrically connected by the bonding of the metal pads BP1 and BP2. The functional chips CH3 are also bonded to the circuit wafer W1 so that the circuit wafer W1 and the functional chip CH3 are electrically connected. Annealing may be carried out in a forming gas (for example, a reducing gas mixture of hydrogen and nitrogen).

[0080] After bonding the array chip CH2 and the functional chip CH3 onto the circuit wafer W1, a component 115 is formed on the circuit wafer W1, the array chip CH2, and the functional chip CH3, as shown in Figure 6H. The component 115 is, for example, a resin such as epoxy resin. The component 115 may also be made of a material other than resin, such as SiO2. After forming the component 115, the component 115 is bevel polished.

[0081] After bevel polishing of component 115, back grinding of component 115 is performed as shown in Figure 6I. After back grinding, degassing and annealing (i.e., degass annealing) of component 115 are performed. By performing buckling and degass annealing, the height of the upper surface of component 115 becomes approximately the same as the height of the upper surface of the semiconductor substrate 121 of the array chip CH2 and the functional chip CH3. Back grinding is performed, for example, by CMP (Chemical Mechanical Polishing).

[0082] In Figures 6J to 6M, the cross-sectional view indicated by symbol B is an enlarged view of the dashed frame Dj to Dm on the cross-sectional view indicated by symbol A. However, the figure indicated by symbol A is merely a supplementary figure to represent the range of the dashed frame Dj to Dm (i.e., the range of the enlarged view of symbol B), and is shown with the same appearance regardless of the progress of the process.

[0083] After buckling and degassing of component 115, a recess 1211 is formed in the semiconductor substrate 121, as shown in Figure 6J. Specifically, a recess 1211 is formed in the semiconductor substrate 121 located on the upper side of the array chip CH2, penetrating from the upper surface to the lower surface of the semiconductor substrate 121. By forming the recess 1211, the upper end of the contact plug C2 is exposed. The recess 1211 is formed, for example, by lithography and RIE (Reactive Ion Etching).

[0084] After forming the recess 1211, an insulating film 124 is formed as shown in Figure 6K. The insulating film 124 is formed, for example, on the side surface of the recess 1211 and on the semiconductor substrate 121. The insulating film 124 is formed, for example, by lithography and curing. The insulating film 124 has an opening in the recess 1211.

[0085] After forming the insulating film 124, a seed layer (not shown) is formed. The seed layer contains, for example, titanium (Ti). The seed layer is formed over the entire surface of the underlying layer (i.e., the insulating film 124 and the upper end of the contact plug C2) by, for example, sputtering. After forming the seed layer, as shown in Figure 6L, a resist 116 is patterned by photolithography so that it has an opening 116a at the position where the metal pad WP is to be formed. After patterning the resist 116, metal members 131 and 132 are formed in the opening 116a by plating. By forming the seed layer and the metal members 131 and 132, a metal pad WP is formed on the upper surface of the array chip CH2. More specifically, a metal pad WP is formed which is integrated with wiring extending from the bottom surface of the recess 1211 to above the semiconductor substrate 121 and is provided above the semiconductor substrate 121.

[0086] After forming the metal pad WP, ​​the resist 116 is peeled off as shown in Figure 6M. After peeling off the resist 116, seed layers other than the seed layer under the metal pad WP (not shown) are removed. After removing the seed layers, an Under Bump Metal (UBM) plating (not shown) is formed. The UBM plating is formed, for example, by wet plating. After forming the UBM plating, dicing is performed. By performing dicing, the circuit wafer W1 is divided into multiple circuit chips CH1 (i.e., semiconductor chips 30-33). In Figure 6M, two circuit chips CH1 divided by dicing are shown in a simplified manner. In the example shown in Figure 6M, an insulating film 124 is present on the member 115 at the right end of the array chip CH2. However, as shown in Figure 3A, the insulating film 124 may be removed from the member 115 before dicing.

[0087] After the semiconductor chips 30-33 are separated into individual chips, the separated semiconductor chips 30-33 are mounted on top of the wiring board 10 to perform a package assembly process. By performing the package assembly process, the semiconductor device 1 shown in Figures 1 and 2 is completed.

[0088] Furthermore, before separating the circuit wafer W1 into individual semiconductor chips 30-33, wiring may be connected to the metal pad WP to measure the electrical characteristics of the semiconductor chips 30-33. By measuring the electrical characteristics of the semiconductor chips 30-33, sorting of the semiconductor chips 30-33 can be performed. Therefore, the metal pad WP can be used as a probe terminal before separating the circuit wafer W1 into individual semiconductor chips 30-33.

[0089] Figure 7 shows an example of the sizes of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 according to the first embodiment. In Figure 7, reference numeral A denotes a plan view of the array chip CH2 and functional chip CH3 bonded to the circuit chip CH1. Reference numeral B denotes a front view of the array chip CH2 and functional chip CH3 bonded to the circuit chip CH1. Reference numeral C denotes a side view of the array chip CH2 and functional chip CH3 bonded to the circuit chip CH1.

[0090] In the example shown in Figure 7, the circuit chip CH1, array chip CH2, and functional chip CH3 have a rectangular shape when viewed from the Z direction (i.e., in a plan view). As shown in Figure 7, the area of ​​array chip CH2 is smaller than the area of ​​circuit chip CH1. More specifically, in the example shown in Figure 7, the Y-direction dimension of array chip CH2 is equal to the Y-direction dimension of circuit chip CH1. In the example shown in Figure 7, the Y-direction is perpendicular to the direction in which array chip CH2 and functional chip CH3 are adjacent (i.e., the X-direction) and the thickness direction of circuit chip CH1 (i.e., the Z-direction). Also, the X-direction dimension of array chip CH2 is smaller than the X-direction dimension of circuit chip CH1.

[0091] As shown in Figure 7, the area of ​​the functional chip CH3 is also smaller than the area of ​​the circuit chip CH1. More specifically, in the example shown in Figure 7, the Y-direction dimension of the functional chip CH3 is equal to the Y-direction dimension of the circuit chip CH1. Also, the X-direction dimension of the functional chip CH3 is smaller than the X-direction dimension of the circuit chip CH1. In the example shown in Figure 7, the area of ​​the array chip CH2 is smaller than the area of ​​the functional chip CH3. The relative sizes of the areas of the array chip CH2 and the functional chip CH3 may be reversed from the case in Figure 7. The array chip CH2 and the functional chip CH3 are joined to different regions R1 and R2 on the upper surface of the circuit chip CH1.

[0092] As shown in the example in Figure 7, the Y-direction dimension of array chip CH2 is equal to the Y-direction dimension of functional chip CH3. Because the Y-direction dimension of array chip CH2 is equal to that of functional chip CH3, for example, when using a passive component as functional chip CH3 to improve the power characteristics of array chip CH2, the power characteristics can be improved uniformly for each bit line BL of array chip CH2.

[0093] Furthermore, as shown in the example in Figure 7, the Y-direction dimensions of the array chip CH2 and the functional chip CH3 are equal to the Y-direction dimensions of the circuit chip CH1, and the sum of the X-direction dimensions of the array chip CH2 and the functional chip CH3 is slightly smaller than the X-direction dimensions of the circuit chip CH1. In other words, the sum of the area of ​​the array chip CH2 and the area of ​​the functional chip CH3 is slightly smaller than the area of ​​the top surface of the circuit chip CH1. Therefore, the array chip CH2 and the functional chip CH3 can cover almost the entire top surface of the circuit chip CH1. Note that in the example shown in Figure 7, the X-direction dimension of the array chip CH2 is smaller than the X-direction dimension of the functional chip CH3. The relative sizes of the X-direction dimensions of the array chip CH2 and the functional chip CH3 may be reversed from the case in Figure 7.

[0094] As shown in the example in Figure 7, since almost the entire upper surface of the circuit chip CH1 can be filled with the array chip CH2 and the functional chip CH3, the amount of resin (i.e., component 115) used to fill the air space on the upper surface of the circuit chip CH1 can be reduced as much as possible. Since the amount of resin used, which has a large difference in coefficient of thermal expansion relative to the circuit chip CH1, can be reduced, warping of the semiconductor chips 30 to 33 can be suppressed. Furthermore, the process can be reduced by omitting the formation of component 115. Reducing the process makes it possible to shorten the manufacturing time and reduce the amount of material used. As a result, it is expected that the manufacturing cost of the semiconductor device 1 can be reduced.

[0095] As described above, according to the first embodiment, the semiconductor device 1 comprises at least one semiconductor chip 30 to 33 having a circuit chip CH1, an array chip CH2, and a function chip CH3. The array chip CH2 is bonded to the circuit chip CH1 on a first region R1 on the upper surface of the circuit chip CH1 so as to be electrically connected to the circuit chip CH1. The function chip CH3 is bonded to the circuit chip CH1 on a second region R2 on the upper surface of the circuit chip CH1 so as to be electrically connected to the circuit chip CH1. The array chip CH2 and the function chip CH3 have an area smaller than the area of ​​the circuit chip CH1.

[0096] As a result, even if a difference arises between the element area of ​​the array chip CH2 and the element area of ​​the circuit chip CH1 due to the miniaturization of the memory cell array 123, the area on the circuit chip CH1 resulting from this difference (i.e., the empty space on the second region R2) can be filled by the functional chip CH3. By filling the area on the circuit chip CH1 with the functional chip CH3, assembly risks such as chip tilt can be suppressed. In other words, by eliminating the step difference between the circuit chip CH1 and the array chip CH2, the assembly of the semiconductor device 1 by stacking semiconductor chips 30 to 33 (i.e., die bonding) can be performed easily and appropriately.

[0097] Figure 21 is a cross-sectional view showing an example of the configuration of semiconductor chips 30 and 31 in semiconductor device 1 according to a comparative example. In the example shown in Figure 21, a resin spacer SP is placed on the region on the circuit chip CH1. According to the example shown in Figure 21, it is possible to eliminate the step difference between the circuit chip CH1 and the array chip CH2. However, since the resin spacer SP does not have an electrical function, the region on the circuit chip CH1 cannot be electrically utilized effectively.

[0098] In contrast, according to the first embodiment, by filling the area on the circuit chip CH1 with a functional chip CH3 instead of a resin spacer SP or dummy chip, the area on the circuit chip CH1 can be electrically utilized effectively. In other words, the area on the circuit chip CH1 can be utilized to improve the electrical performance of the semiconductor device 1. Furthermore, the difference between the coefficient of thermal expansion of the functional chip CH3 and the coefficient of thermal expansion of the circuit chip CH1 is smaller than the difference between the coefficient of thermal expansion of the resin spacer SP and the coefficient of thermal expansion of the circuit chip CH1. Therefore, compared to the case where a resin spacer SP is provided, the warping of the semiconductor chips 30 to 33 caused by the difference in coefficients of thermal expansion can be reduced.

[0099] The following several modifications can be applied to the first embodiment.

[0100] (First variation) First, we will explain the first modification of the first embodiment, in which the Y-direction dimension of the functional chip CH3 is smaller than the Y-direction dimension of the array chip CH2, focusing on the differences from the embodiment described above. Figure 8 shows the sizes of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 according to the first modification of the first embodiment.

[0101] Figure 7 illustrates an example where the Y-direction dimension of the functional chip CH3 is equal to the Y-direction dimension of the array chip CH2. In contrast, in the example shown in Figure 8, the Y-direction dimension of the functional chip CH3 is smaller than the Y-direction dimension of the array chip CH2. More specifically, the -Y-direction end of the functional chip CH3 is located further in the Y-direction than the -Y-direction end of the circuit chip CH1. Also, the Y-direction end of the functional chip CH3 is located further in the -Y-direction than the Y-direction end of the circuit chip CH1. More specifically, the functional chip CH3 is located on the center of the second region R2 in the Y-direction.

[0102] As shown in the example in Figure 8, the functional chip CH3 can be formed to a size that meets the required performance, thereby reducing the manufacturing cost of the functional chip CH3.

[0103] (Second variation) Next, a second modification of the first embodiment, in which multiple functional chips CH3A and CH3B of different sizes are provided along the Y direction, will be described, focusing on the differences from the embodiment described above. Figure 9 shows the sizes of the array chip CH2 and functional chips CH3A and CH3B in the semiconductor device 1 according to the second modification of the first embodiment. In the example shown in Figure 9, two functional chips CH3A and CH3B of different sizes are arranged on the second region R2 with a gap in the Y direction. The area of ​​functional chip CH3A is smaller than the area of ​​functional chip CH3B. That is, the Y-direction dimension of functional chip CH3A is smaller than the Y-direction dimension of functional chip CH3B. Also, the X-direction dimension of functional chip CH3A is equal to the X-direction dimension of functional chip CH3B. The function of functional chip CH3A may be different from the function of functional chip CH3B. For example, the functional chip CH3A may be a boost circuit, and the functional chip CH3B may be a capacitor that stores the voltage boosted by the boost circuit.

[0104] As shown in the example in Figure 9, the constraints on the area, number, and function of the functional chips CH3A and CH3B can be relaxed, thereby improving the design flexibility of the semiconductor device 1.

[0105] (Third variation) Next, we will describe a third modification of the first embodiment, in which multiple functional chips CH3 are provided, the dimensions of which in the Y direction are equal to the dimensions of the array chip CH2 in the Y direction, focusing on the differences from the above-described embodiment. Figure 10 is a diagram showing the sizes of the array chip CH2 and functional chips CH3 in the semiconductor device 1 according to the third modification of the first embodiment. In Figure 7, an example was described in which one functional chip CH3 is provided, the dimensions of which in the Y direction are equal to the dimensions of the array chip CH2 in the Y direction. In contrast, in the example shown in Figure 10, two functional chips CH3 are arranged on the second region R2 so as to be adjacent to each other in the X direction, and the dimensions of which in the Y direction are equal to the dimensions of the array chip CH2 in the Y direction. The areas of the two functional chips CH3 are equal to each other.

[0106] As shown in the example in Figure 10, similar to Figure 7, the power supply characteristics can be uniformly improved for each bit line BL of the array chip CH2. Furthermore, since almost the entire upper surface of the circuit chip CH1 can be filled with the array chip CH2 and the functional chip CH3, warping of the semiconductor chips 30-33 can be suppressed.

[0107] (Fourth variation) Next, a fourth modification of the first embodiment, in which multiple functional chips CH3 of equal size are provided along the Y direction, will be described, focusing on the differences from the above-described embodiment. Figure 11 shows the sizes of the array chip CH2 and functional chips CH3 in the semiconductor device 1 according to the fourth modification of the first embodiment. In the example shown in Figure 11, multiple functional chips CH3 of equal size are arranged on the second region R2 so as to be adjacent to each other in the Y direction. The functions of the multiple functional chips CH3 may be the same or different.

[0108] As shown in the example in Figure 11, for example, when heating an array chip CH2 using multiple heaters as multiple function chips CH3, it is possible to control whether or not the array chip CH2 is regenerated by turning the corresponding heater on or off for each of the multiple planes PLN (not shown) of the array chip CH2. The multiple planes PLN are memory areas that can be controlled independently of each other.

[0109] (Fifth variation) Next, we will describe a fifth modification of the first embodiment in which the size of the functional chip CH3 is not uniform, focusing on the differences from the embodiment described above. Figure 12 shows the sizes of the array chip CH2 and functional chip CH3 in the semiconductor device 1 according to the fifth modification of the first embodiment. In Figure 11, an example was described in which multiple functional chips CH3 of equal size are arranged adjacent to each other in the Y direction on the second region R2. In contrast, in the example shown in Figure 12, multiple functional chips CH3 of non-uniform size (e.g., thickness) are arranged adjacent to each other in the Y direction on the second region R2.

[0110] As shown in the example in Figure 12, the constraints on the thickness of the functional chip CH3 can be relaxed, thereby improving the design flexibility of the semiconductor device 1.

[0111] (Sixth variation) Next, we will describe a sixth modification of the first embodiment, in which the metal pad WP and the circuit chip CH1 are electrically connected via a via 133 that penetrates the array chip CH2, focusing on the differences from the embodiments described above. Figure 13 is a cross-sectional view showing the semiconductor device 1 according to the sixth modification of the first embodiment.

[0112] In Figure 6J, an example is described in which a recess 1211 is formed in the semiconductor substrate 121 until the upper end of the contact plug C2 formed in the lower layer of the semiconductor substrate 121 is exposed, and a metal pad WP is formed above the recess 1211. In contrast, in the example shown in Figure 13, a via 133 is provided below the metal pad WP to electrically connect the metal pad WP and the circuit chip CH1.

[0113] As shown in the example in Figure 13, via holes H penetrating the array chip CH2 can be formed in one step, followed by the formation of vias 133 to fill the via holes H and the formation of metal pads WP on the upper ends of the vias 133 (i.e., rewiring). Therefore, since processing of the recess 1211 is not required, manufacturing man-hours can be reduced.

[0114] (Seventh variation) Next, a seventh modification of the first embodiment, in which a metal pad WP is not formed, will be described, focusing on the differences from the above-described embodiment. Figure 14 is a cross-sectional view showing a semiconductor device 1 according to the seventh modification of the first embodiment. In the example shown in Figure 14, a conductive columnar portion 134 is provided that penetrates the member 115 (i.e., resin or SiO2, etc.). The columnar portion 134 is formed, for example, as a bump for the bonding wire 90 before forming the member 115. Alternatively, the columnar portion 134 is formed to fill a hole after a hole has been formed that penetrates the member 115.

[0115] As shown in the example in Figure 14, the formation of metal pads WP (i.e., rewiring) can be omitted, thus reducing manufacturing man-hours. Furthermore, since it is not necessary to form via holes H that penetrate the array chip CH2 (i.e., it is not necessary to provide space in the array chip CH2 for forming via holes H), the chip size of the array chip CH2 can be reduced. Since the chip size of the array chip CH2 can be reduced, the number of chips that can be obtained from the wafer can be increased. Since the number of chips that can be obtained from the wafer can be increased, costs can be reduced. In addition, since the columnar portion 134 and the array chip CH2 can be separated by the component 115 (i.e., resin or SiO2, etc.), direct damage to the array chip CH2 during wire bonding can be avoided. This makes it possible to suppress the occurrence of chip cracks in the array chip CH2 during wire bonding.

[0116] (Variation 8) Next, we will describe an eighth modified example of the first embodiment in which a metal pad WP is formed on the circuit chip CH1, focusing on the differences from the embodiment described above. Figure 15 is a cross-sectional view showing a semiconductor device according to the eighth modified example of the first embodiment. In the example shown in Figure 15, the metal pad WP is provided on the circuit chip CH1. Also, in the example shown in Figure 15, no member 115 (i.e., resin SiO2, etc.) is provided on the circuit chip CH1.

[0117] As shown in the example in Figure 15, the metal pad WP can be formed directly on the circuit chip CH1, thus reducing manufacturing time. Furthermore, since component 115 is not formed, manufacturing time can be further reduced, as can costs. In addition, the chip size of the array chip CH2 can be reduced compared to the example shown in Figure 13, thus reducing costs.

[0118] (9th variation) Figure 16 is a side view showing a semiconductor device 1 according to the ninth modification of the first embodiment. Note that the semiconductor chip 20 shown in Figure 1 is omitted in Figure 16 and Figures 17 to 20 described later. As shown in Figure 16, the number of stacked semiconductor chips 30 to 37 may be increased compared to the embodiment described above. According to the example shown in Figure 16, the memory capacity and design flexibility of the semiconductor device 1 can be improved.

[0119] (10th variation) Figure 17 is a side view showing a semiconductor device 1 according to a tenth modification of the first embodiment. As shown in Figure 17, the number of semiconductor chips 30 to 37 may be increased in the X direction compared to the embodiment described above. According to the example shown in Figure 17, the memory capacity and design flexibility of the semiconductor device 1 can be improved.

[0120] (Second Embodiment) Next, we will explain the second embodiment in which the functional chip is a photoelectric conversion element, focusing on the differences from the embodiment described above. Figure 18 is a side view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. In the second embodiment, the semiconductor chip 30 (i.e., the third semiconductor chip), the semiconductor chip 31 (i.e., the fourth semiconductor chip), and the semiconductor chips 32 and 33 each include a functional chip CH31 composed of a photoelectric conversion element.

[0121] As shown in Figure 18, the semiconductor chips 30-33 further include optical fiber terminals 5a positioned at locations different from those of the metal pads WP (i.e., the second pads). In the example shown in Figure 18, the optical fiber terminals 5a are located on one side of the functional chip CH31 facing the array chip CH2 and on the opposite side.

[0122] In the semiconductor device 1 according to the second embodiment, data is transmitted to and from the functional chip CH31 via the optical fiber 5 connected to the optical fiber terminal 5a. In addition, power is supplied to the semiconductor chips 30-33 via bonding wires 90 (i.e., second wires) that connect the wiring board 10 (i.e., second board) and the metal pads WP of the semiconductor chips 30-33.

[0123] According to the second embodiment, by providing a functional chip CH31 composed of photoelectric conversion elements, high-speed data transmission to the functional chip CH31 can be achieved. As a result, the processing speed of the semiconductor device 1 can be improved.

[0124] (First variation) Figure 19A is a side view showing a semiconductor device 1 according to a first modification of the second embodiment. In the example shown in Figure 19A, the semiconductor chips 30-32 (i.e., the fifth semiconductor chip) stacked on the wiring board 10 (i.e., the third substrate) include a functional chip CH3 that does not have a photoelectric conversion element. A specific example of the functional chip CH3 that does not have a photoelectric conversion element is as described in the first embodiment. On the other hand, the uppermost semiconductor chip 33 placed on semiconductor chip 32 includes a functional chip CH31 composed of a photoelectric conversion element. Also, in the example shown in Figure 19A, the thickness of the functional chip CH31 is greater than the thickness of the array chip CH2. The wiring board 10, the pads WP of semiconductor chips 30-32 (i.e., the fourth pad), and the pads WP of semiconductor chip 33 (i.e., the third pad) are connected by bonding wires 90 (i.e., the third wire).

[0125] As shown in the example in Figure 19A, by placing the photoelectric conversion element CH31 on the top layer, even when the thickness of the photoelectric conversion element CH31 cannot be matched with the thickness of the array chip CH2, it is possible to increase the number of stacked chips and improve processing speed while avoiding assembly difficulties caused by the tilt of the semiconductor chips 30-33. Furthermore, by placing the photoelectric conversion element CH31 on the top layer, the position of the optical fiber terminal 5a can be freely positioned. For example, instead of placing the optical fiber terminal 5a on the side of the photoelectric conversion element CH31 as in Figure 19A, it is possible to place the optical fiber terminal 5a on the top surface of the photoelectric conversion element CH31 as in Figure 19B.

[0126] (Second variation) Figure 20 is a side view showing a semiconductor device 1 according to a second modification of the second embodiment. As shown in Figure 20, the number of stacked semiconductor chips 33 and 37 equipped with a functional chip CH31 composed of a photoelectric conversion element and semiconductor chips 30-32 and 34-36 equipped with a functional chip CH3 without a photoelectric conversion element may be increased. In the example shown in Figure 20, semiconductor chip 33 equipped with a functional chip CH31 composed of a photoelectric conversion element is placed between semiconductor chips 34 and 35 equipped with a functional chip CH3 without a photoelectric conversion element. According to the example shown in Figure 20, the degree of freedom in designing the semiconductor device 1 can be improved.

[0127] (Other embodiments) In the embodiments described above, the array chip CH2 of the semiconductor chips 30-33 includes a three-dimensional memory cell array in which multiple memory cells are arranged in three dimensions. Alternatively, the array chip CH2 may be a two-dimensional memory cell array or an image sensor, etc. Also, it may be a memory element other than NAND flash memory, such as DRAM or SRAM. The array chip CH2 may also be a CMOS circuit element, etc.

[0128] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0129] 1 Semiconductor device, 5 Optical fiber, 5a Optical fiber terminal, 10 Wiring board, 30-33 Semiconductor chip, 90 Bonding wire, CH1 Circuit chip, CH2 Array chip, CH3 Function chip, WP Metal pad, R1 First region, R2 Second region

Claims

1. The first chip and, A second chip is bonded to the first chip on a first region on the upper surface of the first chip so as to be electrically connected to the first chip, and has an area smaller than the area of ​​the first chip. A third chip is bonded to the first chip on a second region on the upper surface of the first chip so as to be electrically connected to the first chip, having a smaller area than the first chip and having an electrical function different from the electrical function of the second chip. A semiconductor device comprising at least one semiconductor chip having [a certain characteristic].

2. The semiconductor device according to claim 1, wherein the sum of the area of ​​the second chip and the area of ​​the third chip is smaller than the area of ​​the top surface of the first chip.

3. The semiconductor device according to claim 1, wherein the area of ​​the second chip is different from the area of ​​the third chip.

4. The semiconductor device according to claim 1, wherein the thickness of the second chip is different from the thickness of the third chip.

5. The first chip has a CMOS circuit, The semiconductor device according to claim 1, wherein the second chip has a non-volatile memory.

6. The semiconductor device according to claim 1, wherein the semiconductor chip has pads.

7. The circuit board is further equipped, The semiconductor device according to claim 6, wherein the semiconductor chip comprises at least a first semiconductor chip disposed on the substrate and a second semiconductor chip disposed on the first semiconductor chip.

8. The semiconductor device according to claim 7, further comprising a wire connecting the substrate, the pad of the first semiconductor chip, and the pad of the second semiconductor chip.

9. The semiconductor device according to claim 5, wherein the third chip has a photoelectric conversion element.

10. The aforementioned semiconductor chip is The second pad, A fiber optic connection terminal positioned at a location different from that of the second pad, The semiconductor device according to claim 9, further comprising the above.

11. Further comprising a second circuit board, The semiconductor device according to claim 10, wherein the semiconductor chip comprises at least a third semiconductor chip disposed on the second substrate and a fourth semiconductor chip disposed on the third semiconductor chip.

12. The semiconductor device according to claim 11, further comprising a second wire connecting the second substrate, the second pad of the third semiconductor chip, and the second pad of the fourth semiconductor chip.

13. The semiconductor device according to claim 12, wherein data is transmitted to and from the photoelectric conversion element via the optical fiber connected to the optical fiber connection terminal, and power is supplied to the third semiconductor chip and the fourth semiconductor chip via the second wire.

14. The semiconductor chip has a third pad, The aforementioned semiconductor device is The third substrate and A fifth semiconductor chip is disposed on or beneath the semiconductor chip on the third substrate and has a fourth pad and a functional chip that does not have the photoelectric conversion element. A third wire connecting the third substrate, the third pad, and the fourth pad, The semiconductor device according to claim 9, further comprising the above.

15. The first chip has a lower pad located on the upper surface of the first chip, The second chip has an upper pad positioned on the lower surface of the second chip so as to be joined to the lower pad. The semiconductor device according to any one of claims 1 to 14.

16. A second chip having an area smaller than the area of ​​the first chip is bonded to a first region on the upper surface of the wafer before it is separated into first chips, so as to be electrically connected to the first chip. A third chip is bonded to a second region on the upper surface of the wafer, having an area smaller than that of the first chip and having an electrical function different from that of the second chip, so as to be electrically connected to the first chip. A method for manufacturing a semiconductor device, comprising the following:

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