semiconductor devices

Abstract

To provide a semiconductor device that can suppress the degradation of its characteristics. [Solution] The semiconductor device comprises a semiconductor substrate, a source region and a drain region arranged with a gap between them on the upper surface of the semiconductor substrate, a body region arranged between the source region and the drain region, a drift region arranged between the body region and the drain region, a gate insulating film provided on the body region, a gate electrode provided on the gate insulating film, an insulating film provided on the drift region, a silicon oxynitride film provided on the insulating film, and a silicon nitride film provided on the silicon oxynitride film.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having a source region, a drain region, and a body region disposed between the source region and the drain region. A drift region having an impurity concentration lower than that of the drain region is provided between the drain region and the body region. Further, an insulating film made of silicon oxide (described as a silicide blocker in Patent Document 1) is provided on the drift region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a semiconductor device, a silicon nitride (SiN) film for applying stress to the body region may be provided. Due to the structure in which SiO2 and SiN are laminated on the drift region, the characteristics of the semiconductor device may deteriorate.

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing deterioration of characteristics.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment includes a semiconductor substrate, a source region and a drain region arranged at intervals on the upper surface of the semiconductor substrate, a body region arranged between the source region and the drain region, a drift region arranged between the body region and the drain region, a gate insulating film provided on the body region, a gate electrode provided on the gate insulating film, an insulating film provided on the drift region, a silicon oxynitride film provided on the insulating film, and a silicon nitride film provided on the silicon oxynitride film. [Effects of the Invention]

[0007] According to the semiconductor device of the present invention, it is possible to suppress the deterioration of performance. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view taken along line II-II' in Figure 1. [Figure 3] Figure 3 is an explanatory diagram illustrating the energy bands in the stacked structure of the drain region, insulating film, SiON film, and SiN film of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is an explanatory diagram illustrating the energy bands in the stacked structure of the drain region, insulating film, SiN film, and SiO2 film of a semiconductor device relating to a comparative example. [Figure 5] Figure 5 is a plan view showing a semiconductor device according to the second embodiment. [Figure 6] Figure 6 is a cross-sectional view taken along the line VI-VI' in Figure 5. [Figure 7] Figure 7 is a plan view showing a semiconductor device according to the third embodiment. [Figure 8] Figure 8 is a cross-sectional view taken along the line VIII-VIII' in Figure 7. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure will be described in detail below with reference to the drawings. However, these embodiments do not limit the present disclosure. Each embodiment described in this disclosure is illustrative, and partial substitution or combination of configurations is possible between different embodiments. In modifications and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects and benefits due to similar configurations will not be mentioned sequentially for each embodiment.

[0010] (First Embodiment) Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along line II-II' in Figure 1. In Figure 1, the silicon nitride film 38 is shown with a dashed line for clarity. In subsequent drawings, the sidewall of the gate electrode 27, which will be described later, is omitted to avoid clutter in the illustration.

[0011] As shown in Figures 1 and 2, the semiconductor device 1 includes an SOI substrate 10 (semiconductor substrate) and a source region 21, a drain region 22, a body region 23, and a drift region 24 formed on the upper surface of the SOI substrate 10. The semiconductor device 1 further includes a gate insulating film 26, a gate electrode 27, silicides 31, 32, and 33, and each insulating film. The source region 21, drain region 22, body region 23, and drift region 24 are provided overlapping the silicides 31, 32, silicide 33 and gate electrode 27, insulating film 36, and SiON film 37, respectively, and are not shown in Figure 1.

[0012] As shown in Figure 2, the SOI (Silicon on Insulator) substrate 10 has a support substrate 11, an embedded oxide layer 12, and a surface silicon layer 13. The SOI substrate 10 is stacked in the order of support substrate 11, embedded oxide layer 12, and surface silicon layer 13. That is, the embedded oxide layer 12 is positioned between the support substrate 11 and the surface silicon layer 13 in the Z direction. The support substrate 11 is, for example, a silicon substrate with a thickness of about 725 μm. The thickness of the embedded oxide layer 12 is, for example, about 400 nm. The thickness of the surface silicon layer 13 is, for example, about 4 nm to 140 nm, preferably 70 nm or less. When the thickness of the surface silicon layer 13 is 70 nm or less, it becomes a fully depleted type SOI (FDSOI), which can further reduce the influence of the substrate capacitance and improve the characteristics.

[0013] In the following explanation, the direction parallel to the surface of the SOI substrate 10 (surface silicon layer 13) is defined as the X direction. The Y direction is parallel to the surface of the SOI substrate 10 (surface silicon layer 13) and perpendicular to the X direction. The Z direction is perpendicular to the surface of the SOI substrate 10 (surface silicon layer 13) and perpendicular to both the X and Y directions. Furthermore, a plan view refers to the arrangement when viewed from a direction perpendicular to the surface of the SOI substrate 10 (Z direction).

[0014] The surface silicon layer 13 is provided with a source region 21, a drain region 22, a body region 23, and a drift region 24. An insulating region 25 is provided surrounding the source region 21, drain region 22, body region 23, and drift region 24. The insulating region 25 is formed of, for example, silicon oxide.

[0015] The source region 21 and the drain region 22 are arranged on the surface of the surface silicon layer 13 (the main surface of the semiconductor substrate) with a spacing in the X direction. Both the source region 21 and the drain region 22 are high-concentration n-type semiconductors. The body region 23 is arranged between the source region 21 and the drain region 22 in the X direction. The drift region 24 is arranged between the body region 23 and the drain region 22 in the X direction. Therefore, on the surface of the surface silicon layer 13 (the main surface of the semiconductor substrate), the source region 21, the body region 23, the drift region 24, and the drain region 22 are arranged in this order in the X direction.

[0016] The body region 23 is a region overlapping with the gate electrode 27, and a channel region is formed. The body region 23 is a p-type semiconductor formed in the surface silicon layer 13 using boron (B) as a dopant.

[0017] The drift region 24 is an n-type semiconductor with a lower concentration than the drain region 22. Since the semiconductor device 1 has the drift region 24, the electric field concentration between the gate and the drain can be suppressed. Thereby, for example, when a predetermined gate voltage is applied to the gate electrode 27, the semiconductor device 1 can suppress the gate insulating film 26 from being damaged by the accelerated electrons.

[0018] The gate insulating film 26 and the gate electrode 27 are laminated on the body region 23. That is, the gate insulating film 26 is arranged between the body region 23 and the gate electrode 27 in the Z direction. As shown in FIG. 2, the gate insulating film 26 and the gate electrode 27 cover the body region 23, and also cover a part of the source region 21 adjacent to the body region 23 and a part of the drift region 24 adjacent to the body region 23.

[0019] The gate insulating film 26 is, for example, silicon oxide formed by thermal oxidation. The thickness of the gate insulating film 26 is, for example, about 5.5 nm or more and 7.5 nm or less. However, it is not limited thereto. For example, for high-voltage withstand applications, the thickness of the gate insulating film 26 may be, for example, about 10 nm.

[0020] The gate electrode 27 is formed of, for example, polysilicon. The thickness of the gate electrode 27 is, for example, about 100 nm to 160 nm. The gate electrode 27 may be amorphous or non-amorphous. Furthermore, impurities may be added to the gate electrode 27 by ion implantation. In this case, the impurity concentration is, for example, 10 20 cm -3 It is to that extent.

[0021] Silicides 31, 32, and 33 are formed on the surfaces of the source region 21, the drain region 22, and the gate electrode 27, respectively. The silicides 31, 32, and 33 may be self-matching silicides (salicides). The silicide 31 provides low resistance to the connection between the source region 21 and the contact 41. Similarly, the silicide 32 provides low resistance to the connection between the drain region 22 and the contact 42. The silicide 33 provides low resistance to the connection between the gate electrode 27 and the contact 43 (not shown in Figure 2).

[0022] As shown in Figure 1, the silicide 31 (source region 21), silicide 32 (drain region 22), silicide 33, and gate electrode 27 (body region 23) have a rectangular shape extending in the Y direction. The insulating film 36 and the SiON film 37 (drift region 24) have a rectangular shape with a shorter length in the Y direction and a longer length in the X direction compared to the silicides 31, 32, 33, etc.

[0023] The semiconductor device 1 has multiple insulating films: an insulating film 36, a silicon oxynitride film 37, and a silicon nitride film 38. In the following description, the silicon oxynitride film 37 will be referred to as the SiON film 37, and the silicon nitride film 38 will be referred to as the SiN film 38.

[0024] The insulating film 36 is provided on the drift region 24. The insulating film 36 further covers the upper surface 27a and the side surface 27b of the gate electrode 27 on the drain region 22 side. The insulating film 36 is not provided on the upper surface of the gate electrode 27 on the source region 21 side. The insulating film 36 is, for example, silicon oxide (SiO2).

[0025] In the example shown in Figure 2, the insulating film 36 is provided in direct contact with the drift region 24, the upper surface 27a of the gate electrode 27, and the side surface 27b of the gate electrode 27. However, a side wall (not shown) may be formed around the gate electrode 27. In this case, the insulating film 36 is in direct contact with the drift region 24 and the upper surface 27a of the gate electrode 27, and is also positioned on the side surface 27b of the gate electrode 27 via the side wall.

[0026] Since an insulating film 36 is provided on the upper surface 27a of the drift region 24 and the gate electrode 27, the formation of silicides in at least the drift region 24 can be suppressed. In other words, silicides 31, 32, and 33 are formed in the regions of the source region 21, gate electrode 27 (body region 23), drift region 24, and drain region 22 where the insulating film 36 is not provided.

[0027] The SiON film 37 is provided on top of the insulating film 36. The SiON film 37 has a planar shape equivalent to that of the insulating film 36. That is, the SiON film 37 is provided above the drift region 24 and covers the upper surface 27a and the side surface 27b of the gate electrode 27 on the drain region 22 side. Furthermore, neither the insulating film 36 nor the SiON film 37 is provided on the upper surface of the gate electrode 27 on the source region 21 side. The insulating film 36 and the SiON film 37 are provided across the entire surface of the drift region 24.

[0028] The thickness of the SiON film 37 is approximately 5 nm to 50 nm, for example, 10 nm. Preferably, the SiON film 37 has a thickness such that no contact area is formed between the insulating film 36 (SiO2) and the SiN film 38. The SiON film 37 prevents the formation of an interface between the insulating film 36 (SiO2) and the SiN film 38. Note that in Figure 2, an interface is formed between the side surface of the insulating film 36 and the SiN film 38. However, in Figure 2, the thicknesses of the insulating film 36, SiON film 37, and SiN film 38 are exaggerated for clarity; in reality, the interface between the side surface of the insulating film 36 and the SiN film 38 is an extremely small area that can be ignored.

[0029] The SiN film 38 covers the entire semiconductor device 1. The SiN film 38 is continuously provided over the regions overlapping the source region 21, body region 23, drift region 24, and drain region 22. The SiN film 38 is formed to apply stress to the body region 23. However, if the thickness of the SiON film 37 provided beneath the SiN film 38 is, for example, greater than 50 nm, the SiN film 38 may not be able to apply stress effectively.

[0030] More specifically, in the region overlapping with the drift region 24 and the upper surface 27a of the gate electrode 27, the SiN film 38 is provided on the insulating film 36 and the SiON film 37. In the Z direction, the SiON film 37 is positioned between the insulating film 36 and the SiN film 38. In regions where the insulating film 36 and the SiON film 37 are not provided, the SiN film 38 is provided on the silicides 31, 32, and 33 provided in the source region 21, the gate electrode 27 (body region 23), and the drain region 22, respectively.

[0031] Specifically, on the upper surface of the gate electrode 27 on the source region 21 side, the silicide 33 and SiN film 38 are stacked in that order. On the upper surface 27a of the gate electrode 27 on the drain region 22 side, the insulating film 36, SiON film 37, and SiN film 38 are stacked in that order. In addition, in the drift region 24, the insulating film 36, SiON film 37, and SiN film 38 are stacked in that order.

[0032] With the above configuration, the semiconductor device 1 is provided with an SiON film 37, which suppresses direct contact between the insulating film 36 (silicon oxide) and the SiN film 38 during stacking. In other words, no interface is formed between the insulating film 36 and the SiN film 38. This prevents electrons accelerated at the pn junction interface from being trapped at the interface between the insulating film 36 and the SiN film 38 when a predetermined gate voltage is applied to the gate electrode 27. That is, in this embodiment, transient responses caused by electron trapping can be suppressed, thus suppressing a decrease in transistor characteristics compared to a configuration without the SiON film 37.

[0033] Figure 3 is an explanatory diagram illustrating the energy bands in the stacked structure of the drain region, insulating film, SiN film, and SiN film of the semiconductor device according to the first embodiment. Figure 4 is an explanatory diagram illustrating the energy bands in the stacked structure of the drain region, insulating film, SiN film, and SiO2 film of the semiconductor device according to a comparative example.

[0034] The semiconductor device according to the comparative example shown in Figure 4 differs from the semiconductor device 1 according to the first embodiment in that it does not have a SiN film 37. That is, in the comparative example, the insulating film 136 and the SiN film 138 are stacked in that order in the drift region 124. The insulating films 36 and 136 in both the first embodiment and the comparative example are silicon oxide (SiO2). In addition, in the comparative example, an SiO2 film 139 is further provided on top of the SiN film 138. However, the SiO2 film 139 is optional.

[0035] In the graphs shown in Figures 3 and 4, the vertical axis represents the band energy when an electric field is applied to the drain, and the horizontal axis represents the position in the Z direction in drift regions 24 and 124. In the graphs shown in Figures 3 and 4, Ev represents the valence band energy, and Ec represents the conduction band energy. The band gap Eg is expressed as Ec - Ev.

[0036] As shown in Figure 4, in the semiconductor device of the comparative example, the band gap of the SiN film 138 is smaller than the band gap of the insulating film 136 (SiO2). Therefore, when a gate voltage is applied, electrons accelerated at the pn junction interface are thought to be trapped at the insulating film 136 / SiN film 138 interface once they overcome the barrier of the insulating film 136 / drift region 124. Since it takes a predetermined amount of time for the trapped electrons to return to the drift region 124, transient responses may occur in the characteristics of the transistor.

[0037] As shown in Figure 3, in the semiconductor device 1 according to the first embodiment, the band gap of the SiON film 37 is larger than the band gap of the SiN film 38. In other words, the difference in band gaps between the insulating film 36 and the SiON film 37 is smaller than the difference in band gaps between the insulating film 136 and the SiN film 138 in the comparative example (Figure 4). As a result, in the semiconductor device 1 according to the first embodiment, the insulating film 136 / SiN film 138 interface is not formed, and the trapping of electrons at the insulating film 36 / SiON film 37 interface can be suppressed. As a result, transient response in the characteristics of the transistor can be suppressed.

[0038] Note that the plan view shapes of each electrode and insulating film shown in Figure 1 are merely examples and are not limited thereto. For example, the source region 21, drain region 22, body region 23, and drift region 24 are not limited to a rectangular shape in plan view, but may be polygonal, circular, oval, or other shapes. Also, the plan view shapes of silicides 31, 32, 33, gate electrode 27, etc., can be appropriately changed according to the source region 21, drain region 22, body region 23, and drift region 24. The thicknesses of each electrode and insulating film shown in Figure 2 are highlighted for clarity. Again, the thicknesses of each electrode and insulating film described above are merely examples and can be appropriately changed.

[0039] Next, an example of a semiconductor device 1 manufacturing method using an SOI substrate 10 will be described. An insulating region 25 is formed on the surface silicon layer 13 of the SOI substrate 10 by, for example, etching and masking techniques. For example, a mask layer made of photoresist is formed on the SOI substrate 10, and anisotropic etching (for example, reactive ion etching (RIE)) is performed. After that, the insulating region 25 can be formed by filling it with a dielectric material such as silicon oxide.

[0040] After the insulating region 25 is formed, a first well, which will become the body region 23, is formed. The first well is formed using, for example, boron (B) as a dopant.

[0041] Next, a gate insulating film 26 and a gate electrode 27 are formed in the body region 23. The gate insulating film 26 is, for example, a silicon oxide film formed by thermal oxidation, and is formed on the upper surface of the body region 23. The gate electrode 27 is formed on the gate insulating film 26 using, for example, polysilicon. The gate electrode 27 can be formed by, for example, chemical vapor deposition (CVD) to reduce its resistance. The thickness and impurity concentration of the gate electrode 27 are as described above.

[0042] Next, after forming the sidewall (not shown) of the gate electrode 27, a drift region 24 is formed in the surface silicon layer 13. The drift region 24 is an n-type semiconductor, and its dopant concentration is, for example, 10 15 cm -3 The above 10 18 cm -3 It is approximately as follows.

[0043] Next, a source region 21 and a drain region 22 are formed on the surface silicon layer 13. The source region 21 and the drain region 22 are high-concentration n-type semiconductors.

[0044] Next, the insulating film 36 (SiO2) and the SiON film 37 are formed. The insulating film 36 (SiO2) and the SiON film 37 are formed in this order by CVD using the same mask. After that, openings are formed in the regions of the insulating film 36 (SiO2) and the SiON film 37 where silicides 31, 32, and 33 are to be formed. The thickness of the insulating film 36 (SiO2) is, for example, about 40 nm to 100 nm. The thickness of the SiON film 37 is, for example, about 5 nm to 50 nm.

[0045] Subsequently, after the silicides 31, 32, and 33 are formed, the SiN film 38 is deposited over the entire surface to manufacture the semiconductor device 1. Note that the above-described manufacturing method is merely an example and can be modified as appropriate. For example, the insulating film 36 (SiO2) and the SiN film 37 may be formed using different masks to have different planar shapes.

[0046] (Second Embodiment) Figure 5 is a plan view showing a semiconductor device according to the second embodiment. Figure 6 is a cross-sectional view taken along line VI-VI' in Figure 5. As shown in Figures 5 and 6, the semiconductor device 1A according to the second embodiment differs from the first embodiment described above in that the SiON film 37 is not provided in a region that overlaps with the drift region 24.

[0047] The SiON film 37 is formed with a different planar shape and area from the insulating film 36. Specifically, the insulating film 36 is provided covering the drift region 24 and the upper surface 27a and side surface 27b of the gate electrode 27 on the drain region 22 side. The SiON film 37 is provided on the insulating film 36, covering the upper surface 27a and side surface 27b of the gate electrode 27 on the drain region 22 side. Furthermore, the SiON film 37 is not provided on the drain region 22 side of the drift region 24.

[0048] In the drift region 24, in the region near the boundary between the body region 23 and the drift region 24, the insulating film 36, the SiON film 37, and the SiN film 38 are stacked in that order. On the drain region 22 side of the drift region 24, the SiON film 37 is not provided, and the insulating film 36 and the SiN film 38 are stacked in that order.

[0049] In this embodiment, the SiN film 37 is provided in the region overlapping with the boundary between the body region 23 and the drift region 24. In other words, the insulating film 36 / SiN film 38 interface is not formed in the region overlapping with the pn junction interface of the surface silicon layer 13. This effectively suppresses the trapping of electrons generated at the pn junction interface at the insulating film 36 / SiON film 37 interface. Furthermore, since the SiN film 38 is laminated on the insulating film 36 in most of the drift region 24, the effect of the SiN film 38 is better obtained compared to the first embodiment, and stress can be applied efficiently.

[0050] (Third embodiment) Figure 7 is a plan view showing a semiconductor device according to the third embodiment. Figure 8 is a cross-sectional view taken along line VIII-VIII' in Figure 7. As shown in Figures 7 and 8, the semiconductor device 1B according to the third embodiment differs from the embodiment described above in that the insulating film 36 and the SiON film 37 cover the drift region 24 and are not provided on the gate electrode 27.

[0051] The insulating film 36 and the SiON film 37 cover almost the entire surface of the drift region 24. The insulating film 36, SiON film 37, and SiN film 38 are stacked on top of the drift region 24 in that order.

[0052] Unlike the embodiments described above, the insulating film 36 and the SiON film 37 are not provided on the upper surface 27a of the gate electrode 27 on the drain region 22 side. The silicide 33 is formed on the entire upper surface of the gate electrode 27. The SiN film 38 is provided on the gate electrode 27 (silicide 33).

[0053] In this embodiment, the area of ​​the silicide 33 can be increased, thereby reducing the resistance of the gate electrode 27. Furthermore, the insulating film 36 and the SiN film 37 are not provided on the gate electrode 27, and instead a SiN film 38 is provided. As a result, the insulating film 36 / SiN film 38 interface is not formed on the gate electrode 27, thus suppressing electron trapping.

[0054] In the embodiments described above, a configuration in which a SiON film 37 is placed between the insulating film 36 and the SiN film 38 was described, but the invention is not limited to SiON, and a material having a larger band gap than the SiN film 38 may be used. In the example described using an SOI substrate 10 as the semiconductor device 1, the invention is not limited to this, and a bulk semiconductor substrate may be used.

[0055] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention may be modified or improved without departing from its spirit, and equivalents thereof are also included. [Explanation of Symbols]

[0056] 1, 1A, 1B Semiconductor Devices 10 SOI substrates 11 Support substrate 12. Embedded Oxide Layer 13. Surface silicon layer 21 Source Area 22 Drain region 23 Body Region 24 Drift region 25 Insulation Area 26 Gate insulating film 27 Shuttle gate 31, 32, 33 Silicide 36 Insulating Film 37. SiON film (silicon oxynitride film) 38 SiN film (silicon nitride film) 41, 42, 43 Contact

Claims

1. Semiconductor substrate and On the upper surface of the semiconductor substrate, a source region and a drain region are arranged with a gap between them, A body region positioned between the source region and the drain region, A drift region is disposed between the body region and the drain region, A gate insulating film provided on the body region, A gate electrode provided on the gate insulating film, An insulating film provided on the drift region, A silicon oxynitride film provided on the insulating film, Having a silicon nitride film provided on the silicon oxynitride film Semiconductor devices.

2. The insulating film and the silicon oxynitride film are provided to cover the drift region, the upper surface and side surface of the gate electrode on the drain region side, The insulating film and the silicon oxynitride film are not laminated on the upper surface of the gate electrode on the source region side. The semiconductor device according to claim 1.

3. The insulating film and the silicon oxynitride film cover the entire surface of the drift region. A semiconductor device according to claim 1 or claim 2.

4. The drift region is laminated in the order of the insulating film, the silicon oxynitride film, and the silicon nitride film. On the upper surface of the gate electrode on the drain region side, the insulating film, the silicon oxynitride film, and the silicon nitride film are stacked in that order. The silicon nitride film is provided on the upper surface of the gate electrode on the source region side. A semiconductor device according to any one of claims 1 to 3.

5. The insulating film is provided to cover the drift region, the upper surface and side surface of the gate electrode on the drain region side, The silicon oxynitride film covers the upper and side surfaces of the gate electrode on the drain region side. In the drain region side of the drift region, the silicon oxynitride film is not provided, and the insulating film and the silicon nitride film are laminated. The semiconductor device according to claim 1.

6. The insulating film and the silicon oxynitride film cover the drift region. The insulating film and the silicon oxynitride film are not provided on the gate electrode, but the silicon nitride film is provided. The semiconductor device according to claim 1.

7. The insulating film is silicon oxide. A semiconductor device according to any one of claims 1 to 6.

8. The semiconductor substrate is an SO-I substrate. A semiconductor device according to any one of claims 1 to 7.

9. The aforementioned SOI substrate is of the fully depleted type. The semiconductor device according to claim 8.

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