Display boards and display devices

Abstract

To provide a display board and a display device. [Solution] The display substrate includes a display area and a non-display area located around the display area, the display area includes an aperture area and a non-aperture area, the display substrate includes a base substrate and a thin-film transistor provided on one side of the base substrate, the thin-film transistor includes a gate, an active layer, source and drain electrodes and an auxiliary film layer, the auxiliary film layer is provided with a cutout area, and the orthographic projection of the cutout area on the base substrate covers at least partially the aperture area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] With the popularization of high-resolution display products and the increasing demand in the virtual reality (VR) market, the display effect of high-resolution display products has gradually become the focus of research. Currently, high-resolution display products generally have the problem of low light transmittance.

Summary of the Invention

Means for Solving the Problems

[0003] The present invention provides a display substrate, which includes a display area and a non-display area located around the display area. The display area includes an opening area and a non-opening area. The display substrate includes a base substrate and a thin film transistor provided on one side of the base substrate. The thin film transistor includes a gate, an active layer, source-drain electrodes, and an auxiliary film layer. A cutout area is provided in the auxiliary film layer, and the orthographic projection of the cutout area on the base substrate at least partially covers the opening area.

[0004] In an optional implementation manner, the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the opening area.

[0005] In an optional implementation manner, the thin film transistor includes a first thin film transistor located in the display area. The first thin film transistor includes a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source. The first active layer is provided so as to approach the base substrate.

[0006] The auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer.

[0007] In one selectable implementation, the first thin-film transistor further includes a shielding layer and a second interlayer dielectric layer provided between the base substrate and the first active layer, wherein the first active layer is provided on the side of the second interlayer dielectric layer away from the base substrate.

[0008] The auxiliary film layer further includes the second interlayer dielectric layer.

[0009] In one selectable implementation method, the thin-film transistor includes a first thin-film transistor located in the display region and a second thin-film transistor located in the non-display region, and the material of the first active layer of the first thin-film transistor includes a metal oxide.

[0010] The second thin-film transistor includes a buffer layer, a second active layer, a second gate insulating layer, and a second gate, which are laminated on the base substrate, the second active layer being positioned closer to the base substrate, and the first thin-film transistor being located on the side of the second gate away from the base substrate, and the material of the second active layer includes polycrystalline silicon.

[0011] The auxiliary film layer includes the buffer layer and the second gate insulating layer, and the orthographic projection of the cutout region in the buffer layer and the second gate insulating layer on the base substrate covers the display region at least partially.

[0012] In one selectable implementation method, a first flat layer is formed on the side of the first thin-film transistor away from the base substrate.

[0013] At the edges of the buffer layer and the second gate insulating layer approaching the display area, the first flat layer forms a stepped portion, and the thickness of the stepped portion on the side approaching the non-display area is smaller than the thickness of the stepped portion on the side approaching the display area.

[0014] In one selectable implementation method, a first passivation layer and a first transparent electrode layer are further laminated on the side of the first source away from the base substrate, and the first passivation layer is provided so as to be closer to the base substrate.

[0015] The first transparent electrode layer includes a first relay electrode, which is connected to the drain contact region of the first active layer via via holes provided in the first passivation layer, the first interlayer dielectric layer, and the first gate insulating layer.

[0016] The auxiliary film layer further includes the first passivation layer.

[0017] In one selectable implementation, a first drain is further provided on the side of the first interlayer dielectric layer away from the base substrate, and the first drain is provided in the same layer as the first source.

[0018] A first transparent electrode layer is further provided on the side of the first drain away from the base substrate, and the first transparent electrode layer includes a first relay electrode, which is in contact with and connected to the first drain, and the first drain is connected to the drain contact region of the first active layer via via holes provided in the first interlayer dielectric layer and the first gate insulating layer.

[0019] In one selectable implementation, the first transparent electrode layer further includes a second relay electrode formed integrally with the first relay electrode, the second relay electrode being located within the non-aperture region.

[0020] A second flat layer is provided on the side of the first transparent electrode layer away from the base substrate, and a first through-hole is provided in the second flat layer, the first through-hole penetrates the second flat layer so as to expose the second relay electrode.

[0021] On the side of the second flat layer away from the base substrate, a second transparent electrode layer, a third flat layer, and a pixel electrode layer are laminated. Here, the second transparent electrode layer is positioned closer to the base substrate, the orthographic projection of the second transparent electrode layer on the base substrate covers the orthographic projection of the first through-hole on the base substrate, the second transparent electrode layer is for connecting the pixel electrode layer and the second relay electrode, and the third flat layer is for flattening the first through-hole.

[0022] In one selectable implementation, a second passivation layer and a third transparent electrode layer are laminated on the side of the first transparent electrode layer away from the base substrate, the second passivation layer is positioned closer to the base substrate, the third transparent electrode layer is connected to a first fixed potential input terminal, and the orthographic projection of the third transparent electrode layer on the base substrate overlaps with the orthographic projection of the first transparent electrode layer on the base substrate.

[0023] In one selectable implementation, a third passivation layer and data lines are laminated on the side of the third transparent electrode layer away from the base substrate, the third passivation layer is positioned closer to the base substrate, the data lines are connected to the first source via via holes provided in the third passivation layer and the second passivation layer, the first source is connected to the source contact region of the first active layer via via holes provided in the first gate insulating layer and the first interlayer dielectric layer, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer, the first source and the first drain on the base substrate.

[0024] In one selectable implementation, the material of the first active layer comprises a metal oxide, the first active layer includes a drain contact region, and the drain contact region is located within the opening region.

[0025] In an optional implementation manner, the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the opening region, and a fourth flat layer is provided on the side of the drain contact region away from the base substrate. A second through hole is provided in the fourth flat layer, and the second through hole penetrates the fourth flat layer so as to expose the drain contact region.

[0026] On the side of the fourth flat layer away from the base substrate, a fourth transparent electrode layer, a fifth flat layer, and a pixel electrode layer are laminated. Here, the fourth transparent electrode layer is provided so as to approach the base substrate, and the orthographic projection of the fourth transparent electrode layer on the base substrate covers the orthographic projection of the second through hole on the base substrate. The fourth transparent electrode layer is for connecting the pixel electrode layer and the drain contact region, and the fifth flat layer is for planarizing the second through hole.

[0027] In an optional implementation manner, the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the opening region, and a pixel electrode layer is provided on the side of the drain contact region away from the base substrate. The pixel electrode layer is in contact with and connected to the drain contact region.

[0028] In an optional implementation manner, a fourth passivation layer and a common electrode layer are laminated on the side of the pixel electrode layer away from the base substrate. The fourth passivation layer is provided so as to approach the base substrate. Here, the common electrode layer includes a plurality of strip-shaped electrodes, and the material of the common electrode layer is metal.

[0029] In an optional implementation manner, the display region further includes data lines and scanning lines. The first source extends along a first direction to form the data lines, and the first gate extends along a second direction intersecting the first direction to form the scanning lines. The orthographic projections of the data lines and the scanning lines on the base substrate both cover the orthographic projection of the channel region of the first active layer on the base substrate.

[0030] In one selectable implementation method, the material of the first active layer includes polycrystalline silicon, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer on the base substrate.

[0031] In one selectable implementation, the channel region of the first active layer includes a first channel region, a first resistive region, and a second channel region arranged sequentially along a first direction, the first gate includes a separately provided first subgate and a second subgate, the orthographic projection of the first subgate on the base substrate covers the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second subgate on the base substrate covers the orthographic projection of the second channel region on the base substrate.

[0032] In one selectable implementation method, the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the channel region of the first active layer on the base substrate.

[0033] In one selectable implementation, the display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the data lines and scan lines on the base substrate.

[0034] In one selectable implementation method, the shielding layer is connected to the second fixed-potential input terminal.

[0035] In one selectable implementation, the shielding layer is connected to the first source via via holes provided in the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer.

[0036] In one selectable implementation, the material of the shielding layer includes at least one of molybdenum, aluminum, and silver.

[0037] The present invention provides a display device including a display board as described in any embodiment.

[0038] The present invention provides a method for manufacturing a display substrate, wherein the display substrate includes a display area and a non-display area located around the display area, the display area includes an aperture area and a non-aperture area, and the manufacturing method is as follows: The steps include preparing the base board and The invention includes the step of manufacturing a thin-film transistor on one side of the base substrate, comprising a gate, an active layer, source and drain electrodes, and an auxiliary film layer, wherein the auxiliary film layer is provided with a cutout region, and the orthographic projection of the cutout region on the base substrate covers at least a portion of the opening region.

[0039] In one selectable implementation method, the thin-film transistor includes a first thin-film transistor located in the display area, and the step of manufacturing the thin-film transistor on one side of the base substrate is: The process includes the step of sequentially forming a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source on one side of the base substrate within the display area to obtain the first thin-film transistor. Here, the auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer.

[0040] In one selectable implementation method, the thin-film transistor includes a first thin-film transistor located in the display region and a second thin-film transistor located in the non-display region, the material of the first active layer of the first thin-film transistor includes a metal oxide, and the material of the second active layer of the second thin-film transistor includes polycrystalline silicon, and the step of manufacturing the thin-film transistor on one side of the base substrate is: Within the non-display region, a buffer layer, a second active layer, a second gate insulating layer, and a second gate are sequentially formed on one side of the base substrate to obtain the second thin-film transistor; The step of forming the first thin-film transistor on the side of the second gate away from the base substrate within the display area, Here, the auxiliary film layer includes the buffer layer and the second gate insulating layer, and the orthographic projection of the cutout region in the buffer layer and the second gate insulating layer on the base substrate covers the display region at least partially.

[0041] The above description is merely an outline of the proposed technical aspects of the present invention, and in order to further clarify the technical means of the present invention, it can be implemented according to the specifications, and in order to further clarify the above and other objectives, features and merits of the present invention, specific embodiments of the present invention are listed below.

[0042] Below, in order to more clearly explain the technical concepts in the embodiments of the present invention or related technologies, the drawings that need to be used in describing the embodiments or related technologies are briefly introduced. Note that the drawings in the following description represent only some embodiments of the present invention, and those skilled in the art can obtain other drawings from these without requiring any creative work. Also, the proportions in the drawings are schematic and do not represent actual proportions. [Brief explanation of the drawing]

[0043] [Figure 1] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 2] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 3] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 4] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 5] This is a schematic diagram showing the planar structure of a display substrate provided in an embodiment of the present invention. [Figure 6] This is a schematic diagram showing the planar structure of the first thin-film transistor provided in an embodiment of the present invention. [Figure 7] This is a schematic diagram showing the cross-sectional structure of the first thin-film transistor provided in an embodiment of the present invention. [Figure 8]This is a schematic diagram showing the planar structure of the shielding layer provided in an embodiment of the present invention. [Figure 9] This is a schematic diagram showing the cross-sectional structure of a display substrate after the lamination of the buffer layer and active layer materials provided in the embodiment of the present invention has been completed. [Figure 10] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the second active layer and buffer layer provided in an embodiment of the present invention have been completed. [Figure 11] This is a schematic diagram showing the cross-sectional structure of a display substrate with a second gate and shielding layer completed, as provided in an embodiment of the present invention. [Figure 12] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the lamination of the second interlayer dielectric material provided in an embodiment of the present invention has been completed. [Figure 13] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the second interlayer dielectric layer provided in an embodiment of the present invention has been completed. [Figure 14] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first active layer provided in an embodiment of the present invention has been completed. [Figure 15] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first gate insulating layer provided in an embodiment of the present invention has been completed. [Figure 16] This is a schematic diagram showing the cross-sectional structure of a display board after the first gate has been completed, as provided in an embodiment of the present invention. [Figure 17] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first source and the first interlayer dielectric layer provided in an embodiment of the present invention have been completed. [Figure 18] This is a schematic diagram showing the cross-sectional structure of a display substrate in which the fourth flat layer, fourth transparent electrode layer, fifth flat layer, and pixel electrode layer provided in the embodiment of the present invention have been completed. [Modes for carrying out the invention]

[0044] In order to further clarify the purpose, technical proposal, and advantages of the embodiments of the present invention, the technical proposal of the embodiments of the present invention will be described more clearly and completely with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the embodiments described are merely some embodiments of the present invention, not all embodiments. All other embodiments obtained based on the embodiments of the present invention, without requiring any creative work from those skilled in the art, fall within the scope of the protection of the present invention.

[0045] One embodiment of the present invention provides a display substrate, which, referring to Figures 1 to 4, includes a display area including an aperture area and a non-aperture area, and a non-display area located around the display area.

[0046] Referring to Figures 1 to 4, the display substrate includes a base substrate 11 and a thin-film transistor provided on one side of the base substrate 11. The thin-film transistor includes a gate, an active layer, source and drain electrodes, and an auxiliary film layer 10. The auxiliary film layer 10 has a cutout region, and the orthographic projection of the cutout region on the base substrate 11 covers at least a portion of the aperture region.

[0047] In this embodiment, the auxiliary film layer 10 may include at least one inorganic film layer such as a buffer layer, an insulating layer, an interlayer dielectric layer, and a passivation layer, or it may include an organic film layer such as a flat layer, but this embodiment is not limited thereto. In subsequent embodiments, the structure of the auxiliary film layer will be described in detail along with the specific structure of the thin-film transistor.

[0048] In practical implementation, the cutout region may be formed by etching the auxiliary film layer within the opening region, but this embodiment is not limited to that.

[0049] In this embodiment, the cut-out region in the auxiliary film layer 10 overlaps with the aperture region. By cutting out the auxiliary film layer within the aperture region, the thickness of the film layer in the aperture region is reduced, the number of film layer interfaces is reduced, and thereby the light transmittance of the aperture region can be improved.

[0050] The inventors simulated the light transmittance of the display substrate provided in this embodiment and discovered from the simulation results that by providing a cut-out region in the auxiliary film layer, the average light transmittance in the visible light wavelength band can be improved by 21%, and the average light transmittance in the 550 nm wavelength band can be improved by 16%. Although the simulation results are related to the specific structure of the display substrate, the increase in light transmittance is not limited in this embodiment.

[0051] The display substrate provided in this embodiment can significantly improve the light transmittance of the aperture region by providing a cutout region in the auxiliary film layer of the aperture region.

[0052] In a direction perpendicular to the plane on which the display substrate is located, the cutout region may completely penetrate the auxiliary film layer 10 or partially penetrate it, but this embodiment is not limited to that. When the cutout region completely penetrates the auxiliary film layer 10, the light transmittance of the aperture region can be further improved.

[0053] In this embodiment, the thin-film transistor may have a top-gate structure (as shown in Figures 1 to 4) or a bottom-gate structure, but this embodiment is not limited thereto. The gate in the thin-film transistor may have a single-gate structure (as shown in Figures 2 to 4), a dual-gate structure (as shown in Figure 1), or a multi-gate structure, but this embodiment is not limited thereto.

[0054] The active layer material may include amorphous silicon, polycrystalline silicon, or metal oxides, but this embodiment is not limited to these. The active layer may include a source contact region, a drain contact region, and a channel region provided between the source contact region and the drain contact region.

[0055] The source-drain electrodes may include, for example, a source and a drain, where the source is connected to the source contact region of the active layer and the drain is connected to the drain contact region of the active layer.

[0056] In one selectable implementation method, the orthographic projection of the auxiliary film layer 10 on the base substrate 11 does not have to overlap with the aperture region; that is, the orthographic projection of the cut-out region on the base substrate 11 completely covers the aperture region, or the orthographic projection of the cut-out region on the base substrate 11 completely overlaps with the aperture region. In this embodiment, the light transmittance of the aperture region can be further improved by cutting out the auxiliary film layer 10 over the widest possible area in the aperture region.

[0057] In one selectable implementation method, referring to Figures 1 to 4, the thin-film transistor may include a first thin-film transistor 12 located in the display area, and the first thin-film transistor 12 may include a stacked first active layer 121, a first gate insulating layer 122, and a first gate 123, and the auxiliary film layer 10 may include the first gate insulating layer 122.

[0058] Here, the first active layer 121 may be provided so as to be close to the base substrate 11, that is, the first thin-film transistor 12 is a transistor having a top gate structure. In this implementation method, the first thin-film transistor 12 has a top gate structure, and compared to the conventional bottom gate structure, the first gate 123 does not need to shield the backlight, so the size can be reduced, and furthermore, the parasitic capacitance formed between the first gate 123 and other film layers can be reduced, thereby reducing energy consumption.

[0059] Selectively, referring to Figures 1 to 4, the first thin-film transistor 12 may further include a first interlayer dielectric layer 124 and a first source 125 provided on the side of the first gate 123 away from the base substrate 11, wherein the first interlayer dielectric layer 124 is provided so as to be closer to the first gate 123. In this implementation, the auxiliary film layer 10 may further include the first interlayer dielectric layer 124.

[0060] Referring to Figures 1 to 4, since the first thin-film transistor 17 has a top-gate structure, in order to avoid the backlight irradiating the first active layer 121 and affecting the electrical characteristics of the first thin-film transistor 12, in one selectable implementation, the first thin-film transistor 12 may further include a shielding layer 126 and a second interlayer dielectric layer 127 provided between the base substrate 11 and the first active layer 121, and the first active layer 121 is provided on the side of the second interlayer dielectric layer 127 away from the base substrate 11. In this implementation, the auxiliary film layer 10 may further include the second interlayer dielectric layer 127.

[0061] In display substrates for related technologies, thin-film transistors located in the non-display area are generally formed using a low-temperature polycrystalline silicon (LTPS) process to ensure circuit driving capability in the non-display area. At the same time, to ensure the display effect of the display area, thin-film transistors located in the display area are generally formed using an indium gallium zinc oxide (IGZO) process. Thin-film transistors formed using the IGZO process can reduce leakage current and improve voltage retention. However, with such a structure, there are extra film layers, such as buffer layers and gate insulating layers, formed by the LTPS process between the thin-film transistors in the display area and the base substrate, which serve no purpose in the display area. These film layers reduce the light transmittance of the display area.

[0062] In one selectable implementation, the thin-film transistor includes a first thin-film transistor 12 located in a display area and a second thin-film transistor 13 located in a non-display area. The material of the first active layer 121 of the first thin-film transistor 12 includes a metal oxide, and the material of the second active layer 132 of the second thin-film transistor 13 includes polycrystalline silicon. Referring to Figures 2 to 4, the second thin-film transistor 13 may include a buffer layer 131, a second active layer 132, a second gate insulating layer 133, and a second gate 134 laminated on a base substrate 11. The first thin-film transistor 12 is located on the side of the second gate 134 away from the base substrate 11. Here, the second active layer 132 may be provided so as to be closer to the base substrate 11.

[0063] In this implementation, the auxiliary film layer 10 may include a buffer layer 131 and a second gate insulating layer 133. The orthographic projection of the cut-out region of the buffer layer 131 and the second gate insulating layer 133 on the base substrate 11 covers the display area at least partially (including the aperture region and the non-aperture region). That is, the orthographic projection of the cut-out region of the buffer layer 131 and the second gate insulating layer 133 on the base substrate 11 overlaps with the display area. This implementation can improve the light transmittance of the display area by removing these extra film layers within the display area.

[0064] In concrete implementation, referring to Figures 2 to 4, the orthographic projection of the buffer layer 131 on the base substrate 11 does not need to overlap with the display area, and the orthographic projection of the second gate insulating layer 133 on the base substrate 11 does not need to overlap with the display area. In this way, the light transmittance of the display area can be further improved.

[0065] In one selectable implementation method, referring to Figures 2 and 4, a first flat layer is formed on the side of the first thin-film transistor 12 away from the base substrate 11 (as shown by 114 in Figure 2 and 14 in Figure 4). At the edges of the buffer layer 131 and the second gate insulating layer 133 approaching the display area, i.e., the boundary between the display area and the non-display area, the first flat layer (as shown by 114 in Figure 2 and 14 in Figure 4) forms a step, and the thickness d1 of the step on the side approaching the non-display area is smaller than the thickness d2 of the step on the side approaching the display area.

[0066] In one selectable implementation, referring to Figure 4, a first passivation layer 15 and a first transparent electrode layer 16 are further laminated on the side of the first source 125 away from the base substrate 11, with the first passivation layer 15 positioned closer to the base substrate 11. Here, the first transparent electrode layer 16 includes a first relay electrode 161, which is connected to the drain contact region of the first active layer 121 via via holes provided in the first passivation layer 15, the first interlayer dielectric layer 124, and the first gate insulating layer 122. In this implementation, the auxiliary film layer 10 may further include the first passivation layer 15.

[0067] In concrete implementation, referring to Figures 1 to 4, the auxiliary film layer 10 may include at least one of the following: a first gate insulating layer 122, a first interlayer dielectric layer 124, a second interlayer dielectric layer 127, a buffer layer 131, a second gate insulating layer 133, and a first passivation layer 15.

[0068] To maximize the light transmittance of the display area, as shown in Figure 1, the auxiliary film layer 10 includes a first gate insulating layer 122, a first interlayer dielectric layer 124, and a second interlayer dielectric layer 127, and the orthographic projections of the first gate insulating layer 122, the first interlayer dielectric layer 124, and the second interlayer dielectric layer 127 on the base substrate 11 do not overlap with the aperture area.

[0069] To maximize the light transmittance of the display area, as shown in Figures 2 and 3, the auxiliary film layer 10 includes a first gate insulating layer 122, a first interlayer dielectric layer 124, a second interlayer dielectric layer 127, a buffer layer 131, and a second gate insulating layer 133. Here, the orthographic projections of the first gate insulating layer 122, the first interlayer dielectric layer 124, and the second interlayer dielectric layer 127 on the base substrate 11 do not overlap with the aperture region, and the orthographic projections of the buffer layer 131 and the second gate insulating layer 133 on the base substrate 11 do not overlap with the display area (including the aperture region and the non-aperture region).

[0070] To maximize the light transmittance of the display area, as shown in Figure 4, the auxiliary film layer 10 includes a first gate insulating layer 122, a first interlayer dielectric layer 124, a second interlayer dielectric layer 127, a buffer layer 131, a second gate insulating layer 133, and a first passivation layer 15. Here, the orthographic projections of the first gate insulating layer 122, the first interlayer dielectric layer 124, the second interlayer dielectric layer 127, and the first passivation layer 15 on the base substrate 11 do not overlap with the aperture area, and the orthographic projections of the buffer layer 131 and the second gate insulating layer 133 on the base substrate 11 do not overlap with the display area (including the aperture area and the non-aperture area).

[0071] In one selectable implementation, referring to Figure 1, a first drain 128 is further provided on the side of the first interlayer dielectric layer 124 away from the base substrate 11, and the first drain 128 is provided in the same layer as the first source 125. On the side of the first drain 128 away from the base substrate 11, a first transparent electrode layer 16 is further provided, and the first transparent electrode layer 16 includes a first relay electrode 161, which is connected to (i.e., in contact with) the first drain 128, and the first drain 128 is connected to the drain contact region of the first active layer 121 via via holes provided in the first interlayer dielectric layer 124 and the first gate insulating layer 122.

[0072] In this implementation method, the material of the first drain 128 may be metal, which reduces the contact resistance between the first drain 128 and the drain contact area.

[0073] To avoid occupying the opening region, the first drain 128 of the metal material and the drain contact region connected to the first drain 128 may both be located within the non-opening region, for example, within the region corresponding to the data line, thereby improving the aperture ratio.

[0074] The material of the first transparent electrode layer 16 is a transparent conductive material, which may include at least one of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and graphene oxide.

[0075] Referring to Figures 1 and 4, the first transparent electrode layer 16 may further include a second relay electrode 162 formed integrally with the first relay electrode 161, the second relay electrode 162 being located within a non-aperture region.

[0076] The second relay electrode 162 is connected to the pixel electrode layer via a via hole, and since the second relay electrode 162 is located within the non-aperture region, it is possible to avoid providing a light-shielding layer to block light leakage from the via hole location, thereby improving the aperture ratio.

[0077] The orthographic projection of the via hole on the base substrate to which the first relay electrode 161 or the first drain 128 is connected to the first active layer 121 does not have to overlap with the orthographic projection of the via hole on the base substrate to which the second relay electrode 162 is connected to the pixel electrode layer. The first transparent electrode layer 16 functions as a relay layer.

[0078] The integrated first relay electrode 161 and second relay electrode 162 allow via holes connected to the pixel electrode layer to be moved to a region with a large area of ​​continuous non-aperture region, thereby enabling the manufacture of larger via holes, reducing process difficulty, and without affecting the aperture ratio. The first transparent electrode layer 16 with relay function solves the problem of insufficient wiring space due to the small pixel space in display substrates with high pixel density.

[0079] In one selectable implementation method, referring to Figures 1 and 4, a second flat layer 14 may be provided on the side of the first transparent electrode layer 16 away from the base substrate 11, and a first through-hole is provided in the second flat layer 14, and the first through-hole penetrates the second flat layer 14 so as to expose the second relay electrode 162. A second transparent electrode layer 17, a third flat layer 18, and a pixel electrode layer 19 may be stacked on the side of the second flat layer 14 away from the base substrate 11. Here, the second transparent electrode layer 17 is provided so as to be close to the base substrate 11, the orthographic projection of the second transparent electrode layer 17 on the base substrate 11 covers the orthographic projection of the first through-hole on the first base substrate 11, the second transparent electrode layer 17 is for connecting the pixel electrode layer 19 and the second relay electrode 162, and the third flat layer 18 is for flattening the first through-hole.

[0080] Here, the materials of the second transparent electrode layer 17 and the pixel electrode layer 19 may be, for example, transparent conductive materials, but this embodiment is not limited to that.

[0081] The third flat layer 18 provided within the first through-hole flattens the first through-hole, eliminating the deep hole structure in the second flat layer 14 and preventing light leakage caused by the deep hole structure. This eliminates the need to provide a large light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0082] On the other hand, since the pixel electrode layer 19 is provided on a flat surface, it is possible to ensure that the distance between the pixel electrode layer and the common electrode layer remains constant, thereby making the electric field uniform, properly deflecting the liquid crystal, avoiding light leakage due to abnormal liquid crystal deflection, and eliminating the need to provide a larger light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0083] Furthermore, by providing the second transparent electrode layer 17 and the pixel electrode layer 19, the problem of increased contact resistance that occurs when only the second transparent electrode layer 17 is provided can be solved. Additionally, by bringing an extra pixel electrode layer 19 into contact with the side of the third flat layer 18 that is away from the base substrate, the problem of increased contact resistance can be solved.

[0084] In one selectable implementation method, referring to Figure 1, a second passivation layer 110 and a third transparent electrode layer 111 are laminated on the side of the first transparent electrode layer 16 away from the base substrate 11. The second passivation layer 110 is positioned closer to the base substrate 11, and the third transparent electrode layer 111 is connected to the first fixed potential input terminal. The orthographic projection of the third transparent electrode layer 111 on the base substrate 11 overlaps with the orthographic projection of the first transparent electrode layer 16 on the base substrate 11. In this implementation method, the first through-hole in the second flat layer 14 further penetrates the second passivation layer 110 so as to expose the second relay electrode 162.

[0085] Here, the material of the third transparent electrode layer 111 may be, for example, a transparent conductive material, but this embodiment is not limited to that.

[0086] The orthographic projection of the third transparent electrode layer 111 on the base substrate 11 overlaps with the orthographic projection of the first transparent electrode layer 16 on the base substrate 11, thus enabling the formation of an accumulation capacitance. In this way, the accumulation capacitance of the pixel is the first accumulation capacitance C formed between the pixel electrode layer 19 and the common electrode layer 118. st1 In addition, the second storage capacitor C formed in the third transparent electrode layer 111 and the first transparent electrode layer 16 st2, and the third storage capacitance C formed in the third transparent electrode layer 111 and the pixel electrode layer 19 st3 Including the total pixel storage capacity is C st1 +C st2 +C st3 Therefore, sufficient storage capacity is guaranteed even with a small pixel space, the voltage retention rate is increased, and normal display is ensured. Here, the voltage at the third transparent electrode layer 111 may be, for example, a common voltage.

[0087] In one selectable implementation, referring to Figure 1, a third passivation layer 112 and data lines 113 are laminated on the side of the third transparent electrode layer 111 away from the base substrate 11. The third passivation layer 112 is positioned closer to the base substrate 11, and the data lines 113 are connected to the first source 125 via via holes provided in the third passivation layer 112 and the second passivation layer 110. The first source 125 is connected to the source contact region of the first active layer 121 via via holes provided in the first gate insulating layer 122 and the first interlayer dielectric layer 124. In this implementation, the first through-hole in the second flat layer 14 further penetrates the third passivation layer 112 so as to expose the second relay electrode 162.

[0088] In this implementation method, by providing the third transparent electrode layer 111 between the data line 113 and the first transparent electrode layer 16, the formation of coupling capacitance due to the distance between the data line 113 and the first transparent electrode layer 16 being too close can be avoided. Since the third transparent electrode layer 111 is connected to a fixed potential, even when the signal on the data line 113 changes at a high frequency, the influence of the signal on the data line 113 on the first transparent electrode layer 16 is shielded, and furthermore, the influence of the data line 113 on the pixel voltage at the pixel electrode layer is shielded, thereby enabling normal display of the pixels.

[0089] In this implementation method, the difficulty of the drilling process can be reduced and the yield can be improved by realizing the connection between the data line 113 and the source contact region of the first active layer 121 using the first source 125.

[0090] The material of the first source 125 may be metal. The orthographic projections of the first source 125 and the source contact area connected to the first source 125 on the base substrate may be located within the range of the orthographic projection of the data line 113 on the base substrate, so as not to occupy the aperture area, thereby improving the aperture ratio of the display area.

[0091] In concrete implementation, the material of the first source 125 may be the same as the material of the first drain 128, but this embodiment is not limited to that.

[0092] In one selectable implementation method, referring to Figures 2 and 3, the material of the first active layer 121 includes a metal oxide, the first active layer 121 includes a drain contact region 21, and the drain contact region 21 is located within the opening region.

[0093] In this implementation method, within the aperture region, the drain contact region 21 may be connected to the pixel electrode layer via a via hole, and since there is no need to manufacture a relay electrode or drain, the aperture ratio and light transmittance can be improved.

[0094] In one selectable implementation, the source contact region and channel region of the first active layer 121 may be arranged along a first direction, and the orthographic projection of the source contact region and channel region of the first active layer 121 on the base substrate 11 may be located within the range of the orthographic projection of the data line 113 on the base substrate 11. The orthographic projection of the drain contact region 21 on the base substrate 11 is located in the opening region, forming an L-shaped active layer.

[0095] In one selectable implementation method, referring to Figure 2, the orthographic projection of the auxiliary film layer 10 on the base substrate 11 does not overlap with the aperture region, a fourth flat layer 114 is provided on the side of the drain contact region 21 away from the base substrate 11, and a second through-hole is provided in the fourth flat layer 114, the second through-hole penetrates the fourth flat layer 114 so as to expose the drain contact region 21. In this implementation method, a fourth transparent electrode layer 115, a fifth flat layer 116, and a pixel electrode layer 19 are stacked on the side of the fourth flat layer 114 away from the base substrate 11. Here, the fourth transparent electrode layer 115 is provided so as to be close to the base substrate 11, the orthographic projection of the fourth transparent electrode layer 115 on the base substrate 11 covers the orthographic projection of the second through hole on the base substrate 11, the fourth transparent electrode layer 115 is for connecting the pixel electrode layer 19 and the drain contact region, and the fifth flat layer 116 is for flattening the second through hole.

[0096] The material of the fourth transparent electrode layer 115 may be, for example, a transparent conductive material, and the pixel electrode layer 19 may also be, for example, a transparent conductive material, but this embodiment is not limited thereto.

[0097] The fifth flat layer 116 provided within the second through-hole flattens the second through-hole, eliminating the deep hole structure in the fourth flat layer 114. By eliminating light leakage caused by the deep hole structure, it becomes unnecessary to provide a large light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0098] On the other hand, since the pixel electrode layer 19 is provided on a flat surface, it is possible to ensure that the distance between the pixel electrode layer and the common electrode layer remains constant, thereby making the electric field uniform, properly deflecting the liquid crystal, avoiding light leakage due to abnormal liquid crystal deflection, and eliminating the need to provide a larger light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0099] Furthermore, by providing the fourth transparent electrode layer 115 and the pixel electrode layer 19, the problem of increased contact resistance that occurs when only the fourth transparent electrode layer 115 is provided can be solved. Additionally, by bringing an extra pixel electrode layer 19 into contact with the side of the fifth flat layer 116 that is away from the base substrate, the problem of increased contact resistance can be solved.

[0100] In one of the selectable implementation methods, referring to Figure 3, the orthographic projection of the auxiliary film layer 10 on the base substrate 11 does not overlap with the aperture region, and a pixel electrode layer 19 is provided on the side of the drain contact region 21 away from the base substrate 11, and the pixel electrode layer 19 is in contact with and connected to the drain contact region 21 (i.e., in contact). Compared to the structure shown in Figure 2, this implementation method does not have a flat layer and a via hole structure, so the process steps can be simplified, the yield can be improved and costs can be reduced. In addition, since the number of film layers and film layer interfaces is reduced, the light transmittance of the aperture region can be further improved.

[0101] In order to form a horizontal electric field, in one selectable implementation method, referring to Figures 1 to 4, a fourth passivation layer 117 and a common electrode layer 118 are stacked on the side of the pixel electrode layer 19 away from the base substrate 11, and the fourth passivation layer 117 is provided so as to be close to the base substrate 11.

[0102] The material of the common electrode layer 118 may be a transparent conductive material or a metallic material, but this embodiment is not limited thereto.

[0103] Here, the common electrode layer 118 may include a plurality of strip-shaped electrodes, which can form a horizontal electric field with the pixel electrode layer 19. The width and pitch of the strip-shaped electrodes may be designed according to actual requirements, but this embodiment is not limited thereto. To reduce light ray crosstalk between adjacent pixels, the material of the common electrode layer 118 may be metal.

[0104] Referring to Figure 5, the display area further includes data lines 113 and scan lines 119, where the data lines 113 extend along a first direction, and the first gate 123 extends along a second direction intersecting the first direction to constitute the scan lines 119, and the orthographic projections of the data lines 113 and scan lines 119 on the base substrate 11 both cover the orthographic projection of the channel region 22 of the first active layer 121 on the base substrate 11.

[0105] Note that, in order to clearly identify the first active layer 121, the scan line 119 and the single data line 113 on the left in Figure 4 are not fully shown. As shown in Figure 5, the data line 113 may be formed by the first source 125 extending along the first direction.

[0106] In one selectable implementation method, the material of the first active layer 121 includes polycrystalline silicon, and as shown in Figure 5, the orthographic projection of the data lines 113 on the base substrate 11 can cover the orthographic projection of the first active layer 121 on the base substrate 11. That is, the orthographic projection of the data lines 113 on the base substrate 11 can cover the orthographic projections of the channel region 22, source contact region 20, and drain contact region 21 on the base substrate 11. This implementation method can avoid the first active layer 121 occupying the aperture region and improve the aperture ratio.

[0107] In one selectable implementation, referring to Figures 6 and 7, the channel region 22 of the first active layer 121 may include a first channel region 61, a first resistive region 62, and a second channel region 63 arranged sequentially along a first direction, the first gate 123 includes separately provided first subgates 64 and 2 subgates 65, the orthographic projection of the first subgate 64 on the base substrate 11 covers the orthographic projection of the first channel region 61 on the base substrate 11, and the orthographic projection of the second subgate 65 on the base substrate 11 covers the orthographic projection of the second channel region 63 on the base substrate 11.

[0108] Note that, in order to clearly identify the first active layer 121, the first subgate 64 and the second subgate 65 in Figure 6 are not fully shown.

[0109] Referring to Figures 6 and 7, the first channel region 61, the first resistance region 62, and the second channel region 63 are arranged sequentially along the first direction to form an I-shaped channel. The first channel region 61 and the second channel region 63 may be equivalent to two thin-film transistor switches connected in series, and the first resistance region 62 may be equivalent to a resistor connected in series between the two thin-film transistor switches. Here, the first resistance region 62 may be formed by performing processes such as ion doping or plasma treatment on the material of the first active layer 121.

[0110] In this embodiment, by providing a first resistance region 62 between the first channel region 61 and the second channel region 63, it is equivalent to connecting a resistor in series between the two thin-film transistor switches. By providing the resistor, the generation of leakage current can be suppressed, thereby reducing the leakage current of the thin-film transistor and improving the stability of the threshold voltage.

[0111] The first subgate 64 is for receiving a signal that controls the on / off state of the first channel region 61. The second subgate 65 is for receiving a signal that controls the on / off state of the second channel region 63. In one selectable implementation, the signals received by the first subgate 64 and the second subgate 65 may be the same, but this embodiment is not limited to that.

[0112] In this implementation method, the first thin-film transistor has a double-gate structure, resulting in high electrical stability and good voltage retention, thus improving the display effect and reliability of the display substrate. Furthermore, because the channel of the first thin-film transistor is an I-type channel, it occupies a small area within the pixel unit of the display substrate, improving the aperture ratio of the display substrate, and significantly improving the aperture ratio, especially for display substrates with high pixel density. This display substrate can also be applied to virtual reality (VR) and augmented reality (AR) display technologies.

[0113] Referring to Figures 6 and 7, the source contact region 20 may include a first conductor region 66 and a second resistance region 67, the second resistance region 67 being positioned close to the first channel region 61. The drain contact region 21 may include a second conductor region 69 and a third resistance region 68, the third resistance region 68 being positioned close to the second channel region 63. By providing the second resistance region 67 and the third resistance region 68, leakage current can be further reduced.

[0114] In one selectable implementation method, referring to Figures 1 to 4, the orthographic projection of the shielding layer 126 on the base substrate 11 covers the orthographic projection of the channel region of the first active layer 121 on the base substrate 11.

[0115] In one selectable implementation method, referring to Figure 8, the display area further includes data lines 113 and scan lines 119, and the orthographic projection of the shielding layer 126 on the base substrate 11 covers the orthographic projection of the data lines 113 and scan lines 119 on the base substrate 11. That is, the shielding layer 126 has a mesh structure. A shielding layer having a mesh structure can increase the area of ​​the shielding layer without affecting the aperture ratio, thereby reflecting more backlight and improving the backlight transmittance.

[0116] In one selectable implementation method, the shielding layer 126 is connected to a second fixed-potential input terminal. This second fixed-potential input terminal may be a fixed-potential input terminal such as a power supply voltage. This implementation method can prevent display abnormalities due to drift in the threshold voltage of the first thin-film transistor and improve the uniformity of the display.

[0117] Referring to Figures 2 and 3, the shielding layer 126 is connected to the first source 125 via via holes provided in the second interlayer dielectric layer 127, the first gate insulating layer 122, and the first interlayer dielectric layer 124.

[0118] To further improve the utilization rate of the backlight, the material of the shielding layer 126 can be a highly reflective metallic material, which may include at least one of molybdenum, aluminum, silver, and tin. By using a shielding layer made of a highly reflective material, the backlight shining on the shielding layer can be reflected, and the reflected backlight can be reused, thereby improving the transmittance of the backlight.

[0119] The shielding layer material may be, for example, Al / top TIN, Al / top Mo, Al alloy / top TIN, or Al alloy / top Mo, and these materials have excellent high-temperature stability and stable reflectivity before and after high-temperature annealing.

[0120] Another embodiment of the present invention further provides a display substrate, referring to Figures 2 and 3, which includes a display area comprising an aperture area and a non-aperture area, and a non-display area located around the display area.

[0121] Referring to Figures 2 and 3, the display substrate includes a base substrate 11 and a first thin-film transistor 12 provided on one side of the base substrate 11. The first thin-film transistor 12 is located within the display area and includes a stacked first active layer 121, a first gate insulating layer 122, and a first gate 123. Here, the material of the first active layer 121 is a metal oxide, and the first active layer 121 includes a drain contact region 21, which is located within the opening region.

[0122] In this embodiment, the display substrate has a drain contact region 21 located within the aperture region. Therefore, the drain contact region 21 may be connected to the pixel electrode layer within the aperture region via a via hole, eliminating the need to manufacture a relay electrode or drain. This allows for improvements in the aperture ratio and light transmittance of the display region. Furthermore, since the material of the first active layer 121 is a transparent metal oxide, even when it is provided in the aperture region, it does not affect the aperture ratio and light transmittance of the display region.

[0123] In this embodiment, the first thin-film transistor 12 may have a top-gate structure (as shown in Figures 2 and 3) or a bottom-gate structure, but this embodiment is not limited thereto. The first gate 123 may have a single-gate structure (as shown in Figures 2 and 3), a dual-gate structure, or a multi-gate structure, but this embodiment is not limited thereto.

[0124] The first active layer 121 further includes a source contact region and a channel region. In one selectable implementation, as shown in Figures 2 and 3, the source contact region and the channel region may be located within a non-opening region, and the source contact region and the channel region of the first active layer 121 may be arranged along a first direction, and the orthographic projection of the source contact region and the channel region of the first active layer 121 on the base substrate 11 may be located within the range of the orthographic projection of the data lines 113 on the base substrate 11. In this implementation, the first active layer 121 is L-shaped.

[0125] In one selectable implementation, referring to Figures 2 and 3, the display substrate further includes a second thin-film transistor 13 located in a non-display area, the second thin-film transistor 13 may include a buffer layer 131, a second active layer 132, a second gate insulating layer 133, and a second gate 134 laminated on the base substrate 11. Here, the second active layer 132 may be provided so as to be close to the base substrate 11, and the material of the second active layer 132 of the second thin-film transistor 13 includes polycrystalline silicon. The first thin-film transistor 12 is located on the side of the second gate 134 away from the base substrate 11.

[0126] The second thin-film transistor 13 may be formed by a low-temperature polycrystalline silicon (LTPS) process, which can improve the circuit driving capability of the non-display area. The first thin-film transistor 12 may be formed by an indium gallium zinc oxide (IGZO) process, which can reduce leakage current, improve voltage retention, and enhance the display effect of the display area.

[0127] In one selectable implementation method, referring to Figure 2, a fourth flat layer 114 is provided on the side of the first thin-film transistor 12 away from the base substrate 12, and a second through-hole is provided in the fourth flat layer 114, the second through-hole penetrates the fourth flat layer 114 so as to expose the drain contact region 21. On the side of the fourth flat layer 114 away from the base substrate 11, a fourth transparent electrode layer 115, a fifth flat layer 116, and a pixel electrode layer 19 are stacked. Here, the fourth transparent electrode layer 115 is provided so as to be close to the base substrate 11, the orthographic projection of the fourth transparent electrode layer 115 on the base substrate 11 covers the orthographic projection of the second through-hole on the base substrate 11, the fourth transparent electrode layer 115 is for connecting the pixel electrode layer 19 and the drain contact region, and the fifth flat layer 116 is for flattening the second through-hole.

[0128] The material of the fourth transparent electrode layer 115 may be, for example, a transparent conductive material, and the pixel electrode layer 19 may also be, for example, a transparent conductive material, but this embodiment is not limited thereto.

[0129] The fifth flat layer 116 provided within the second through-hole flattens the second through-hole, eliminating the deep hole structure in the fourth flat layer 114. By eliminating light leakage caused by the deep hole structure, it becomes unnecessary to provide a large light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0130] On the other hand, since the pixel electrode layer 19 is provided on a flat surface, it is possible to ensure that the distance between the pixel electrode layer and the common electrode layer remains constant, thereby making the electric field uniform, properly deflecting the liquid crystal, avoiding light leakage due to abnormal liquid crystal deflection, and eliminating the need to provide a larger light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0131] Furthermore, by providing the fourth transparent electrode layer 115 and the pixel electrode layer 19, the problem of increased contact resistance that occurs when only the fourth transparent electrode layer 115 is provided can be solved. Additionally, by bringing an extra pixel electrode layer 19 into contact with the side of the fifth flat layer 116 that is away from the base substrate, the problem of increased contact resistance can be solved.

[0132] In one selectable implementation method, referring to Figure 3, a pixel electrode layer 19 is provided on the side of the drain contact region 21 away from the base substrate 11, and the pixel electrode layer 19 is in contact with and connected to the drain contact region 21 (i.e., in contact). Compared to the structure shown in Figure 2, this implementation method does not have a flat layer or via hole structure, so the process steps can be simplified, the yield can be improved, and the cost can be reduced. In addition, since the number of film layers and film layer interfaces is reduced, the light transmittance of the aperture region can be further improved.

[0133] In order to form a horizontal electric field, in one selectable implementation method, referring to Figures 2 and 3, a fourth passivation layer 117 and a common electrode layer 118 are stacked on the side of the pixel electrode layer 19 away from the base substrate 11, and the fourth passivation layer 117 is provided so as to be close to the base substrate 11.

[0134] The material of the common electrode layer 118 may be a transparent conductive material or a metallic material, but this embodiment is not limited thereto.

[0135] Here, the common electrode layer 118 may include a plurality of strip-shaped electrodes, which can form a horizontal electric field with the pixel electrode layer 19. The width and pitch of the strip-shaped electrodes may be designed according to actual requirements, but this embodiment is not limited thereto. To reduce light ray crosstalk between adjacent pixels, the material of the common electrode layer 118 may be metal.

[0136] In one selectable implementation method, the first active layer 121 may be provided so as to be close to the base substrate 11, that is, the first thin-film transistor 12 is a transistor having a top-gate structure. In this implementation method, the first thin-film transistor 12 has a top-gate structure, and compared to the conventional bottom-gate structure, the first gate 123 does not need to shield the backlight, so the size can be reduced, and furthermore, the parasitic capacitance formed between the first gate 123 and other film layers can be reduced, thereby reducing energy consumption.

[0137] Selectively, referring to Figures 2 and 3, the first thin-film transistor 12 may further include a first interlayer dielectric layer 124 and a first source 125 provided on the side of the first gate 123 away from the base substrate 11, wherein the first interlayer dielectric layer 124 is provided so as to be closer to the first gate 123. The fourth flat layer 114 is provided on the side of the first source 125 away from the base substrate 11.

[0138] Referring to Figures 2 and 3, since the first thin-film transistor 17 has a top-gate structure, in one selectable implementation, in order to avoid the backlight irradiating the first active layer 121 and affecting the electrical characteristics of the first thin-film transistor 12, the first thin-film transistor 12 may further include a shielding layer 126 and a second interlayer dielectric layer 127 provided between the base substrate 11 and the first active layer 121, and the first active layer 121 is provided on the side of the second interlayer dielectric layer 127 away from the base substrate 11.

[0139] In one selectable implementation method, referring to Figures 1 to 4, the orthographic projection of the shielding layer 126 on the base substrate 11 covers the orthographic projection of the channel region of the first active layer 121 on the base substrate 11.

[0140] In one selectable implementation method, referring to Figure 8, the display area further includes data lines 113 and scan lines 119, and the orthographic projection of the shielding layer 126 on the base substrate 11 covers the orthographic projection of the data lines 113 and scan lines 119 on the base substrate 11. That is, the shielding layer 126 has a mesh structure. A shielding layer having a mesh structure can increase the area of ​​the shielding layer without affecting the aperture ratio, thereby reflecting more backlight and improving the backlight transmittance.

[0141] In one selectable implementation method, the shielding layer 126 is connected to a second fixed-potential input terminal. This second fixed-potential input terminal may be a fixed-potential input terminal such as a power supply voltage. This implementation method can prevent display abnormalities due to drift in the threshold voltage of the first thin-film transistor and improve the uniformity of the display.

[0142] In one selectable implementation, the shielding layer 126 may be connected to the first source 125. Referring to Figures 2 and 3, the shielding layer 126 is connected to the first source 125 via via holes provided in the second interlayer dielectric layer 127, the first gate insulating layer 122, and the first interlayer dielectric layer 124. A relay electrode 22 may be further provided on the side of the first active layer 121 away from the base substrate, and the first source 125 is connected to the relay electrode 22 via via holes in the first interlayer dielectric layer 124, and the relay electrode 22 is connected to the shielding layer 126 via via holes provided in the second interlayer dielectric layer 127 and the first gate insulating layer 122. The relay electrode 22 enables the connection between the shielding layer 126 and the first source 125, reducing the difficulty of the drilling process.

[0143] To further improve the utilization rate of the backlight, the material of the shielding layer 126 can be a highly reflective metallic material, which may include at least one of molybdenum, aluminum, silver, and tin. By using a shielding layer made of a highly reflective material, the backlight shining on the shielding layer can be reflected, and the reflected backlight can be reused, thereby improving the transmittance of the backlight.

[0144] The material of the shielding layer 126 may be, for example, Al / top TIN, Al / top Mo, Al alloy / top TIN, or Al alloy / top Mo, and these materials have excellent high-temperature stability and stable reflectivity before and after high-temperature annealing.

[0145] To improve the light transmittance of the display area, as shown in Figures 2 and 3, a cutout region is provided in the auxiliary film layer 10 within the display area, and the orthographic projection of the cutout region on the base substrate 11 covers at least partially the aperture region. That is, the cutout region in the auxiliary film layer 10 overlaps with the aperture region. By cutting out the auxiliary film layer within the aperture region, the thickness of the film layer in the aperture region is reduced, the number of film layer interfaces is reduced, and thereby the light transmittance of the aperture region can be improved.

[0146] Referring to Figures 2 and 3, the auxiliary film layer 10 may include at least one of the following: a first gate insulating layer 122, a first interlayer dielectric layer 124, a second interlayer dielectric layer 127, a buffer layer 131, and a second gate insulating layer 133.

[0147] The inventors simulated the light transmittance of the display substrate provided in this embodiment and discovered from the simulation results that by providing a cut-out region in the auxiliary film layer, the average light transmittance in the visible light wavelength band can be improved by 21%, and the average light transmittance in the 550 nm wavelength band can be improved by 16%. Although the simulation results are related to the specific structure of the display substrate, the increase in light transmittance is not limited in this embodiment.

[0148] In a direction perpendicular to the plane on which the display substrate is located, the cutout region may completely penetrate the auxiliary film layer 10 or partially penetrate it, but this embodiment is not limited to that. When the cutout region completely penetrates the auxiliary film layer 10, the light transmittance of the aperture region can be further improved.

[0149] In practical implementation, the cutout region may be formed by etching the auxiliary film layer within the opening region, but this embodiment is not limited to that.

[0150] In one selectable implementation method, the orthographic projection of the auxiliary film layer 10 on the base substrate 11 does not have to overlap with the aperture region; that is, the orthographic projection of the cut-out region on the base substrate 11 completely covers the aperture region, or the orthographic projection of the cut-out region on the base substrate 11 completely overlaps with the aperture region. In this embodiment, the light transmittance of the aperture region can be further improved by cutting out the auxiliary film layer 10 over the widest possible area in the aperture region.

[0151] To maximize the light transmittance of the display area, as shown in Figures 2 and 3, the auxiliary film layer 10 includes a first gate insulating layer 122, a first interlayer dielectric layer 124, a second interlayer dielectric layer 127, a buffer layer 131, and a second gate insulating layer 133. Here, the orthographic projections of the first gate insulating layer 122, the first interlayer dielectric layer 124, and the second interlayer dielectric layer 127 on the base substrate 11 do not overlap with the aperture region, and the orthographic projections of the buffer layer 131 and the second gate insulating layer 133 on the base substrate 11 do not overlap with the display area (including the aperture region and the non-aperture region).

[0152] In one selectable implementation method, referring to Figure 2, a first flat layer 114 is formed on the side of the first thin-film transistor 12 away from the base substrate 11. At the edge of the buffer layer 131 and the second gate insulating layer 133 approaching the display area, i.e., at the boundary between the display area and the non-display area, the first flat layer 114 forms a step, and the thickness d1 of the step on the side approaching the non-display area is smaller than the thickness d2 of the step on the side approaching the display area.

[0153] The material of the first source 125 may be metal. The orthographic projections of the first source 125 and the source contact area connected to the first source 125 on the base substrate may be located within the range of the orthographic projection of the data line 113 on the base substrate, so as not to occupy the aperture area, thereby improving the aperture ratio of the display area.

[0154] Referring to Figure 5, the display area further includes data lines 113 and scan lines 119, where the data lines 113 extend along a first direction, and the first gate 123 extends along a second direction intersecting the first direction to constitute the scan lines 119, and the orthographic projections of the data lines 113 and scan lines 119 on the base substrate 11 both cover the orthographic projection of the channel region 22 of the first active layer 121 on the base substrate 11.

[0155] Note that, in order to clearly identify the first active layer 121, the scan line 119 and the single data line 113 on the left in Figure 4 are not fully shown. As shown in Figure 5, the data line 113 may be formed by the first source 125 extending along the first direction.

[0156] In one selectable implementation, referring to Figures 6 and 7, the channel region 22 of the first active layer 121 may include a first channel region 61, a first resistive region 62, and a second channel region 63 arranged sequentially along a first direction, the first gate 123 includes separately provided first subgates 64 and 2 subgates 65, the orthographic projection of the first subgate 64 on the base substrate 11 covers the orthographic projection of the first channel region 61 on the base substrate 11, and the orthographic projection of the second subgate 65 on the base substrate 11 covers the orthographic projection of the second channel region 63 on the base substrate 11.

[0157] Note that, in order to clearly identify the first active layer 121, the first subgate 64 and the second subgate 65 in Figure 6 are not fully shown.

[0158] Referring to Figures 6 and 7, the first channel region 61, the first resistance region 62, and the second channel region 63 are arranged sequentially along the first direction to form an I-shaped channel. The first channel region 61 and the second channel region 63 may be equivalent to two thin-film transistor switches connected in series, and the first resistance region 62 may be equivalent to a resistor connected in series between the two thin-film transistor switches. Here, the first resistance region 62 may be formed by performing processes such as ion doping or plasma treatment on the material of the first active layer 121.

[0159] In this embodiment, by providing a first resistance region 62 between the first channel region 61 and the second channel region 63, it is equivalent to connecting a resistor in series between the two thin-film transistor switches. By providing the resistor, the generation of leakage current can be suppressed, thereby reducing the leakage current of the thin-film transistor and improving the stability of the threshold voltage.

[0160] The first subgate 64 is for receiving a signal that controls the on / off state of the first channel region 61. The second subgate 65 is for receiving a signal that controls the on / off state of the second channel region 63. In one selectable implementation, the signals received by the first subgate 64 and the second subgate 65 may be the same, but this embodiment is not limited to that.

[0161] In this implementation method, the first thin-film transistor has a double-gate structure, resulting in high electrical stability and good voltage retention, thus improving the display effect and reliability of the display substrate. Furthermore, since the channel of the first thin-film transistor is an I-type channel, the area it occupies in the pixel unit of the display substrate is small, which improves the aperture ratio of the display substrate, and can significantly improve the aperture ratio of display substrates with high pixel density. This display substrate may be applied to virtual reality (VR) display technology, augmented reality (AR) display technology, and the like.

[0162] Referring to Figures 6 and 7, the source contact region 20 may include a first conductor region 66 and a second resistance region 67, the second resistance region 67 being positioned close to the first channel region 61. The drain contact region 21 may include a second conductor region 69 and a third resistance region 68, the third resistance region 68 being positioned close to the second channel region 63. By providing the second resistance region 67 and the third resistance region 68, leakage current can be further reduced.

[0163] Another embodiment of the present invention further provides a display device which may include a display substrate as described in any embodiment.

[0164] In this embodiment, the display device may be any product or component having 2D or 3D display capabilities, such as a display panel, electronic paper, mobile phone, tablet, television, laptop computer, digital camera, or navigator.

[0165] Another embodiment of the present invention further provides a method for manufacturing a display substrate, the display substrate comprising a display area including an aperture area and a non-aperture area, and a non-display area located around the display area, the manufacturing method comprising the following steps.

[0166] Step 11: Prepare the base board.

[0167] Step 12: A thin-film transistor is fabricated on one side of a base substrate, including a gate, an active layer, source and drain electrodes, and an auxiliary film layer, wherein a cutout region is provided in the auxiliary film layer, and the orthographic projection of the cutout region on the base substrate covers at least a portion of the aperture region.

[0168] The manufacturing method provided in this embodiment can be used to manufacture the display board described in any of the above embodiments.

[0169] In one selectable implementation, the thin-film transistor includes a first thin-film transistor located in the display region, and step 12 may include the following steps.

[0170] Within the display area, a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source are sequentially formed on one side of the base substrate to obtain a first thin-film transistor. Here, the auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer.

[0171] In one selectable implementation, the thin-film transistor includes a first thin-film transistor located in a display area and a second thin-film transistor located in a non-display area, wherein the material of the first active layer of the first thin-film transistor includes a metal oxide, and the material of the second active layer of the second thin-film transistor includes polycrystalline silicon, and step 12 may include the following steps: A second thin-film transistor is obtained by sequentially forming a buffer layer, a second active layer, a second gate insulating layer, and a second gate on one side of the base substrate within the non-display area. Here, the auxiliary film layer includes a buffer layer and a second gate insulating layer, and the orthographic projection of the cut-out area of ​​the buffer layer and second gate insulating layer on the base substrate covers at least partially the display area. Within the display area, the first thin-film transistor is formed on the side of the second gate away from the base substrate.

[0172] In one selectable implementation method, the method for manufacturing the display board may specifically include the following steps.

[0173] Step 1: A buffer layer 131 and a-Si are stacked on the base substrate 11, and a-Si is crystallized to form p-Si, thereby obtaining the structure shown in Figure 9.

[0174] Step 2: The p-Si is patterned to obtain the second active layer 132. The buffer layer 131 is patterned to leave only the buffer layer 131 in the non-display area, and the buffer layer 131 in the display area is etched to obtain the structure shown in Figure 10.

[0175] Step 3: The second gate insulating layer 133 is stacked, and the second gate insulating layer 133 in the display area is cut out and patterned to form the second gate 134 and shielding layer 126, obtaining the structure shown in Figure 11.

[0176] Step 4: The second interlayer dielectric layer 127 is stacked to obtain the structure shown in Figure 12. The second interlayer dielectric layer 127 is patterned, and the second interlayer dielectric layer 127 in the opening region is cut out to obtain the structure shown in Figure 13.

[0177] Step 5: IGZO is stacked, and the IGZO is patterned and made conductive to form the first active layer 121, obtaining the structure shown in Figure 14.

[0178] Step 6: The first gate insulating layer 122 is laminated, the first gate insulating layer 122 in the opening region is cut out, and via holes are formed at the corresponding positions to obtain the structure shown in Figure 15.

[0179] Step 7: The gate metal is stacked and patterned to form the first gate 123 and the source and drain of the second thin-film transistor 13, obtaining the structure shown in Figure 16.

[0180] Step 8: The first interlayer dielectric layer 124 and the metal material are stacked and patterned to form the first source 125, and the first interlayer dielectric layer 124 in the opening region is cut out to obtain the structure shown in Figure 17.

[0181] Step 9: The fourth flat layer 114, the fourth transparent electrode layer 115, and the fifth flat layer 116 are formed sequentially to obtain the structure shown in Figure 18.

[0182] Step 10: The pixel electrode layer 19, the fourth passivation layer 117, and the common electrode layer 118 are formed sequentially to obtain the structure shown in Figure 2.

[0183] The various embodiments described herein are described incrementally, with each embodiment focusing on its differences from the others, while identical or similar parts between the embodiments are referenced to one another.

[0184] Finally, it should be noted that, in this specification, relational terms such as "first" and "second" are used solely to distinguish one entity or operation from another, and do not necessarily require or imply that such an actual relationship or order exists between these entities or operations. Also, the terms "include," "contain," or any other variation thereof are intended to mean non-exclusive inclusion. Thus, a process, method, product, or equipment containing a set of elements includes not only those elements but also other elements not explicitly listed, or elements specific to such a process, method, product, or equipment. Unless otherwise specified, an element limited by the phrase "...includes one" does not preclude the existence of other similar elements in a process, method, product, or equipment containing that element.

[0185] The display substrate, its manufacturing method, and display device provided by the present invention have been described in detail above. In this specification, the principles and embodiments of the present invention have been described using specific examples, but the above description of examples is merely to aid in understanding the method and gist of the present invention. Furthermore, those skilled in the art will know that there are changes to the specific embodiments and scope of application based on the concept of the present invention, and therefore, the contents of this specification should not be understood as limitations on the present invention.

[0186] Those skilled in the art will readily acquire other embodiments of the present invention through understanding the specification and practicing the inventions described herein. The present invention includes any modifications, uses, or adaptive variations of the present invention, such modifications, uses, or adaptive variations, in accordance with the general principles of the present invention, and include prior art knowledge or common technical means not disclosed herein. The specification and examples are merely illustrative, and the true scope and spirit of the present invention are indicated by the following claims.

[0187] The present invention is not limited to the specific configurations described above and illustrated in the drawings, and various modifications and changes may be made without departing from its scope. The scope of the present invention is limited only to the appended claims.

[0188] In this specification, “one example,” “an example,” or “one or more examples” means that the specific features, structure, or properties described in conjunction with the examples are included in at least one example of the present invention. It should also be noted that examples of the term “in one example” do not necessarily refer to the same example.

[0189] Many specific details are described in the description provided herein. However, it can be understood that embodiments of the present invention may be realized without these specific details. In some examples, known methods, structures, and techniques are not illustrated in detail so as not to obscure the understanding of this specification.

[0190] In the claims, no reference numerals placed between parentheses shall be configured to limit the scope of the claims. The word “including” shall not preclude the existence of elements or steps not described in the claims. The word “1” or “one” preceding an element shall not preclude the existence of multiple such elements. The present invention can be realized by hardware comprising several different elements and a appropriately programmed computer. In a claim for a unit listing several devices, some of these devices may be concretely embodied by the same hardware. The use of words such as “first,” “second,” “third,” etc., shall not indicate any order. These words may be interpreted as names.

[0191] Finally, the above embodiments are for explaining the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in each of the above embodiments may be modified, or some of their technical features may be equivalently replaced. These modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of each embodiment of the present invention.

Description of Reference Numerals

[0192] 10 Auxiliary film layer 11 Base substrate, first base substrate 12 First thin film transistor 13 Second thin film transistor 14 Second flat layer 15 First passivation layer 16 First transparent electrode layer 17 Second transparent electrode layer 18 Third flat layer 19 Pixel electrode layer 20 Source contact region 21 Drain contact region 22 Relay electrode 61 First channel region 62 First resistance region 63 Second channel region 64 First sub - gate 65 Second sub - gate 66 First conductor region 67 Second resistance region 68 Third resistance region 69 Second conductor region 110 Second passivation layer 111 Third transparent electrode layer 112 Third passivation layer 113 Data line 114 Fourth flat layer 115 Fourth transparent electrode layer 116 Fifth flat layer 117 Fourth passivation layer 118 Common electrode layer 119 Scanning line 121 1st active layer 122 First gate insulating layer 123 Gate 1 124 First interlayer dielectric layer 125 First Source 126 Shielding layer 127 Second Interlayer Dielectric Layer 128 First Drain 131 Buffer Layer 132 2nd active layer 133 Second gate insulating layer 134 Gate 2 161 First relay electrode 162 Second relay electrode

Claims

1. A display substrate comprising a display area and a non-display area located around the display area, wherein the display area includes an aperture area and a non-aperture area, The invention comprises a base substrate and a thin-film transistor provided on one side of the base substrate, wherein the thin-film transistor includes a gate, an active layer, source and drain electrodes, and an auxiliary film layer, the auxiliary film layer having a cutout region, and the orthographic projection of the cutout region on the base substrate covers at least partially the aperture region. The thin-film transistor includes a first thin-film transistor located in the display region and a second thin-film transistor located in the non-display region, and the material of the first active layer of the first thin-film transistor includes a metal oxide. The second thin-film transistor includes a buffer layer, a second active layer, a second gate insulating layer, and a second gate, which are laminated on the base substrate, wherein the second active layer is positioned closer to the base substrate than the buffer layer, the second gate insulating layer, and the second gate, and the material of the second active layer includes polycrystalline silicon. The auxiliary film layer includes the buffer layer and the second gate insulating layer, and the orthographic projection of the cutout region in the buffer layer and the second gate insulating layer on the base substrate covers at least partially the display region. Display board.

2. The display substrate according to claim 1, wherein the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the aperture region.

3. The first thin-film transistor includes a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, wherein the first active layer is positioned to be close to the base substrate. The display board according to claim 1 or 2, characterized by the above.

4. The first thin-film transistor further includes a shielding layer and a second interlayer dielectric layer provided between the base substrate and the first active layer, wherein the first active layer is provided on the side of the second interlayer dielectric layer away from the base substrate. The display board according to claim 3.

5. A first flat layer is formed on the side of the first thin-film transistor that is away from the base substrate. At the edges of the buffer layer and the second gate insulating layer approaching the display area, the first flat layer forms a stepped portion, and the thickness of the stepped portion corresponding to the non-display area is smaller than the thickness of the stepped portion corresponding to the display area. The display board according to claim 1.

6. A first passivation layer and a first transparent electrode layer are further laminated on the side of the first source away from the base substrate, and the first passivation layer is provided so as to be closer to the base substrate than the first transparent electrode layer. The first transparent electrode layer includes a first relay electrode, which is connected to the drain contact region of the first active layer via via holes provided in the first passivation layer, the first interlayer dielectric layer, and the first gate insulating layer. The auxiliary film layer further includes the first passivation layer The display board according to claim 3.

7. A first drain is further provided on the side of the first interlayer dielectric layer away from the base substrate, and the first drain is provided in the same layer as the first source. A first transparent electrode layer is further provided on the side of the first drain closest to the base substrate, and the first transparent electrode layer includes a first relay electrode, which is in contact with and connected to the first drain, and the first drain is connected to the drain contact region of the first active layer via via holes provided in the first interlayer dielectric layer and the first gate insulating layer. The display board according to claim 3.

8. The first transparent electrode layer further includes a second relay electrode formed integrally with the first relay electrode, the second relay electrode being located within the non-aperture region. A second flat layer is provided on the side of the first transparent electrode layer away from the base substrate, and a first through-hole is provided in the second flat layer, and the first through-hole penetrates the second flat layer so as to expose the second relay electrode. On the side of the second flat layer away from the base substrate, a second transparent electrode layer, a third flat layer, and a pixel electrode layer are provided. The second transparent electrode layer is positioned closer to the base substrate than the third flat layer and the pixel electrode layer. The orthographic projection of the second transparent electrode layer on the base substrate covers the orthographic projection of the first through-hole on the base substrate. The second transparent electrode layer connects the pixel electrode layer and the second relay electrode, and the third flat layer flattens the first through-hole. The display board according to claim 6 or 7.

9. A display substrate according to claim 7, wherein a second passivation layer and a third transparent electrode layer are laminated on the side of the first transparent electrode layer away from the base substrate, the second passivation layer is provided so as to be closer to the base substrate than the third transparent electrode layer, the third transparent electrode layer is connected to a first fixed potential input terminal, and the orthographic projection of the third transparent electrode layer on the base substrate overlaps with the orthographic projection of the first transparent electrode layer on the base substrate.

10. A display substrate according to claim 9, wherein a third passivation layer and data lines are laminated on the side of the third transparent electrode layer away from the base substrate, the third passivation layer is provided closer to the base substrate than the data lines, the data lines are connected to the first source via via holes provided in the third passivation layer and the second passivation layer, the first source is connected to the source contact region of the first active layer via via holes provided in the first gate insulating layer and the first interlayer dielectric layer, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer, the first source and the first drain on the base substrate.

11. The display substrate according to claim 3, wherein the material of the first active layer comprises a metal oxide, the first active layer includes a drain contact region, and the drain contact region is located within the opening region.

12. The orthographic projection of the auxiliary film layer on the base substrate does not overlap with the opening region, a fourth flat layer is provided on the side of the drain contact region away from the base substrate, a second through-hole is provided in the fourth flat layer, the second through-hole penetrates the fourth flat layer so as to expose the drain contact region, On the side of the fourth flat layer away from the base substrate, a fourth transparent electrode layer, a fifth flat layer, and a pixel electrode layer are provided. The fourth transparent electrode layer is positioned closer to the base substrate than the fifth flat layer and the pixel electrode layer. The orthographic projection of the fourth transparent electrode layer on the base substrate covers the orthographic projection of the second through-hole on the base substrate. The fourth transparent electrode layer connects the pixel electrode layer and the drain contact region, and the fifth flat layer flattens the second through-hole. The display board according to claim 11.

13. The display substrate according to claim 11, wherein the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the aperture region, a pixel electrode layer is provided on the side of the drain contact region away from the base substrate, and the pixel electrode layer is in contact with and connected to the drain contact region.

14. A display substrate according to any one of claims 8, 12, or 13, wherein a fourth passivation layer and a common electrode layer are laminated on the side of the pixel electrode layer away from the base substrate, the fourth passivation layer is provided so as to be closer to the base substrate than the common electrode layer, the common electrode layer includes a plurality of strip-shaped electrodes, and the material of the common electrode layer is metal.

15. The display substrate according to claim 3, wherein the display area further includes data lines and scan lines, the first source extends along a first direction to constitute the data lines, the first gate extends along a second direction intersecting the first direction to constitute the scan lines, and the orthographic projections of the data lines and scan lines on the base substrate each cover the orthographic projection of the channel area of ​​the first active layer on the base substrate.

16. The display substrate according to claim 15, wherein the material of the first active layer includes polycrystalline silicon, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer on the base substrate.

17. The display substrate according to claim 3, wherein the channel region of the first active layer includes a first channel region, a first resistive region, and a second channel region arranged sequentially along a first direction, the first gate includes a separately provided first subgate and a second subgate, the orthographic projection of the first subgate on the base substrate covers the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second subgate on the base substrate covers the orthographic projection of the second channel region on the base substrate.

18. The display substrate according to claim 4, wherein the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the channel region of the first active layer on the base substrate.

19. The display substrate according to claim 18, wherein the display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the data lines and scan lines on the base substrate.

20. The display board according to claim 19, wherein the shielding layer is connected to the second fixed potential input terminal.

21. The display substrate according to claim 20, wherein the shielding layer is connected to the first source via via holes provided in the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer.

22. The display substrate according to claim 4, wherein the material of the shielding layer comprises at least one of molybdenum, aluminum, and silver.

23. A display device comprising a display board according to any one of claims 1 to 22.

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