Semiconductor equipment

Abstract

This disclosure provides a semiconductor device that can repeatedly write and erase data in a memory structure located adjacent to the side of a planar gate structure. [Solution] The semiconductor device 1 according to the present disclosure includes a semiconductor layer 2 having a first main surface 3, an n-type well region 21 formed on the surface of the first main surface 3 of the semiconductor layer 2, a p-type source region formed on the surface of the well region 21, and a p-type drain region formed on the surface of the well region 21 at a distance from the source region. The semiconductor device 1 further includes an N-LDD region 25 formed on the surface of the first main surface 3 adjacent to the source region, a planar gate structure 30 formed on the first main surface 3 of the semiconductor layer 2 so as to face an n-type channel region between the source region and the drain region, and a memory structure including a nitride film 42 which is a charge storage film arranged adjacent to the side of the planar gate structure 30 on the source region side.

Claims

1. A semiconductor layer having a main surface, A first conductivity type well region formed on the surface portion of the main surface of the semiconductor layer, A first region of a second conductivity type formed on the surface of the well region, A second region of the second conductivity type formed on the surface of the well region at a distance from the first region, The first diffusion layer of the second conductivity type is formed on the surface portion of the main surface adjacent to the first region and the second region, A second diffusion layer of the first conductivity type formed on the surface portion of the main surface adjacent to the first diffusion layer in the first region, A planar gate structure is formed on the main surface of the semiconductor layer so as to face a channel region of a first conductivity type between the first region and the second region, and includes a gate insulating film formed on the main surface and a gate electrode formed on the gate insulating film, A memory structure including a charge storage film arranged adjacent to the side of the planar gate structure on the first region side, A coating insulating film covering a part of the first region, a part of the second region, the planar gate structure, and the memory structure, The coating insulating film includes an interlayer insulating film covering the aforementioned coating insulating film, A semiconductor device wherein, in a plan view, the second diffusion layer has a region that overlaps with a part of the gate insulating film and a part of the memory structure.

2. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. The semiconductor device according to claim 1 or 2, wherein the memory structure is configured to inject hot electrons into the charge storage film using the BTBT phenomenon during a write operation.

4. The semiconductor device according to any one of claims 1 to 3, wherein the memory structure sets the gate-source voltage to 0V during a read operation.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first region is a source region and the second region is a drain region.

6. The semiconductor device according to any one of claims 1 to 5, wherein the charge storage film is formed on the channel region and on an insulating film formed on the side of the planar gate structure.

7. The semiconductor device according to claim 6, wherein the charge storage film is an insulator different from the insulating film.

8. The charge storage film is made of SiN, and the insulating film is made of SiO ２ The semiconductor device according to claim 7, comprising the above.

9. The semiconductor device according to any one of claims 1 to 8, wherein the charge storage film is formed as a sidewall structure covering the sides of the gate insulating film and the gate electrode.

10. The semiconductor device according to any one of claims 1 to 9, further comprising a silicide film formed on the surface portions of the first region and the second region on the side opposite to the memory structure side with respect to the coating insulating film.

11. The semiconductor device according to any one of claims 1 to 10, wherein the first region and the second diffusion layer of the first conductivity type have a region that partially overlaps.

12. The semiconductor device according to any one of claims 1 to 11, wherein the concentration gradient of the first conductivity type impurity in the region adjacent to the first region is greater than the concentration gradient of the first conductivity type impurity in the region adjacent to the second region.

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