Superjunction semiconductor device and method for manufacturing the same

Abstract

Providing a superjunction semiconductor device and a method for manufacturing the same. [Solution] The present invention provides a superjunction semiconductor element and a method for manufacturing the same, which enable cell pitch reduction by forming the source contact in a plug structure, thereby limiting the horizontal width size of the source contact to a certain level or less while ensuring sufficient contact area between the source contact and the source region. The present invention also provides a superjunction semiconductor element and a method for manufacturing the same, which enable easy securing of channel length within the body region and prevent the threshold voltage characteristics of the element from deteriorating by dividing the source region into a first region and a second region enclosed by the first region, thereby preventing the overall concentration of the source region from decreasing and the resistance of the source region from increasing.

Description

Technical Field

[0001] The present invention relates to a super junction semiconductor device and a method for manufacturing the same. More specifically, by forming a source contact in a plug structure, while restricting the horizontal width size of the source contact to a certain level or less, a super junction semiconductor device and a method for manufacturing the same are provided, which can sufficiently secure the contact area between the source contact and the source region and enable cell pitch reduction.

Background Art

[0002] Generally, high-voltage semiconductor devices such as power MOS field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) include a source region and a drain region on the upper and lower surfaces of a drift region, respectively. Further, the high-voltage semiconductor device includes a gate insulating film formed on the upper surface of the drift region adjacent to the source region, and a gate electrode formed on the gate insulating film. In the turn-on state of such a high-voltage semiconductor device, the drift region not only provides a conductive path for the drift current flowing from the drain region to the source region, but also provides a depletion region that expands vertically by the reverse bias voltage applied in the turn-off state.

[0003] The breakdown voltage of these high-voltage semiconductor devices is determined by the characteristics of the depletion region provided by such a drift region. In such high-voltage semiconductor devices, in order to minimize the conduction loss generated in the turn-on state and ensure a rapid switching speed, research has been continued to reduce the on-state resistance of the drift region that provides a conductive path. Generally, it is known that the on-resistance of the drift region can be reduced by increasing the impurity concentration in the drift region. However, when increasing the impurity concentration in the drift region, there is a problem that the breakdown voltage decreases due to an increase in space charge in the drift region.

[0004] To solve these problems, there is a growing trend to utilize high-voltage semiconductor elements with a superjunction structure, which has a novel junction structure that can secure a high brake-down voltage while reducing the resistance in the turn-on state.

[0005] Figure 1 is a cross-sectional view illustrating a conventional superjunction semiconductor device. The structure of the conventional superjunction semiconductor device 9 and its associated problems will be described below.

[0006] A conventional superjunction semiconductor element 9 has a substrate 901, a drain electrode 910 on the bottom surface of the substrate 901, and an epitaxial layer 920 on the top surface of the substrate 901. A filler 930 is formed within the epitaxial layer 920, and a body region 940 is formed on the filler 930 within the epitaxial layer 920. A source region 942 and a body contact region 944 are formed within the body region 940.

[0007] Furthermore, an insulating film 960 is formed to cover the gate electrode 950 on the epitaxial layer 920, and a source metal 970 is formed on the insulating film 960. A source contact 980 can then be formed within the insulating film 860 such that its upper surface is in contact with the source metal 970 and its bottom surface is in contact with the source region 942. Such a source contact 980 can be formed in a planar structure with its bottom surface located on the source region 942.

[0008] Currently, the cell pitch (CP) of superjunction semiconductor elements 9 tends to be narrower. As a result, the source region 942 extends within the body region 940 to the side adjacent to the edge of the body region 940, making it difficult to secure a desired level of channel length CL within the limited cell pitch CP.

[0009] Furthermore, in order to ensure a sufficient contact area between the bottom surface of the planar structure source contact 980 and the source region 942, the horizontal width A of the source contact 980 must be made sufficiently large, which presents the problem of increasing the cell pitch CP of the element 9.

[0010] Furthermore, during the ion implantation and drive-in process for forming the body region 940, if the drive-in process is not performed for a sufficient amount of time, the first conductivity type impurity will not diffuse sufficiently to the lower part of the body region 940, and the concentration of the first conductivity type impurity in the lower part of the body region 940 may not reach the desired level. This can degrade the UIS (Unclamped Inductive Switching) characteristics of the element 9.

[0011] To solve the aforementioned problems, the inventors of the present invention aim to present a novel superjunction semiconductor element having an improved structure and a method for manufacturing the same. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Korean Published Patent No. 10-2005-0052597, "Superjunction Semiconductor Device" [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] The present invention aims to solve the problems of the prior art described above, and its objective is to provide a superjunction semiconductor element and a method for manufacturing the same that can reduce the cell pitch by forming the source contact with a plug structure, thereby limiting the horizontal width size of the source contact to a certain level while ensuring sufficient contact area between the source contact and the source region.

[0014] Another object of the present invention is to provide a superjunction semiconductor element and a method for manufacturing the same, which prevents a decrease in the threshold voltage characteristics of the element by dividing the source region into a first region and a second region enclosed by the first region, thereby easily securing the channel length within the body region, and preventing the overall concentration of the source region from decreasing and the resistance of the source region from increasing.

[0015] Another object of the present invention is to provide a superjunction semiconductor device and a method for manufacturing the same, which prevents a decrease in the UIS characteristics of the device by ensuring that the impurity doping concentration in the lower part of the body region is at a desired level, by having each body region formed through two or more ion implantation and drive-in processes.

[0016] Another object of the present invention is to provide a superjunction semiconductor element and a method for manufacturing the same, which ensures a sufficient channel length within the body region by forming a sidewall on the side wall of the gate electrode before the source region is formed. [Means for solving the problem]

[0017] The above objectives can be achieved by an embodiment having the following configuration.

[0018] According to one embodiment of the present invention, the superjunction semiconductor element according to the present invention is characterized by comprising: a substrate; an epitaxial layer on the substrate; a filler in the epitaxial layer; a body region on the filler in the epitaxial layer; a source region in the body region; a gate electrode on the epitaxial layer; an interlayer insulating film covering the gate electrode on the epitaxial layer; a source metal on the interlayer insulating film; and a source contact connected to the source metal, with its bottom surface located within the body region.

[0019] According to another embodiment of the present invention, the source contact of the super junction semiconductor device according to the present invention is characterized in that the bottom surface is located within the source region.

[0020] According to another embodiment of the present invention, the source contact of the super junction semiconductor device according to the present invention is characterized in that at least one side of its side wall is in contact with the source region.

[0021] According to another embodiment of the present invention, the source region of the super junction semiconductor device according to the present invention includes a first region and a second region surrounded by the first region.

[0022] According to another embodiment of the present invention, the first region of the super junction semiconductor device according to the present invention is characterized in that it contains impurities of an element different from that of the second region.

[0023] According to another embodiment of the present invention, the first region of the super junction semiconductor device according to the present invention is characterized in that it contains impurities of an element having a higher diffusion coefficient with respect to heat than the second region.

[0024] According to another embodiment of the present invention, the super junction semiconductor device according to the present invention further includes an ohmic contact region within the body region, and the ohmic contact region is in contact with the bottom surface of the source contact.

[0025] According to another embodiment of the present invention, the super junction semiconductor device according to the present invention further includes sidewalls on the sidewalls of the gate electrode.

[0026] According to another embodiment of the present invention, the body regions of the super junction semiconductor device according to the present invention are each completed through two or more ion implantation steps and drive-in steps.

[0027] According to another embodiment of the present invention, the super junction semiconductor device according to the present invention includes a substrate, an epitaxial layer of a second conductivity type on the substrate, a filler of a first conductivity type in the epitaxial layer, a body region of the first conductivity type on the filler in the epitaxial layer, a source region of the second conductivity type in the body region, a gate electrode on the epitaxial layer, an interlayer insulating film covering the gate electrode on the epitaxial layer, a source metal on the interlayer insulating film, and a source contact connected to the source metal and the source region. The source region includes a first region and a second region which are impurity doping regions of different elements from each other.

[0028] According to another embodiment of the present invention, the first region of the super junction semiconductor device according to the present invention has a horizontal width size larger than that of the second region.

[0029] According to another embodiment of the present invention, the first region of the super junction semiconductor device according to the present invention is an impurity doping region of P element, and the second region is an impurity doping region of As element.

[0030] According to another embodiment of the present invention, the source contact of the super junction semiconductor device according to the present invention has a bottom surface located in the source region and side walls contacting the first region and the second region.

[0031] According to another embodiment of the present invention, the super junction semiconductor device according to the present invention further includes a first conductivity type ohmic contact region below the source contact in the body region.

[0032] According to another embodiment of the present invention, the super junction semiconductor device according to the present invention further includes a sidewall on a sidewall of the gate electrode, and the sidewall is formed on the sidewall of the gate electrode before formation of the source region.

[0033] According to one embodiment of the present invention, a method for manufacturing a superjunction semiconductor element according to the present invention is characterized by comprising the steps of: forming an epitaxial layer on a substrate; forming a filler in the epitaxial layer; forming a body region on the filler in the epitaxial layer; forming a gate electrode on the epitaxial layer; forming a source region and an ohmic contact region in the body region; forming an interlayer insulating film on the epitaxial layer so as to cover the gate electrode; forming a source contact in the interlayer insulating film such that its bottom surface is located in the body region or the source region; and forming a source metal on the source interlayer insulating film so as to be connected to the source contact.

[0034] According to another embodiment of the present invention, in a method for manufacturing a superjunction semiconductor device according to the present invention, the body region formation step is characterized by comprising the steps of forming a prebody region on the filler in the epitaxial layer and, after forming the gate electrode, using the gate electrode as a mask pattern to ion implant a first conductivity type impurity into the prebody region and performing a drive-in process to form a body region.

[0035] According to another embodiment of the present invention, in a method for manufacturing a superjunction semiconductor device according to the present invention, the source region formation step includes the step of forming a first region which is a second conductivity type impurity doping region within the body region, and the step of forming a second region which is a second conductivity type impurity doping region within the first region, wherein the second conductivity type impurity for forming the second region has a smaller thermal diffusion coefficient than the second conductivity type impurity for forming the first region.

[0036] According to another embodiment of the present invention, the method for manufacturing a superjunction semiconductor element according to the present invention further comprises the step of forming a sidewall on the sidewall of the gate electrode before forming the source region and the ohmic contact region.

[0037] According to another embodiment of the present invention, in a method for manufacturing a superjunction semiconductor element according to the present invention, the source contact formation step includes the step of forming a trench in the interlayer insulating film and the source region, and the step of completing the source contact by gap-filling the trench with a conductive material, wherein the source contact is characterized in that its side wall is in contact with the source region. [Effects of the Invention]

[0038] The present invention has the following effects due to the configuration described above.

[0039] The present invention has the effect of enabling a reduction in cell pitch by forming the source contact with a plug structure, thereby limiting the horizontal width size of the source contact to a certain level while ensuring sufficient contact area between the source contact and the source region.

[0040] Furthermore, the present invention has the effect of easily securing the channel length within the body region by dividing the source region into a first region and a second region enclosed by the first region, and preventing a decrease in the threshold voltage characteristics of the element by preventing the overall concentration of the source region from decreasing and the resistance of the source region from increasing.

[0041] Furthermore, the present invention has the effect of preventing a decrease in the UIS characteristics of the device by ensuring that the impurity doping concentration in the lower part of the body region is at a desired level, by forming each body region through two or more ion implantation and drive-in processes.

[0042] Furthermore, the present invention has the effect of ensuring a sufficient channel length within the body region by forming a sidewall on the side wall of the gate electrode before the source region is formed.

[0043] On the other hand, even effects not explicitly mentioned herein, as well as the effects described below in the specification and their provisional effects that are expected by the technical features of the present invention, shall be treated as described in the specification of the present invention. [Brief explanation of the drawing]

[0044] [Figure 1] This is a cross-sectional view illustrating a conventional superjunction semiconductor device. [Figure 2] This is a cross-sectional view illustrating a superjunction semiconductor device according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 9] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 10]This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 11] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 12] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 14] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 15] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 16] This is a cross-sectional view illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention. [Figure 17] This graph illustrates the doping concentration levels of a superjunction semiconductor device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0045] Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Embodiments of the present invention can be modified in various forms, and the scope of the invention should not be construed as being limited to these embodiments, but rather as being construed based on the claims. Furthermore, these embodiments are provided only as reference to further fully illustrate the present invention to those who are ordinary skill in the art.

[0046] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Also, as used herein, “comprise” and / or “comprising” identify the presence of the shape, figure, step, action, member, element, and / or group thereof mentioned, and do not exclude the presence or addition of one or more other shapes, figures, actions, members, elements, and / or groups thereof.

[0047] In the following, when it is stated that one component (or layer) is placed on another component (or layer), it should be noted that the component may also be placed directly on the other component, or another component or layer may be interposed between them. Also, when it is stated that one component is placed directly on another component, there is no other component located between them. Furthermore, being located "on top," "above," "below," "upper side," "lower side," "one side," or "side" of a component refers to a relative positional relationship.

[0048] Furthermore, terms such as "first," "second," etc., can be used to describe various items such as various elements, domains, and / or parts, but the items are not limited to those terms.

[0049] Furthermore, it should be noted that in cases where a particular embodiment can be realized in a different manner, the specific sequence of steps may differ from the order described below. For example, two steps described sequentially may be performed substantially simultaneously or in the opposite order.

[0050] Furthermore, the conductivity type or doping region of the constituent elements can be defined as "P-type" or "N-type" depending on the main carrier characteristics, but this is for illustrative purposes only, and the technical concept of the present invention is not limited to what is illustrated. For example, below, "P-type" or "N-type" will be used as the more general terms "first conductivity type" or "second conductivity type," where the first conductivity type means P-type and the second conductivity type means N-type. Alternatively, "N-type" can be set as the "first conductivity type" and "P-type" as the "second conductivity type."

[0051] Furthermore, the terms "high concentration" and "low concentration," used to describe doping concentrations in the impurity range, should be understood as referring to the relative doping concentrations of one component and other components.

[0052] Furthermore, the structure described below is understood to be limited to the cell region, which is the active region of the superjunction semiconductor element 1.

[0053] Figure 2 is a cross-sectional view illustrating a superjunction semiconductor device according to one embodiment of the present invention.

[0054] In the following, a superjunction semiconductor element 1 according to one embodiment of the present invention will be described in detail with reference to the attached drawings.

[0055] Referring to Figure 2, the present invention relates to a superjunction semiconductor element 1, and more particularly to a superjunction semiconductor element 1 that enables cell pitch reduction by forming the source contact in a plug structure, thereby limiting the horizontal width size of the source contact to a certain level or less while ensuring sufficient contact area between the source contact and the source region.

[0056] The structure of the superjunction semiconductor device 1 according to one embodiment of the present invention will be described as follows: First, a substrate 101 can be formed. The substrate 101 may be, for example, a silicon substrate, and a drain electrode 110 can be formed on its bottom surface.

[0057] An epitaxial layer 120 can then be formed on the substrate 101. Such an epitaxial layer 120 may be, for example, a low-concentration doping region of a second conductivity type impurity. Furthermore, a number of fillers 130 can be formed within the epitaxial layer 120, spaced apart from each other along the lateral direction. The fillers 130 can be spaced apart along one lateral direction and can extend for a long distance along the other lateral direction. Therefore, the epitaxial layer 120 and the fillers 130 can be arranged alternately at a predetermined depth of the epitaxial layer 120. Such fillers 130 are first conductivity type impurity doping regions and can be extended downward to a predetermined depth from the side adjacent to the upper surface of the epitaxial layer 120 toward the substrate 101.

[0058] Furthermore, the individual filler 130 can be formed such that the surface in contact with the epitaxial layer 120 is bent in opposite directions to the epitaxial layer 120. Alternatively, the outer surface of the individual filler 130 can extend substantially linearly and flatly along the vertical direction.

[0059] A body region 140 can be formed on the upper side of the filler 130. For example, the body region 130 can correspond one-to-one with an individual filler 130 and be connected to the upper part of the corresponding filler 130. Alternatively, the body region 140 may be a first conductivity type impurity doping region. Each body region 140 can be formed through multiple ion implantation and drive-in processes of the first conductivity type impurity, the details of which will be described later.

[0060] Furthermore, a source region 142 can be formed within the body region 140. The source region 142 may be a region doped with a high concentration of second conductivity type impurities. Such a source region 142 is preferably formed of multiple layers, and more preferably of two layers.

[0061] For example, the source region 142 may include a first region 1421 enclosing a second region 1423, and a second region 1423 enclosing the first region 1421. The first region 1421 and the second region 1423 can be formed through ion implantation and drive-in processes of impurities containing different elements. For example, the impurities in the first region 1421 preferably contain or consist of elements with a higher thermal diffusion coefficient than the impurities in the second region 1423. For example, the element of the impurity in the first region 1421 may be P (Phosphorus) and the element of the impurity in the second region 1423 may be As (Arsenic), but the scope of the present invention is not limited thereto.

[0062] Generally, when a source region 142 is formed by ion implanting an impurity of element P, which has a relatively large thermal diffusion coefficient, the only way to ensure a desired channel length CL is to ion implant the impurity at a relatively low concentration. Conversely, if an impurity with a large diffusion coefficient is ion implanted at a relatively high concentration, and then the drive-in process is performed to form the source region 142, the ends of the source region 142 and the adjacent body region 140 become closer together, which inevitably narrows the channel length CL.

[0063] In this case, if the source region 142 is completed by ion implanting an impurity with a large diffusion coefficient, such as electrons, at a relatively low concentration, the overall concentration of the source region 142 will decrease, and the resistance of the source region 142 may increase. To prevent this problem, in one embodiment of the present invention, in order to compensate for the relatively low concentration of the source region 142, the first region 1421 is formed, and then the second region 1423 is further formed to complete the source region 142.

[0064] In other words, the channel length CL can be set first by forming the first region 1421, and then the source region 142 can be adjusted to the desired doping concentration by forming the second region 1423. At this time, since the impurities ion-implanted to form the second region 1423 have a lower diffusion coefficient than the impurities ion-implanted when forming the first region 1421, the doping concentration of the source region 142 can be increased without affecting the set channel length CL.

[0065] In the example above, it was explained that the first region 1421 is formed before the second region 1423, but in some cases, the second region 1423 may be formed first, and the scope of the present invention is not limited by specific examples. By forming the source region 142 in this way, the threshold voltage characteristics of the element 1 can be improved.

[0066] Furthermore, an ohmic contact region 144 can be formed within the body region 140 on the side adjacent to the source region 142, or on the side in contact with the source region 142. The ohmic contact region 144 may be a region doped with a high concentration of the first conductivity type impurity. As an example, the ohmic contact region 144 can be formed on the side in contact with the bottom surface of the source contact.

[0067] A gate insulating film 151 can be formed on the epitaxial layer 120, and a gate electrode 153 can be formed on the gate insulating film 151. The gate insulating film 151 can include, for example, a silicon oxide film, a high dielectric film, or a combination thereof, and the scope of the present invention is not limited by specific examples. Furthermore, the gate insulating film 151 can extend without interruption on the epitaxial layer 120, except on the side where the source contact 160 described later is formed. As an example, the gate insulating film 151 can be extended so as to be in contact with the side wall of the adjacent source contact 160 below the gate electrode 153. Such a gate insulating film 151 can also function as a buffer oxide film when forming the body region 140, and details of this will be described later.

[0068] The gate electrode 153 can be formed on the gate insulating film 151 on the side surface of the source region 142 or the body region 140. Such a gate electrode 153 can include, for example, a polysilicon film, a metal, a conductive metal nitride, or a combination thereof, and the scope of the present invention is not limited by the above examples. A sidewall 155 can also be formed on the side wall of the gate electrode 153. This sidewall 155 is completed before the formation of the source region 142 and can be used as a mask pattern when the source region 142 is formed. Thus, the sidewall 155 can extend the distance between the end of the source region 142 and the end of the adjacent body region 140 to ensure a sufficient channel length CL. The sidewall 155 can also include, for example, a nitride film, but the scope of the present invention is not limited by the above examples.

[0069] Furthermore, an interlayer insulating film 160 can be formed on the epitaxial layer 120 and / or gate insulating film 151 to cover the gate electrode 153. Such an interlayer insulating film 160 may include, for example, a silicon oxide film, but the scope of the present invention is not limited by the above examples.

[0070] Furthermore, a source contact 170 can be formed within the interlayer insulating film 160 on the source region 142. The source contact 170 may be a region that contacts the source electrode 180 on the interlayer insulating film 160 and the source region 142 within the body region 140. With the above structure, the source contact 170 can be formed in a shape that penetrates the interlayer insulating film 160. Also, the lower part of the source contact 170 can be formed in a shape that penetrates the gate insulating film 151. With such a shape, the bottom of the source contact 170 may be located within the body region 140 or within the source region 142. In some cases, the bottom of the source contact 170 may be located on the interface side between the body region 140 and the source region 142.

[0071] Referring to Figure 1, generally, when a source contact 980 is formed in a planar structure so that it is located on the source region 942, the horizontal width of the source contact 980 must be made sufficiently large in order to increase the contact area between the bottom surface of the source contact 980 and the source region 942. When the horizontal width of the source contact 980 is widened in this way, the cell pitch CP of the element 9 must also widen accordingly. When the cell pitch CP becomes larger, the size of the element 9 must also increase.

[0072] Referring to Figure 2, in order to solve these problems, a source contact 170 according to one embodiment of the present invention is characterized in that its lower part is in direct contact with the source region 142. Therefore, the bottom portion 170a of the source contact 170 can be in contact with the source region 142, and the side wall 170b of the source contact 170 can also be in contact with the source region 142. In other words, even if the horizontal width A of the source contact 170 is narrowed, the contact area with the source region 142 can be set to be sufficiently wide. Therefore, it is possible to prevent the cell pitch CP of the element 1 from becoming large. Furthermore, the source contact 170 may include, for example, W (Tungsten), but the scope of the present invention is not limited by the above examples.

[0073] A source metal 180 is formed on the interlayer insulating film 160, and the source metal 180 can be electrically and / or physically connected to the source contact 170.

[0074] Figures 3 to 16 are cross-sectional views illustrating a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention.

[0075] The following describes in detail a method for manufacturing a superjunction semiconductor device according to one embodiment of the present invention, with reference to the attached drawings.

[0076] First, a number of spaced-apart fillers 130 are formed within the epitaxial layer 120. For example, implant regions of the first conductivity type are formed in predetermined areas of individual epitaxial layers of the second conductivity type. The number of epitaxial layers of the second conductivity type can form the epitaxial layer 120 in a stacked structure. Subsequently, fillers can be formed by the diffusion of the implant regions of the first conductivity type through a drive-in process.

[0077] Subsequently, a pre-body region 140a can be formed on the individual filler 130 within the epitaxial layer 120. The process of forming the pre-body region 140a will be described in detail below. Referring to Figure 3, first, a buffer oxide film B can be formed on the epitaxial layer 120. The buffer oxide film B is a structure that protects the surface of the epitaxial layer 120 and can be removed after the formation of the pre-body region 140a. In some cases, the buffer oxide film B may not be used in the pre-body region 140a formation process. Subsequently, a mask pattern M can be formed on the epitaxial layer 120 or the buffer oxide film B.

[0078] Referring to Figure 4, a first conductivity type impurity D1 can then be ion-implanted onto the individual fillers 130 within the epitaxial layer 120. Referring to Figure 5, a drive-in process can then be performed to form the prebody region 140a. The first conductivity type impurity implanted for the formation of the prebody region 140a can be ion-implanted at a deeper position from the top surface of the epitaxial layer 120 (E1>E2; see Figures 4 and 7) than the first conductivity type impurity implanted for the completion of the body region 140, and it is preferable that they be implanted at different concentrations, but the scope of the present invention is not limited thereto.

[0079] Referring to Figure 6, a gate insulating film 151 can then be formed on the epitaxial layer 120. Then, a gate film, for example a polysilicon film, is formed on the gate insulating film 151, and the gate electrode 153 can be completed by performing an etching process.

[0080] Subsequently, the body region 140 can be completed. Referring to Figure 7, for this purpose, first, the first conductivity type impurity D2 can be ion-implanted into the prebody region 140. At this time, the gate insulating film 151 can function as a buffer oxide film. During this ion implantation process, by not forming a separate mask pattern on the gate insulating film 151 and instead using the gate electrode 153 as a mask pattern, a decrease in overall process efficiency can be prevented. Referring to Figure 8, subsequently, by performing a drive-in process, the first conductivity type impurity diffuses and the body region 140 can be completed. It is preferable that the ion implantation energy of the first conductivity type impurity D2 in this process is lower than the ion implantation energy of the first conductivity type impurity D1 for forming the prebody region 140a.

[0081] Figure 17 is a graph illustrating the doping concentration level of a superjunction semiconductor device according to one embodiment of the present invention. In the graph, the x-axis represents the depth from the top to the bottom of the epitaxial layer (in the direction of the arrow in Figure 2), and the y-axis represents the impurity doping concentration level.

[0082] Referring to the graph in Figure 17, generally, in order to form the body region 940, if the ion implantation and drive-in process of a single first conductivity type impurity is not performed for a sufficient amount of time, the first conductivity type impurity may not diffuse to the lower part 941 of the body region 940 to the desired level. In this case, the concentration of the first conductivity type impurity in the lower part 941 of the body region 940 may not reach the desired level. This can degrade the UIS (Unclamped Inductive Switching) characteristics of the element 9.

[0083] To solve these problems, one embodiment of the present invention is characterized by forming a prebody region 140a, then ion-implanting a first conductivity type impurity again, and performing a drive-in process therefor. This makes it possible to increase the doping concentration of the first conductivity type impurity in the lower part 141 (see Figure 2) of the completed body region 140.

[0084] Referring to Figures 9 and 10, after depositing the insulating film I on the gate insulating film 151 so as to cover the gate electrode 153, etching can be performed to form a sidewall 155 on the side wall of the gate electrode 153.

[0085] Subsequently, the gate electrode 153 and sidewall 155 can be used as a mask pattern to form the source region 142. The process for forming the source region 142 will be described below. Referring to Figure 11, first, in order to form the first region 1421, a second conductivity type impurity D3 can be injected to a predetermined depth within the body region 140. Then, in order to form the second region 1423, another second conductivity type impurity D4 can be injected within the body region 140 at a shallower position than the second conductivity type impurity D3.

[0086] Referring to Figure 12, a drive-in process can then be performed to form a first region 1421 and a second region 1423 enclosed by the first region 1421. As mentioned above, the impurities for forming the first region 1421 may include or consist of elements with a higher thermal diffusion coefficient than the impurities for forming the second region 1423. For example, the impurity element of the first region 1421 may be P (Phosphorus) and the impurity element of the second region 1423 may be As (Arsenic), but the scope of the present invention is not limited thereto.

[0087] Referring to Figure 13, an interlayer insulating film 160 can then be formed on the gate insulating film 151. Such an interlayer insulating film 160 can be deposited on the gate insulating film 151 so as to cover the gate electrode 153.

[0088] Referring to Figure 14, a trench T can then be formed within the interlayer insulating film 160. The trench T can be formed by performing an etching process after forming a mask pattern (not shown) on the interlayer insulating film 160. Such a trench T can expose one side of the body region 140 or the source region 142.

[0089] Referring to Figure 15, an ohmic contact region 144 can then be further formed within the body region 140. For example, an ohmic contact region 144 can be formed within the body region 140 by performing an ion implantation process into the trench T.

[0090] Referring to Figure 16, a source contact 170 can then be formed in the trench T of the interlayer insulating film 160. The source contact 170 can be completed by gap-filling the conductive film (not shown) in the trench T and then removing the conductive film deposited on the interlayer insulating film 160.

[0091] Subsequently, the source metal 180 can be formed on the interlayer insulating film 160.

[0092] The above detailed description is illustrative of the present invention. Furthermore, the foregoing describes preferred embodiments of the present invention, and the present invention can be used in a variety of other combinations, modifications, and environments. That is, modifications and alterations are possible within the scope of the concept of the invention disclosed herein, within the scope equivalent to the disclosed content, and / or within the scope of the art or knowledge. The embodiments described herein describe the best possible state for realizing the technical idea of ​​the present invention, and a variety of modifications are possible as required in the specific field of application and use of the present invention. Therefore, the above detailed description of the invention is not intended to limit the present invention to the disclosed embodiments. [Explanation of symbols]

[0093] 1. Superjunction semiconductor device 101 circuit board 110 Drain electrode 120 Epitaxial Layer 130 Filler 140 Body area 140a Prebody region 141 Lower part of the body area 142 Source Area 1421 First area 1423 Second area 144 Ohmic Contact Region 151 Gate Insulator 153 Guard gate 155 Sidewall 160 Interlayer insulating film 170 Source Contacts 170a Bottom of source contact 170b Sidewall of source contact 180 Source Metal A. Horizontal width of source contact B buffer oxide film CL channel length CP cell pitch D1, D2 First Conductivity Type Impurities D3, D4 Second Conductivity Type Impurities E1, E2 Doping depth of first conductivity type impurities I insulating film M Mask Pattern T Trench

Claims

1. circuit board and The epitaxial layer on the substrate, The filler in the epitaxial layer, The body region on the filler within the epitaxial layer, The source region within the body region, The gate electrode on the epitaxial layer, An interlayer insulating film covering the gate electrode on the epitaxial layer, The source metal on the interlayer insulating film, A superjunction semiconductor element characterized by including a source contact connected to the source metal, the bottom surface of which is located within the body region.

2. The superjunction semiconductor element according to claim 1, characterized in that the bottom surface of the source contact is located within the source region.

3. The superjunction semiconductor element according to claim 2, characterized in that at least one side of the side wall of the source contact is in contact with the source region.

4. The superjunction semiconductor element according to claim 1, characterized in that the source region includes a first region and a second region enclosed by the first region.

5. The superjunction semiconductor device according to claim 4, characterized in that the first region contains impurities of an element different from that of the second region.

6. The superjunction semiconductor device according to claim 5, characterized in that the first region contains impurities of an element with a higher thermal diffusion coefficient than the second region.

7. The body region further includes an ohmic contact region, The superjunction semiconductor element according to claim 1, characterized in that the ohmic contact region is in contact with the bottom surface of the source contact.

8. The superjunction semiconductor element according to claim 1, further comprising a sidewall which is the side wall of the gate electrode.

9. The superjunction semiconductor element according to claim 1, characterized in that the body region is completed through two or more ion implantation and drive-in processes.

10. circuit board and The second conductivity type epitaxial layer on the substrate, The first conductive type filler in the epitaxial layer, A first conductive body region on the filler within the epitaxial layer, The source region of the second conductivity type within the body region, The gate electrode on the epitaxial layer, An interlayer insulating film covering the gate electrode on the epitaxial layer, The source metal on the interlayer insulating film, The source metal and source contact connected to the source region are included, A superjunction semiconductor device characterized in that the source region includes a first region and a second region which are impurity doping regions of different elements.

11. The superjunction semiconductor element according to claim 10, characterized in that the first region has a larger horizontal width size than the second region.

12. The first region is a region doped with P-element impurities, The superjunction semiconductor device according to claim 10, characterized in that the second region is an As element impurity doping region.

13. The aforementioned source contact is The superjunction semiconductor element according to claim 10, characterized in that its bottom surface is located within the source region and its side walls are in contact with the first region and the second region.

14. The superjunction semiconductor element according to claim 10, further comprising an ohmic contact region of a first conductivity type below the source contact within the body region.

15. Further including a side wall on the side wall of the gate electrode, The superjunction semiconductor element according to claim 10, characterized in that the sidewall is formed on the sidewall of the gate electrode before the formation of the source region.

16. The steps include forming an epitaxial layer on a substrate and forming a filler within the epitaxial layer, The steps include forming a body region on the filler within the epitaxial layer, The steps include forming a gate electrode on the epitaxial layer, The steps include forming a source region and an ohmic contact region within the body region, The steps include forming an interlayer insulating film on the epitaxial layer so as to cover the gate electrode, The steps include forming a source contact within the interlayer insulating film such that its bottom surface is located within the body region or the source region, A method for manufacturing a superjunction semiconductor element, comprising the step of forming a source metal on the interlayer insulating film so as to be connected to the source contact.

17. The body region forming step is, The steps include forming a prebody region on the filler within the epitaxial layer, A method for manufacturing a superjunction semiconductor device according to claim 16, characterized by comprising the steps of forming the gate electrode, using the gate electrode as a mask pattern to ion implant a first conductivity type impurity into the prebody region, and performing a drive-in process to form a body region.

18. The source region formation step is, The steps include forming a first region which is a second conductivity type impurity doping region within the body region, The process includes the step of forming a second region which is a second conductivity type impurity doping region within the first region, The second conductivity type impurity for forming the second region is A method for manufacturing a superjunction semiconductor device according to claim 16, characterized in that it has a smaller thermal diffusion coefficient compared to the second conductivity type impurity for forming the first region.

19. The method for manufacturing a superjunction semiconductor element according to claim 16, further comprising the step of forming a sidewall on the sidewall of the gate electrode before forming the source region and the ohmic contact region.

20. The source contact formation step is, The steps include forming a trench in the interlayer insulating film and the source region, The step includes completing the source contact by gap-filling the trench with conductive material, The method for manufacturing a superjunction semiconductor element according to claim 16, characterized in that the side wall of the source contact is in contact with the source region.

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