Electro-optical devices and electronic equipment

Abstract

To provide electro-optical devices and electronic devices with superior display quality. [Solution] The electro-optical apparatus comprises a substrate, a plurality of pixel electrodes, a laminate of a plurality of insulating layers disposed between the substrate and the plurality of pixel electrodes, a first transistor disposed in the laminate, comprising a first semiconductor layer including a first source region and a first drain region, and a first gate electrode located above the first semiconductor layer, a second transistor disposed in the laminate, comprising a second semiconductor layer including a second source region and a second drain region, and a second gate electrode located above the first semiconductor layer, a first element and a second element disposed in the laminate, disposed in the same layer of the laminate and having different potentials from each other, and a shield portion disposed between the first element and the second element in a plan view in the thickness direction of the substrate, and having a different potential from each of the first element and the second element.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In an electronic device such as a projector, an electro-optical device such as a liquid crystal display device whose optical characteristics can be changed for each pixel is used.

[0003] The electro-optical device described in Patent Document 1 has a pixel region and a peripheral region located outside thereof. In the pixel region, a pixel electrode and a transistor having a semiconductor layer are provided for each pixel. The transistor is electrically connected to a scanning line and a data line via various wirings and contacts. In addition, in the peripheral region, a scanning line drive circuit electrically connected to the scanning line and a data line drive circuit electrically connected to the data line are provided.

Prior Art Documents

Patent Documents

[0004] [[ID=并27]]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In an electro-optical device, a transistor is provided for each pixel. In addition, each circuit provided in the peripheral region is provided with a plurality of transistors and various wirings connected thereto.

[0006] For example, as panel resolution increases, the density of transistors and other components also increases, which shortens the distance between two wires with different potentials located on the same layer. This can lead to noise generation due to capacitive coupling between these two wires. Similarly, if the distance between the semiconductor layers of two transistors located on the same layer decreases, noise can be generated due to capacitive coupling between these two semiconductor layers. However, conventional technology has the problem of not addressing this noise. [Means for solving the problem]

[0007] One aspect of the electro-optical apparatus of the present invention comprises a substrate, a plurality of pixel electrodes, a laminate of a plurality of insulating layers disposed between the substrate and the plurality of pixel electrodes, a first transistor disposed in the laminate, comprising a first semiconductor layer including a first source region and a first drain region, and a first gate electrode located in a layer above the first semiconductor layer, a second transistor disposed in the laminate, comprising a second semiconductor layer including a second source region and a second drain region, and a second gate electrode located in a layer above the first semiconductor layer, a first element and a second element disposed in the same layer of the laminate and having different potentials from each other, and a shield portion disposed between the first element and the second element in a plan view in the thickness direction of the substrate, and having a different potential from each of the first element and the second element.

[0008] One embodiment of the electronic device of the present invention comprises an electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of an electro-optical device according to the first embodiment. [Figure 2] This is a cross-sectional view of the AA line of the electro-optical apparatus shown in 1. [Figure 3] This figure schematically shows the peripheral circuits of the electro-optical device shown in Figure 1. [Figure 4]This is a cross-sectional view showing some of the transistors in the peripheral circuit shown in Figure 3. [Figure 5] This is a plan view showing the arrangement of the light-shielding portions for the first and second transistors in Figure 4. [Figure 6] Figure 1 is an equivalent circuit diagram showing the electrical configuration of each pixel in the element substrate. [Figure 7] This is a plan view showing a portion of the pixel region in Figure 1. [Figure 8] This diagram corresponds to the cross-section along line B1-B1 in Figure 7. [Figure 9] This diagram corresponds to the cross-section along line B2-B2 in Figure 7. [Figure 10] This is a perspective view showing a personal computer, an example of an electronic device. [Figure 11] This is a plan view showing a smartphone, which is an example of an electronic device. [Figure 12] This is a schematic diagram showing a projector, which is an example of an electronic device. [Modes for carrying out the invention]

[0010] Preferred embodiments of the present invention will be described below with reference to the attached drawings. Note that the dimensions and scale of parts in the drawings may differ from actual dimensions as appropriate, and some parts are shown schematically for ease of understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise stated in the following description.

[0011] A. Electro-optical devices A1.Basic configuration Figure 1 is a plan view of the electro-optical apparatus 100 according to an embodiment. Figure 2 is a cross-sectional view of the electro-optical apparatus 100 shown in Figure 1, along line AA. For convenience of explanation, the following will use mutually orthogonal X, Y, and Z axes as appropriate. One direction along the X axis will be denoted as the X1 direction, and the direction opposite to the X1 direction will be denoted as the X2 direction. Similarly, one direction along the Y axis will be denoted as the Y1 direction, and the direction opposite to the Y1 direction will be denoted as the Y2 direction. One direction along the Z axis will be denoted as the Z1 direction, and the direction opposite to the Z1 direction will be denoted as the Z2 direction. The Z axis is typically a vertical axis. The Z1 direction is upward, and the Z2 direction is downward. However, the Z axis does not necessarily have to be a vertical axis.

[0012] The electro-optical device 100 shown in Figures 1 and 2 is a transmissive electro-optical device with an active matrix drive system. The electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in Figure 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Although the shape of the electro-optical device 100 in plan view shown in Figure 1 is a rectangle, it may also be a polygon other than a rectangle or a circle.

[0013] The element substrate 2 shown in Figure 2 comprises a light-transmitting element substrate 21, a light-transmitting laminate 22, a plurality of light-transmitting pixel electrodes 25, and a light-transmitting first alignment film 29. The element substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are stacked in this order in the Z1 direction. Therefore, the laminate 22 is placed between the element substrate 21, which acts as the "substrate," and the plurality of pixel electrodes 25. "Light-transmitting" refers to the ability to transmit visible light, preferably with a visible light transmittance of 50% or more.

[0014] The element substrate 21 corresponds to the "substrate". Looking at it from the Z1 direction or the Z2 direction which is the thickness direction of the element substrate 21 is defined as "planar view". The element substrate 21 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of insulating films having translucency. Also, various wirings and the like are provided on the laminate 22. The pixel electrode 25 is used to apply an electric field to the liquid crystal layer 5. The pixel electrode 25 includes, for example, a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown in the figure, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in planer view. Also, the first alignment film 29 has translucency and insulation. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. The first alignment film 29 is arranged to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0015] The counter substrate 3 is arranged to face the element substrate 2. The counter substrate 3 has a second substrate 31 having translucency, an inorganic insulating layer 32 having translucency, a common electrode 33 having translucency, and a second alignment film 34 having translucency. Although not shown in the figure, the counter substrate 3 has a light-shielding cut-off that surrounds the plurality of pixel electrodes 25 in planer view. Note that the "light-shielding property" means light-shielding property against visible light, preferably the transmittance of visible light is less than 50%, and more preferably 10% or less.

[0016] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are laminated in the Z2 direction in this order. The second substrate 31 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 has translucency and insulation, and is formed of an inorganic material containing silicon such as silicon oxide. The common electrode 33 is a counter electrode disposed with respect to the plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 has translucency and conductivity. The common electrode 33 contains, for example, a transparent conductive material such as ITO, IZO, and FTO. The second alignment film 34 has translucency and insulation. The second alignment film 34 aligns the liquid crystal molecules included in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide.

[0017] The seal member 4 is disposed between the element substrate 2 and the counter substrate 3. The seal member 4 is formed using an adhesive or the like containing various curable resins such as an epoxy resin. The seal member 4 may include a gap material composed of an inorganic material such as glass.

[0018] The liquid crystal layer 5 is disposed within a region surrounded by the element substrate 2, the counter substrate 3, and the seal member 4. The liquid crystal layer 5 is an electro-optical layer whose optical characteristics change according to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The alignment of the liquid crystal molecules changes according to the voltage applied to the liquid crystal layer �.

[0019] Such an electro-optical device 100 has a pixel region A10 and a peripheral region A20 located outside the pixel region A10 in plan view. The pixel region A10 is a region for displaying an image, and a plurality of pixels P arranged in a matrix are provided. A plurality of pixel electrodes 2 * are arranged one-to-one with respect to the plurality of pixels P. The above-described common electrode 33 is provided in common for the plurality of pixels P * Also, the peripheral region A20 surrounds the pixel region A10 in plan view.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Figure 2, an image is displayed by modulating the light LL between the time it is incident on the opposing substrate 3 and the time it is emitted from the element substrate 2. Alternatively, an image may be displayed by modulating the light incident on the element substrate 2 while it is emitted from the opposing substrate 3.

[0021] Furthermore, the electro-optical device 100 is applied to, for example, a color display device such as a personal computer and a smartphone, which will be described later. When applied to such a display device, a color filter is appropriately used for the electro-optical device 100. Also, the electro-optical device 100 is applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light bulb. In this case, a color filter is omitted for the electro-optical device 100.

[0022] A2. Peripheral circuits Figure 3 is a schematic diagram showing the peripheral circuit 10 in the electro-optical device 100 shown in Figure 1. As shown in Figure 3, the peripheral region A20 of the electro-optical device 100 is provided with the peripheral circuit 10 and a plurality of external terminals 13. The plurality of external terminals 13 are connected to wiring (not shown) that is routed from the peripheral circuit 10.

[0023] Furthermore, the pixel region A10 has n scan lines 241 and m data lines 242, where n and m are integers greater than or equal to 2. The n scan lines 241 extend along the X-axis and are spaced equally along the Y-axis. The m data lines 242 extend along the Y-axis and are spaced equally along the X-axis. The n scan lines 241 and m data lines 242 are electrically insulated from each other and are arranged in a grid pattern in a planar view. The region enclosed by two adjacent scan lines 241 and two adjacent data lines 242 corresponds to pixel P.

[0024] Furthermore, the peripheral circuit 10 includes two scan line drive circuits 11, a data line drive circuit 12, a test circuit 14, and a sampling circuit 16.

[0025] In the illustrated example, the two scan line drive circuits 11 are arranged on either side of the pixel area A10. Each scan line drive circuit 11 includes multiple transistors. For example, the scan line drive circuit 11 located on the left side of the pixel area A10 drives the odd-numbered scan lines 241, and the scan line drive circuit 11 located on the right side of the pixel area A10 drives the even-numbered scan lines 241. Alternatively, the same scan line 241 may be driven by scan line drive circuits 11 located on both the left and right sides.

[0026] The inspection circuit 14 is located, for example, on the opposite side of the multiple external terminals 13 of the pixel area A10. Data lines 242 are connected to the inspection circuit 14. The inspection circuit 14 is used to inspect the electro-optical device 100 for operational defects, etc., by detecting the image signal during the manufacturing or shipment of the electro-optical device 100. The inspection circuit 14 has, for example, a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to an inspection line (not shown). In addition, the gate of each transistor is electrically connected to a control signal line (not shown).

[0027] The data line drive circuit 12 and the sampling circuit 16 are arranged, for example, on the opposite side of the pixel region A10 from the inspection circuit 14. The data line drive circuit 12 is electrically connected to m data lines 242 via the sampling circuit 16. The data line drive circuit 12 includes, for example, an inverter circuit and a transmission gate, and has multiple transistors. Based on the sampling signal output from the data line drive circuit 12, the sampling circuit 16 samples the image signal and supplies it to the data lines 242.

[0028] The sampling circuit 16 has a transistor provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to a constant potential line (not shown). In addition, the gate of each transistor is electrically connected to a signal line (not shown) to which the sampling signal is supplied.

[0029] A3. Peripheral Circuit 10 Figure 4 is a cross-sectional view showing some of the transistors 15 in the peripheral circuit 10 shown in Figure 3. Figure 5 is a plan view showing the arrangement of the light-shielding portion 50 relative to the first transistor 15a and the second transistor 15b in Figure 4.

[0030] The aforementioned peripheral circuit 10 is provided with multiple transistors 15. These multiple transistors 15 may be located in any of the peripheral circuits 10, including the scan line drive circuit 11, the data line drive circuit 12, the test circuit 14, and the sampling circuit 16.

[0031] For example, multiple transistors 15 are arranged in a line along the X or Y axis. For example, the multiple transistors 15 include a first transistor 15a and a second transistor 15b, which are any two adjacent transistors 15. Figures 4 and 5 illustrate the first transistor 15a and the second transistor 15b.

[0032] As shown in Figure 4, the element substrate 2 has a laminate 22. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, and 226. The insulating layers 221, 222, 223, 224, 225, and 226 are laminated in this order from the element substrate 21. The laminate 22 is transparent and insulating. The material of the laminate 22 is an inorganic material containing silicon, such as silicon oxide and silicon oxynitride.

[0033] Furthermore, the laminate 22 has multiple elements arranged within it. Each element is a component arranged in the laminate 22 and composed of a conductor or semiconductor. The "first element" and the "second element" are any two conductors or semiconductors with different potentials from each other among the multiple elements. Examples of conductors include wiring, electrodes, and contacts. Examples of semiconductors include the semiconductor layer of a transistor. In particular, the "first element" and the "second element" are arranged adjacent to each other in the same layer in the XY plane.

[0034] Multiple light-shielding portions 50 are provided on the element substrate 21. The multiple light-shielding portions 50 are spaced apart from each other. Each light-shielding portion 50 is a light-shielding film. The light-shielding portions 50 are provided to suppress the incidence of light onto the semiconductor layer 151 of the corresponding transistor 15. The element substrate 21 may also have a recess that opens in the Z1 direction. In this case, the light-shielding portions 50 may be arranged in the recess.

[0035] Multiple light-shielding portions 50 are provided with an insulating layer 221. Multiple transistors 15 are provided on the insulating layer 221. Each transistor 15 has a semiconductor layer 151, a gate electrode 152, and a gate insulating film (not shown). The gate insulating film is positioned between the semiconductor layer 151 and the gate electrode 152. The semiconductor layer 151 is positioned on the insulating layer 221, and the gate electrode 152 is positioned on the insulating layer 222. The semiconductor layer 151 has a drain region 1513, a source region 1512, and a channel region 1511. The channel region 1511 is located between the drain region 1513 and the source region 1512.

[0036] Therefore, the first transistor 15a has a first semiconductor layer 151a, a first gate electrode 152a, and a gate insulating film (not shown). The first semiconductor layer 151a has a first drain region 1513a, a first source region 1512a, and a first channel region 1511a. Similarly, the second transistor 15b has a second semiconductor layer 151b, a second gate electrode 152b, and a gate insulating film (not shown). The second semiconductor layer 151b has a second drain region 1513b, a second source region 1512b, and a second channel region 1511b. Furthermore, the first semiconductor layer 151a and the second semiconductor layer 151b are located on and provided in the insulating layer 221.

[0037] The semiconductor layer 151 is formed from, for example, polysilicon. The drain region 1513 and the source region 1512 are doped with impurities. The gate electrode 152 is formed, for example, by doping polysilicon with impurities that enhance conductivity. The gate electrode 152 may also be formed from conductive materials such as metals, metal oxides, and metal compounds. The gate insulating film is composed of a silicon oxide film formed by, for example, thermal oxidation or CVD (chemical vapor deposition).

[0038] Furthermore, each transistor 15 may have an LDD (Lightly Doped Drain) structure.

[0039] Drain wiring 53 and source wiring 52 are provided on multiple transistors 15. The drain wiring 53 is connected to the drain region 1513 via contact 592. Therefore, the first drain region 1513a is electrically connected to the corresponding drain wiring 53. The second drain region 1513b is electrically connected to the corresponding drain wiring 53. The source wiring 52 is connected to the source region 1512 via contact 591. Therefore, the first source region 1512a is electrically connected to the corresponding source wiring 52. The second source region 1512b is electrically connected to the corresponding source wiring 52. The drain wiring 53 and source wiring 52 are provided on the insulating layer 224, but they may also be located on the insulating layer 224.

[0040] Furthermore, a first conductive portion 51 is arranged in the same layer as the drain wiring 53 and source wiring 52. The first conductive portion 51 is made of a conductive material. A shield portion 81 is connected to the first conductive portion 51, which is located in a through hole provided in the insulating layers 221 to 224. The first conductive portion 51 is connected via the shield portion 81 to a light-shielding portion 50 located directly below the first conductive portion 51.

[0041] A second conductive portion 54 is positioned on the insulating layer 225. The second conductive portion 54 is made of a conductive material. For example, a power supply potential or a reference potential is supplied to the second conductive portion 54. A shield portion 82 is connected to the second conductive portion 54, which is positioned in through holes provided in the insulating layers 224 and 225.

[0042] Each of the aforementioned source wiring 52, drain wiring 53, light shielding portion 50, first conductive portion 51, second conductive portion 54, and contacts 591 and 594 contains metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), as well as metal nitrides and metal silicides.

[0043] As shown in Figure 5, one light-shielding portion 50 overlaps two adjacent semiconductor layers 151 in a plan view. For example, one light-shielding portion 50 overlaps a part of the first semiconductor layer 151a and a part of the second semiconductor layer 151b in a plan view. Specifically, one light-shielding portion 50 overlaps the first source region 1512a and the second drain region 1513b in a plan view. Therefore, in a plan view, the light-shielding portion 50 overlaps the drain region 1513 and the source region 1512. On the other hand, one light-shielding portion 50 does not overlap the gate electrode 152 in a plan view. Therefore, one light-shielding portion 50 does not overlap the first gate electrode 152a and the second gate electrode 152b in a plan view.

[0044] Furthermore, the shield portion 81 overlaps the light-shielding portion 50 in a plan view. Also, in the illustrated example, the shield portion 82 overlaps the gate electrode 152 in a plan view, but does not overlap the light-shielding portion 50. However, the shield portion 82 may be provided at a different location from the gate electrode 152 in a plan view.

[0045] As mentioned above, the shield portion 81 is positioned between the first source region 1512a of the first semiconductor layer 151a and the second drain region 1513b of the second semiconductor layer 151b, which have different potentials when viewed in a plan view in the thickness direction of the element substrate 21. The first semiconductor layer 151a and the second semiconductor layer 151b are located in the same layer. The shield portion 81 has a different potential from the first source region 1512a and the second drain region 1513b. The first source region 1512a is the "first element," and the second drain region 1513b is the "second element."

[0046] Here, as the resolution of the panel increases, the first source region 1512a and the second drain region 1513b become closer together, and the degree of capacitive coupling between them increases. As a result, this capacitive coupling affects the first transistor 15a and the second transistor 15b as noise. Consequently, malfunctions may occur in the first transistor 15a and the second transistor 15b, which may degrade the display quality of the electro-optical device 100.

[0047] The shield portion 81 prevents the formation of capacitive coupling between the first source region 1512a and the second drain region 1513b. The provision of this shield portion 81 suppresses malfunctions of the first transistor 15a and the second transistor 15b. Therefore, a decrease in the display quality of the electro-optical device 100 can be suppressed.

[0048] Furthermore, as shown in Figure 4, the shield portion 81 is positioned from the upper layer to the lower layer of the first source region 1512a and the second drain region 1513b. Therefore, the shield portion 81 can effectively block the formation of capacitive coupling between the first source region 1512a and the second drain region 1513b.

[0049] Furthermore, the shield portion 81 is connected to the first conductive portion 51 and the light-shielding portion 50. The first conductive portion 51 is located above the first transistor 15a and the second transistor 15b. Specifically, the first conductive portion 51 is located above the first gate electrode 152a and the second gate electrode 152b and is provided on the same layer as the source wiring 52 and the drain wiring 53. The light-shielding portion 50 is located below the first transistor 15a and the second transistor 15b. Specifically, the light-shielding portion 50 is placed between the element substrate 21 and the insulating layer 221. By providing the shield portion 81 in this position, the shield portion 81 is positioned from the upper layer to the lower layer of the first source region 1512a and the second drain region 1513b, so that the formation of capacitive coupling between the first source region 1512a and the second drain region 1513b can be effectively blocked. Furthermore, for example, if the first conductive portion 51 is at a different potential from the first source region 1512a and the second drain region 1513b, the potential of the shield portion 81 can be made different from the potential of the first source region 1512a and the second drain region 1513b via the first conductive portion 51.

[0050] The shield portion 81 does not necessarily have to be connected to the first conductive portion 51 and the light-shielding portion 50.

[0051] Furthermore, the light-shielding portion 50 overlaps with the first source region 1512a and the second drain region 1513b in a plan view. Therefore, the light-shielding portion 50 suppresses the incidence of light to the first source region 1512a, the second drain region 1513b, and their vicinity. Thus, malfunctions of the first transistor 15a and the second transistor 15b can be suppressed even more effectively.

[0052] On the other hand, the light-shielding portion 50 does not overlap the first gate electrode 152a and the second gate electrode 152b in a plan view. Therefore, the planar area of ​​the light-shielding portion 50 can be reduced compared to the case where the light-shielding portion 50 overlaps the first gate electrode 152a and the second gate electrode 152b in a plan view. As a result, distortion such as warping of the element substrate 21 and the light-shielding portion 50 can be suppressed. Therefore, peeling or damage to the light-shielding portion 50 can be suppressed.

[0053] The light-shielding portion 50 may overlap the first gate electrode 152a and the second gate electrode 152b in a plan view.

[0054] Furthermore, as shown in Figure 5, the shield portion 82 is positioned between the source wiring 52 and the drain wiring 53, which have different potentials, in a plan view in the thickness direction of the element substrate 21. The source wiring 52 and the drain wiring 53 are located on the same layer. The shield portion 82 has a different potential from the source wiring 52 and the drain wiring 53. The source wiring 52 is the "first element," and the drain wiring 53 is the "second element."

[0055] As the resolution of the panel increases, the source wiring 52 and the drain wiring 53 become closer together, increasing the degree of capacitive coupling between them. In this embodiment, a shield 82 is provided between the source wiring 52 and the drain wiring 53. Therefore, the formation of capacitive coupling between the source wiring 52 and the drain wiring 53 is suppressed, and crosstalk, i.e., noise, can be suppressed. Thus, a decrease in the display quality of the electro-optical device 100 can be suppressed.

[0056] Furthermore, the shield portion 82 is positioned from the upper layer to the lower layer of the source wiring 52 and drain wiring 53. Therefore, the shield portion 82 can effectively prevent the formation of capacitive coupling between the source wiring 52 and the drain wiring 53.

[0057] Furthermore, as shown in Figure 4, the shield portion 82 is connected to a second conductive portion 54 located in the upper layer of the source wiring 52 and drain wiring 53, and extends from the second conductive portion 54 to the lower layer of the source wiring 52 and drain wiring 53. With the shield portion 82 provided in this way, the shield portion 82 is positioned from the upper layer to the lower layer of the source wiring 52 and drain wiring 53, so the formation of capacitive coupling between the source wiring 52 and drain wiring 53 can be effectively blocked. Also, for example, if the second conductive portion 54 is at a different potential from the source wiring 52 and drain wiring 53, the potential of the shield portion 82 can be made different from the potential of the source wiring 52 and drain wiring 53 via the second conductive portion 54.

[0058] Furthermore, it is preferable that the shield 81 and shield 82, respectively, are at the power supply potential or the reference potential. The reference potential is the potential that serves as the reference for the potential supplied to each pixel P. By having the shield 81 and shield 82 at the power supply potential or the reference potential, the formation of the capacitive coupling described above can be stably blocked.

[0059] Note that the potentials of shield 81 and shield 82 may be other than the power supply potential or the reference potential. For example, shield 81 and shield 82 may each be in a floating state where no potential is supplied.

[0060] Furthermore, each of the shield portions 81 and 82 contains, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), metal nitrides, and metal silicides. These may be in single layers or laminates. The shield portions 81 and 82 are preferably formed by, for example, the damascene method. By using the damascene method, plug-shaped shield portions 81 and 82 with a small aspect ratio can be formed. In addition, the shield portions 81 and 82 preferably contain tungsten. By including tungsten, it is easier to accurately form plug-shaped shield portions 81 and 82 that fill through holes.

[0061] Furthermore, the shield section 81, the shield section 82, the first semiconductor layer 151a, the second semiconductor layer 151b, the source wiring 52, and the drain wiring 53 are provided in the peripheral circuit 10 located in the peripheral region A20. Multiple transistors 15 provided in the peripheral circuit 10 are more likely to be provided adjacent to each other than multiple transistors provided in multiple pixels P. For this reason, providing a "shield section" between the "first element" and the "second element" on which the peripheral circuit 10 is provided is particularly beneficial.

[0062] A4. Electrical configuration of each pixel P in pixel region A10 Figure 6 is an equivalent circuit diagram showing the electrical configuration of each pixel P in the element substrate 2 of Figure 1. As shown in Figure 6, each pixel P in the pixel region A10 of the element substrate 2 is provided with a transistor 23, a pixel electrode 25, and a capacitive element 24. Each transistor 23 includes a gate, source, and drain. The pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23. In addition, as described above, n scan lines 241 and m data lines 242, as well as n constant potential lines 243, are arranged in the pixel region A10.

[0063] Each of the n scan lines 241 is electrically connected to the gate of a corresponding set of transistors 23. Scan signals G1, G2, ..., and Gn are supplied to the 1 to n scan lines 241 sequentially from the scan line drive circuit 11.

[0064] Each of the m data lines 242 is electrically connected to the source of a corresponding set of transistors 23. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m data lines 242 from the aforementioned data line driving circuit 12 via the sampling circuit 16.

[0065] n constant potential lines 243 extend in the X1 direction and are arranged at equal intervals in the Y2 direction. Furthermore, the n constant potential lines 243 are electrically insulated from the n scan lines 241 and m data lines 242, and are spaced apart from them. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitive element 24. The other electrode of each capacitive element 24 is electrically connected to the corresponding pixel electrode 25. Each capacitive element 24 is a holding capacitor for maintaining the potential of the pixel electrode 25. A constant potential Vcom is applied to one electrode of the capacitive element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0066] As scanning signals G1, G2, ..., and Gn become sequentially active and n scanning lines 241 are selected sequentially, the transistor 23 connected to the selected scanning line 241 turns ON. Then, image signals S1, S2, ..., and Sm, whose magnitudes correspond to the grayscale to be displayed, are taken up via m data lines 242 to the pixel P corresponding to the selected scanning line 241 and applied to the pixel electrode 25. As a result, a voltage corresponding to the grayscale to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in Figure 2, and the orientation of the liquid crystal molecules changes according to the applied voltage. Furthermore, the applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates the light, enabling grayscale display.

[0067] A5. Configuration of each pixel P in pixel area A10 Figure 7 is a plan view showing a portion of the pixel region A10 in Figure 1. Figure 8 is a diagram corresponding to the B1-B1 cross-section in Figure 7. Figure 9 is a diagram corresponding to the B2-B2 cross-section in Figure 4.

[0068] As shown in Figure 7, the pixel region A10 has multiple aperture regions A11 and a light-shielding region A12. The multiple aperture regions A11 are arranged in a matrix in a plan view. The shape of the light-shielding region A12 in a plan view is a frame shape located between the multiple aperture regions A11. Each aperture region A11 is the region where the pixel electrode 25 is placed and is a region through which light is transmitted. On the other hand, the transistor 23 is placed in the light-shielding region A12. Although not shown in Figure 7, the light-shielding region A12 also has multiple wirings such as the scan line 241, data line 242, and constant potential line 243 shown in Figure 6, as well as a capacitive element 24.

[0069] As shown in Figures 8 and 9, the laminate 22 of the element substrate 2 has insulating layers 226, 227, 228, and 229 in addition to the insulating layers 221 to 225 mentioned above.

[0070] A third light-shielding portion 8 is placed on the element substrate 21. The third light-shielding portion 8 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. The element substrate 21 may have a recess that opens in the Z1 direction. In this case, the third light-shielding portion 8 may be placed in the recess.

[0071] The aforementioned light-shielding portion 50 is located in the same layer as the third light-shielding portion 8. The light-shielding portion 50 and the third light-shielding portion 8 are manufactured, for example, in the same process.

[0072] A transistor 23 is placed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is placed on the insulating layer 221. The gate electrode 232 is placed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. The region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0073] The transistor 23 has an LDD structure. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a low-concentration drain region 231d, and a low-concentration source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The low-concentration drain region 231d is located between the channel region 231c and the drain region 231a. The low-concentration source region 231e is located between the channel region 231c and the source region 231b. For example, the transistor 23 does not necessarily have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. Also, the semiconductor layer 231 overlaps the third light-shielding portion 8 in a plan view.

[0074] For example, the aforementioned transistor 15 is manufactured using the same process as transistor 23.

[0075] A first light-shielding section 6 and a second light-shielding section 7 are positioned above and to the sides of the transistor 23. Each of the first light-shielding section 6 and the second light-shielding section 7 is composed of, for example, a multi-layer laminate. Each of the first light-shielding section 6 and the second light-shielding section 7 is formed, for example, using the damascene method. The first light-shielding section 6 is electrically connected to the drain region 231a of the semiconductor layer 231. The second light-shielding section 7 is electrically connected to the gate electrode 232. As shown in Figure 6, the second light-shielding section 7 is directly connected to the third light-shielding section 8, and the second light-shielding section 7 is electrically connected to the third light-shielding section 8. The third light-shielding section 8 functions as a back gate. By providing the first light-shielding section 6, the second light-shielding section 7, and the third light-shielding section 8, the incidence of light into the low-concentration drain region 231d of the semiconductor layer 231 can be suppressed.

[0076] The aforementioned shield portion 81 is provided, for example, across the same insulating layers 221 to 224 as the second light-shielding portion 7. For example, the shield portion 81 and the second light-shielding portion 7 are manufactured in the same process.

[0077] As shown in Figure 8, a relay electrode 244 is placed in the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole that penetrates the insulating layers 222 and 223. The relay electrode 244 and the contact 271 are integrally formed from the same material, but they may be formed from different materials.

[0078] A scan line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scan line 241 is electrically connected to the gate electrode 232 via the second light-shielding portion 7. The relay electrode 245 is electrically connected to the first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224. Note that contacts 272 and 273 are, for example, contact plugs that fill holes penetrating the insulating layer 224.

[0079] Intermediate electrodes 247 and 248 are arranged on the insulating layer 225. Intermediate electrode 247 is electrically connected to intermediate electrode 246 via a contact 275 that penetrates the insulating layer 225. The contact 275 is, for example, integrally formed with intermediate electrode 246 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225. Intermediate electrode 248 is electrically connected to intermediate electrode 245 via a contact 274 that penetrates the insulating layer 225. The contact 274 is integrally formed with intermediate electrode 248 and is a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225.

[0080] A data line 242 is placed on the insulating layer 226. The data line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. The contact 276 is integrally formed with the data line 242 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0081] As shown in Figure 9, a relay electrode 249 is placed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer. The contact 277 is integrally formed with the relay electrode 249 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0082] A capacitive element 24 is placed on the insulating layer 227. The capacitive element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. Electrode 2401 is placed on the insulating layer 227. Electrode 2402 is placed on the insulating layer 228. The dielectric layer 2403 is placed between electrodes 2401 and 2402. Electrode 2401 also serves as the constant potential line 243 in Figure 6. Electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. The contact 278 is integrally formed with electrode 2402 and has a trench structure provided along the inner wall surface of the holes formed in the insulating layers 227 and 228.

[0083] As shown in Figure 9, the pixel electrode 25 is placed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229. The contact 279 is integrally formed with the pixel electrode 25 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 229.

[0084] Each of the aforementioned scanning lines 241, data lines 242, electrodes 2401, 2402, and relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or multi-layer. For example, they may be composed of a laminate of an aluminum film and a titanium nitride film.

[0085] Furthermore, each of the aforementioned contacts 271 to 279 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), as well as metal nitrides and metal silicides. Each of the contacts 271 to 279 may be single-layer or multi-layer. Also, each of the contacts 271 to 279 may be integrally formed with the electrode or wiring to be connected, or may be formed separately. Each of the contacts 271 to 279 may be a trench structure or a contact plug.

[0086] Note that the configuration of the element substrate 2 shown in Figures 8 and 9 is just one example. For example, it may include other capacitive elements besides the capacitive element 24. Also, although the scan line 241, data line 242, and capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.

[0087] A6. Variant The embodiments illustrated above can be modified in various ways. Specific examples of modifications that can be applied to the aforementioned embodiments are given below. Two or more embodiments arbitrarily selected from the following examples can be combined as appropriate, to the extent that they do not contradict each other.

[0088] In the embodiments described above, an active-matrix electro-optical device 100 is exemplified, but the device is not limited thereto, and the driving method of the electro-optical device 100 may be, for example, a passive-matrix method.

[0089] The driving method for the "electro-optical device" is not limited to a longitudinal electric field method, but may also be a transverse electric field method. An example of a transverse electric field method is the IPS (In Plane Switching) mode. Examples of longitudinal electric field methods include the TN (Twisted Nematic) mode, VA (Vertical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode.

[0090] B.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0091] Figure 10 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main unit 2010 in which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0092] Figure 11 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has operation buttons 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to the operation of the operation buttons 3001. The control unit 3002 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0093] Figure 12 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. Electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b, corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and memory, and controls the operation of the electro-optical device 100.

[0094] The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is the light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator, such as a light bulb, that modulates the monochromatic light supplied from the illumination optical system 4001 according to the displayed image. The projection optical system 4003 combines the light emitted from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0095] The above electronic device comprises the aforementioned electro-optical device 100 and control units 2003, 3002, or 4005. The aforementioned electro-optical device 100 has excellent display quality. Therefore, by including the electro-optical device 100, it is possible to provide a personal computer 2000, a smartphone 3000, or a projection display device 4000 with excellent display quality.

[0096] Furthermore, the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices, but include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of Sale) terminals. In addition, electronic devices to which the present invention is applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0097] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added.

[0098] Furthermore, while the above description described a liquid crystal display device as an example of the electro-optical device of the present invention, the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to image sensors and the like. [Explanation of symbols]

[0099] 2...Element substrate, 3...Opposite substrate, 4...Sealing member, 5...Liquid crystal layer, 6...First light-shielding part, 7...Second light-shielding part, 8...Third light-shielding part, 10...Peripheral circuit, 11...Scanning line driving circuit, 12...Data line driving circuit, 13...External terminal, 14...Test circuit, 15...Transistor, 15a...First transistor, 15b...Second transistor, 16...Sampling circuit, 21...Element substrate, 22...Laminate, 25...Pixel electrode, 50...Light-shielding part, 51...First conductive part, 52...Source wiring, 53...Drain wiring, 54...Second conductive part, 81...Shielding part, 82 ...shield section, 100...electro-optical device, 151a...first semiconductor layer, 151b...second semiconductor layer, 152...gate electrode, 152a...first gate electrode, 152b...second gate electrode, 241...scan line, 242...data line, 1511a...first channel region, 1511b...second channel region, 1512a...first source region, 1512b...second source region, 1513a...first drain region, 1513b...second drain region, A10...pixel region, A11...aperture region, A12...light-shielding region, A20...peripheral region, LL...light, P...pixel.

Claims

1. circuit board and Multiple pixel electrodes, A laminate of multiple insulating layers disposed between the substrate and the multiple pixel electrodes, A first transistor is disposed in the laminate, comprising a first semiconductor layer including a first source region and a first drain region, and a first gate electrode located above the first semiconductor layer. A second transistor is disposed in the laminate, comprising a second semiconductor layer including a second source region and a second drain region, and a second gate electrode located above the first semiconductor layer. The laminate comprises a first element and a second element arranged in the same layer, each having a different potential, A shield portion is positioned between the first element and the second element in a plan view in the thickness direction of the substrate, and has a potential different from that of the first element and the second element, An electro-optical device characterized by comprising:

2. The shield portion prevents the formation of a capacitive coupling between the first element and the second element. The electro-optical apparatus according to claim 1.

3. The first semiconductor layer and the second semiconductor layer are located in the same layer, The first element is the first source region, and the second element is the second drain region. The electro-optical apparatus according to claim 1.

4. The system further comprises a source wiring electrically connected to the first source region and a drain wiring electrically connected to the first drain region, The first element is the source wiring, and the second element is the drain wiring. The electro-optical apparatus according to claim 1.

5. The shield portion is columnar in shape, arranged from the upper layer to the lower layer of the first and second elements. The electro-optical apparatus according to any one of claims 1 to 4.

6. It comprises a pixel area for displaying an image and a peripheral area provided outside the pixel area, The first element, the second element, and the shield portion are provided in the peripheral region. The electro-optical apparatus according to any one of claims 1 to 4.

7. A first conductive portion located on the upper layer of the first transistor and the second transistor, The device comprises a light-shielding portion located below the first transistor and the second transistor, The shield portion is connected to the first conductive portion and the light-shielding portion, The electro-optical apparatus according to claim 3.

8. The light-shielding portion overlaps the first source region and the second drain region in the plan view. The electro-optical apparatus according to claim 7.

9. It comprises a second conductive portion located above the source wiring and the drain wiring, The shield portion is connected to the second conductive portion and extends from the second conductive portion to the lower layer of the source wiring and the drain wiring. The electro-optical apparatus according to claim 4.

10. The shielding portion is at the power supply potential or the reference potential. The electro-optical apparatus according to any one of claims 1 to 4.

11. The electro-optical apparatus described in claim 1, An electronic device characterized by having a control unit that controls the operation of the electro-optical device.

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