Semiconductor device and method for manufacturing a semiconductor device

Abstract

To facilitate the extraction of electrodes onto the sealing member. [Solution] The semiconductor device of the embodiment comprises a wiring board, a laminate, a sealing member, and through electrodes. The laminate includes first to third semiconductor chips positioned opposite the wiring board such that a first surface is inclined with respect to the wiring board. Each of the first to third semiconductor chips has an electrode pad at the edge of its first surface. A second semiconductor chip is laminated in a first direction on one layer above the first semiconductor chip so as not to overlap with the electrode pad of the first semiconductor chip, and a third semiconductor chip is laminated in a first direction on one layer above the second semiconductor chip so as not to overlap with the electrode pad of the second semiconductor chip. The sealing member covering the laminate has a third surface on the electrode pad side that is substantially parallel to the plane containing the electrode pads of at least two semiconductor chips. Multiple through electrodes extend from the electrode pads through the sealing member in a second direction perpendicular to the first direction and connect to the wiring board.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] There is a semiconductor package in which a plurality of semiconductor chips are sealed with a sealing member. In the manufacturing process of such a semiconductor package, electrodes for transferring electrical signals to the plurality of semiconductor chips are drawn out on the sealing member.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device in which electrodes can be easily drawn out on a sealing member, and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a wiring substrate, a laminate, a sealing member, and through electrodes. The laminate includes first to third semiconductor chips, each having a first face and a second face opposite the first face, and positioned opposite the wiring substrate such that the first face is inclined with respect to the wiring substrate. Each of the first to third semiconductor chips has an electrode pad at the edge of the first face, and a second semiconductor chip is laminated on one upper layer of the first semiconductor chip in a first direction along the wiring substrate such that the second face of the second semiconductor chip and the electrode pad of the first semiconductor chip do not overlap, and a third semiconductor chip is laminated on one upper layer of the second semiconductor chip in the first direction such that the second face of the third semiconductor chip and the electrode pad of the second semiconductor chip do not overlap. The sealing member covers the laminate. The sealing member has a third surface on the electrode pad side that is substantially parallel to a plane containing the electrode pads of at least two of the plurality of semiconductor chips. Multiple through electrodes extend from the electrode pads through the sealing member in a second direction perpendicular to the first direction and connect to the wiring board. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 5A] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to a modified example 1 of the embodiment. [Figure 5B] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to a modified example 1 of the embodiment. [Figure 6A] A diagram illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to a modified example 2 of the embodiment. [Figure 6B] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 2 of the embodiment. [Figure 7A] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 3 of the embodiment. [Figure 7B] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 3 of the embodiment. [Figure 8] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 4 of the embodiment. [Figure 9A] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 5 of the embodiment. [Figure 9B] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 5 of the embodiment. [Figure 10] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 6 of the embodiment. [Figure 11A] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 6 of the embodiment. [Figure 11B] A diagram sequentially illustrating a part of the procedure of the manufacturing method of the semiconductor device according to Modification Example 6 of the embodiment. [Figure 12] A diagram illustrating a part of the procedure of the manufacturing method of the semiconductor device according to the comparative example. [Embodiments for Carrying Out the Invention]

[0007] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the components in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0008] [Embodiment] Hereinafter, the embodiment will be described in detail with reference to FIGS. 1 to 4.

[0009] The semiconductor device of the embodiment has a flat plate shape in which a sealing member that seals a plurality of stacked semiconductor chips is joined to a wiring board. In this specification, the thickness direction of the flat plate of the semiconductor device is defined as the Z direction.

[0010] Also, although details will be described later, each of the plurality of semiconductor chips is arranged to be inclined at an angle θ with respect to a wiring board extending in a predetermined direction intersecting the Z direction, and is sequentially stacked along the predetermined direction. The predetermined direction in which the plurality of semiconductor chips are stacked is defined as the X direction. That is, the X direction is a direction along the wiring board. Also, a direction intersecting both the Z direction and the X direction is defined as the Y direction. Also, the direction along the Z direction is the vertical direction, the side of the support described later is the lower side, and the side of the wiring board is the upper side. Also, the direction indicated by the arrow of each axis is the positive direction, and the opposite direction of the arrow of each axis is the negative direction. The negative direction of X is an example of the first direction, and the positive and negative directions of Z are examples of the second direction.

[0011] (Configuration example of semiconductor device) FIG. 1 is a diagram showing an example of the configuration of a semiconductor device 1 according to an embodiment. FIG. 1 is a cross-sectional view along the XZ plane of the semiconductor device 1. For the sake of clarity, in FIG. 1, the hatching of some configurations such as a plurality of semiconductor chips 210 and a semiconductor chip 220 is omitted.

[0012] As shown in FIG. 1, the semiconductor device 1 includes a support 100a, a stacked body 200a, a sealing member 300a, a vertical wire 400a, and a wiring board 500.

[0013] A laminate 200a is placed on the upper surface of the support 100a. The laminate 200a has a structure in which semiconductor chips 210-1 to 210-p (where p is an integer of 3 or more) and a semiconductor chip 220 are stacked. The laminate 200a is covered with a sealing member 300a. A vertical wire 400a extending from the laminate 200a is exposed on the surface 310a of the sealing member 300a. A wiring board 500 is placed opposite the laminate 200a. That is, the wiring board 500 and the support 100a are opposite each other with the laminate 200a in between. The wiring board 500 is electrically connected to the vertical wire 400a.

[0014] From this point forward, unless semiconductor chips 210-1 to 210-p are individually distinguished, each of them may be referred to as "semiconductor chip 210".

[0015] The support 100a has a plate-like portion 110 that aligns with the XY plane, and a base portion 120 that protrudes upward from the plate surface 111 of the plate-like portion 110. Multiple semiconductor chips 210 and semiconductor chips 220 that constitute the laminate 200a are each arranged at an angle on the plate surface 111 of the plate-like portion 110. The plate surface 111 supports each of the multiple semiconductor chips 210 and semiconductor chips 220. The plate-like portion 110 and the base portion 120 include, for example, a resin material.

[0016] The base portion 120 has a vertical surface 121 facing the positive direction of X and an inclined surface 122 facing the negative direction of X. The vertical surface 121 extends approximately vertically upward from the plate surface 111. The inclined surface 122 extends diagonally upward from the plate surface 111 at a position on the negative direction of X side of the vertical surface 121, and is in contact with the vertical surface 121 at its upper end. That is, the inclined surface 122 is a surface that slopes downward from its upper end, which is the connection end with the vertical surface 121, toward the plate surface 111. The inclined surface 122 supports the semiconductor chip located on the positive direction side of X among the stacked semiconductor chips 210 and semiconductor chips 220, thereby maintaining the inclination of each of the semiconductor chips 210 and semiconductor chips 220.

[0017] The angle θ between the plate surface 111 and the inclined surface 122 is, for example, between 3° and 30°. This allows each of the multiple semiconductor chips 210 and 220 to be tilted relative to the plate surface 111 at an angle θ within the above range. Furthermore, by setting the angle θ within the above range, the height in the Z direction of each of the multiple inclined semiconductor chips 210 and 220 can be kept below a predetermined level. The angle θ is just one example of an inclination angle.

[0018] As mentioned above, the wiring board 500 and the support 100a are facing each other with the laminate 200a in between. Therefore, the inclined surface 122 also forms an angle θ with respect to the wiring board 500. In other words, each of the multiple semiconductor chips 210 and semiconductor chips 220, which are arranged at an angle θ with respect to the board surface 111, is also arranged at an angle θ with respect to the wiring board 500. In this specification, for the sake of explanation, the inclination of each configuration of the multiple semiconductor chips 210 and semiconductor chips 220 will be explained with respect to the board surface 111 as the reference, but being inclined with respect to the board surface 111 means that it is also inclined by the same amount with respect to the wiring board 500.

[0019] Each of the multiple semiconductor chips 210 is formed in a rectangular, flat shape and has a main surface 211 as a first surface and a back surface 222 on the opposite side of the main surface 211. The main surface 211 and the back surface 222 are planar and not curved or bent. Each of the multiple semiconductor chips 210 is arranged on the plate surface 111 with the back surface 222 positioned on the inclined surface 122 side of the main surface 211. The back surface 222 is an example of a second surface.

[0020] Each of the multiple semiconductor chips 210 has a semiconductor element (not shown) on its main surface 211 side, which serves as the first surface. The semiconductor element is, for example, a non-volatile memory such as a NAND flash memory. Electrode pads 240 for electrically leading out the semiconductor element are provided at the edges 212 of the main surface 211 of each of the multiple semiconductor chips 210. Note that each of the multiple semiconductor chips 210 is not limited to chips having NAND flash memory or the like.

[0021] Furthermore, in this embodiment, the length of each side constituting the main surface 211 of each semiconductor chip 210 is common to the corresponding side of each of the multiple semiconductor chips 210.

[0022] Each of the multiple semiconductor chips 210 is positioned on the plate surface 111 with the end 212, where the electrode pads 240 are provided, facing upwards, and the end 213 opposite to the end 212 facing downwards. End 212 is an example of a first end, and end 213 is an example of a second end.

[0023] Of the multiple semiconductor chips 210, semiconductor chip 210-1, designated as the first semiconductor chip, is positioned on the inclined surface 122. The back surface 222 of semiconductor chip 210-1 is in contact with the inclined surface 122. As a result, the main surface 211 of semiconductor chip 210-1 forms an angle θ with respect to the plate surface 111. The lower end 215 of the back surface 222 of semiconductor chip 210-1 is in contact with the plate surface 111.

[0024] A second semiconductor chip, semiconductor chip 210-2, is stacked on the layer directly above semiconductor chip 210-1, i.e., on the negative side of X. The main surface 211 of semiconductor chip 210-1 is in contact with the back surface 222 of semiconductor chip 210-2. As a result, the main surface 211 of semiconductor chip 210-2 also forms an angle θ with respect to the plate surface 111.

[0025] At this time, the semiconductor chip 210-2 is stacked with a offset towards the edge 213 side relative to the semiconductor chip 210-1 so that the back surface 222 of the semiconductor chip 210-2 and the electrode pads 240 of the semiconductor chip 210-1 do not overlap. The lower edge 215 of the back surface 222 of the semiconductor chip 210-2 is in contact with the plate surface 111.

[0026] Furthermore, a third semiconductor chip, semiconductor chip 210-3, is stacked on the layer directly above semiconductor chip 210-2, i.e., on the negative side of X. The main surface 211 of semiconductor chip 210-2 is in contact with the back surface 222 of semiconductor chip 210-3. As a result, the main surface 211 of semiconductor chip 210-3 forms an angle θ with respect to the plate surface 111.

[0027] At this time, the semiconductor chip 210-3 is stacked with the semiconductor chip 210-2 offset towards the edge 213 side so that the back surface 222 of the semiconductor chip 210-3 and the electrode pads 240 of the semiconductor chip 210-2 do not overlap. The lower edge 215 of the back surface 222 of the semiconductor chip 210-3 is in contact with the plate surface 111.

[0028] Similarly, the remaining semiconductor chips 210 from the group of semiconductor chips 210 are stacked sequentially on top of semiconductor chip 210-3. In this way, the group of semiconductor chips 210 are stacked sequentially with their respective main surfaces 211 tilted at an angle θ with respect to the board surface 111, and shifted towards the edge 213 side relative to the semiconductor chip 210 one layer below, i.e., the semiconductor chip 210 on the positive X side.

[0029] The electrode pads 240 provided on the main surface 211 of each semiconductor chip 210-1 to 210-3 are aligned at approximately equal heights when viewed from the plate surface 111. In other words, each of the electrode pads 240 of semiconductor chips 210-1 to 210-3 lies on the same plane along the XY plane.

[0030] As described above, the lengths of the edges constituting the main surface 211 are common to each corresponding edge of the semiconductor chip 210. That is, the lengths of one edge of the main surface 211 of semiconductor chips 210-1 to 210-3 along the XZ plane are approximately equal. By shifting each of the semiconductor chips 210-1 to 210-3 in common until they touch the plate surface 111, the electrode pads 240 are aligned approximately parallel to the plate surface 111.

[0031] On the other hand, for example, if the lengths of the sides of the main surfaces 211 of semiconductor chips 210-1 to 210-3 along the XZ plane are different, the amount of displacement of each semiconductor chip 210-1 to 210-3 relative to the semiconductor chip 210 one layer below it is adjusted so that the electrode pads 240 are aligned at approximately equal height positions when viewed from the plate surface 111.

[0032] Hereafter, the surface containing the electrode pads 240 of each semiconductor chip 210-1 to 210-3 will be referred to as the planar SFA. The planar SFA is a surface parallel to the XY plane.

[0033] Furthermore, it is not necessary for all electrode pads 240 of semiconductor chips 210-1 to 210-3 to be included in the planar SFA; it is sufficient for at least two electrode pads 240 of semiconductor chips 210 to be included in the planar SFA.

[0034] The semiconductor chip 220 is, for example, a controller chip that controls NAND flash memory and the like on multiple semiconductor chips 210. Electrode pads 250 are provided at both ends of the main surface 221 of the semiconductor chip 220.

[0035] The semiconductor chip 220 is formed in a flat plate shape and has a main surface 221 as a first surface and a back surface 232 on the opposite side of the main surface 221. The semiconductor chip 220 is positioned such that the back surface 232 is in contact with the main surface 211 of the uppermost semiconductor chip 210. The semiconductor chip 220 is positioned offset from the uppermost semiconductor chip 210 such that at least one of the electrode pads 250 provided at both ends of the main surface 221 is included on the planar SFA.

[0036] However, not all of the electrode pads 240, nor any of the two electrode pads 250, are necessarily included on the planar SFA. For example, it is sufficient if at least two of the electrode pads 240 and 250 are included on the planar SFA.

[0037] An adhesive layer (not shown) may be provided on the underside of each of the multiple semiconductor chips 210 and semiconductor chips 220.

[0038] Metal bumps 600 are connected to electrode pads 240 and 250. The metal bumps 600 include a metal such as Cu. The metal bumps 600 are formed using, for example, thermocompression bonding technology or ultrasonic bonding technology. Vertical wires 400a, described later, are connected to the metal bumps 600.

[0039] The sealing member 300a seals the entire laminate 200a, including the metal bumps 600. The sealing member 300a includes, for example, a thermosetting resin material such as epoxy resin or acrylic resin. The sealing member 300a has a surface 310a that aligns with the XY plane on the side of the laminate 200a to which the metal bumps 600 are connected, i.e., the electrode pad 240 side. In other words, surface 310a is also a surface parallel to the plane SFA.

[0040] Furthermore, surface 310a is also a surface parallel to the plate surface 111 which is aligned with the XY plane. As described above, each of the multiple semiconductor chips 210 and semiconductor chip 220 is tilted at an angle θ with respect to the plate surface 111. That is, surface 310a extends in a direction intersecting the direction in which the main surfaces 211 of the multiple semiconductor chips 210 and the main surface 221 of the semiconductor chip 220 extend. Surface 310a is an example of a third surface.

[0041] The vertical wire 400a connects to one of the metal bumps 600 at its lower end, extends in the positive Z direction through the sealing member 300a, and is exposed on the surface 310a of the sealing member 300a at its upper end 410a. This electrically leads out the multiple semiconductor chips 210 and semiconductor chips 220 onto the surface 310a. The vertical wire 400a contains a metal such as Cu, for example. The vertical wire 400a is an example of a through electrode. In addition to being a through electrode, the vertical wire 400a may also be a vertical electrode or a via.

[0042] As a result, each of the vertical wires 400a is formed to be approximately equal in length, because, as described above, the plane SFA containing the electrode pads 240 and 250 and the surface 310a are formed to be approximately parallel.

[0043] A wiring layer 700 is connected to the upper end 410a of the vertical wire 400a. The wiring layer 700 has a wiring pattern extending along the XY direction on the surface 310a. The wiring layer 700 contains a metal such as Cu. A metal bump 800 is connected to the upper surface of the wiring layer 700. The metal bump 800 is formed using, for example, thermocompression bonding technology or ultrasonic bonding technology. The metal bump 800 contains a metal such as Cu.

[0044] This wiring layer 700 causes the upper end 410a of the vertical wire 400a to be further drawn onto the metal bump 800. As a result, although not shown in the figures, the exposed position of the upper end 410a of the vertical wire 400a on the surface 310a and the drawn-out position of these vertical wires 400a on the metal bump 800 can be made different as needed.

[0045] Above the metal bump 800, a wiring board 500 is provided that extends along the XY plane. At its lower end, the metal bump 800 is connected to the wiring layer 700, and at its upper end, it is connected to electrodes 510 provided on the lower surface of the wiring board 500. This electrically connects the wiring board 500 to the multiple semiconductor chips 210 and semiconductor chip 220.

[0046] Furthermore, adhesive 900 is filled around the metal bump 800. The adhesive 900 is, for example, called an underfill agent and contains liquid epoxy resin or the like. The adhesive 900 is placed between the lower surface of the wiring board 500 and the surface 310a of the sealing member 300a. This protects the connection between the wiring layer 700 and the metal bump 800, and the connection between the metal bump 800 and the electrodes 510 of the wiring board 500.

[0047] The wiring board 500 has a structure in which an insulating layer 520 and a conductive layer 530 are alternately laminated multiple times. The wiring board 500 also has electrodes 510 exposed on its lower surface. The insulating layer 520 includes, for example, carbon fibers, glass fibers, or aramid fibers impregnated with a thermosetting resin such as epoxy resin before curing. The conductive layer 530 is made of a metal such as Cu. The conductive layer 530 has a wiring pattern extending along the XY plane and is connected to the electrodes 510.

[0048] Although not shown in the diagram, solder balls that connect to the conductive layer 530 may be placed on the upper surface of the wiring board 500. By connecting the solder balls to, for example, a motherboard (not shown), the semiconductor device 1 can be mounted on the motherboard or the like.

[0049] (Method of manufacturing semiconductor devices) Next, the manufacturing method of the semiconductor device 1 according to the embodiment will be described using Figures 2 to 4. Figures 2 to 4 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor device 1 according to the embodiment.

[0050] First, the procedure for forming the laminate 200a will be explained using Figures 2(a) to 2(c).

[0051] Prior to the process shown in Figure 2(a), metal bumps 600 are placed on the electrode pads 240 provided on the edges 212 of the main surface 211 of the multiple semiconductor chips 210, and on the electrode pads 250 provided on both ends of the main surface 221 of the semiconductor chip 220. The metal bumps 600 protect the electrode pads 240 and 250 from laser light and the like when contact holes Hr are formed later.

[0052] However, this does not apply to the timing of placement of the metal bumps 600. For example, the metal bumps 600 may be placed after the laminate 200a has been formed.

[0053] As shown in Figure 2(a), a support 100a for arranging the laminate 200a is prepared. The support 100a has a plate-like portion 110 that is aligned with the XY plane and a base portion 120. The base portion 120 has an inclined surface 122 that extends in a direction forming an angle θ from the plate surface 111.

[0054] The laminate 200a includes semiconductor chips 210-1 to 210-p. Each semiconductor chip 210-1 to 210-p has a main surface 211 as the first surface and a back surface 222 opposite to the main surface 211. Electrode pads 240 are provided at the edges 212 of the main surface 211 of each semiconductor chip 210-1 to 210-p.

[0055] First, the semiconductor chip 210-1 is placed on the inclined surface 122 of the support 100a. As a result, the main surface 211 of the semiconductor chip 210-1 is tilted at an angle θ with respect to the plate surface 111. The back surface 222 of the semiconductor chip 210-1 is in contact with the inclined surface 122. That is, the main surface 211 of the semiconductor chip 210-1 is facing upward. The semiconductor chip 210-1 is also positioned such that the end 212 of the main surface 211 is on the upper side of the inclined surface 122, and the end 213 is on the lower side of the inclined surface 122. The end 215 of the back surface 222 of the semiconductor chip 210-1 is in contact with the plate surface 111.

[0056] Next, as shown in Figure 2(b), semiconductor chip 210-2 is stacked on the layer above semiconductor chip 210-1, i.e., on the negative side of X. The main surface 211 of semiconductor chip 210-1 and the back surface 222 of semiconductor chip 210-2 are in contact. As a result, the main surface 211 of semiconductor chip 210-2 is tilted at an angle θ with respect to the plate surface 111.

[0057] Furthermore, the semiconductor chip 210-2 is positioned such that its end 212 is on the upper side and its end 213 is on the lower side. At this time, the semiconductor chip 210-2 is offset towards the end 213 side relative to the semiconductor chip 210-1 so that the back surface 222 of the semiconductor chip 210-2 and the electrode pads 240 of the semiconductor chip 210-1 do not overlap.

[0058] The semiconductor chip 210-2 has its back surface 222 edge 215 shifted towards the edge 213 until it contacts the board surface 111. As a result, the electrode pads 240 of semiconductor chip 210-1 and semiconductor chip 210-2 are aligned on a plane SFA along the XY plane. This is because the lengths of one side of the main surface 211 of semiconductor chips 210-1 and 210-2 along the XZ plane are approximately equal.

[0059] As shown in Figure 2(c), semiconductor chip 210-3 is stacked on the layer above semiconductor chip 210-2, i.e., on the negative side of X. The main surface 211 of semiconductor chip 210-2 and the back surface 222 of semiconductor chip 210-3 are in contact. As a result, the main surface 211 of semiconductor chip 210-3 is also tilted at an angle θ with respect to the plate surface 111.

[0060] Furthermore, the semiconductor chip 210-3 is positioned such that its end 212 is on the upper side and its end 213 is on the lower side. In this configuration, the semiconductor chip 210-3 is offset towards the end 213 side relative to the semiconductor chip 210-2 so that the back surface 222 of the semiconductor chip 210-3 does not overlap with the electrode pads 240 of the semiconductor chip 210-2.

[0061] The semiconductor chip 210-3 has its back surface 222 edge 215 shifted towards the edge 213 until it contacts the board surface 111. As a result, the electrode pads 240 of semiconductor chip 210-2 and semiconductor chip 210-3 are aligned on a plane SFA along the XY plane. This is because the lengths of one side of the main surface 211 of semiconductor chips 210-2 and 210-3 along the XZ plane are approximately equal.

[0062] In this way, the fourth, fifth, and subsequent semiconductor chips 210 are sequentially placed on the semiconductor chip 210-3. As a result, the main surfaces 211 of the fourth, fifth, and subsequent semiconductor chips 210 are also tilted at an angle θ with respect to the plate surface 111.

[0063] The fourth, fifth, and subsequent semiconductor chips 210 are also shifted towards the edge 213 side of the back surface 222 until the edge 215 of the back surface 222 touches the board surface 111, relative to the semiconductor chip 210 on the lower layer, i.e., the semiconductor chip 210 on the positive X side.

[0064] Next, a semiconductor chip 220 is placed on the main surface 211 of the uppermost semiconductor chip 210. The semiconductor chip 220 is offset from the uppermost semiconductor chip 210 such that at least one of the electrode pads 250 provided on the main surface 221 is included on the planar SFA. In this way, the laminate 200a is formed.

[0065] Next, as shown in Figure 3(a), a sealing member 300a is formed to cover the laminate 200a. Specifically, for example, the sealing member 300a before hardening is placed at the bottom of a mold (not shown), the support 100a is inverted upside down so that the plate surface 111 faces downward, and the support 100a is inserted into the mold together with the support 100a. Then, the mold is heated to harden the sealing member 300a, and the mold is removed. As a result, the entire laminate 200a is covered with the sealing member 300a. The surfaces 310a of the sealing member 300a on the electrode pads 240 and 250 side extend along the XY plane.

[0066] Next, as shown in Figure 3(b), a resist pattern RP for forming a wiring layer 700 is formed on the surface 310a of the sealing member 300a. The resist pattern RP is obtained by exposing and developing the resist layer. The resist pattern RP has a wiring pattern extending in the XY direction.

[0067] Next, a laser or the like is irradiated from above the resist pattern RP to form contact holes Hr that extend from surface 310a through the sealing member 300a in the negative Z direction and reach each of the metal bumps 600. The contact holes Hr are configured to later become vertical wires 400a.

[0068] However, the formation order of the resist pattern RP and the contact holes Hr is not limited to this. For example, after forming the contact holes Hr, a resist layer (not shown) may be formed to cover the contact holes Hr and the surface 310a, and the resist pattern RP may be formed by exposing and developing the resist layer.

[0069] Next, a plating layer MPa is formed to cover the contact hole Hr and the opening of the resist pattern RP, as shown in Figure 3(c), for example, by an electroplating method. The plating layer MPa contains a metal such as Cu. This forms a vertical wire 400a in the area corresponding to the contact hole Hr. At this time, the plating layer MPa may also be partially formed on the upper surface of the resist pattern RP. Next, the resist pattern RP is removed by a lift-off method or the like. In this way, a wiring layer 700 is formed on the surface 310a.

[0070] Next, as shown in Figure 4(a), metal bumps 800 are formed to connect to the wiring layer 700. The metal bumps 800 include, for example, a metal such as Cu or Au.

[0071] Next, as shown in Figure 4(b), the metal bump 800 and the electrode 510 provided on the lower surface of the wiring board 500 are connected vertically. Specifically, the electrode 510 of the wiring board 500 and the metal bump 800 are stacked vertically and heated to approximately 200°C. As a result, the molten metal bump 800 and the electrode 510 are joined together, and the wiring board 500 is electrically connected to each of the semiconductor chips 210 and semiconductor chips 220.

[0072] Subsequently, adhesive 900 is filled between the lower surface of the wiring board 500 and surface 310a. Specifically, the paste-like liquid adhesive 900, which is the adhesive before curing, is applied to the lower surface of the wiring board 500, the side surface of the metal bump 800, and surface 310a using at least one of the following methods: coating, adhesion, and spraying. Then, the adhesive 900 is cured by heating, for example, in an oven.

[0073] Next, the wiring board 500 is cut in the Z direction to separate it into individual pieces. This completes the manufacturing of the semiconductor device 1 according to this embodiment.

[0074] However, the timing of individualization is not limited to this. For example, the wiring board 500 and the laminate 200a may be individually separated in advance, and the individualized wiring board 500 and the laminate 200a may be electrically connected.

[0075] (Comparative example) Next, the semiconductor device of the comparative example will be described using Figure 12. Figure 12 is a diagram illustrating a part of the procedure for manufacturing the semiconductor device according to the comparative example.

[0076] As shown in Figure 12(a), in the comparative example of semiconductor device manufacturing method, no inclined surface 122 is formed on the support 100x. Multiple semiconductor chips 210 and 220 are sequentially stacked parallel to the plate surface 111, for example, while being shifted toward the negative direction of X. Therefore, the height position of the electrode pads 240 as viewed from the plate surface 111 increases from the lower layer. Furthermore, the electrode pad 250 is located even above the uppermost electrode pad 240.

[0077] Next, in the manufacturing method of the comparative example semiconductor device, as shown in Figure 12(b), vertical wires 400x are formed, connected to the electrode pads 240 and 250 respectively, and extending in the Z direction. Each of the vertical wires 400x reaches a position higher than the main surface 221 of the semiconductor chip 220, and the height position in the Z direction of their upper ends is approximately equal. For this reason, the length of the vertical wires 400x is longer the lower the semiconductor chip 210 is. Also, the length of the vertical wires 400x increases as the number of stacked semiconductor chips 210 and 220 increases. When the length of the vertical wires 400x increases, the electrical resistance of the vertical wires 400x increases, which may degrade the electrical characteristics of the semiconductor device.

[0078] Furthermore, in the semiconductor device manufacturing method of the comparative example, the sealing member 300a is not formed at the stage where the vertical wires 400x are formed. Therefore, each of the vertical wires 400x extends through an atmosphere such as gas. Since the vertical wires 400x extending through the atmosphere are not fixed in position, they may interfere with each other. When the vertical wires 400x interfere with each other, a short circuit may occur between multiple semiconductor chips 210 and semiconductor chips 220. Also, the longer the length of the vertical wires 400x, the higher the possibility of the vertical wires 400x interfering with each other, and therefore the higher the possibility of a short circuit between multiple semiconductor chips 210 and semiconductor chips 220.

[0079] Furthermore, in the manufacturing method of the semiconductor device in the comparative example, as shown in Figure 12(c), when forming the sealing member 300a, the position of the vertical wire 400x may shift due to contact with the sealing member 300a. When the position of the vertical wire 400x shifts, the exposed position of the upper end portion 410x of the vertical wire 400x on the surface 310a may shift. As a result, connection to the wiring board 500 may become difficult.

[0080] Furthermore, the vertical wire 400x may contain, for example, Au (gold). Using relatively expensive Au can increase production costs.

[0081] (Overview) In contrast, the laminated structure 200a of the semiconductor device 1 in this embodiment includes semiconductor chips 210-1 to 210-3 arranged such that their main surfaces 211 are tilted with respect to the wiring substrate 500. One layer above semiconductor chip 210-1, semiconductor chip 210-2 is laminated on the negative X side so as not to overlap with the electrode pads 240 of semiconductor chip 210-1, and one layer above semiconductor chip 210-2, semiconductor chip 210-3 is laminated on the negative X side so as not to overlap with the electrode pads 240 of semiconductor chip 210-2. As a result, the electrode pads 240 of at least two of the semiconductor chips 210-1 to 210-3 are included in the planar SFA.

[0082] The sealing member 300a has a surface 310a on the electrode pad 240 side that is substantially parallel to the planar SFA. Multiple vertical wires 400a extend from each of the electrode pads 240 in a direction perpendicular to the surface 310a and are exposed to the surface 310a. As a result, the distance between the planar SFA and the surface 310a is equally shortened. This makes it easier to pull out the vertical wires 400a to the surface 310a. In addition, since the length of each of the multiple vertical wires 400a extending between the planar SFA and the surface 310a is equally shortened, the electrical resistance in the vertical wires 400a is reduced, and the electrical characteristics of the semiconductor device 1 are improved.

[0083] Furthermore, each of the multiple semiconductor chips 210 and 220 is stacked at an angle such that its end 212 is positioned above its end 213. The angle θ of each of the multiple semiconductor chips 210 and 220 with respect to the wiring board 500 is between 3 and 30 degrees. This allows the height of each of the multiple semiconductor chips 210 and 220 in the Z direction to be kept below a predetermined level.

[0084] Furthermore, it is desirable that each of the multiple semiconductor chips 210 and 220 has an elongated rectangular shape with a short side along the XZ plane and a long side along the YZ plane. This is because the height in the Z direction of each of the multiple semiconductor chips 210 and 220, which are arranged at an angle on the upper surface of the support 100a, will be the height corresponding to the length of one side of each semiconductor chip along the XZ plane. By making the length of one side of each semiconductor chip along the XZ plane short, the height in the Z direction of each of the multiple semiconductor chips 210 and 220 can be reduced, and as a result, the semiconductor device 1 can be made thinner.

[0085] Furthermore, in the semiconductor device manufacturing method of this embodiment, after forming the sealing member 300a, vertical wires 400a extending through the sealing member 300a are formed. Since the position of each vertical wire 400a is fixed by the sealing member 300a, interference between the vertical wires 400a can be prevented. As a result, short circuits between multiple semiconductor chips 210 and semiconductor chips 220 can be suppressed. In addition, since displacement of the vertical wires 400a can be prevented, the difficulty of electrical connection between the vertical wires 400a and the wiring board 500 can be reduced.

[0086] Furthermore, by forming the sealing member 300a first, and then forming the vertical wire 400a extending through the sealing member 300a, a plating method can be used to form the vertical wire 400a. By using a plating method, relatively inexpensive metals such as Cu can be used as the material for the vertical wire 400a. As a result, production costs can be reduced.

[0087] [Example 1] A method for manufacturing the semiconductor device 1a of the modified embodiment 1 will be described using Figures 5A and 5B. The method for manufacturing the semiconductor device 1a of the modified embodiment 1 differs from the above-described embodiment in that it does not form a wiring layer 700.

[0088] In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0089] Figures 5A and 5B are diagrams illustrating, in order, a part of the procedure for manufacturing a semiconductor device 1a according to a modified example 1 of the embodiment.

[0090] Prior to Figure 5A(a), the manufacturing method of the semiconductor device 1a of Modified Example 1 involves the processes up to Figure 3(a) of the above-described embodiment.

[0091] As shown in Figure 5A(a), a resist layer RF is formed to cover the surface 310a of the sealing member 300a. By covering the surface 310a with the resist layer RF, it is possible to suppress the adhesion of the plating layer MPb to the surface 310a when the vertical wire 400a is formed later. After the formation of the resist layer RF, a laser or the like is irradiated from above the resist layer RF to form a contact hole Hr.

[0092] Next, a plating layer MPb covering the contact hole Hr is formed, for example, using an electroplating method, as shown in Figure 5A(b). This forms a vertical wire 400a in the area where the contact hole Hr was previously formed. At this time, a portion of the plating layer MPb may also be formed on the upper surface of the resist layer RF.

[0093] Next, the resist layer RF formed on the surface 310a is removed by a lift-off method or the like. If the upper end 410a of the vertical wire 400a protrudes above the surface 310a, the vertical wire 400a may be ground from above using a method such as CMP (Chemical Mechanical Polishing) to align the height of the surface 310a with the upper end 410a of the vertical wire 400a.

[0094] Next, as shown in Figure 5A(c), a metal bump 800 is formed to connect to the upper end 410a of the vertical wire 400a.

[0095] Following Figure 5A(c), the processes shown in Figure 4(b) and subsequent figures of the embodiment are carried out. In this way, the semiconductor device 1a shown in Figure 5B is formed. With this, the manufacturing of the semiconductor device 1a of Modification 1 is completed.

[0096] According to the manufacturing method of semiconductor device 1a of Modification 1, a semiconductor device that has the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0097] [Differentiation 2] A method for manufacturing the semiconductor device 1b of the modified embodiment 2 will be described using Figures 6A and 6B. The method for manufacturing the semiconductor device 1b of the modified embodiment 2 differs from the above-described embodiment in that a wire 420a is used as the through electrode instead of a vertical wire 400a.

[0098] In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0099] Figures 6A and 6B are diagrams illustrating, in order, a part of the procedure for manufacturing a semiconductor device 1b according to a modified example 2 of the embodiment.

[0100] Prior to Figure 6A(a), the manufacturing method of the semiconductor device 1b of the modified example 2 involves the processes up to Figure 2(c) of the above-described embodiment.

[0101] As shown in Figure 6A(a), multiple wires 420a are formed to connect adjacent electrode pads 240 located vertically to each other, and to connect electrode pads 250 located on the semiconductor chip 220 to each other. In other words, some of the multiple wires 420a connect adjacent electrode pads 240 located vertically to each other, and some of the wires 420a connect electrode pads 250 to each other.

[0102] Some of the multiple wires 420a extend in the positive Z direction from a metal bump 600 covering one of the electrode pads 240, curve and fold back at their upper ends 421a, and connect to a metal bump 600 covering an adjacent electrode pad 240. Other wires 420a extend in the positive Z direction from a metal bump 600 covering one electrode pad 250, curve and fold back at their upper ends 421a, and connect to a metal bump 600 covering the other electrode pad 250.

[0103] The wire 420a is formed by a wire bonding method. The upper end portion 421a is an example of a folded portion. The positive direction of Z is an example of a second direction.

[0104] Next, as shown in Figure 6A(b), a sealing member 300b is formed to cover the entire laminate 200a including the wire 420a. However, at this stage, the wire 420a is not exposed from the sealing member 300b. That is, the sealing member 300b does not have a surface 310a.

[0105] Next, the sealing member 300b is ground from above, i.e., from the positive Z direction side, using a method such as CMP until the upper end portion 421a of the wire 420a is cut off. That is, as shown in Figure 6A(c), the sealing member 300b is ground until the upper end portion 421a is removed and the wire 420a becomes wire 420a-1 and wire 420a-2. As a result, the height of the sealing member 300b is reduced and a surface 310aa is formed, and the respective ends 430a of wire 420a-1 and wire 420a-2 are exposed on this surface 310aa. Surface 310aa is a surface parallel to the plane SFA. Surface 310aa is an example of a third surface.

[0106] Following Figure 6A(c), the process from Figure 5A(c) onward in Modification 1 is carried out. However, in Modification 2, metal bumps 800 are formed to connect to the respective ends 430a of wires 420a-1 and 420a-2. In this way, the semiconductor device 1b shown in Figure 6B is formed. With this, the manufacturing of the semiconductor device 1b of Modification 2 is completed.

[0107] According to the manufacturing method of semiconductor device 1b of the modified example 2, a semiconductor device that has the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0108] [Difference 3] The method for manufacturing the semiconductor device 1c of the third modified embodiment will be described using Figures 7A and 7B. The method for manufacturing the semiconductor device 1c of the third modified embodiment is a modification corresponding to the second modified embodiment, and the procedure from when the laminate 200a is placed on the support 100b until it is sealed differs from the above-described embodiment and the second modified embodiment.

[0109] In the following, components similar to those in the embodiments and modified examples described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0110] Figures 7A and 7B are diagrams illustrating, in order, a part of the procedure for manufacturing a semiconductor device 1c according to a modified example 3 of the embodiment.

[0111] As shown in Figure 7A(a), the support 100b of the semiconductor device 1c according to Modification 3 does not have an inclined surface 122. Multiple semiconductor chips 210 and semiconductor chips 220 are sequentially stacked parallel to the plate surface 111, for example, while being shifted towards the negative direction of X. In this way, the laminate 200a is formed.

[0112] The plate surface 111 and the back surface 222 of the semiconductor chip 210-1 overlap. Furthermore, when stacking semiconductor chips 210-2, 210-3, etc. on top of semiconductor chip 210-1 which is in contact with the plate surface 111, the amount of displacement relative to the semiconductor chip 210 directly below is adjusted so that each of the electrode pads 240 provided on the edge 212 of the main surface 211 is included on the same planar SFB. The planar SFB extends in a direction that forms an angle θ with respect to the plate surface 111. The direction that forms an angle θ with respect to the plate surface 111 is an example of a third direction.

[0113] Next, as shown in Figure 7A(b), multiple wires 420b are formed to connect adjacent electrode pads 240 and electrode pads 250 to each other.

[0114] Some of the multiple wires 420b extend from the metal bump 600 covering one of the electrode pads 240 in the direction of arrow R in Figure 7A(b), curve and fold back at the upper end 421b, and connect to the metal bump 600 covering the adjacent electrode pad 240. Also, some of the wires 420b extend from the metal bump 600 covering one electrode pad 250 in the direction of arrow R, curve and fold back at the upper end 421b, and connect to the metal bump 600 covering the other electrode pad 250. The direction of arrow R is perpendicular to the plane SFB. That is, the direction of arrow R is the +X and +Z direction in Figure 7A(b). The direction of arrow R is an example of a fourth direction. The upper end 421b is an example of a folded portion.

[0115] Next, the semiconductor chip 210-1 is peeled off from the plate surface 111, thereby separating the entire laminate 200a from the support 100b. Then, as shown in Figure 7A(c), the laminate 200a is tilted so that the planar SFB is aligned with the plate surface 111, and the tilted laminate 200a is repositioned on the plate surface 111. As a result, the electrode pads 240 and 250 are aligned at approximately equal height positions when viewed from the plate surface 111, and each of the wires 420b extending from each electrode pad extends in the positive Z direction. The plate surface 111 is an example of the upper surface of the support 100b.

[0116] In this case, the plate surface 111 of the support 100b on which the laminate 200a is repositioned may be provided with a projection 130 for supporting the tilted laminate 200a.

[0117] Following Figure 7A(c), the processes shown in Figure 6A(b) and subsequent steps of Modification 2 are carried out. In this way, the semiconductor device 1c shown in Figure 7B is formed. With this, the manufacturing of the semiconductor device 1c of Modification 3 is completed.

[0118] According to the manufacturing method of semiconductor device 1c of Modification 3, a semiconductor device that has the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0119] [Differentiation Example 4] Using Figure 8, the manufacturing method for the semiconductor device 1d of the modified embodiment 4 will be described. The manufacturing method for the semiconductor device 1d of modified embodiment 4 is a modified version corresponding to modified embodiment 1, and differs from the above-described embodiment and modified embodiment 1 in that metal bumps 800 are not formed.

[0120] In the following, components similar to those in the embodiments and modified examples described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0121] Figure 8 is a diagram illustrating, in sequence, a part of the procedure for manufacturing a semiconductor device 1d according to a modified example 4 of the embodiment.

[0122] Prior to Figure 8(a), the manufacturing method of the semiconductor device 1d in Modification 4 involves the processes up to Figure 5A(b) of Modification 1 described above.

[0123] As shown in Figure 8(a), each electrode 510 provided on the lower surface of the wiring board 500 has a projection 511 that protrudes downward. The projection 511 is wedge-shaped. The projection 511 is made of, for example, SUS (Steel Special Use Stainless) containing Ni.

[0124] However, the projection 511 does not necessarily have to contain SUS; it is sufficient if it contains a metal with higher hardness than the metal such as Cu contained in the vertical wire 400a.

[0125] As shown in Figure 8(b), the projection 511 and the upper end 410a of the vertical wire 400a are positioned opposite each other vertically, and the wiring board 500 is pressed against the surface 310a. This causes the projection 511 to be inserted into the upper end 410a of the vertical wire 400a. At this time, the metal contained in the vertical wire 400a, which is pressed downward by the projection 511, experiences stress that tries to return it upward. This stress on the metal ensures a more secure connection between the projection 511 and the vertical wire 400a.

[0126] As described above, the wiring board 500 and the vertical wire 400a can be electrically connected without using the metal bump 800. As mentioned above, the metal bump 800 in this embodiment is heated to approximately 200°C to melt the solder when joining it with the electrode 510. When the metal bump 800 is heated, the temperature of the surrounding components such as the wiring board 500 may also rise. The presence of the protrusion 511 reduces the thermal impact on each component.

[0127] Next, adhesive 900 is filled between the lower surface and surface 310a of the wiring board 500, and then the wiring board 500 is cut in the Z direction to separate it into individual pieces. This completes the manufacturing of the semiconductor device 1d of the modified example 4.

[0128] According to the manufacturing method of the semiconductor device 1d of the modified example 4, a semiconductor device that provides the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0129] [Difference 5] The manufacturing method for the semiconductor device 1e of the modified embodiment 5 will be described with reference to Figures 9A and 9B. The manufacturing method for the semiconductor device 1e of the modified embodiment 5 differs from the above-described embodiment in that passive components are further stacked on top of the semiconductor chip 220.

[0130] In the following, components similar to those in the embodiments and modified examples described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0131] Figures 9A and 9B illustrate, in sequence, a part of the procedure for manufacturing a semiconductor device 1e according to modified embodiment 5. In Figure 9B, the cross-section including the semiconductor chip 220 and the cross-section including the passive component 290 are shown superimposed for convenience.

[0132] Prior to Figure 9A, the manufacturing method of the semiconductor device 1e in Modification 5 involves the processes up to Figure 2(c) of the above-described embodiment.

[0133] As shown in Figure 9A, in the process of forming the laminate 200a, a passive component 290 is placed in an area on the main surface 211 of the uppermost semiconductor chip 210 where the semiconductor chip 220 is not placed. The passive component 290 is, for example, a capacitor. The side of the passive component 290 opposite to the uppermost semiconductor chip 210 is covered by an electrode layer 291. The passive component 290 is appropriately offset from the uppermost semiconductor chip 210 so that the electrode layer 291 is included on the planar SFA.

[0134] Furthermore, the passive component 290 does not necessarily have to be located on the main surface 211 of the uppermost semiconductor chip 210; for example, it may be located on the main surface 221 of the semiconductor chip 220. Also, in the examples of Figures 9A and 9B, it is assumed that the semiconductor chip 220 and the passive component 290 are not included in the same cross-section, but this is not limited to this. The semiconductor chip 220 and the passive component 290 may be included in the same cross-section.

[0135] Following Figure 9A, the processes shown in Figure 3(a) and subsequent figures of the embodiment are carried out. However, in Modification 5, a vertical wire 400aa is also formed that connects to the electrode layer 291 of the passive component 290 at the lower end, extends upward through the sealing member 300a, and is exposed on the surface 310a. In this way, the semiconductor device 1e shown in Figure 9B is formed. With this, the manufacturing of the semiconductor device 1e of Modification 5 is completed.

[0136] According to the manufacturing method of semiconductor device 1e in Modification 5, a semiconductor device that has the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0137] [Modification 6] The manufacturing method for the semiconductor device 1f of the modified embodiment 6 will be described using Figures 10 to 11B. The manufacturing method for the semiconductor device 1f of modified embodiment 6 is a modified version of modified embodiment 3, and differs from the above-described embodiment and modified embodiment 3 in that laminates 200a sealed by sealing members 300c are stacked in the Z direction.

[0138] In the following, components similar to those in the embodiments and modified examples described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0139] Figures 10 to 11B are diagrams illustrating, in order, a part of the procedure for manufacturing a semiconductor device 1f according to a modified example 6 of the embodiment.

[0140] Prior to Figure 10(a), the manufacturing method of the semiconductor device 1f of Modification 6 is carried out up to Figure 7A(b) of Modification 3 described above. That is, on the plate surface 111 of the support 100b, a plurality of semiconductor chips 210 and semiconductor chips 220 are stacked parallel to the plate surface 111 while being shifted toward the negative direction of X, forming the first layer of the stacked body 200a. The electrode pads 240 and 250 of the plurality of semiconductor chips 210 and semiconductor chips 220 are contained on the same planar SFB.

[0141] Furthermore, each of the first layer of laminated material 200a has a wire 420b formed thereon that connects the electrode pads 240 to each other and the electrode pads 250 to each other. The wire 420b extends in the direction of arrow R perpendicular to the planar SFB and curves and folds back at its upper end 421b.

[0142] As shown in Figure 10(a), a first layer of sealing member 300c is formed that covers the entire laminate 200a including the wire 420b. However, at this stage, the sealing member 300c has a surface 320 on its upper side. The wire 420b is not exposed on surface 320. In other words, the sealing member 300c does not have a surface 310a.

[0143] Next, as shown in Figure 10(b), the second layer of laminate 200a is placed on the surface 320. Specifically, on the surface 320, a plurality of semiconductor chips 210 and semiconductor chips 220 are stacked parallel to the surface 320 while being shifted toward the negative direction of X, forming the second layer of laminate 200a. At this time, the placement positions of the respective electrode pads 240 and 250 of the second layer of laminate 200a are adjusted so that they are included on the same plane as the planar SFB.

[0144] Each of the second layer of laminate 200a also has a wire 420b that extends in the direction of arrow R. Next, a second layer sealing member 300c is formed that covers the entire second layer of laminate 200a, including the wires 420b.

[0145] Next, as shown in Figure 11A(a), the first and second layers of sealing member 300c are cut along the dicing line DL that runs along the planar SFB. The dicing line DL passes through the position where the upper end 421b of the wire 420b is cut. As a result, a surface 310b is formed on the sealing member 300c, and the end 430b of the wire 420b is exposed on the surface 310b.

[0146] Following Figure 11A(a), the process shown in Figure 5A(c) and subsequent steps of Modification 1 is performed. Specifically, as shown in Figure 11A(b), a metal bump 800 is formed to connect to the end 430b of the wire 420b. After that, the process shown in Figure 6A(c) and subsequent steps of Modification 2 is performed. In this way, the semiconductor device 1f shown in Figure 11B is formed. With this, the manufacturing of the semiconductor device 1f of Modification 6 is completed.

[0147] According to the manufacturing method of the semiconductor device 1f of Modification 6, more semiconductor devices 1f can be cut out from the sealing member 300c before it is separated into individual pieces. In addition, a semiconductor device that has the same effects as the semiconductor device 1 of the embodiment can be obtained.

[0148] [Other variations] In the embodiments and modifications described above, the supports 100a and 100b include, for example, a resin material, but are not limited thereto. For example, the supports 100a and 100b may include a material similar to that of the wiring board 500. By making the supports 100a and 100b and the wiring board 500 have similar configurations, the thermal expansion rates of the supports 100a and 100b and the wiring board 500 will be approximately the same. Since the thermal expansion rates of the supports 100a and 100b and the wiring board 500, which are arranged opposite each other in the Z direction, are approximately equal, the stress due to their respective expansion and contraction is suppressed, and as a result, warping of the semiconductor device 1 is suppressed.

[0149] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0150] 1, 1a~1f... Semiconductor device, 100a, 100b... Support, 122... Inclined surface, 200a... Laminate, 210, 220... Semiconductor chip, 211, 221... Main surface, 212, 213, 215... End, 240, 250... Electrode pad, 300a, 300b, 300c... Sealing member, 310a, 310aa, 310b, 320... Surface, 400a... Vertical wire, 410a... Upper end, 420a, 420b... Wire, 500... Wiring board, 600, 800... Metal bump, 700... Wiring layer, 900... Adhesive.

Claims

1. Wiring board and Each of the first to third semiconductor chips has a first surface and a second surface opposite to the first surface, and is positioned opposite the wiring board such that the first surface is tilted relative to the wiring board, each of the first to third semiconductor chips has an electrode pad at the end of the first surface, and on one upper layer of the first semiconductor chip, the second semiconductor chip is stacked in a first direction along the wiring board such that the second surface of the second semiconductor chip and the electrode pad of the first semiconductor chip do not overlap, and on one upper layer of the second semiconductor chip, the third semiconductor chip is stacked in the first direction such that the second surface of the third semiconductor chip and the electrode pad of the second semiconductor chip do not overlap, A sealing member that covers the laminate and has a third surface on the electrode pad side that is substantially parallel to the plane containing the electrode pads of at least two of the first to third semiconductor chips, The system comprises a plurality of through electrodes extending from the electrode pad into the sealing member in a second direction perpendicular to the third surface and connected to the wiring board. Semiconductor equipment.

2. The inclination angle of the first surface of each of the first to third semiconductor chips with respect to the wiring substrate is 3 degrees or more and 30 degrees or less. The semiconductor device according to claim 1.

3. The plurality of through electrodes include Cu, The semiconductor device according to claim 1.

4. A wiring layer extending on the third surface and connecting the through electrode and the wiring substrate, Furthermore, The semiconductor device according to claim 1.

5. The plurality of through electrodes and the wiring board are, The wiring board is connected via a wedge-shaped projection formed on the surface facing the third surface. The semiconductor device according to claim 1.

6. Each of the first to third semiconductor chips has a first surface and a second surface opposite to the first surface, and each of the first to third semiconductor chips has an electrode pad at the edge of the first surface, and on one upper layer of the first semiconductor chip, the second semiconductor chip is stacked in a first direction such that the second surface of the second semiconductor chip and the electrode pad of the first semiconductor chip do not overlap, and on one upper layer of the second semiconductor chip, the third semiconductor chip is stacked in a first direction such that the second surface of the third semiconductor chip and the electrode pad of the second semiconductor chip do not overlap, forming a laminate. A sealing member is formed that covers the laminate and has a third surface on the electrode pad side that is substantially parallel to the plane containing the electrode pads of at least two of the first to third semiconductor chips. A through electrode is formed extending from the electrode pad into the sealing member in a second direction perpendicular to the third surface and exposed to the third surface. The through electrode and the wiring board are connected in the second direction. A method for manufacturing a semiconductor device.

7. Each of the first to third semiconductor chips has a first surface and a second surface opposite to the first surface, and each of the first to third semiconductor chips has an electrode pad at the edge of the first surface, and on one upper layer of the first semiconductor chip, the second semiconductor chip is stacked in a first direction such that the second surface of the second semiconductor chip and the electrode pad of the first semiconductor chip do not overlap, and on one upper layer of the second semiconductor chip, the third semiconductor chip is stacked in a first direction such that the second surface of the third semiconductor chip and the electrode pad of the second semiconductor chip do not overlap, forming a laminate. Connecting two adjacent electrode pads, a wire is formed having a folded portion on the second direction side perpendicular to the plane containing the electrode pads of at least two of the first to third semiconductor chips. A sealing member is formed to cover the laminate and the wire. The end of the wire is exposed on a third surface substantially parallel to the plane formed by cutting the sealing member from the second direction side until the folded portion is cut off. The end of the wire and the wiring board are connected in the second direction. A method for manufacturing a semiconductor device.

8. Forming the aforementioned laminate is This includes arranging the first semiconductor chip on the upper surface of the support such that the upper surface and the second surface of the first semiconductor chip overlap, Forming the aforementioned wire is The wire having the folded portion is formed in a fourth direction perpendicular to the plane that extends along the third direction which forms an angle with respect to the upper surface of the support, Before forming the sealing member, The laminate including the first semiconductor chip is peeled off from the upper surface of the support. This includes rearranging the laminate on the upper surface of the support such that the plane extends along a plane perpendicular to the second direction. The method for manufacturing a semiconductor device according to claim 7.

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