Indium phosphide substrate, semiconductor epitaxial wafer, and method for manufacturing an indium phosphide substrate

Abstract

This invention provides indium phosphide substrates and semiconductor epitaxial wafers with good surface morphology. [Solution] An indium phosphide substrate containing at least one of S, Fe, Zn, and Sn as a dopant, with a haze of 1.0 ppm or less.

Description

[Technical Field]

[0001] This invention relates to an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for manufacturing an indium phosphide substrate. [Background technology]

[0002] Indium phosphide (InP) is a III-V compound semiconductor material composed of indium (In) of Group III and phosphorus (P) of Group V. Its semiconductor properties include a band gap of 1.35 eV and an electron mobility of ~5400 cm⁻¹. 2 It has a value of / V·s, and its electron mobility under high electric fields is higher than that of other common semiconductor materials such as silicon and gallium arsenide. Furthermore, its stable crystal structure at room temperature and pressure is a cubic zincblende type structure, and its lattice constant is larger compared to compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP).

[0003] Patent Document 1 discloses an indium phosphide substrate comprising a first main surface and a second main surface, wherein the average value m1 of the surface roughness Ra1 at the center of the first main surface and the surface roughness Ra2, Ra3, Ra4, and Ra5 at four locations arranged at equal intervals along the outer edge 5 mm inward from the outer edge of the first main surface is 0.1 nm or more and 0.3 nm or less, the standard deviation σ1 of the surface roughness Ra1, Ra2, Ra3, Ra4, and Ra5 is 10% or less of the average value m1, the average value m2 of the surface roughness Ra6 at the center of the second main surface and the surface roughness Ra7, Ra8, Ra9, and Ra10 at four locations arranged at equal intervals along the outer edge 5 mm inward from the outer edge of the second main surface is 0.5 nm or more and 2 nm or less, and the standard deviation σ2 of the surface roughness Ra6, Ra7, Ra8, Ra9, and Ra10 is 10% or less of the average value m2. Furthermore, it is stated that with this configuration, the surface roughness of the substrate can be controlled, the uniformity of the epitaxial film grown on the substrate can be improved, and an indium phosphide substrate can be provided that can improve the PL characteristics of an epitaxial wafer using the epitaxial film. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 6508373 [Overview of the project] [Problems that the invention aims to solve]

[0005] When performing heteroepitaxial growth of materials such as AlInGaAs and InGaAsP on an indium phosphide substrate, if the surface morphology is non-uniform throughout the substrate, uniform epitaxial growth becomes difficult, which may lead to deterioration of photoluminescence (PL) and electrical properties.

[0006] The technology disclosed in Patent Document 1 suppresses surface roughness, which is one of the surface morphologies of a substrate, but it does not disclose to what extent the surface roughness is suppressed over the entire substrate.

[0007] This invention was made to solve the above-mentioned problems and aims to provide an indium phosphide substrate and a semiconductor epitaxial wafer with good surface morphology. [Means for solving the problem]

[0008] The above problems are solved by embodiments of the present invention, which are specified as follows. (1) An indium phosphide substrate containing at least one of S, Fe, Zn, and Sn as a dopant, with a haze of 1.0 ppm or less. (2) The indium phosphide substrate according to (1), wherein the dopant is S and the haze is 0.4 to 1.0 ppm. (3) The indium phosphide substrate according to (1), wherein the dopant is Fe and the haze is 0.5 to 0.8 ppm. (4) The indium phosphide substrate according to (1), wherein the dopant is Zn and the haze is 0.5 to 0.9 ppm. (5) The indium phosphide substrate according to (1), wherein the dopant is Sn and the haze is 0.3 to 0.8 ppm. A semiconductor epitaxial wafer having an indium phosphide substrate as described in any of (6)(1) to (5), and an epitaxial crystal layer provided on the main surface of the indium phosphide substrate. (7) A process of grinding an indium phosphide ingot into a cylinder, A step of cutting a wafer having a main surface and a back surface from the ground indium phosphide ingot, The process involves performing double-sided etching (primary etching) on ​​the wafer, After the initial etching, the outer edge of the wafer is chamfered, followed by a step of rough polishing both sides of the wafer. A step of performing double-sided etching (secondary etching) on the wafer after rough grinding; A step of polishing both surfaces of the wafer after the secondary etching; The main surface of the wafer after the double-sided polishing is mirror-polished with a processing pressure of 300 to 500 g / cm 2 ; A method for manufacturing an indium phosphide substrate having the above steps.

Advantages of the Invention

[0009] According to an embodiment of the present invention, an indium phosphide substrate and a semiconductor epitaxial wafer with good surface morphology can be provided.

Brief Description of the Drawings

[0010] [Figure 1] It is a graph plotting the haze numerical values corresponding to the sample numbers according to Examples 1 to 3. [Figure 2] It is a graph plotting the haze numerical values corresponding to the sample numbers according to Examples 1, 4 to 6.

Modes for Carrying Out the Invention

[0011] Next, the modes for carrying out the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and modifications and improvements in design can be appropriately made based on the ordinary knowledge of those skilled in the art without departing from the spirit of the present invention.

[0012] 〔Indium Phosphide Substrate〕 Hereinafter, the configuration of the indium phosphide substrate of the present embodiment will be described. The indium phosphide (InP) substrate of the present embodiment includes a substrate surface (main surface), a substrate back surface, and an edge portion. The edge portion may have an orientation flat (OF) indicating the crystal orientation and an index flat (IF) for distinguishing the main surface and the back surface of the substrate.

[0013] The main surface of the indium phosphide substrate of the present embodiment can be a surface for forming an epitaxial crystal layer. The surface for forming an epitaxial crystal layer is the surface on which epitaxial growth is actually carried out when the indium phosphide substrate of the present embodiment is used as a substrate for epitaxial growth for the formation of a semiconductor element structure.

[0014] The diameter of the main surface of the indium phosphide substrate of the present embodiment is not particularly limited and may be, for example, 70 to 160 mm. More specifically, the diameter may be 3 inches (75 to 76.2 mm), 4 inches (100 to 101.6 mm), or 6 inches (150 to 152.4 mm). The planar shape of the indium phosphide substrate may be circular or rectangular such as a square.

[0015] The thickness of the indium phosphide substrate of the present embodiment is not particularly limited, but for example, it is preferably 300 to 900 μm, and more preferably 300 to 700 μm. Particularly when the diameter (aperture) of the indium phosphide substrate is large, if the thickness of the indium phosphide substrate is less than 300 μm, there is a risk of cracking, and if it exceeds 900 μm, there may be a problem that the base crystal becomes wasted.

[0016] The indium phosphide substrate of the present embodiment contains at least one of S (sulfur), Fe (iron), Zn (zinc), and Sn (tin) as a dopant (impurity). Further, the indium phosphide substrate of the present embodiment contains S as a dopant such that the carrier concentration is 1×10 16 cm -3 or more and 1×10 19 cm -3 or less, Fe such that the resistivity is 1×10 5 Ωcm or more and 1×10 8 Ωcm or less, Zn such that the carrier concentration is 1×10 16 cm -3 or more and 1×10 19 cm -3 or less, and Sn such that the carrier concentration is 1×10 16 cm -3 or more and 1×1019 cm -3 It may include the following:

[0017] The indium phosphide substrate in this embodiment has a haze controlled to 1.0 ppm or less. Here, the surface roughness of the substrate and the haze are different concepts, and different characteristics are evaluated for each. First, surface roughness is a parameter used to evaluate the surface irregularities of an object. It is quantitatively evaluated by analyzing the wavelength components of the surface and using specific parameters (e.g., Ra and Rz). Furthermore, the surface roughness of a substrate is generally evaluated locally using an atomic force microscope (AFM). However, while AFM can evaluate the surface roughness of a substrate, it cannot evaluate fine particles on the substrate surface because, due to the principle of measurement, they do not contribute to the surface roughness. In contrast, substrate haze evaluates the entire surface of the substrate. Substrate haze is generally defined as the value obtained by dividing the intensity of scattered light obtained when light is incident on the substrate surface from a predetermined light source by the intensity of the incident light from the light source. In the embodiment of the present invention, the reflectance of the substrate is R0, and the root mean square roughness (R ms If we represent σ as the value of the light and λ as the wavelength of the incident light, the haze can be expressed by the following equation (1). Since the haze includes parameters of the substrate's reflectance and surface roughness, by expressing it by equation (1), we can evaluate not only the surface roughness but also the fine particles that affect the reflectance. Hayes = R0(4πσ / λ) 2 ×10 6 ...(1)

[0018] Indium phosphide substrates are epitaxially grown using methods such as molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). When performing heteroepitaxial growth of materials such as AlInGaAs and InGaAsP on an indium phosphide substrate, if the surface morphology is uniform across the entire substrate surface (excluding the vicinity of the edges), it becomes easier to grow a uniform epitaxial layer, improving photoluminescence (PL) and electrical properties. Specifically, electrical properties are improved by reducing variations in the peak wavelength and emission intensity of PL within the substrate surface of the epitaxial layer, and by reducing variations in electrical resistivity within the surface, such as the introduction of defects in the epitaxial layer due to surface roughness and an increase in electrical resistivity due to surface particles. In this embodiment, as an improvement to the overall morphology (surface morphology) of the important substrate surface, the haze is controlled in order to control not only the low surface roughness and uniformity of the entire substrate surface, but also all elements of surface properties such as the low number of particles.

[0019] Indium phosphide substrates with haze controlled to 1.0 ppm or less exhibit good surface regularity and surface morphology, resulting in a uniform film after epitaxial growth and excellent photoluminescence (PL) and electrical properties. Furthermore, haze also indicates the proportion of fine particles; indium phosphide substrates with haze controlled to 1.0 ppm or less have fewer fine particles, good surface morphology, and are less prone to surface defects in the film after epitaxial growth, thus improving yield. In this embodiment, the indium phosphide substrate preferably has a haze of 0.7 ppm or less, and more preferably 0.5 ppm or less.

[0020] One example of equipment used for measuring haze is the Tencor Surfscan 6220 surface evaluation system. At this time, the entire substrate surface is measured, excluding the area near the edge (for example, a 3mm wide area from the edge).

[0021] In this embodiment, when the dopant is S, the indium phosphide substrate preferably has a haze of 0.4 to 1.0 ppm, and more preferably a haze of 0.4 to 0.5 ppm.

[0022] In this embodiment, when the dopant is Fe, the indium phosphide substrate preferably has a haze of 0.5 to 0.8 ppm, and more preferably a haze of 0.5 to 0.6 ppm.

[0023] In this embodiment, when the dopant is Zn, the indium phosphide substrate preferably has a haze of 0.5 to 0.9 ppm, and more preferably a haze of 0.5 to 0.6 ppm.

[0024] In this embodiment, when the dopant is Sn, the indium phosphide substrate preferably has a haze of 0.3 to 0.8 ppm, and more preferably a haze of 0.3 to 0.4 ppm.

[0025] [Method for manufacturing indium phosphide substrates] Next, a method for producing an indium phosphide substrate according to an embodiment of the present invention will be described. As a method for manufacturing an indium phosphide substrate, first, an ingot of indium phosphide is prepared by a known method. Next, the indium phosphide ingot is ground into a cylinder. At this time, an orientation flat (OF) and an index flat (IF) may be formed at predetermined positions on the outer circumference of the wafer. Next, wafers having a main surface and a back surface are cut from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot are cut along predetermined crystal planes using a wire saw or the like, and multiple wafers are cut to a thickness of, for example, 400 to 1000 μm.

[0026] In the wafer cutting process, it is preferable to continuously feed new wire by moving the wire back and forth horizontally, while simultaneously moving the stage on which the indium phosphide ingot is placed vertically toward the wire.

[0027] Next, in order to remove the processed altered layer generated during the wire saw cutting process, the cut wafer is etched on both sides with a predetermined etching solution (primary etching). The wafer can be etched by immersing the entire wafer in the etching solution. As the etching solution, for example, a mixed solution of 85% by mass of phosphoric acid aqueous solution and 30% by mass of hydrogen peroxide aqueous solution can be used.

[0028] Next, the outer edge of the wafer is chamfered to control it to a predetermined diameter. After chamfering, both sides of the wafer are roughly polished. This rough polishing process is also called the lapping process, and by polishing with a predetermined abrasive, irregularities on the wafer surface are removed while maintaining the flatness of the wafer.

[0029] Next, the wafer is etched on both sides with a predetermined etching solution (secondary etching). The wafer can be etched by immersing the entire wafer in the etching solution. As the etching solution, for example, a mixed solution of 85% by mass of phosphoric acid aqueous solution, 30% by mass of hydrogen peroxide solution, and ultrapure water can be used.

[0030] Next, one or both sides of the wafer are polished. This step is for removing any irregularities that could not be removed in the lapping step described above, and from a productivity standpoint, it is preferable to polish both sides of multiple wafers simultaneously. In order to uniformly remove irregularities across the surface of all wafers being polished simultaneously, it is preferable to supply sufficient polishing fluid to the wafer from multiple polishing fluid supply ports so that the polishing fluid can sufficiently penetrate the entire polishing pads provided on the upper and lower polishing plates when polishing both sides of the wafer with the upper and lower polishing plates.

[0031] Next, the main surface of the wafer is polished to a mirror finish using a polishing compound for mirror polishing (mirror polishing). For this mirror polishing, for example, a Speedfam 36GPAW single-sided polishing machine can be used. At this time, the processing pressure for mirror polishing should be 300 to 500 g / cm². 2 The rotational speed for mirror polishing is controlled to 40-80 rpm. The processing pressure for mirror polishing is 300-500 g / cm². 2 By doing so, the haze of the resulting indium phosphide substrate can be controlled to 1.0 ppm or less, or to 0.3-1.0 ppm. In addition, the occurrence of chipping in the indium phosphide substrate can be suppressed.

[0032] Next, the indium phosphide substrate according to the embodiment of the present invention is manufactured by cleaning. Alternatively, the indium phosphide substrate may be manufactured by cleaning after the mirror finishing described above.

[0033] [Semiconductor epitaxial wafers] An epitaxial crystalline layer can be formed on the main surface of an indium phosphide substrate according to an embodiment of the present invention by epitaxially growing a semiconductor thin film using a known method, thereby producing a semiconductor epitaxial wafer. As an example of such epitaxial growth, an HEMT structure may be formed on the main surface of the indium phosphide substrate by epitaxially growing an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, and an InP electron supply layer. When producing a semiconductor epitaxial wafer having such a HEMT structure, generally, an indium phosphide substrate with a mirror finish is subjected to etching with an etching solution such as sulfuric acid / hydrogen peroxide to remove impurities such as silicon (Si) adhering to the substrate surface. With the back surface of the indium phosphide substrate after this etching treatment in contact with a susceptor and supported, an epitaxial film is formed on the main surface of the indium phosphide substrate by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).

[0034] As described above, the semiconductor epitaxial wafer according to the embodiment of the present invention is fabricated using the indium phosphide substrate according to this embodiment, which has good surface morphology. This facilitates uniform epitaxial growth and improves photoluminescence (PL) and electrical properties. [Examples]

[0035] The following examples are provided to better understand the present invention and its advantages, but the present invention is not limited to these examples.

[0036] (Example 1) First, as a Dopant, S is 1 x 10 16 cm -3 An ingot of indium phosphide containing [a specific concentration] was prepared. Next, the indium phosphide ingot was ground into a cylinder. Next, wafers with a main surface and a back surface were cut from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot were cut along predetermined crystal planes using a wire saw or the like, and multiple wafers were cut to a thickness of 0.84 mm.

[0037] In the wafer cutting process, a wire was continuously fed by moving it back and forth horizontally, while a stage carrying an indium phosphide ingot was moved vertically toward the wire.

[0038] Next, in order to remove the processed layer that occurred during the wire saw cutting process, the cut wafer was etched from both sides to a total thickness of 15 μm with a mixed solution of 85% by mass phosphoric acid aqueous solution and 30% by mass hydrogen peroxide aqueous solution (primary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0039] Next, the outer edge of the wafer was chamfered to control the diameter to 50 mm or more. After chamfering, both sides of the wafer were roughly polished (lapped). Specifically, 150 g / cm² 2While applying pressure, a total thickness of 120 μm was removed from both the front and back surfaces of the wafer by lapping.

[0040] Next, the wafer was etched from both sides to a total thickness of 7 μm using a mixed solution of 85% by mass phosphoric acid aqueous solution, 30% by mass hydrogen peroxide solution, and ultrapure water (secondary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0041] Next, both sides of the wafer were polished. During this double-sided polishing process, sufficient polishing fluid was supplied to the wafer from multiple supply ports so that the polishing fluid could thoroughly penetrate the entire polishing pads on the upper and lower polishing plates.

[0042] Next, the main surface of the wafer was polished to a mirror finish using a polishing compound for mirror polishing. A Speedfam 36GPAW single-sided polishing machine was used for this mirror polishing. The processing pressure for mirror polishing was set to 300 g / cm². 2 The rotation speed for mirror polishing was controlled to 50 rpm. Next, a sample of indium phosphide substrate with a diameter of 76.2 mm was prepared by cleaning. Furthermore, a total of six samples, No. 1 to No. 6, were prepared under the same conditions.

[0043] (Example 2) The processing pressure used when mirror-polishing the main surface of the wafer is 400 g / cm². 2 A sample of indium phosphide substrate was prepared under the same conditions as in Example 1, except as otherwise noted.

[0044] (Example 3) The processing pressure used when mirror-polishing the main surface of the wafer is 500 g / cm². 2 A sample of indium phosphide substrate was prepared under the same conditions as in Example 1, except as otherwise noted.

[0045] (Example 4) As a Dopant, Sn is 1 x 10 16 cm -3A sample of an indium phosphide substrate was prepared under the same conditions as in Example 1, except that an ingot containing indium phosphide at the specified concentration was prepared.

[0046] (Example 5) As a dopant, Fe is 1 × 10 16 cm -3 A sample of an indium phosphide substrate was prepared under the same conditions as in Example 1, except that an ingot containing indium phosphide at the specified concentration was prepared.

[0047] (Example 6) As a dopant, Zn is 1 × 10 16 cm -3 A sample of an indium phosphide substrate was prepared under the same conditions as in Example 1, except that an ingot containing indium phosphide at the specified concentration was prepared.

[0048] (Hayes's evaluation) For measuring haze, we prepared a surface evaluation system (Surfscan 6220) manufactured by Tencor. Next, for each indium phosphide substrate sample from Examples 1 to 6 (No. 1 to No. 6), the entire substrate surface, excluding the area near the edge (a 3 mm wide region from the edge), was measured using the surface evaluation device (Surfscan6220) to evaluate the haze. For the measurement, Haze Suppression was set to 0 ppm, Gain to 7, and Haze Range to 0.0049 to 2.5 ppm, and only haze was measured.

[0049] The manufacturing conditions and evaluation results described above are shown in Table 1. Figure 1 is a graph plotting the haze values ​​corresponding to the sample numbers for Examples 1 to 3. Figure 2 is a graph plotting the haze values ​​corresponding to the sample numbers for Examples 1, 4 to 6.

[0050] [Table 1]

[0051] (Consideration) Examples 1 to 6 all contained at least one of S, Fe, Zn, and Sn as a dopant, and the haze was 0.3 to 1.0 ppm. Therefore, it was confirmed that indium phosphide substrates with good surface morphology were obtained.

[0052] According to one embodiment of the present invention, it is possible to provide an indium phosphide substrate and a semiconductor epitaxial wafer with good surface morphology. Since the indium phosphide substrate is a material used for light-emitting and receiving elements for optical communications, one embodiment of the present invention may contribute to the advancement of optical communications technology. For this reason, one embodiment of the present invention may contribute to Goal 9 of the United Nations Sustainable Development Goals (SDGs), "Build resilient infrastructure, promote inclusive and sustainable industrialization and foster innovation."

Claims

1. An indium phosphide substrate containing at least one of S, Fe, Zn, and Sn as a dopant, with a haze of 1.0 ppm or less.

2. The indium phosphide substrate according to claim 1, wherein the dopant is S and the haze is 0.4 to 1.0 ppm.

3. The indium phosphide substrate according to claim 1, wherein the dopant is Fe and the haze is 0.5 to 0.8 ppm.

4. The indium phosphide substrate according to claim 1, wherein the dopant is Zn and the haze is 0.5 to 0.9 ppm.

5. The indium phosphide substrate according to claim 1, wherein the dopant is Sn and the haze is 0.3 to 0.8 ppm.

6. A semiconductor epitaxial wafer comprising an indium phosphide substrate according to any one of claims 1 to 5, and an epitaxial crystal layer provided on the main surface of the indium phosphide substrate.

7. The process of grinding an indium phosphide ingot into a cylinder, A step of cutting a wafer having a main surface and a back surface from the ground indium phosphide ingot, The process involves performing double-sided etching (primary etching) on ​​the wafer, After the initial etching, the outer edge of the wafer is chamfered, followed by a step of rough polishing both sides of the wafer. The process involves etching both sides (secondary etching) the wafer after the rough polishing, The process of polishing both sides of the wafer after secondary etching, The main surface of the wafer after double-sided polishing is processed under a pressure of 300 to 500 g / cm². 2 The process involves mirror polishing, A method for manufacturing an indium phosphide substrate, comprising the characteristics of the indium phosphide substrate.

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