Semiconductor package with electrodes

Abstract

The present invention provides a semiconductor package having electrodes and a method for forming the same. [Solution] The semiconductor package includes a wiring structure 21, which includes a first insulating layer 23, a conductive pad 48 on the first insulating layer, a second insulating layer 25 on the conductive pad, through holes that penetrate the second insulating layer and are superimposed on the conductive pad, a protruding pattern 57 placed on the conductive pad within the through holes, and a UBM (Under Bump Metallurgy) layer 63 that contacts the upper and side surfaces of the protruding pattern and is connected to the conductive pad. A semiconductor chip 90 connected to the UBM layer is placed on the wiring structure.

Description

Technical Field

[0001] Relates to a semiconductor package having electrodes and a method of forming the same.

Background Art

[0002] In response to the trend of making semiconductor packages thinner, lighter, shorter, and smaller, the technology of mounting semiconductor chips on a substrate including wiring has become increasingly difficult. A semiconductor chip can be electrically connected to wiring in the substrate via a conductive interconnect. The bond between the conductive interconnect and an adjacent component affects the electrical characteristics and reliability of the semiconductor package.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure provide a semiconductor package having electrodes and a method of forming the same.

Means for Solving the Problems

[0004] A semiconductor package according to an embodiment of the present disclosure may include a wiring structure. The wiring structure may include a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a through hole penetrating the second insulating layer and overlapping the conductive pad, a protruding pattern disposed on the conductive pad within the through hole, and a UBM (Under Bump Metallurgy) layer contacting upper and side surfaces of the protruding pattern and connected to the conductive pad. A semiconductor chip connected to the UBM layer may be disposed on the wiring structure.

[0005] A semiconductor package according to one embodiment of the present disclosure may include a wiring structure. The wiring structure may include a first insulating layer, a plurality of conductive pads on the first insulating layer, a second insulating layer on the plurality of conductive pads, a plurality of through holes penetrating the second insulating layer and superimposed on the electrodes of the conductive pads, a plurality of protruding patterns disposed on the plurality of conductive pads within the plurality of through holes, and a plurality of UBM layers in contact with the upper and side surfaces of each of the plurality of protruding patterns and connected to the plurality of conductive pads. First and second semiconductor chips may be disposed on the wiring structure. A sealing layer covering the first and second semiconductor chips may be disposed on the wiring structure.

[0006] A semiconductor package according to one embodiment of the present disclosure may include a conductive pad on a first insulating layer. A second insulating layer may be disposed on the conductive pad. A through-hole may be disposed superimposed on the conductive pad, penetrating the second insulating layer. A projection pattern having a horizontal width smaller than the through-hole may be disposed on the conductive pad within the through-hole. A UBM layer having a horizontal width larger than the through-hole may be disposed in contact with the upper and side surfaces of the projection pattern. The upper surface of the UBM layer may have a recessed region superimposed between the projection pattern and the second insulating layer. A semiconductor chip may be disposed on the UBM layer. [Effects of the Invention]

[0007] According to embodiments of this disclosure, a semiconductor package having electrodes and a method for forming the same can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0009] [Figure 2] This is a partial diagram illustrating a portion of Figure 1.

[0010] [Figure 3] This is a cross-sectional view illustrating a part of the configuration of a semiconductor package according to an embodiment of the present disclosure.

[0011] [Figure 4] This is a cross-sectional view illustrating a part of the configuration of a semiconductor package according to an embodiment of the present disclosure.

[0012] [Figure 5] This is a perspective view illustrating some of the configurations of a semiconductor package according to embodiments of the present disclosure. [Figure 6] This is a perspective view illustrating some of the configurations of a semiconductor package according to embodiments of the present disclosure.

[0013] [Figure 7] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. [Figure 8] This is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0014] [Figure 9] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 10] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 11] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 12] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 13] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 14] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 15] This is a cross-sectional view illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. [Figure 16] A cross-sectional view for explaining a method of forming a semiconductor package according to an embodiment of the present disclosure. [Figure 17] A cross-sectional view for explaining a method of forming a semiconductor package according to an embodiment of the present disclosure. [Figure 18] A cross-sectional view for explaining a method of forming a semiconductor package according to an embodiment of the present disclosure. [Figure 19] A cross-sectional view for explaining a method of forming a semiconductor package according to an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0015] Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples for explaining the concepts disclosed in this specification. Embodiments or exemplifications according to the concepts of the present disclosure can be implemented in various forms, and the scope of the present disclosure is not limited to the embodiments or exemplifications described in this specification.

[0016] The same hatching shown throughout the drawings indicates corresponding or identical regions in the drawings and does not indicate the materials associated with those regions.

[0017] When an element is described as being "connected" or "coupled" to another element, the element may be directly connected or directly coupled, or may be connected or coupled through an intermediate element between the elements. When two elements are described as being "directly connected" or "directly coupled", one element is directly connected or directly coupled to the other element without an intermediate element between the two elements.

[0018] When an element is described as being "above" or "below" another element, those elements may be in direct contact with each other, or an intermediate element may be disposed between the elements.

[0019] The terms “vertical,” “horizontal,” “top,” “bottom,” “up,” “down,” “top,” “bottom,” “front,” “back,” “side,” “left and right,” “column,” “row,” “level,” and other terms indicating relative spatial relationships or directions are used solely for the purpose of facilitating the description or reference of the drawings, and are not otherwise limited. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of this specification.

[0020] Terms such as "first" and "second" are used to distinguish elements from one another and do not imply the size, order, priority, quantity, or importance of the elements. For example, in one embodiment, the first element may be referred to as the second element, and in another embodiment, the second element may be referred to as the first element.

[0021] In this specification, when an element included in an embodiment is described in the singular, that element may be interpreted as including multiple elements that perform the same or similar functions.

[0022] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 is a partial view illustrating a portion of Figure 110. Figures 3 and 4 are cross-sectional views illustrating a portion of the configuration of a semiconductor package according to an embodiment of the present disclosure. Figures 5 and 6 are perspective views illustrating a portion of the configuration of a semiconductor package according to an embodiment of the present disclosure.

[0023] Referring to Figure 1, the semiconductor package according to an embodiment of the present disclosure may include a wiring structure 21, a first semiconductor chip 90, a base chip 310, core chips 320, 330, 340, a top chip 350, an external solder interconnection 572, a first sealing layer 591, and a second sealing layer 592.

[0024] The wiring structure 21 may include a first insulating layer 23, a second insulating layer 25, a third insulating layer 27, a first via electrode 31, a first horizontal electrode 38, a second via electrode 41, a conductive pad 48, a second horizontal electrode 48', a protruding pattern 57, an Under Bump Metallurgy (UBM) layer 63, and an external electrode 589. In one embodiment, the wiring structure 21 may include a Si-Less Interposer (SLIP) or Redistribution Layer (RDL) substrate.

[0025] The first insulating layer 23, the second insulating layer 25, and the third insulating layer 27 can be sequentially laminated. The first via electrode 31 can penetrate the first insulating layer 23 vertically. The first horizontal electrode 38 can be positioned between the first insulating layer 23 and the second insulating layer 25. The first via electrode 31 can be in contact with the side surface of the first horizontal electrode 38.

[0026] The second via electrode 41 may penetrate the second insulating layer 25 vertically and contact the first horizontal electrode 38. The conductive pad 48 and the second horizontal electrode 48' may be positioned between the second insulating layer 25 and the third insulating layer 27. The second horizontal electrode 48' may contact the second via electrode 41. The conductive pad 48 may contact the side surface of the second horizontal electrode 48'.

[0027] The protruding pattern 57 may be placed on the conductive pad 48. The UBM layer 63 may be placed on the conductive pad 48 and the protruding pattern 57. The first solder interconnection 72 may be placed on the UBM layer 63. The UBM layer 63 and the protruding pattern 57 will be described again with reference to Figures 2 to 6.

[0028] The first semiconductor chip 90 may be mounted on the wiring structure 21. The first semiconductor chip 90 may include a first solder interconnection 72, chip electrodes 89, a first substrate 91, and a first circuit layer 93. The first circuit layer 93 may be placed on the underside of the first substrate 91. Chip electrodes 89 may be placed on the first circuit layer 93. The first solder interconnection 72 may be placed between the UBM layer 63 and the chip electrodes 89.

[0029] The base chip 310, core chips 320, 330, 340, top chip 350, and first encapsulation layer 591 can constitute a multi-chip package. In one embodiment, the base chip 310, core chips 320, 330, 340, top chip 350, and first encapsulation layer 591 may be an HBM (High Bandwidth Memory) package. The base chip 310 may include a base substrate 311, a base circuit layer 317, and a through-base electrode 319. The base circuit layer 317 may be located on the underside of the base substrate 311. The through-base electrode 319 may penetrate the base substrate 311 vertically and be connected to the base circuit layer 317.

[0030] The core chips 320, 330, and 340 may include a first core chip 320, a second core chip 330, and a third core chip 340. The first core chip 320 may include a first core substrate 321, a first core circuit layer 327, and a first through-core electrode 329. The first core circuit layer 327 may be located on the underside of the first core substrate 321. The first through-core electrode 329 may penetrate the first core substrate 321 vertically and be connected to the first core circuit layer 327.

[0031] The second core chip 330 may include a second core substrate 331, a second core circuit layer 337, and a second through-core electrode 339. The second core circuit layer 337 may be located on the underside of the second core substrate 331. The second through-core electrode 339 may penetrate the second core substrate 331 perpendicularly and be connected to the second core circuit layer 337.

[0032] The third core chip 340 may include a third core substrate 341, a third core circuit layer 347, and a third through-core electrode 349. The third core circuit layer 347 may be located on the underside of the third core substrate 341. The third through-core electrode 349 may penetrate the third core substrate 341 perpendicularly and be connected to the third core circuit layer 347.

[0033] The top chip 350 may include a top substrate 351 and a top circuit layer 357. The top circuit layer 357 may be located on the underside of the top substrate 351.

[0034] Core chips 320, 330, and 340 can be sequentially stacked on the base chip 310. The top chip 350 can be stacked on the uppermost core chip. In one embodiment, the top chip 350 can be stacked on the third core chip 340. The first sealing layer 591 can cover the base chip 310, the core chips 320, 330, 340, and the top chip 350. The first sealing layer 591 can extend between the base chip 310, the core chips 320, 330, 340, and the top chip 350. The upper surface of the first sealing layer 591 and the upper surface of the top chip 350 can be substantially the same plane. In one embodiment, one or more additional core chips can be further stacked between the base chip 310 and the first core chip 320, between the core chips 320, 330, and 340, and between the third core chip 340 and the top chip 350.

[0035] The base chip 310 is placed on a base substrate 311 and may include a base back electrode 416 superimposed on a base through electrode 319. A first core front electrode 429 may be placed on a first core circuit layer 327. A second solder interconnection 472 may be placed between the base back electrode 416 and the first core front electrode 429.

[0036] In one embodiment, the second solder interconnection 472 may be omitted. The first core front electrode 429 may be in contact with the base back electrode 416. The base chip 310, core chips 320, 330, 340, and top chip 350 may be connected using hybrid bonding technology.

[0037] The first core chip 320 may be placed on the first core substrate 321 and may include a first core back electrode 426 superimposed on the first core through electrode 329. A second core front electrode 439 may be placed on the second core circuit layer 337. A second solder interconnection 472 may be placed between the first core back electrode 426 and the second core front electrode 439.

[0038] The second core chip 330 may be placed on the second core substrate 331 and may include a second core back electrode 436 superimposed on the second core through electrode 339. A third core front electrode 449 may be placed on the third core circuit layer 347. A second solder interconnection 472 may be placed between the second core back electrode 436 and the third core front electrode 449.

[0039] The third core chip 340 may be placed on the third core substrate 341 and may include a third core back electrode 446 superimposed on the third core through electrode 349. A top front electrode 459 may be placed on the top circuit layer 357. A second solder interconnection 472 may be placed between the third core back electrode 446 and the top front electrode 459.

[0040] The base chip 310 may include a base chip electrode 189 placed on the base circuit layer 317. A third solder interconnection 172 may be placed between the UBM layer 63 and the base chip electrode 189.

[0041] The second encapsulation layer 592 can cover the wiring structure 21, the first semiconductor chip 90, the base chip 310, the core chips 320, 330, 340, the top chip 350, and the first encapsulation layer 591. The second encapsulation layer 592 can extend between the wiring structure 21 and the first semiconductor chip 90, and between the wiring structure 21 and the base chip 310. In one embodiment, the second encapsulation layer 592 can be in direct contact with the sides of the UBM layer 63, the first solder interconnection 72, the chip electrode 89, the third solder interconnection 172, and the base chip electrode 189.

[0042] The wiring structure 21 may include an external electrode 589 positioned on its lower surface. The external electrode 589 may be superimposed on the first via electrode 31. An external solder interconnection 572 may be positioned on the external electrode 589.

[0043] In one embodiment, the first semiconductor chip 90 may include a graphics processing unit, a controller, an application processor, a microprocessor, or a combination thereof. The base chip 310 may include logic circuits. In one embodiment, the base chip 310 may include through-silicon electrodes such as a through-base electrode 319. The base chip 310 can play a role in controlling the memory contained in the core chips 320, 330, and 340. The base chip 310 can perform calculations. The core chips 320, 330, 340 and the top chip 350 may include volatile memory, non-volatile memory, or a combination thereof. The top chip 350 may include a dummy chip.

[0044] Referring to Figure 2, the conductive pad 48 and the second horizontal electrode 48' may be placed on the second insulating layer 25. The conductive pad 48 may be in contact with the side surface of the second horizontal electrode 48'. The conductive pad 48 and the second horizontal electrode 48' may include sequentially laminated first barrier layers 43, 43', first seed layers 44, 44', and first conductive layers 45, 45'. In one embodiment, the first seed layers 44, 44' may be omitted. If the first seed layers 44, 44' and the first conductive layers 45, 45' are made of the same material, the boundary between the first seed layers 44, 44' and the first conductive layers 45, 45' may be difficult to distinguish. The third insulating layer 27 may cover the second insulating layer 25, the conductive pad 48, and the second horizontal electrode 48'. Through holes 27H may be provided that penetrate vertically through the third insulating layer 27. The through-hole 27H can be superimposed on the conductive pad 48.

[0045] A second barrier layer 53 may be provided to cover the bottom and side walls of the through-hole 27H and extend over the third insulating layer 27. The second barrier layer 53 may be in contact with the first conductive layer 45 of the conductive pad 48. The second barrier layer 53 may be in contact with the side and top surfaces of the third insulating layer 27. A second seed layer 54 may be provided on the second barrier layer 53.

[0046] A protruding pattern 57 may be placed on the second seed layer 54. The protruding pattern 57 may have a horizontal width smaller than the through hole 27H. The protruding pattern 57 may be superimposed on the center of the through hole 27H. The uppermost surface of the protruding pattern 57 may be at substantially the same level as the uppermost surface of the third insulating layer 27, or at a lower level than the uppermost surface of the third insulating layer 27.

[0047] A UBM layer 63 covering the protruding pattern 57 may be placed on the second seed layer 54. The UBM layer 63 may have a horizontal width greater than the through-hole 27H. The UBM layer 63 may completely fill the through-hole 27H and extend onto the third insulating layer 27. The UBM layer 63 may be in contact with the top and side surfaces of the protruding pattern 57. The UBM layer 63 may be superimposed on the conductive pad 48. The top surface of the UBM layer 63 may be positioned at a higher level than the top surface of the third insulating layer 27.

[0048] The base chip 310 may include a base substrate 311, a base circuit layer 317, an insulating spacer 318, and a base through-electrode 319. The base circuit layer 317 may be located on the underside of the base substrate 311. The base circuit layer 317 may include a plurality of conductive patterns 313 and a plurality of circuit insulating layers 315. The plurality of conductive patterns 313 may include chip pads. The base through-electrode 319 may penetrate the base substrate 311 vertically and be connected to the conductive patterns 313. The insulating spacer 318 may surround the sides of the base through-electrode 319. The base through-electrode 319 may be insulated from the base substrate 311 by the insulating spacer 318.

[0049] The base chip 310 may include a base chip electrode 189 positioned on the underside of the base circuit layer 317. The base chip electrode 189 may penetrate the circuit insulating layer 315 and be connected to the conductive pattern 313. In one embodiment, the base chip electrode 189 may include sequentially stacked third barrier layer 83, third seed layer 84, second conductive layer 85, and third conductive layer 88.

[0050] A third solder interconnection 172 may be placed between the UBM layer 63 and the chip electrode 89. A first intermetallic layer (IM1) may be placed between the UBM layer 63 and the third solder interconnection 172. A second intermetallic layer IM2 may be placed between the third solder interconnection 172 and the base chip electrode 189.

[0051] According to embodiments of this disclosure, the protruding pattern 57 can serve to mitigate steps on the upper surface of the UBM layer 63. The protruding pattern 57 can minimize surface irregularities of the UBM layer 63. The protruding pattern 57 can form the upper surface of the central region of the UBM layer 63 at the same or similar level as the upper surface of the edge region of the UBM layer 63. Defects such as voids can be prevented from occurring between the third solder interconnection 172 and the UBM layer 63. The coupling between the third solder interconnection 172 and the UBM layer 63 can be strengthened.

[0052] In one embodiment, each of the first circuit layer (93 in Figure 1), the first core circuit layer (327 in Figure 1), the second core circuit layer (337 in Figure 1), the third core circuit layer (347 in Figure 1), and the top circuit layer (357 in Figure 1) may include substantially the same configuration as the plurality of conductive patterns 313 and the plurality of circuit insulating layers 315.

[0053] Referring to Figure 3, a conductive pad 48 and a second horizontal electrode 48' may be placed on a second insulating layer 25. A third insulating layer 27 may be placed on the second insulating layer 25, covering the conductive pad 48 and the second horizontal electrode 48'. The conductive pad 48 and the second horizontal electrode 48' may include sequentially laminated first barrier layers 43, 43', first seed layers 44, 44', and first conductive layers 45, 45'.

[0054] A through-hole 27H may be provided that penetrates the third insulating layer 27 vertically. The lower part of the through-hole 27H may have a smaller horizontal width than the upper part. The cross-section of the through-hole 27H may include an inverted trapezoid. The through-hole 27H may have inclined side walls. Within the through-hole 27H, the third insulating layer 27 may have inclined sides.

[0055] A second barrier layer 53 may be provided that conformally covers the bottom and side walls of the through-hole 27H and extends onto the third insulating layer 27. The second barrier layer 53 may be in contact with the conductive pad 48. The second barrier layer 53 may be in contact with the side and top surfaces of the third insulating layer 27. The second barrier layer 53 may cover the inclined side surfaces of the third insulating layer 27. A second seed layer 54 may be provided on the second barrier layer 53.

[0056] In one embodiment, the second barrier layer 53 may be positioned between the conductive pad 48 and the protruding pattern 57. The second barrier layer 53 may extend over the conductive pad 48 between the third insulating layer 27 and the protruding pattern 57. The second barrier layer 53 may extend over the side and top surfaces of the third insulating layer 27. The second barrier layer 53 may be superimposed on the conductive pad 48.

[0057] A protruding pattern 57 may be positioned on the second seed layer 54 within the through-hole 27H. The protruding pattern 57 may have a horizontal width smaller than the through-hole 27H. The protruding pattern 57 may be superimposed on the center of the through-hole 27H. The protruding pattern 57 may have a horizontal width smaller than the second seed layer 54. The protruding pattern 57 may have a horizontal width smaller than the second barrier layer 53. The uppermost surface of the protruding pattern 57 may be positioned at substantially the same level as the uppermost surface of the third insulating layer 27, or at a lower level than the uppermost surface of the third insulating layer 27.

[0058] A UBM layer 63 can be placed over the third insulating layer 27, filling the through-hole 27H. The horizontal width of the UBM layer 63 may be greater than the horizontal width of the through-hole 27H. The UBM layer 63 can cover the sides and top of the protruding pattern 57. The UBM layer 63 can fill the space between the sidewall of the through-hole 27H and the protruding pattern 57. The UBM layer 63 can be in contact with the second seed layer 54 between the sidewall of the through-hole 27H and the protruding pattern 57. The protruding pattern 57 can serve to mitigate any steps on the top surface of the UBM layer 63. The UBM layer 63 can have a flat top surface.

[0059] A capping layer 65 may be placed on the UBM layer 63. The capping layer 65 may have a thinner thickness than the UBM layer 63. The capping layer 65 can conformally cover the UBM layer 63. In one embodiment, the capping layer 65 may be omitted. A second barrier layer 53 and a second seed layer 54 may be placed between the conductive pad 48 and the protruding pattern 57, between the conductive pad 48 and the UBM layer 63, and between the third insulating layer 27 and the UBM layer 63.

[0060] In one embodiment, the UBM layer 63 may include a first portion 68A1, a second portion 68A2, and a third portion 68A3. The first portion 68A1 may be superimposed on the protruding pattern 57. The first portion 68A1 may be superimposed on the center of the through hole 27H. The second portion 68A2 may be superimposed between the third insulating layer 27 and the protruding pattern 57. The second portion 68A2 may not be superimposed on the third insulating layer 27. The second portion 68A2 may be continuous with the outside of the first portion 68A1. The third portion 68A3 may be superimposed on the third insulating layer 27. The third portion 68A3 may be continuous with the outside of the second portion 68A2. The second portion 68A2 may be positioned between the first portion 68A1 and the third portion 68A3. The upper surfaces of the first portion 68A1, the second portion 68A2, and the third portion 68A3 may be positioned at a higher level than the uppermost edge of the third insulating layer 27.

[0061] In one embodiment, the upper surfaces of the first portion 68A1, the second portion 68A2, and the third portion 68A3 can form substantially the same plane. The upper surfaces of the first portion 68A1, the second portion 68A2, and the third portion 68A3 can be positioned at substantially the same level.

[0062] Referring to Figure 4, the UBM layer 63 may include a first portion 68A1, a second portion 68A2, and a third portion 68A3. The upper surfaces of the first portion 68A1, the second portion 68A2, and the third portion 68A3 may be positioned at a higher level than the uppermost edge of the third insulating layer 27.

[0063] The upper surface of the first portion 68A1 may be positioned at substantially the same level as the upper surface of the third portion 68A3. The distance between the upper surface of the first portion 68A1 and the conductive pad 48 may be substantially equal to the distance between the upper surface of the third portion 68A3 and the conductive pad 48.

[0064] The upper surface of the second portion 68A2 may include a recessed area 68C. In one embodiment, the UBM layer 63 can be formed using an electroplating method. The process of forming the UBM layer 63 may include forming a nickel (Ni) layer in a substantially uniform proportion along the surface of the second seed layer 54 and the protruding pattern 57. The nickel layer formed by electroplating may be formed along the surface shape. The recessed area 68C may be formed in correspondence with the surface steps of the second seed layer 54 and the protruding pattern 57.

[0065] The through-hole 27H can penetrate the third insulating layer 27 vertically. The third portion 68A3 of the UBM layer 63 may be defined as a region superimposed on the third insulating layer 27. The first portion 68A1 of the UBM layer 63 may be defined as a region superimposed on the protruding pattern 57. The second portion 68A2 of the UBM layer 63 may be defined between the first portion 68A1 and the third portion 68A3. The second portion 68A2 does not superimpose on the third insulating layer 27 and the protruding pattern 57. A recessed region 68C may be formed in the center of the second portion 68A2. The recessed region 68C may be superimposed in the center between the third insulating layer 27 and the protruding pattern 57. The distance between the recessed region 68C and the conductive pad 48 may be shorter than the distance between the uppermost edge of the third portion 68A3 and the conductive pad 48. The distance between the recessed region 68C and the conductive pad 48 may be smaller than the distance between the uppermost end of the first portion 68A1 and the conductive pad 48.

[0066] The capping layer 65 can conformally cover the UBM layer 63. An undercut region UC1 may be placed between the third insulating layer 27 and the UBM layer 63. The second barrier layer 53 and the second seed layer 54 may have a narrower horizontal width than the UBM layer 63.

[0067] Referring to Figures 5 and 6, the protruding pattern 57 may have a horizontal width smaller than the through-hole 27H. The protruding pattern 57 may be superimposed on the center of the through-hole 27H. The protruding pattern 57 may have a cylindrical shape. The UBM layer 63 may cover the protruding pattern 57 and fill the through-hole 27H. The UBM layer 63 may have a horizontal width larger than the through-hole 27H. As described with reference to Figure 4, the upper surface of the UBM layer 63 may include a recessed region 68C formed in correspondence with the surface step between the second seed layer 54 and the protruding pattern 57. The recessed region 68C may be aligned along the space between the third insulating layer 27 and the protruding pattern 57. The recessed region 68C may be formed as a circular trench shape. In one embodiment, the recessed region 68C may be superimposed on the center between the third insulating layer 27 and the protruding pattern 57.

[0068] Figures 7 and 8 are cross-sectional views illustrating a semiconductor package according to an embodiment of the present disclosure.

[0069] Referring to Figure 7, the semiconductor package according to an embodiment of the present disclosure may include a wiring structure 21, a first semiconductor chip 90, a second semiconductor chip 97, an external solder interconnect 572, an external electrode 589, and a second sealing layer 592.

[0070] The first semiconductor chip 90 and the second semiconductor chip 97 can be mounted on the wiring structure 21. The second semiconductor chip 97 may include a semiconductor chip of a different type than the first semiconductor chip 90. The second semiconductor chip 97 may include a fourth solder interconnection 72', a second chip electrode 89', a second substrate 95, and a second circuit layer 96. The second circuit layer 96 may be placed on the underside of the second substrate 95. The second chip electrode 89' may be placed on the second circuit layer 96. The fourth solder interconnection 72' may be placed between the UBM layer 63 and the second chip electrode 89'. The second sealing layer 592 can cover the wiring structure 21, the first semiconductor chip 90, and the second semiconductor chip 97.

[0071] Referring to Figure 8, a semiconductor package according to an embodiment of the present disclosure may include a wiring structure 21, a base chip 310, core chips 320, 330, 340, a top chip 350, an external solder interconnect 572, a first encapsulation layer 591, and a second encapsulation layer 591. A multi-chip package including the base chip 310, core chips 320, 330, 340, top chip 350, and the first encapsulation layer 591 may be mounted on the wiring structure 21.

[0072] The base chip 310 may include a base chip electrode 189 placed on the base circuit layer 317. A third solder interconnection 172 may be placed between the UBM layer 63 and the base chip electrode 189. The second sealing layer 592 may cover the wiring structure 21, the base chip 310, the core chips 320, 330, 340, the top chip 350, and the first sealing layer 591. The second sealing layer 592 may extend between the wiring structure 21 and the base chip 310. The second sealing layer 592 may be in direct contact with the sides of the UBM layer 63, the third solder interconnection 172, and the base chip electrode 189.

[0073] Figures 9 and 16-19 are cross-sectional views illustrating a method for forming a semiconductor package according to embodiments of the present disclosure. Figures 10-15 are partial views showing a portion 110' of Figures 9 and 16.

[0074] Referring to Figures 9 and 10, a buffer layer 212 may be formed on the carrier substrate 211. A wiring structure 21 may be formed on the buffer layer 212. The wiring structure 21 may include a first insulating layer 23, a second insulating layer 25, a third insulating layer 27, through holes 27H, a first via electrode 31, a first horizontal electrode 38, a second via electrode 41, a conductive pad 48, and a second horizontal electrode 48'. The conductive pad 48 and the second horizontal electrode 48' may include a first barrier layer 43, 43', a first seed layer 44, 44', and a first conductive layer 45, 45'.

[0075] The first insulating layer 23 may be formed on the buffer layer 212. The first via electrode 31 may penetrate the first insulating layer 23 perpendicularly. The first horizontal electrode 38 may be formed on the first insulating layer 23. The first via electrode 31 may be in contact with the side surface of the first horizontal electrode 38.

[0076] The second insulating layer 25 can cover the first insulating layer 23, the first via electrode 31, and the first horizontal electrode 38. The second via electrode 41 can penetrate the second insulating layer 25 vertically and contact the first horizontal electrode 38. A conductive pad 48 and the second horizontal electrode 48' can be formed on the second insulating layer 25. The second horizontal electrode 48' can contact the second via electrode 41. The conductive pad 48 can contact the side surface of the second horizontal electrode 48'.

[0077] The third insulating layer 27 can cover the second insulating layer 25, the second via electrode 41, the conductive pad 48, and the second horizontal electrode 48'. The through-hole 27H can penetrate the third insulating layer 27 vertically. The through-hole 27H can be superimposed on the conductive pad 48. The conductive pad 48 may be exposed at the bottom of the through-hole 27H.

[0078] The carrier substrate 211 may include a glass wafer or a silicon wafer. The buffer layer 212 may include a release layer, an adhesive, or a combination thereof. The first insulating layer 23, the second insulating layer 25, and the third insulating layer 27 may each include polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), polyhydroxystyrene (PHS), polyimide isoindolo quinazolinedione (PIQ), or a combination thereof.

[0079] In one embodiment, each of the first via electrode 31, the first horizontal electrode 38, the second via electrode 41, the conductive pattern 48, and the second horizontal electrode 48' may be formed using an electroplating method. Each of the first via electrode 31, the first horizontal electrode 38, the second via electrode 41, the conductive pattern 48, and the second horizontal electrode 48' may include a copper layer.

[0080] In one embodiment, the conductive pattern 48 and the second horizontal electrode 48' may include a first barrier layer 43, 43', a first seed layer 44, 44' on the first barrier layer 43, 43', and a first conductive layer 45, 45' on the first seed layer 44, 44'. The first barrier layer 43, 43' may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The first seed layer 44, 44' may include a conductive material such as copper. The first seed layer 44, 44' may be formed using a PVD method. The first conductive layer 45, 45' may include a copper layer. The first conductive layer 45, 45' may be formed using an electroplating method. Electroplating may be advantageous for forming a copper layer with low electrical resistivity in a short time. Electroplating may have a relatively faster thin-film formation rate than PVD or CVD methods.

[0081] Referring to Figure 11, a second barrier layer 53 may be formed on the third insulating layer 27. The second barrier layer 53 can conformally cover the inner wall of the through hole 27H. The second barrier layer 53 may be in contact with the second horizontal electrode 48. The second barrier layer 53 may be in contact with the side and top surfaces of the third insulating layer 27. The second barrier layer 53 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0082] A second seed layer 54 may be formed on the second barrier layer 53. The second seed layer 54 may include a conductive material such as copper. The second seed layer 54 may be omitted.

[0083] Referring to Figure 12, a first mask pattern 57M can be formed on the second barrier layer 53 and the second seed layer 54. The first mask pattern 57M can cover the edges of the through holes 27H.

[0084] Referring to Figure 13, a protruding pattern 57 may be formed on the second seed layer 54. The space between the protruding pattern 57 and the sidewall of the through hole 27H may be covered by a first mask pattern 57M. The protruding pattern 57 may have a horizontal width smaller than the through hole 27H. The protruding pattern 57 may be superimposed on the center of the through hole 27H. The uppermost surface of the protruding pattern 57 may be at substantially the same level as the uppermost surface of the third insulating layer 27, or at a lower level than the uppermost surface of the third insulating layer 27. In one embodiment, the protruding pattern 57 may include a copper layer. The protruding pattern 57 may be formed using an electroplating method.

[0085] Referring to Figure 14, a second mask pattern 62M may be formed on the second barrier layer 53 and the second seed layer 54. The second mask pattern 62M may be formed after removing the first mask pattern 57M, or by further processing the first mask pattern 57M. The second seed layer 54 may be exposed between the second mask pattern 62M and the protruding pattern 57.

[0086] Referring to Figure 15, a UBM layer 63 can be formed to cover the protruding pattern 57 and fill the through-hole 27H. A capping layer 65 can be formed on the UBM layer 63. In one embodiment, the UBM layer 63 may include a nickel (Ni) layer. The UBM layer 63 may be formed using an electroplating method. The capping layer 65 may include a gold (Au) layer.

[0087] The UBM layer 63 can completely fill the through-hole 27H and extend onto the third insulating layer 27. The UBM layer 63 can have a horizontal width greater than the through-hole 27H. The UBM layer 63 can cover the sides and top of the protruding pattern 57. The UBM layer 63 can fill the space between the side wall of the through-hole 27H and the protruding pattern 57.

[0088] The process of forming the UBM layer 63 may include forming a plating layer at a substantially uniform rate along the surface of the electrode. In one embodiment, the process of forming the UBM layer 63 may include forming a nickel (Ni) layer at a substantially uniform rate along the surface of the second seed layer 54 and the protruding pattern 57. In one embodiment, since the nickel layer formed by electroplating is formed along the surface shape, the nickel layer formed on a surface containing through-holes 27H may form irregularities in the shape of the through-holes 27H. If solder interconnections are formed on irregularities in the shape of the through-holes 27H, the irregularities may create voids inside, which may weaken the bonding strength of the solder interconnections. The protruding pattern 57 can serve to mitigate steps on the upper surface of the UBM layer 63. The protruding pattern 57 can minimize surface irregularities of the UBM layer 63.

[0089] The capping layer 65 can cover the UBM layer 63. The capping layer 65 can have a thinner thickness than the UBM layer 63. The capping layer 65 may be omitted.

[0090] Referring to Figure 16, the UBM layer 63 and the third insulating layer 27 can be exposed by removing the second mask pattern 62M and partially removing the second barrier layer 53 and the second seed layer 54. The UBM layer 63 and the third insulating layer 27 can include various shapes, as shown in Figures 3 to 6.

[0091] In one embodiment, the step of removing the second barrier layer 53 and the second seed layer 54 to expose the third insulating layer 27 may include an etching step. As shown in Figure 4, while the etching step is being performed, the second barrier layer 53 and the second seed layer 54 may be over-etched, which can form an undercut region UC1 between the third insulating layer 27 and the UBM layer 63.

[0092] Referring to Figure 17, a first semiconductor chip 90 can be mounted on the wiring structure 21. The first semiconductor chip 90 may include a first substrate 91 and a first circuit layer 93. Chip electrodes 89 may be formed on the first circuit layer 93. A first solder interconnection 72 may be formed between the UBM layer 63 and the chip electrodes 89.

[0093] A multi-chip package including a base chip 310, core chips 320, 330, 340, top chip 350, and a first sealing layer 591 can be mounted on the wiring structure 21. A base chip electrode 189 can be placed on the base circuit layer 317 of the base chip 310. A third solder interconnection 172 can be formed between the UBM layer 63 and the base chip electrode 189.

[0094] Referring again to Figures 2, 3 and 17, each of the chip electrode 89, base chip electrode 189, conductive pattern 313, base through electrode 319, first core through electrode 329, second core through electrode 339, third core through electrode 349, base back surface 416, first core back electrode 426, second core back electrode 436, third core back electrode 446, first core front electrode 429, second core front electrode 439, third core front electrode 449, and top front electrode 459 may include metal, metal nitride, conductive carbon, or a combination thereof.

[0095] In one embodiment, the third barrier layer 83 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The third seed layer 84 may include a conductive material such as copper. The second conductive layer 85 may include a pillar shape. The second conductive layer 85 may be formed using an electroplating method. The second conductive layer 85 may include a copper layer. The third conductive layer 88 may be formed on the second conductive layer 85. The third conductive layer 88 may be formed using an electroplating method. The third conductive layer 88 may include a nickel (Ni) layer.

[0096] Each of the first solder interconnection 72, the third solder interconnection 172, and the second solder interconnection 472 may contain tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or a combination thereof. The first intermetallic compound layer IM1 may contain both the materials constituting the third solder interconnection 172 and the UBM layer 63. In one embodiment, the first intermetallic compound layer IM1 may contain all the materials constituting the third solder interconnection 172, the UBM layer 63, and the capping layer (65 in Figure 15). The second intermetallic compound layer IM2 may contain both the materials constituting the third solder interconnection 172 and the third conductive layer 88.

[0097] Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include a III-V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include single-crystal silicon, polysilicon, amorphous silicon, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0098] The first sealing layer 591 may include an epoxy molding compound.

[0099] Referring to Figure 18, a second sealing layer 592 may be formed covering the wiring structure 21, the first semiconductor chip 90, the base chip 310, the core chips 320, 330, 340, the top chip 350, and the first sealing layer 591. The second sealing layer 592 may extend between the wiring structure 21 and the first semiconductor chip 90, and between the wiring structure 21 and the base chip 310. The second sealing layer 592 may contain an epoxy molding compound.

[0100] Referring to Figure 19, the carrier substrate 211 and buffer layer 212 can be removed. An external electrode 589 can be formed on the underside of the wiring structure 21. The external electrode 589 can be in contact with the first via electrode 31. An external solder interconnection 572 can be formed on the external electrode 589. The semiconductor package can be separated using a singulation process.

[0101] The external electrode 589 may include copper (Cu). The external solder interconnection 572 may include tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or a combination thereof.

[0102] The technical concepts are disclosed in conjunction with the examples and embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and technical concepts of this disclosure. The embodiments disclosed herein should be considered in an exemplary rather than restrictive manner. Accordingly, the scope of this disclosure is not limited to the foregoing description. All changes within the meaning of the claims and their equivalents are included within the scope of the claims.

Claims

1. A wiring structure comprising a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a through hole penetrating the second insulating layer and superimposed on the conductive pad, a protruding pattern disposed on the conductive pad within the through hole, and a UBM (Under Bump Metallurgy) layer connected to the conductive pad and in contact with the upper and side surfaces of the protruding pattern; and A semiconductor package including a semiconductor chip arranged on the wiring structure and connected to the UBM layer.

2. The semiconductor package according to claim 1, wherein the protruding pattern has a horizontal width smaller than the through-hole.

3. The semiconductor package according to claim 1, wherein the protruding pattern is superimposed on the center of the through hole.

4. The semiconductor package according to claim 1, wherein the uppermost surface of the protruding pattern is the same as or at a lower level than the uppermost surface of the second insulating layer.

5. The UBM layer includes a first portion superimposed on the protruding pattern, a second portion superimposed between the second insulating layer and the protruding pattern and not superimposed on the second insulating layer, and a third portion superimposed on the second insulating layer. The semiconductor package according to claim 1, wherein the upper surfaces of the first portion, the second portion, and the third portion are positioned at a higher level than the uppermost surface of the second insulating layer.

6. The semiconductor package according to claim 5, wherein the upper surfaces of the first portion, the second portion, and the third portion are substantially coplanar.

7. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 5, wherein the distance between the recessed region and the conductive pad is smaller than the distance between the upper surface of the third portion and the conductive pad.

8. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 5, wherein the distance between the recessed region and the conductive pad is smaller than the distance between the upper surface of the first portion and the conductive pad.

9. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 5, wherein the recessed region is superimposed at the center between the second insulating layer and the protruding pattern.

10. The present invention further includes a barrier layer disposed between the protruding pattern and the conductive pad, extending onto the conductive pad between the protruding pattern and the second insulating layer, and extending between the UBM layer and the second insulating layer, The semiconductor package according to claim 1, wherein the barrier layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

11. The system further includes a seed layer between the protruding pattern and the barrier layer, and between the UBM layer and the barrier layer. The semiconductor package according to claim 10, wherein the seed layer includes a conductive material.

12. The semiconductor package according to claim 1, wherein the protruding pattern includes a copper (Cu) layer.

13. The semiconductor package according to claim 1, wherein the UBM layer includes a nickel (Ni) layer.

14. The invention further includes a solder interconnection between the UBM layer and the semiconductor chip, The semiconductor package according to claim 1, wherein the solder interconnection includes tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or a combination thereof.

15. A wiring structure comprising a first insulating layer, a plurality of conductive pads on the first insulating layer, a second insulating layer on the plurality of conductive pads, a plurality of through holes penetrating the second insulating layer and superimposed on the plurality of conductive pads, a plurality of protruding patterns disposed on the plurality of conductive pads within the plurality of through holes, and a plurality of UBM layers in contact with the upper and side surfaces of each of the plurality of protruding patterns and connected to the plurality of conductive pads; First and second semiconductor chips on the wiring structure; and A semiconductor package comprising a sealing layer disposed on the wiring structure and covering the first and second semiconductor chips.

16. The system further includes a plurality of solder interconnections disposed between the plurality of UBM layers and the first semiconductor chip, and between the plurality of UBM layers and the second semiconductor chip, The sealing layer extends between the wiring structure and the first semiconductor chip, and between the wiring structure and the second semiconductor chip. The semiconductor package according to claim 15, wherein the sealing layer is in contact with the sides of the plurality of UBM layers and the plurality of solder interconnections.

17. Each of the plurality of UBM layers includes a first portion superimposed on one of the plurality of protruding patterns, a second portion superimposed between the second insulating layer and one of the plurality of protruding patterns, but not superimposed on the second insulating layer, and a third portion superimposed on the second insulating layer. The semiconductor package according to claim 15, wherein the upper surfaces of the first portion, the second portion, and the third portion are positioned at a higher level than the uppermost surface of the second insulating layer.

18. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 17, wherein the distance between the recessed region and one of the plurality of conductive pads is smaller than the distance between the upper surface of the third portion and one of the plurality of conductive pads.

19. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 17, wherein the distance between the recessed region and one of the plurality of conductive pads is smaller than the distance between the upper surface of the first portion and one of the plurality of conductive pads.

20. The upper surface of the second part includes a recessed area, The semiconductor package according to claim 17, wherein the recessed region is superimposed at the center between the second insulating layer and one of the plurality of protruding patterns.

21. First insulating layer; A conductive pad on the first insulating layer; A second insulating layer on the conductive pad; A through-hole that penetrates the aforementioned second insulating layer and is superimposed on the conductive pad; A protruding pattern having a horizontal width smaller than the through-hole, which is positioned on the conductive pad within the through-hole; A UBM layer that is in contact with the upper and side surfaces of the protruding pattern and has a horizontal width greater than the through-hole, the upper surface of the UBM layer having a recessed region superimposed between the protruding pattern and the second insulating layer; and A semiconductor package containing semiconductor chips on a UBM layer.

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