Circuit board and semiconductor package comprising the same

Abstract

The circuit board according to an embodiment includes: an insulating layer in which a plurality of inorganic fillers are embedded; a wiring layer disposed on the insulating layer; and a protective layer disposed on the wiring layer, wherein the wiring layer includes a plurality of protrusions projecting toward the insulating layer, and wherein the protrusions do not contact the plurality of inorganic fillers, and the protrusions overlap at least one of the plurality of inorganic fillers in a horizontal direction.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor packaging substrate including the circuit board. Background Technology

[0002] As the performance of electrical / electronic products increases, techniques for arranging a greater number of semiconductor devices on semiconductor packaging substrates of limited size have been proposed and studied. However, since general semiconductor packaging is based on mounting a single semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been provided. Such semiconductor packages have a structure in which multiple semiconductor devices are interconnected on the substrates in a horizontal and / or vertical direction. Therefore, the advantage of this semiconductor package is that it effectively utilizes the mounting area of ​​the semiconductor devices and can transmit high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, in semiconductor packaging used in products providing the Internet of Things (IoT), autonomous vehicles, high-performance servers, etc., the number of semiconductor devices and / or the size of each semiconductor device are increasing due to the trend towards higher integration. However, due to limitations such as reticles, the concept extends to semiconductor chiplets, where the functional parts of the semiconductor device are divided.

[0005] Therefore, communication between semiconductor devices and / or semiconductor chiplets becomes important, and there is a trend to place an interposer between the semiconductor packaging substrate and the semiconductor device.

[0006] Intermediate layers facilitate communication between semiconductor devices and / or semiconductor chiplets, or perform the function of redistribution layers with increasing width or linewidth of circuit patterns from semiconductor devices toward semiconductor packages to interconnect semiconductor devices and semiconductor package substrates, thereby enabling smooth electrical signals between semiconductor package substrates and semiconductor devices with circuit patterns that are relatively larger than those of semiconductor devices.

[0007] Simultaneously, as the spacing between terminals of semiconductor devices becomes smaller, the linewidth, thickness, and spacing of wiring layers disposed in the packaging substrate and / or interposer can also become smaller. In this case, when the linewidth, thickness, and spacing of the wiring layers become smaller, the adhesion between the wiring layers and the insulating layer can be reduced. Therefore, the surface of the insulating layer can be provided with a certain level or higher surface roughness value, thereby improving the adhesion between the insulating layer and the wiring layer.

[0008] At this point, in conventional technology, a de-smear process using plasma or chemical reagents is performed on the surface of the insulating layer to provide an insulating layer with a certain level or higher surface roughness value.

[0009] However, conventional techniques cannot provide a uniform surface roughness value across the entire surface of the insulating layer, thus resulting in reduced adhesion between the insulating layer and the wiring layer. In other words, the insulating layer includes inorganic fillers, and these fillers provide a surface roughness value with significant variations on the surface of the insulating layer.

[0010] For example, during the decontamination process, the resin in the insulating layer may be removed, but the inorganic fillers, including SiO2 or TiO2, are not removed. Therefore, the inorganic fillers are exposed on the surface of the insulating layer after the decontamination process. Furthermore, at least a portion of the inorganic fillers exposed outside the insulating layer separates from the insulating layer and is removed.

[0011] Therefore, the surface of the insulating layer includes a first region formed by resin etched through a decontamination process, a second region formed by exposed inorganic filler, and a third region from which the inorganic filler is separated. In this case, different surface roughness values ​​can be provided to the first to third regions of the insulating layer, thus potentially leading to the following problem: due to the non-uniformity of surface roughness values, the adhesion between the insulating layer and the wiring layer increases. This problem reduces the reliability of the adhesion between the insulating layer and the wiring layer. Furthermore, the wiring layer disposed on the second region of the insulating layer can contact the inorganic filler of the insulating layer, thus potentially degrading the electrical properties of the wiring layer. For example, the dielectric constant of the inorganic filler may be higher than that of the resin in the insulating layer, and due to the high dielectric constant of the inorganic filler, there is an increase in the transmission loss of signals transmitted through the wiring layer. Additionally, the adhesion between the inorganic filler and the wiring layer may be weaker than the adhesion between the inorganic filler and the resin in the insulating layer, thus reducing the reliability of the adhesion between the wiring layer and the insulating layer.

[0012] Therefore, a new method is needed that can provide a uniform surface roughness value on the surface of the insulating layer. Summary of the Invention

[0013] Technical issues

[0014] The embodiment provides a circuit board that provides a uniform roughness value on the surface of an insulating layer, and a semiconductor package including the circuit board.

[0015] Furthermore, the embodiments provide a circuit board with improved adhesion between the insulating layer and the wiring layer, and a semiconductor package including the circuit board.

[0016] Furthermore, the embodiments provide a circuit board including a wiring layer with improved electrical characteristics, and a semiconductor package including the circuit board.

[0017] Additionally, the embodiments provide a circuit board that minimizes the height deviation of wiring layers disposed on the same layer, and a semiconductor package including the circuit board.

[0018] The technical problems to be solved by the proposed embodiments are not limited to those described above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0019] Technical solution

[0020] The circuit board according to an embodiment includes: an insulating layer in which a plurality of inorganic fillers are embedded; a wiring layer disposed on the insulating layer; and a protective layer disposed on the wiring layer, wherein the wiring layer includes a plurality of protrusions projecting toward the insulating layer, and wherein the protrusions do not contact the plurality of inorganic fillers, and the protrusions overlap at least one of the plurality of inorganic fillers in a horizontal direction.

[0021] In addition, the protective layer includes multiple protrusions that project toward the insulating layer.

[0022] Furthermore, the protrusions of the protective layer do not contact the multiple inorganic fillers, and the protrusions of the protective layer overlap with at least one of the multiple inorganic fillers in the horizontal direction.

[0023] In addition, at least one of the protrusions in the wiring layer and the protrusions in the protective layer is in direct contact with the insulation layer.

[0024] In addition, the protrusions of the protective layer overlap with the protrusions of the wiring layer in the horizontal direction.

[0025] Furthermore, the thickness of at least one of the protrusions in the wiring layer is different from the thickness of at least another protrusion in the wiring layer.

[0026] In addition, the upper surface of the insulating layer is provided with a recess corresponding to the protrusion of the wiring layer, and the lower surface of the insulating layer is provided with multiple protrusions.

[0027] In addition, the circuit board also includes a connecting member embedded in the insulating layer, wherein the connecting member overlaps with at least one of a plurality of protrusions in a vertical direction.

[0028] Furthermore, the curvature of the protrusion differs from that of the inorganic filler.

[0029] In addition, the circuit board also includes a via electrode that penetrates at least a portion of the insulating layer in a vertical direction and is connected to the wiring layer, and at least one of the plurality of inorganic fillers contacts the side surface of the via electrode.

[0030] On the other hand, the circuit board according to the embodiment includes: a first insulating layer in which a plurality of inorganic fillers are embedded; and a second insulating layer disposed on the first insulating layer, wherein the lower surface of the second insulating layer is provided with a plurality of protrusions protruding toward the first insulating layer, and the protrusions do not contact the plurality of inorganic fillers, and the protrusions overlap with at least one of the plurality of inorganic fillers in the horizontal direction.

[0031] The circuit board also includes a wiring layer disposed between the first insulating layer and the second insulating layer, wherein the lower surface of the wiring layer is provided with a plurality of protrusions protruding toward the first insulating layer, and the protrusions of the wiring layer do not contact the plurality of inorganic fillers, and the protrusions of the wiring layer overlap with at least one of the plurality of inorganic fillers in the horizontal direction.

[0032] In addition, the protrusions of the second insulating layer and the wiring layer directly contact the upper surface of the first insulating layer.

[0033] In addition, the protrusions of the second insulating layer overlap with the protrusions of the wiring layer in the horizontal direction.

[0034] In addition, the circuit board also includes a connecting member embedded in the first insulating layer, wherein the connecting member overlaps with at least one of the plurality of protrusions in a vertical direction.

[0035] On the other hand, the semiconductor package according to the embodiment includes: an insulating layer in which a plurality of inorganic fillers are embedded; a wiring layer disposed on the insulating layer; a protective layer disposed on the wiring layer; and a semiconductor device disposed on the protective layer, wherein the wiring layer includes a plurality of protrusions protruding toward the insulating layer and the protrusions directly contact the insulating layer, the protrusions do not contact the plurality of inorganic fillers, and the protrusions overlap with at least one of the plurality of inorganic fillers in a horizontal direction.

[0036] In addition, the protective layer includes a plurality of protrusions projecting toward the insulating layer, wherein the protrusions of the protective layer directly contact the insulating layer, the protrusions of the protective layer do not contact the plurality of inorganic fillers, and the protrusions of the protective layer overlap with at least one of the plurality of inorganic fillers in the horizontal direction.

[0037] In addition, the protrusions of the protective layer overlap with the protrusions of the wiring layer in the horizontal direction.

[0038] In addition, the upper surface of the insulating layer is provided with a recess corresponding to the protrusion of the wiring layer, and the lower surface of the insulating layer is provided with multiple protrusions.

[0039] In addition, the semiconductor package includes a connection member embedded in an insulating layer, wherein the connection member overlaps with at least one of a plurality of protrusions in a vertical direction.

[0040] Beneficial effects

[0041] The embodiments can improve the physical and / or electrical reliability of the circuit board and the semiconductor package including the circuit board.

[0042] Specifically, the embodiment includes an insulating layer. The insulating layer comprises a resin and an inorganic filler embedded in the resin. In this case, a plurality of recesses are provided on the upper surface of the insulating layer. Furthermore, each of the plurality of recesses on the upper surface of the insulating layer may have a curvature different from that of the inorganic filler. For example, the inorganic filler embedded in the insulating layer is not exposed through the recesses on the upper surface of the insulating layer.

[0043] Therefore, the embodiments can provide multiple recesses on the upper surface of the insulating layer while preventing the inorganic filler embedded in the insulating layer from being exposed to the outside of the insulating layer. Thus, the embodiments can solve the problem of physical and / or electrical reliability caused by the exposure of the inorganic filler of the insulating layer to the outside during the process of providing a certain level of surface roughness on the upper surface of the insulating layer.

[0044] Specifically, when inorganic fillers are exposed on the outside of the insulation layer, the adhesion between the insulation layer and the wiring layer can be reduced. That is, the adhesion between the inorganic filler of the insulation layer and the wiring layer is lower than the adhesion between the resin of the insulation layer and the wiring layer. Therefore, the adhesion between the insulation layer and the wiring layer in the area where the inorganic filler is exposed can be reduced, which may lead to delamination of the wiring layer from the insulation layer.

[0045] In contrast, this embodiment can transfer the recess to the upper surface of the insulating layer corresponding to the protrusions provided in the metal layer, instead of using a decontamination process, thereby providing a recess with a uniform depth on the upper surface of the insulating layer. Therefore, this embodiment can prevent inorganic fillers from being exposed to the outside of the insulating layer. As a result, this embodiment can enable wiring layers disposed on the same layer to have a uniform thickness and further improve the adhesion between the insulating layer and the wiring layer.

[0046] Furthermore, in conventional techniques using a decontamination process, spaces are formed in the insulating layer from which exposed inorganic fillers detach. In this case, the depth of these detachment spaces in the vertical direction can be greater than the depth of other portions. Therefore, when an electroless copper plating process for forming wiring layers is performed in these detachment spaces, voids can form because electroless copper plating is not performed in at least a portion of the detachment spaces. Moreover, stress applied to the insulating layer can concentrate in the detachment spaces of the reinforcing members, which have a relatively large depth, thus reducing the physical and / or electrical reliability of the semiconductor package.

[0047] In contrast, this embodiment can eliminate voids by forming uniform recesses on the surface of the insulating layer, thereby further improving the physical and electrical reliability of the semiconductor package. Furthermore, when stress is applied to the insulating layer, this embodiment can prevent stress concentration in specific areas of the insulating layer by providing uniform recesses on the upper surface of the insulating layer, and can further distribute the stress uniformly as a whole, thereby improving the physical and electrical reliability of the semiconductor package.

[0048] In addition, the embodiments can prevent the detachment of inorganic fillers embedded in the insulating layer during the process of forming recesses on the surface of the insulating layer, and can prevent changes in the dielectric constant of the insulating layer that may occur due to the detachment of inorganic fillers, thereby further improving the electrical characteristics of the circuit board and semiconductor package.

[0049] Furthermore, the embodiment includes a wiring layer disposed on an insulating layer, and the wiring layer may include protrusions projecting toward the insulating layer. These protrusions may correspond to recesses disposed in the insulating layer. In this case, the protrusions of the wiring layer may overlap, along a horizontal direction, at least one of a plurality of inorganic fillers embedded in the insulating layer. Therefore, the embodiment can improve the rigidity of the circuit board and further enhance mechanical reliability by minimizing the degree of thermal deformation occurring at the interface between the insulating layer and the wiring layer due to thermal cycling by using inorganic fillers overlapping in the horizontal direction as described above.

[0050] Furthermore, the embodiment includes a protective layer disposed on the insulating layer, and the protective layer may include protrusions projecting toward the insulating layer. The protrusions of the protective layer may correspond to recesses disposed in the insulating layer. In this case, the protrusions of the protective layer may overlap, along a horizontal direction, at least one of a plurality of inorganic fillers embedded in the insulating layer. Therefore, the embodiment can improve the rigidity of the circuit board and further improve mechanical reliability by minimizing the degree of thermal deformation occurring at the interface between the insulating layer and the protective layer due to thermal cycling by using inorganic fillers overlapping in the horizontal direction as described above. Furthermore, the embodiment can prevent stress caused by thermal cycling from being transmitted through the protective layer to the bump layer, thus preventing cracks in the bump layer due to stress. Therefore, the embodiment can enable semiconductor devices to be stably mounted on the bump layer, thereby enabling the semiconductor package to operate stably. Attached Figure Description

[0051] Figure 1 This is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0052] Figure 2 It is shown Figure 1 A diagram of an embodiment of the insulating layer of a circuit board.

[0053] Figure 3These are optical microscope images of the surface roughness values ​​of the insulating layers used for comparing the embodiments and comparative examples.

[0054] Figure 4 It is shown Figure 1 A diagram of another embodiment of the insulating layer of the circuit board.

[0055] Figure 5 yes Figure 1 An enlarged cross-sectional view of the first region A of the semiconductor package.

[0056] Figure 6 yes Figure 1 An enlarged cross-sectional view of the second region B of the semiconductor package.

[0057] Figure 7 This is a diagram illustrating a semiconductor package according to a second embodiment.

[0058] Figure 8 This is a diagram illustrating a semiconductor package according to a third embodiment.

[0059] Figures 9 to 15 Manufacturing is shown in the order of processes. Figure 1 A diagram illustrating a semiconductor packaging method. Detailed Implementation

[0060] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] However, the spirit and scope of this disclosure are not limited to the portion of the described embodiments, and may be implemented in a variety of other forms. Furthermore, one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of this disclosure.

[0062] Furthermore, unless otherwise explicitly defined and described, the terms used in the embodiments of this disclosure (including technical and scientific terms) may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in common dictionaries may be interpreted as having the same meaning as they have in the context of the relevant field.

[0063] Furthermore, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit this disclosure. In this specification, unless specifically stated in the wording, singular forms may also include plural forms, and when described as “at least one (or more) of A (and), B, and C,” it may include at least one of all combinations that can be combined among A, B, and C. Additionally, terms such as first, second, A, B, (a), and (b) may be used when describing elements of embodiments of this disclosure.

[0064] These terms are used only to distinguish an element from other elements, and these terms are not limited to the nature, order, or sequence of the elements. Furthermore, when an element is described as being “connected,” “joined,” or “in contact” with another element, it can include not only when the element is directly “connected,” “joined,” or “in contact” with another element, but also when the element is “connected,” “joined,” or “in contact” by yet another element between the element and the other element.

[0065] Furthermore, when described as being formed or disposed "above" or "below" in each element, "above" or "below" can include not only cases where two elements are directly connected to each other, but also cases where one or more other elements are formed or disposed between two elements. Additionally, when expressed as "above" or "below," it can include not only the upward direction based on a single element but also the downward direction.

[0066] The terminology used in this application is for describing specific embodiments only and is not intended to limit this disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and should be understood to not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0067] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and shall not be interpreted in an ideal or overly formal sense unless expressly defined in this application.

[0068] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Regardless of the reference numerals, identical or corresponding parts are assigned the same reference numerals, and redundant descriptions will be omitted.

[0069] Before describing the embodiments, the electronic devices (not shown) to which the semiconductor packages of the embodiments are applied will be briefly described. The electronic devices may be smartphones, personal digital assistants, digital cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive equipment, etc. However, the electronic devices are not limited to these and may be any other electronic devices that process data.

[0070] The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to a semiconductor package according to an embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor device and the circuit board, a resin portion filling the space between the semiconductor device and the circuit board, and a molding portion that integrally surrounds the semiconductor device.

[0071] Semiconductor devices can include active and / or passive devices and can have a variety of functions. Active devices can be in the form of integrated circuits (ICs) with hundreds to millions or more transistors integrated in a single semiconductor device, and can be, for example, logic chips, memory chips, etc. For example, a logic chip can be an application processor (AP) device that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or a group of devices including specific combinations of those listed above. Memory chips can be stacked memory such as HBM. In addition, memory chips can include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0072] The semiconductor package of the embodiment can be any of, but is not limited to, chip-scale package (CSP), flip chip-scale package (FC-CSP), flip chip ball grid array (FC-BGA), package-on-package (POP), and system-in-package (SIP).

[0073] Figure 1 This is a cross-sectional view showing a semiconductor package according to the first embodiment. Figure 2 It is shown Figure 1 A diagram of one embodiment of the insulating layer of a circuit board. Figure 3 These are optical microscope images of the surface roughness values ​​of the insulating layers used for comparing the embodiments and comparative examples. Figure 4 It is shown Figure 1 A diagram of another embodiment of the insulating layer of the circuit board, Figure 5 yes Figure 1 An enlarged cross-sectional view of the first region A of the semiconductor package, and Figure 6 yes Figure 1 An enlarged cross-sectional view of the second region B of the semiconductor package.

[0074] Reference Figure 1 The semiconductor package 1000 may include a circuit board 100, a connecting member 200 embedded in the circuit board 100, semiconductor devices 320 and 330 disposed on the circuit board 100, and a connecting portion 310 disposed between the circuit board 100 and the semiconductor devices 320 and 330.

[0075] In the following text, for the convenience of describing the semiconductor package of the embodiments, terms relating to the respective components constituting the semiconductor package will be described, and a detailed description of the respective components will be provided later.

[0076] The circuit board 100 may include an insulating layer 110, a wiring layer 120, a via electrode 130, a bump layer 140, and protective layers 150 and 160.

[0077] The insulating layer 110 may have a structure in which multiple layers are stacked along a vertical direction. The insulating layer 110 may include a core layer 111, an upper stacked insulating layer 112 disposed on a first surface of the core layer 111, and a lower stacked insulating layer 113 disposed on a second surface of the core layer 111. Here, being disposed on the first and second surfaces should not be construed as simply being in direct contact with the first and second surfaces, but may also include a configuration in which another component is interposed between the first surface and the upper stacked insulating layer 112 and between the second surface and the lower stacked insulating layer 113.

[0078] The core layer 111 is formed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and is used to improve the rigidity of the circuit board 100.

[0079] As the number of terminals of the semiconductor devices 320 and 330 disposed on the nearest circuit board 100 increases, the wiring becomes more complex, and therefore, the thickness of the upper stacked insulating layer 112 and the lower stacked insulating layer 113 tends to increase. Therefore, the core layer 111 can have a thickness of 120 μm to 1200 μm to improve the overall rigidity of the circuit board 100 and prevent excessive signal loss. Vias penetrating the first and second surfaces can be formed in the core layer 111. The vias in the core layer 111 can be formed using a mechanical drilling process or a CO2 laser. When forming vias in the core layer 111 using mechanical drilling, the inner wall of the via can be orthogonal to the first and / or second surfaces of the core layer 111. When forming vias using a CO2 laser, the inner wall of the via can include a plurality of recesses and / or protrusions alternately stacked in a vertical direction. Here, a recess refers to a region recessed in the horizontal direction away from the center of the via, and a protrusion refers to a region protruding in the horizontal direction towards the center of the via. Recesses and protrusions can be alternately arranged along the vertical direction on the inner wall forming the via. Here, "alternately arranged" can mean that protrusions are arranged between multiple recesses, or that recesses are arranged between multiple protrusions. When forming the via using a mechanical drilling process, the path for transmitting electrical signals can be shortened, which is advantageous in terms of electrical characteristics, but process costs may increase. Furthermore, when using a CO2 laser to form recesses and protrusions on the inner wall of the via, the thickness of the core via electrode 131 provided on the inner wall of the via can be increased in subsequent processes, thereby reducing impedance and process costs. Therefore, depending on the application of the semiconductor packaging, the processing method for vias provided in the core layer 111 can be selectively used.

[0080] A via electrode 131 can be disposed in a via of the core layer 111. The via electrode 131 is used for electrical connection of the wiring layer 120 and / or via electrode 130 disposed in the upper stacked insulating layer 112 and the wiring layer 120 and / or via electrode 130 disposed in the lower stacked insulating layer 113. Therefore, the via electrode 131 is preferably densely packed in the via for resistance or heat dissipation. However, when the thickness of the core layer 111 increases as described above, it may be difficult to densely pack the via electrode 131 in the via. For example, when attempting to fill the via formed in a thick core layer 111 by electroplating, voids may appear inside the via electrode 131. These voids expand due to heat generated during semiconductor packaging operation, thereby reducing the mechanical reliability of the circuit board. Therefore, a via electrode 131 with a predetermined thickness can be disposed on the inner wall of the via of the core layer 111. The thickness of the core via electrode 131 refers to its thickness in the horizontal direction orthogonal to the vertical direction of the stacked core layer 111, upper stacked insulating layer 112, and lower stacked insulating layer 113. The core via electrode 131 can have a thickness of 5 μm to 20 μm to prevent voltage drop due to increased core layer 111 thickness and to prevent voids. Because it is difficult to densely fill the internal portion of the core via electrode 131 with metal by electroplating or the like, empty spaces may form. These empty spaces may cause problems where the upper stacked insulating layer 112 and / or the lower stacked insulating layer 113 cannot be flatly disposed on the upper and / or lower surfaces of the core layer 111.

[0081] Therefore, the insulating member 110A can be disposed inside the core via electrode 131 to ensure the flatness of the core layer 111. For example, the insulating member 110A can be disposed in the via of the core layer 111, and the core via electrode 131 can be disposed between the inner wall of the via and the outer surface of the insulating member 110A, while surrounding the side surface of the insulating member 110A.

[0082] The upper surface of insulating member 110A may be in the same plane as the upper surface of core layer 111, or it may be positioned vertically closer to the upper stacked insulating layer 112 than the upper surface of core layer 111. The lower surface of insulating member 110A may be in the same plane as the lower surface of core layer 111, or it may be positioned vertically closer to the lower stacked insulating layer 113 than the lower surface of core layer 111. This can be freely designed to ensure flatness during the stacking of upper and lower stacked insulating layers 112 and 113, or to ensure the flatness of the first wiring layer 121 and / or the fourth wiring layer 124, which will be described later.

[0083] An insulating layer 112, multiple wiring layers 121, 122 and 123, multiple via electrodes 132 and 133, and a first protective layer 150 may be disposed on the first surface of the core layer 111.

[0084] The stacked insulating layer 112 may include a first insulating layer disposed on the upper surface of the core layer 111 and a second insulating layer disposed on the upper surface of the first insulating layer. Furthermore, the plurality of wiring layers 121, 122, and 123 disposed on the first surface of the core layer 111 may include a first wiring layer 121 closest to the core layer 111 in the vertical direction, a second wiring layer 122 further away from the core layer 111 in the vertical direction than the first wiring layer 121, and a third wiring layer 123 further away from the core layer 111 in the vertical direction than the second wiring layer 122. The first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 can be used to electrically connect semiconductor devices 320 and 330 disposed on the circuit board 100. Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 can be freely designed considering impedance.

[0085] Furthermore, via electrodes 132 and 133 can be provided to connect the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123. For example, the first via electrode 132 can be disposed between the first wiring layer 121 and the second wiring layer 122, and the second via electrode 133 can be disposed between the second wiring layer 122 and the third wiring layer 123, thereby electrically connecting the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123.

[0086] The first via electrode 132 and the second via electrode 133 can be formed simultaneously in the process of forming the first to third wiring layers 121, 122, and 123. For example, in the process of forming the second wiring layer 122 on the first wiring layer 121, vias can be formed in the first insulating layer on which the insulating layer 112 is deposited to expose a portion of the first wiring layer 121, and the second wiring layer 122 can be formed together with the first via electrode 132 filling the vias in the first insulating layer. Therefore, the first via electrode 132 can be regarded as a protruding electrode of the second wiring layer 122. Similarly, each of the first via electrode 132 and the second via electrode 133 can be regarded as a protruding electrode of the second wiring layer 122 and the third wiring layer 123, and can be connected to another wiring layer disposed below each wiring layer.

[0087] The first wiring layer 121 can contact the first surface of the core layer 111. In this case, a portion of the first wiring layer 121 can be configured to cover the aforementioned insulating member 110A. The portion of the first wiring layer 121 covering the insulating member 110A can have a smaller thickness than other portions that do not perpendicularly overlap with the insulating member 110A. Here, the thickness of the first wiring layer 121 refers to the thickness along the vertical direction. Depending on the degree of freedom in wiring design, the first wiring layer 121 can cover the insulating member 110A or may not cover the insulating member 110A, thus increasing the degree of freedom in wiring connections. When the first wiring layer 121 does not cover the insulating member 110A, the insulating member 110A can directly contact the first insulating layer. When the first wiring layer 121 contacts the first insulating layer on which the stacked insulating layer 112 is applied, the bonding strength can be better and heat dissipation can be advantageous compared to the case where the insulating member 110A directly contacts the first insulating layer. However, to reduce process costs, the first wiring layer 121 can be configured not to cover the insulating member 110A. Furthermore, depending on the design of the first via electrode 132, the first wiring layer 121 may or may not cover the insulating member 110A. For example, when a first via electrode 132 is provided that overlaps with the first wiring layer 121 in the vertical direction, the first wiring layer 121 may be configured to cover the insulating member 110A to ensure electrical connection and / or mechanical engagement with the first via electrode 132. When no first via electrode 132 is provided that overlaps with the first wiring layer 121 in the vertical direction, the first wiring layer 121 may be configured not to cover the insulating member 110A.

[0088] The upper stacked insulating layer 112 may include a first insulating layer that is closest to the core layer 111 in the vertical direction and a second insulating layer that is positioned further away from the core layer 111 in the vertical direction than the first insulating layer. Although the upper stacked insulating layer 112 is shown as including two insulating layers, this disclosure is not limited thereto. For example, the upper stacked insulating layer 112 may include three or more insulating layers, thereby achieving a smoother electrical connection between the semiconductor device and the semiconductor package substrate.

[0089] The first and second insulating layers of the upper stacked insulating layer 112 are configured for insulation in the vertical direction between the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123. For example, thermosetting insulating materials containing inorganic fillers in resin can be used for the first and second insulating layers of the upper stacked insulating layer 112, and Ajinomoto stacked film (ABF) can be used. However, the embodiments are not limited to this, and photosensitive imaging dielectrics (PIDs) for forming fine patterns can be used.

[0090] The first protective layer 150 can protect the third wiring layer 123 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the first protective layer 150 serves to prevent short circuits between solders due to low wettability with the solder. A photocurable insulating material can be used as the first protective layer 150, and, for example, a solder resist can be used.

[0091] On the second surface of the core layer 111, there are a lower stacked insulating layer 113, a plurality of wiring layers 124, 125 and 126, a plurality of via electrodes 134 and 135, and a second protective layer 160.

[0092] The plurality of wiring layers 124, 125, and 126 disposed on the second surface of the core layer 111 may include a fourth wiring layer 124 closest to the core layer 111 along the vertical direction, a fifth wiring layer 125 disposed below the fourth wiring layer 124, and a sixth wiring layer 126 disposed below the fifth wiring layer 125. The fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 can be used to electrically connect a motherboard (not shown) of an electronic device and semiconductor devices 320 and 330 disposed on the circuit board 100. Each of the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 can be freely designed considering impedance.

[0093] Furthermore, via electrodes 134 and 135 can be configured to connect to the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126, respectively. The third via electrode 134 is disposed between the fourth wiring layer 124 and the fifth wiring layer 125, and the fourth via electrode 135 is disposed between the fifth wiring layer 125 and the sixth wiring layer 126, thereby electrically connecting the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126.

[0094] As described above regarding the first via electrode 132 and the second via electrode 133 disposed on the first surface of the core layer 111, the third via electrode 134 and the fourth via electrode 135 can also be formed simultaneously in the process of forming the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126. Therefore, as described above, the third via electrode 134 can be considered as a protruding electrode of the fifth wiring layer 125. However, since the fourth wiring layer 124, the fifth wiring layer 125, and the sixth wiring layer 126 are stacked in a direction different from that of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123, the tilt direction of the first via electrode 132 and the second via electrode 133 can be opposite to the tilt direction of the third via electrode 134 and the fourth via electrode 135. For example, the first via electrode 132 and the second via electrode 133 may have an inclination that narrows towards the core layer 111, and the third via electrode 134 and the fourth via electrode 135 may also have an inclination that narrows towards the core layer 111. For example, the inclination of the first via electrode 132 and the second via electrode 133 may be symmetrical with respect to the core layer 111 as the inclination of the third via electrode 134 and the fourth via electrode 135 may be.

[0095] The fourth wiring layer 124 can contact the second surface of the core layer 111. In this case, a portion of the fourth wiring layer 124 can be configured to cover the insulating member 110A. The portion of the fourth wiring layer 124 covering the insulating member 110A can have a smaller thickness than other portions that do not perpendicularly overlap with the insulating member 110A. Here, the thickness of the fourth wiring layer 124 refers to the thickness along the vertical direction. Depending on the degree of freedom in wiring design, the fourth wiring layer 124 can or can not cover the insulating member 110A, thus increasing the degree of freedom in wiring connections. When the fourth wiring layer 124 does not cover the insulating member 110A, the insulating member 110A can directly contact the third insulating layer beneath the stacked insulating layer 113. When the fourth wiring layer 124 contacts the third insulating layer, the bonding strength can be better and heat dissipation can be advantageous compared to the case where the insulating member 110A directly contacts the third insulating layer beneath the stacked insulating layer 113. However, to reduce process costs, the fourth wiring layer 124 can be configured not to cover the insulating member 110A. Furthermore, depending on the design of the third via electrode 134, the fourth wiring layer 124 may or may not cover the insulating member 110A. For example, when a third via electrode 134 is provided that overlaps with the fourth wiring layer 124 in the vertical direction, the fourth wiring layer 124 may be configured to cover the insulating member 110A to ensure electrical connection and / or mechanical engagement between the fourth wiring layer 124 and the third via electrode 134. Alternatively, when no third via electrode 134 is provided that overlaps with the fourth wiring layer 124 in the vertical direction, the fourth wiring layer 124 may be configured not to cover the insulating member 110A.

[0096] The lower stacked insulating layer 113 can be configured as multiple layers, and may include, for example, a third insulating layer closest to the core layer 111 along the vertical direction and a fourth insulating layer disposed below the third insulating layer. The third and fourth insulating layers of the lower stacked insulating layer 113 are configured for vertical insulation between the aforementioned fourth wiring layer 124, fifth wiring layer 125, and sixth wiring layer 126. Alternatively, for example, thermosetting insulating materials containing inorganic fillers in the resin can be used for the third and fourth insulating layers of the lower stacked insulating layer 113, and Ajinomoto's Ajinomoto stacked film (ABF) can be used. However, the embodiments are not limited to this, and photosensitive imaging dielectrics (PIDs) for forming fine patterns can be used.

[0097] The second protective layer 160 can protect the sixth wiring layer 126 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the second protective layer 160 serves to prevent short circuits between solders due to low wettability with the solder. A photocurable insulating material can be used as the second protective layer 160, and, for example, a solder resist can be used.

[0098] The bump layer 140 penetrates the first protective layer 150 and is electrically connected to the wiring layer 120. For example, the first protective layer 150 may include a via that overlaps with the third wiring layer 123 in the vertical direction, and the bump layer 140 may be disposed in the via of the first protective layer 150 and electrically connected to the third wiring layer 123.

[0099] The bump layer 140 may refer to having bonding members, such as solder, thereon for electrodes to be bonded to semiconductor devices, and may include through portions 141 disposed in vias of the first protective layer 150 and bonding portions 142 disposed on the through portions 141 and protruding onto the first protective layer 150. Recently, with the increasing functionality and performance of semiconductor devices, the number of I / O terminals disposed in semiconductor devices has also increased. Therefore, as the width and / or spacing of the I / O terminals disposed in semiconductor devices becomes smaller, electrical short circuits may occur when multiple bonding members come into contact with each other during the process of connecting the I / O terminals of the semiconductor device via bonding members, such as solder. Therefore, as the terminal density of semiconductor devices increases, in order to reduce the amount of bonding members, such as solder, fine bonding processes can be performed, such as applying a connection portion 310 to the upper surface of the bonding portion 142 protruding onto the first protective layer 150 of the bump layer 140 and performing thermo-press bonding (hereinafter referred to as "TC bonding"). When performing a fine bonding process, the bump layer 140 may include a bonding portion 142 protruding onto the first protective layer 150 as described above, in order to improve the alignment accuracy between the terminals of the semiconductor device and the bump layer 140. Furthermore, when the circuit board 100 and the semiconductor device are bonded by a thermoforming method, cracks may appear in the through-holes 141 of the bump layer 140 due to the resulting load. Therefore, cracking can be prevented by providing a material with an elastic modulus higher than that of the third wiring layer 123 in the portion of the through-holes 141 of the bump layer 140 adjacent to the third wiring layer 123. Nickel (Ni) can be used as such a material, but a copper layer with a low grain density can be formed by chemical plating. In this case, the through-holes 141 of the bump layer 140 can be formed by various methods. For example, the first protective layer 150 can be exposed and developed to form an opening in the first protective layer 150, and then a process of forming the through-holes 141 and bonding portions 142 of the bump layer 140 in the opening can be performed. Furthermore, a laser can be used to form the through-hole of the first protective layer 150, and then a process of forming the through portion 141 and the bonding portion 142 of the bump layer 140 in the opening can be performed. Alternatively, using a dry film resist (DFR), the DFR can first be placed in the area where the through portion 141 is to be formed, then the first protective layer 150 can be formed to cover the DFR, then a portion of the first protective layer 150 can be etched with a chemical solution to expose the DFR, then the DFR can be peeled off to form an opening in the first protective layer 150, after which the through portion 141 and the bonding portion 142 of the bump layer 140 can be formed. Therefore, depending on the process method, the through portion 141 of the bump layer 140 can have various shapes. For example, when the opening of the first protective layer 150 is formed by an exposure process, the side surface of the through portion 141 of the bump layer 140 can have a structure in which the width gradually decreases towards the third wiring layer 123.When the opening of the first protective layer 150 is formed by a laser process, the side surface of the through-hole 141 may include a vertical side surface and a bent portion recessed at the portion adjacent to the third wiring layer 123. When the opening of the first protective layer 150 is formed using a DFR (Digital Fractional Frame), the side surface of the through-hole 141 may only have a vertical side surface. As described above, when a semiconductor device is bonded to the circuit board 100 by thermocompression bonding, a load can be applied to the through-hole 141. In this case, when the through-hole 141 is formed using a DFR, stress can be applied uniformly, thereby increasing manufacturing yield.

[0100] The circuit board 100 may also include at least one connecting member 200. Recently, with the increasing number of signals to be processed by semiconductor devices, the size of semiconductor devices has tended to increase. This increase in the area of ​​semiconductor devices leads to problems with reduced semiconductor device yield. Therefore, there is a trend where the pattern size or functional portions of semiconductor devices are divided, chiplets are placed on the circuit board 100, and connecting members 200 having the function of electrically connecting them are embedded in the circuit board 100. However, the connecting member 200 is not limited to this, and can also connect semiconductor devices to another semiconductor device with different functions, such as memory. Additionally, the connecting member 200 may be disposed in the core layer 111 of the circuit board. For example, the core layer 111 may include a cavity, and the connecting member 200 may be disposed in the cavity of the core layer 111. In this case, the first insulating layer of the upper stacked insulating layer 112 and the third insulating layer of the lower stacked insulating layer 113 may surround the side surface of the connecting member 200 and fill the cavity of the core layer 111. However, the embodiments are not limited to this, and the connecting member 200 may be embedded in the upper stacked insulating layer 112 instead of the core layer 111. For example, when the connecting member 200 is embedded in the upper stacked insulating layer 112, the signal transmission distance to the semiconductor devices can be reduced, which helps prevent signal loss. That is, the connecting member 200 electrically connects to multiple semiconductor devices disposed on the circuit board 100; therefore, it may be advantageous to reduce signal transmission loss by reducing the signal transmission distance while being adjacent to multiple semiconductor devices. In this case, when the connecting member 200 is disposed in the upper stacked insulating layer 112, at least one of the first and second insulating layers of the upper stacked insulating layer 112 may include a cavity. Typically, a cavity is provided in only one specific insulating layer to embed the connecting member 200; however, in this case, a problem of reduced flatness of the uppermost insulating layer may occur. Furthermore, when the thickness of the connecting member 200 is greater than the thickness of a specific insulating layer of the upper stacked insulating layer 112, the problem of reduced flatness may become more severe. Therefore, it is necessary to improve flatness by reducing the difference between the thickness of the connecting member 200 and the depth of the cavity. Therefore, cavities can be provided in at least two insulating layers, and the connecting member 200 can be embedded in cavities provided in at least two insulating layers.

[0101] The connecting member 200 may be formed of the same material as the semiconductor device (such as silicon), or it may be formed of an organic material (such as a photosensitive resin or a thermosetting resin). Small chip cells divided according to function and / or spacing, or multiple semiconductor devices with different functions (e.g., CPU and GPU or GPU and HBM), may be mounted on a circuit board, and the connecting member 200 may be embedded in the circuit board to horizontally electrically connect multiple semiconductor devices.

[0102] Semiconductor devices 320 and 330 may be disposed on circuit board 100. Semiconductor devices 320 and 330 may include, but are not limited to, a first semiconductor device 320 and a second semiconductor device 330. For example, three or more semiconductor devices may be disposed on circuit board 100, or a single semiconductor device may be disposed on circuit board 100.

[0103] The semiconductor package includes a connection portion 310 disposed between semiconductor devices 320 and 330 and a circuit board 100. The connection portion 310 electrically connects terminals 325 and 335 of the semiconductor devices 320 and 330 and a bump layer 140 of the circuit board 100. The connection portion 310 electrically connects the bump layer 140 of the circuit board 100 to the terminals 325 and 335 of the semiconductor devices 320 and 330 using at least one of wire bonding, solder bonding, and metal-to-metal direct bonding methods.

[0104] Wire bonding refers to using wires such as gold (Au) to electrically connect the bump layer 140 of the circuit board 100 to the terminals 325 and 335 of the semiconductor devices 320 and 330. Solder bonding refers to using a material including at least one of Sn, Ag, and Cu to electrically connect the bump layer 140 of the circuit board 100 to the terminals 325 and 335 of the semiconductor devices 320 and 330. Metal-to-metal direct bonding refers to applying heat and pressure between the bump layer 140 of the circuit board 100 and the terminals 325 and 335 of the semiconductor devices 320 and 330 without the need for components such as solder, wires, or conductive adhesives to induce recrystallization, thereby directly bonding the electrode portions of the substrate 100 to the terminals 325 and 335 of the semiconductor devices 320 and 330. In this case, the connection portion 310 may refer to the metal layer disposed between the bump layer 140 of the circuit board 100 and the terminals 325 and 335 of the semiconductor devices 320 and 330 through recrystallization.

[0105] The structure of the circuit board 100 described above is only one embodiment of this disclosure, and the technical concept of this disclosure is not limited to the stacked structure of this embodiment.

[0106] The circuit board 100 requires adhesion between the insulating layer 110 and the wiring layer 120 to achieve stable electrical connections with semiconductor devices 320 and 330, as well as stable transmission of electrical signals between the motherboard of the electronic device and semiconductor devices 320 and 330. When the adhesion between the insulating layer 110 and the wiring layer 120 decreases, the wiring layer 120 will delaminate from the insulating layer 110, thus reducing the mechanical and / or electrical reliability of the circuit board 100 and the semiconductor package 1000.

[0107] In conventional circuit boards, to ensure adhesion between the insulating layer 110 and the wiring layer 120, at least one surface of the insulating layer 110 is decontaminated, thereby providing a certain level of roughness to the surface of the insulating layer 110. However, when the surface of the insulating layer 110 is decontaminated, a uniform roughness may not be provided on the surface of the insulating layer 110 due to the inorganic fillers provided in the insulating layer 110.

[0108] In the circuit board of this embodiment, a metal layer (not shown) with a uniform roughness is stacked on the insulating layer 110, so the roughness provided on the metal layer can be transferred to the surface of the insulating layer 110. As a result, the surface of the insulating layer 110 can be provided with a uniform surface roughness corresponding to the roughness provided on the surface of the metal layer, and the adhesion between the insulating layer 110 and the wiring layer 120 can be improved.

[0109] Reference Figure 2 At least one surface of the insulating layer 110 may be provided with a recess 110C. The recess 110C may be provided on one surface of the insulating layer 110 and may be recessed vertically from one surface of the insulating layer 110 toward the other surface of the insulating layer 110. A plurality of recesses 110C may be provided on at least one surface of the insulating layer 110, while being spaced apart from each other and / or connected to each other horizontally. Here, the insulating layer 110 having the recess 110C may refer to the aforementioned upper stacked insulating layer 112 and / or lower stacked insulating layer 113.

[0110] The recess 110C may be provided on each of one surface and the other surface of the insulating layer 110, but is not limited thereto. The recess 110C may be provided on one surface of the insulating layer 110 based on the stacking direction of the insulating layer 110.

[0111] For example, the upper stacked insulating layer 112 can be stacked vertically from the second surface of the core layer 111 toward the first surface of the core layer 111. Therefore, a recess 110C in the upper stacked insulating layer 112 can be provided on the upper surface of the upper stacked insulating layer 112. Similarly, the lower stacked insulating layer 113 can be stacked vertically from the first surface of the core layer 111 toward the second surface of the core layer 111. Therefore, a recess 110C in the lower stacked insulating layer 113 can be provided on the lower surface of the lower stacked insulating layer 113.

[0112] Furthermore, the insulating layer 110 may have a structure in which multiple layers are stacked along a vertical direction, and depending on the stacking structure, at least one surface of the insulating layer 110 may be provided with a protrusion corresponding to the recess 110C (described later). For example, the upper stacked insulating layer 112 may include a first insulating layer and a second insulating layer. In this case, the upper surface of the first insulating layer may be provided with a recess 110C, and the lower surface of the second insulating layer may be provided with a protrusion 120P corresponding to the recess 110C provided on the upper surface of the first insulating layer 110 (see [link to documentation]). Figure 5 That is, the second insulating layer of the upper stacked insulating layer 112 can be stacked in the state where the recess 110C is disposed in the first insulating layer of the upper stacked insulating layer 112. Therefore, the second insulating layer can fill the recess 110C disposed in the first insulating layer and can include the protrusion 120P corresponding to the recess 110C.

[0113] Each of the plurality of recesses 110C provided in the insulating layer 110 may have a uniform curvature. Here, having a uniform curvature may mean that the difference between the width of each recess 110C in the horizontal direction and / or the depth in the vertical direction is less than 1 μm, less than 0.8 μm, or less than 0.5 μm.

[0114] In this embodiment, because the plurality of recesses 110C have uniform curvature, a wiring layer 120 with uniform thickness can be formed on the insulating layer 110. Therefore, height deviations between wiring layers 120 can be minimized, and semiconductor devices 320 and 330 can be stably mounted on the wiring layer 120, thus enabling stable operation of the semiconductor package. Furthermore, in this embodiment, because the recesses 110C with uniform curvature are provided in the insulating layer 110, the adhesion between the insulating layer 110 and the wiring layer 120 can be improved. For example, when the plurality of recesses 110C do not have uniform curvature, problems may arise where plating of the wiring layer 120 cannot be performed smoothly in areas with relatively large curvature or great depth. For example, when plating the wiring layer 120 on the insulating layer 110, plating may not be performed smoothly in areas with relatively large curvature or great depth, resulting in areas that may not be completely filled with metal material and potentially creating gaps between the insulating layer 110 and the wiring layer 120. Voids can reduce the adhesion between the insulating layer 110 and the wiring layer 120, potentially causing the wiring layer 120 to delaminate from the insulating layer 110. Furthermore, due to stress caused by thermal cycling, cracks (or popcorn defects) may appear in the areas providing the voids. In contrast, in this embodiment, because recesses 110C with uniform curvature are provided on the surface of the insulating layer 110, voids can be completely eliminated, and the adhesion between the wiring layer 120 and the insulating layer 110 can be further improved.

[0115] In other words, one surface of the insulating layer 110 in the embodiment may be provided with a plurality of recesses 110C having uniform width and / or depth. In this case, the recesses 110C can provide a certain level of surface roughness for one surface of the insulating layer 110. Therefore, one surface of the insulating layer 110 can be provided with uniform surface roughness. Therefore, the embodiment can further improve the adhesion between the wiring layer 120 and the insulating layer 110, can solve the problem of cracks appearing at the interface between the insulating layer 110 and the wiring layer 120 due to stress caused by thermal cycling, and can form a wiring layer 120 with uniform thickness on the insulating layer 110 by improving electroplating processability.

[0116] Furthermore, the curvature of the recess 110C provided on the surface of the insulating layer 110 may differ from the curvature of the inorganic filler 110F embedded in the insulating layer 110. Here, a different curvature may mean that the shape of the recess 110C and the shape of the inorganic filler 110F are different, but is not limited to this. For example, a different curvature may mean that the inorganic filler 110F embedded in the insulating layer 110 is not exposed to the outside of the insulating layer 110 through the recess 110C. Furthermore, a different curvature may mean that during the process of forming the recess 110C on the surface of the insulating layer 110, the inorganic filler 110F embedded in the insulating layer 110 does not detach from the insulating layer 110.

[0117] In this embodiment, the recess 110C is provided on the surface of the insulating layer 110, while preventing the inorganic filler 110F embedded in the insulating layer 110 from being exposed to and / or detached from the outside of the insulating layer 110. Therefore, this embodiment can solve the physical and / or electrical reliability problems that arise during the process of providing a certain level of surface roughness on the surface of the insulating layer 110 when the inorganic filler 110F of the insulating layer 110 is exposed to and / or detached from the surface of the insulating layer 110.

[0118] Furthermore, at least one of the inorganic fillers 110F embedded in the insulating layer 110 may overlap with a recess 110C disposed on the surface of the insulating layer 110 in a horizontal direction. For example, at least one inorganic filler 110F may be disposed between a plurality of recesses 110C disposed on the surface of the insulating layer 110. In this case, the inorganic filler 110F overlapping with the recess 110C in a horizontal direction can serve as a reinforcing portion that reduces the degree of thermal deformation caused by thermal expansion and / or thermal contraction due to thermal cycling of the insulating layer 110, preventing the aforementioned stress from being transmitted to the wiring layer 120 disposed on the insulating layer 110, and further improving the adhesion between the insulating layer 110 and the wiring layer 120.

[0119] Furthermore, the recess 110C provided on the insulating layer 110 can overlap with the connecting member 200 in the vertical direction. Therefore, the protrusion 120P of the wiring layer 120 corresponding to the recess 110C of the insulating layer 110 can overlap with the connecting member 200 in the vertical direction. Thus, the embodiment can prevent stress caused by thermal cycling from being transmitted to the connecting member 200, ensuring the rigidity of the circuit board, thereby allowing the connecting member 200 to be stably disposed in the circuit board and to operate stably.

[0120] Reference Figure 3 In (a), in conventional technology, a recess corresponding to a certain level of surface roughness is formed on the surface of the insulating layer 10 by a decontamination process.

[0121] In this case, in conventional techniques, recesses are formed on the surface of the insulating layer 10 by performing a decontamination process using chemical reagents to etch and remove contaminants. According to the conventional techniques described above, during the decontamination process of the insulating layer 10, the inorganic filler 10F embedded in the insulating layer 10 may be exposed to the outside of the insulating layer 10. In this case, when the inorganic filler 10F is exposed to the outside of the insulating layer 10, the adhesion between the insulating layer 10 and the wiring layer is reduced. That is, the adhesion between the inorganic filler 10F of the insulating layer 10 and the wiring layer is lower than the adhesion between the resin of the insulating layer 10 and the wiring layer. Therefore, the adhesion between the insulating layer 10 and the wiring layer in the area where the inorganic filler 10F is exposed may be reduced, potentially leading to delamination of the wiring layer from the insulating layer. Furthermore, when the wiring layer and the inorganic filler 10F come into contact with each other, loss of electrical signals and / or power applied to the semiconductor devices 320 and 330 and / or the connection member 200 may occur.

[0122] Additionally, a plurality of recesses are provided on the surface of the conventional insulating layer 10. In this case, the plurality of recesses on the surface of the conventional insulating layer 10 include a first recess 10C1 and a second recess 10C2, wherein the first recess 10C1 is the region from which the resin of the insulating layer 10 is removed during a cleaning process, and the second recess 10C2 corresponds to the space from which the inorganic filler 10F is separated. In this case, the first recess 10C1 and the second recess 10C2 may have different depths in the vertical direction. For example, the depth of the second recess 10C2 in the vertical direction may be greater than the depth of the first recess 10C1 in the vertical direction. Therefore, when an electroless copper plating layer, serving as a seed layer for wiring, is formed on the surface of the insulating layer 10, electroless copper plating may not be performed in at least a portion of the second recess 10C2, thus potentially providing voids. Furthermore, stress caused by thermal cycling may concentrate in the second recess 10C2, which has a relatively large depth, thus potentially reducing the physical and / or electrical reliability of the semiconductor package.

[0123] Furthermore, inorganic fillers can be embedded in the insulating layer 10, giving the insulating layer 10 a certain level of dielectric constant. However, during the decontamination process of the insulating layer 10, the inorganic fillers embedded in the insulating layer 10 can be removed, and the dielectric constant of the removed inorganic fillers can be used to change the insulating layer 10, thereby altering the dielectric properties of the insulating layer 110 and consequently the dielectric properties of the circuit board.

[0124] In contrast, refer to Figure 3 (b) In an embodiment, protrusions with uniform thickness may be provided on the surface of the metal layer, and the metal layer may be stacked on the surface of the insulating layer 110, thereby transferring the recess 110C to the surface of the insulating layer 110 corresponding to the protrusion.

[0125] Therefore, in this embodiment, by using a metal layer with protrusions to form recesses 110C, the inorganic filler 110F embedded in the insulating layer 110 can be kept from being exposed to the surface of the insulating layer 110. For example, when the metal layer with protrusions is pressed down while it is positioned on the surface of the insulating layer 110, the inorganic filler 110F located near the upper surface of the insulating layer 110 can be moved downwards by pressing the metal layer, thus avoiding exposure to the surface of the insulating layer 110. Therefore, this embodiment not only prevents the inorganic filler 110F from being exposed, but also allows the formation of multiple recesses 110C with a more uniform curvature or uniform depth on the upper surface 110T of the insulating layer 110 than conventional techniques.

[0126] Therefore, when stress caused by thermal cycling acts on the insulating layer 110, in the embodiment, since a plurality of recesses 110C with uniform curvature are provided on the upper surface of the insulating layer 110, stress concentration in a specific area of ​​the insulating layer 110 can be prevented, and the stress can be uniformly distributed as a whole, thereby improving the physical and electrical reliability of the semiconductor package.

[0127] Furthermore, in this embodiment, the inorganic filler 110F disposed adjacent to the surface of the insulating layer 110 can be moved into the insulating layer 110 by pressing the metal layer. Therefore, a dense region of the inorganic filler 110F can be disposed in the region adjacent to the recess 110C. A dense region of the inorganic filler 110F can mean that the spacing between multiple inorganic fillers 110F is smaller than the spacing in other regions. Therefore, in this embodiment, a region where the inorganic filler 110F is densely disposed near the surface of the insulating layer 110 can be provided, thereby solving the problem of significant warping of the semiconductor package in a particular direction. For example, in this embodiment, the insulating layer 110 can be firmly held in the region where the inorganic filler 110F is densely disposed, thereby preventing significant warping of the semiconductor package in a particular direction.

[0128] Furthermore, in the embodiments, during the process of forming the recess 110C on the surface of the insulating layer 110, the inorganic filler 110F embedded in the insulating layer 110 can be prevented from detaching from the insulating layer 110. Therefore, the embodiments can prevent the dielectric constant of the insulating layer 110 from changing due to the detachment of the inorganic filler 110F, and can correspondingly improve the dielectric properties of the circuit board.

[0129] Reference Figure 4 In some embodiments, recesses of different depths may be provided on the surface of the insulating layer 110. For example, a first recess 110C having a first depth in the vertical direction may be provided on the surface of the insulating layer 110. The first recess 110C corresponds to a reference. Figure 2 and Figure 3The described recess will therefore omit its detailed description. A second recess 110E with a second depth in the vertical direction, different from the first recess 110C, may be provided on the surface of the insulating layer 110. The second recess 110E may refer to a region provided by etching along with the metal layer on the surface of the insulating layer 110 during a process of removing the metal layer stacked on the surface of the insulating layer 110 by etching. In this case, when the first recess 110C is provided only on the surface of the insulating layer 110, the portion of the surface of the insulating layer 110 where the first recess 110C is not provided may be flat, and a height difference with the first recess 110C may occur. Therefore, in an embodiment, the second recess 110E may be provided among a plurality of first recesses 110C on the surface of the insulating layer 110, thereby minimizing the height difference on the surface of the insulating layer 110. Therefore, in an embodiment, a uniform electroless copper layer may be provided on the surface of the insulating layer 110, concentration of plating current in areas with relatively high heights may be prevented during the electroplating process of the wiring layer 120, and a wiring layer 120 with a uniform thickness may be formed. For example, the second recess 110E can be disposed between a plurality of first recesses 110C and can be used as a bridge to disperse the plating current in the electroplating process of forming the wiring layer 120, thereby further improving the adhesion between the insulating layer 110 and the wiring layer 120, while minimizing the thickness deviation of the wiring layer 120.

[0130] Furthermore, as described above, the wiring layer 120 can be disposed on the surface of the insulating layer 110, and the insulating layer 110 can have a structure in which multiple layers are stacked along a vertical direction. Therefore, recesses and / or protrusions can be provided at the interfaces between the multiple insulating layers and / or at the interfaces between the insulating layer and the wiring layer.

[0131] Reference Figure 5 In some embodiments, the insulating layer 110 may have a structure in which multiple layers are stacked along a vertical direction. In the following, based on... Figure 1 The upper stacked insulating layer 112 will be described as having recesses and / or protrusions at the interfaces between multiple insulating layers and recesses and / or protrusions at the interfaces between the insulating layer and the wiring layer.

[0132] The circuit board may include a first insulating layer 510 and a second insulating layer 520 disposed on the first insulating layer 510. In addition, a wiring layer 530 may be disposed between the first insulating layer 510 and the second insulating layer 520, a first via electrode 540 may be disposed to penetrate at least a portion of the first insulating layer 510, and a second via electrode 550 may be disposed to penetrate at least a portion of the second insulating layer 520.

[0133] The recess 510C may be provided on the upper surface of the first insulating layer 510. The recess 510C may be configured to give the upper surface of the first insulating layer 510 a certain level of roughness, and may be configured to improve the adhesion between the first insulating layer 510 and the second insulating layer 520 and the adhesion between the first insulating layer 510 and the wiring layer 530.

[0134] The upper surface of the first insulating layer 510 may include a first upper surface that contacts the second insulating layer 520 and a second upper surface that contacts the wiring layer 530. A recess 510C may be provided on each of the first and second upper surfaces of the first insulating layer 510.

[0135] The recess 510C provided on the first upper surface of the first insulating layer 510 can be filled with the second insulating layer 520, and the recess 510C provided on the second upper surface of the first insulating layer 510 can be filled with the wiring layer 530.

[0136] For example, a protrusion 520P that fills the recess 510C provided on the first upper surface of the first insulating layer 510 can be provided on the lower surface of the second insulating layer 520. The protrusion 520P provided on the lower surface of the second insulating layer 520 can have a curvature and / or thickness corresponding to the curvature and / or depth of the recess 510C provided on the first upper surface of the first insulating layer 510.

[0137] The protrusion 520P disposed on the lower surface of the second insulating layer 520 can directly contact the upper surface of the first insulating layer 510 without contacting the inorganic filler 510F embedded in the first insulating layer 510, and can overlap with at least one inorganic filler 510F1 embedded in the first insulating layer 510 along the horizontal direction. Therefore, this embodiment can improve the adhesion between the first insulating layer 510 and the second insulating layer 520, improve rigidity to minimize the degree of thermal deformation at the interface between the first insulating layer 510 and the second insulating layer 520 according to thermal cycling, and correspondingly further improve mechanical reliability.

[0138] Additionally, the protrusion 530P that fills the recess 510C provided on the second upper surface of the first insulating layer 510 can be provided on the lower surface of the wiring layer 530. The protrusion 530P provided on the lower surface of the wiring layer 530 can have a curvature and / or thickness corresponding to the curvature and / or depth of the recess 510C provided on the second upper surface of the first insulating layer 510.

[0139] The protrusion 530P disposed on the lower surface of the wiring layer 530 can directly contact the upper surface of the first insulating layer 510 without contacting the inorganic filler 510F embedded in the first insulating layer 510, and can also overlap with at least one inorganic filler 510F1 embedded in the first insulating layer 510F along the horizontal direction. Therefore, the embodiment can further improve the adhesion between the first insulating layer 510 and the wiring layer 530, can improve rigidity to minimize the degree of thermal deformation at the interface between the first insulating layer 510 and the wiring layer 530 according to thermal cycling, and can correspondingly further improve mechanical reliability.

[0140] Furthermore, a first via electrode 540 penetrating the first insulating layer 510 can be formed by filling the interior of a via penetrating at least a portion of the first insulating layer 510 with a conductive material. In this case, during the process of forming the via in the first insulating layer 510, at least one of the inorganic fillers 510F embedded in the first insulating layer 510 can be exposed through the via. Therefore, the first via electrode 540 may include a first side surface 540S1 that contacts the inorganic filler 510F. Furthermore, during the process of forming the via in the first insulating layer 510, at least one of the inorganic fillers 510F embedded in the first insulating layer 510 can detach from the first insulating layer 510. Therefore, the first via electrode 540 may include a second side surface 540S2 protruding toward the outer surface of the first insulating layer 510, while filling the space where the inorganic filler 510F has separated. In this configuration, the second side surface 540S2 of the first via electrode 540 can serve as an anchor to securely fix the first via electrode 540 to the first insulating layer 510, while simultaneously improving the adhesion between the first insulating layer 510 and the first via electrode 540. Therefore, this embodiment can further improve the adhesion between the first insulating layer 510 and the first via electrode 540, thereby further improving the physical and / or electrical reliability of the semiconductor package.

[0141] Furthermore, the recesses provided in the insulating layer can be filled with a protective layer, so that the protrusions corresponding to the recesses provided on the surface of the insulating layer can be provided on the lower surface of the protective layer.

[0142] Reference Figure 6 The circuit board may include an insulating layer 610, a wiring layer 620, a via electrode 630, a protective layer 650, and a bump layer 640. The insulating layer 610 may refer to the outermost (e.g., the uppermost) insulating layer among the multiple insulating layers described in the foregoing embodiments.

[0143] Multiple recesses 610C can be provided on the surface of the insulating layer 610. That is, the recesses 610C can be provided on the upper surface of the insulating layer 610 and can be recessed toward the lower surface of the insulating layer 610. The recesses 610C can be configured to give the upper surface of the insulating layer 610 a certain level of roughness and can be configured to improve the adhesion between the insulating layer 610 and the protective layer 650 and the adhesion between the insulating layer 610 and the wiring layer 620.

[0144] The upper surface of the insulating layer 610 may include a first upper surface of the contact protective layer 650 and a second upper surface of the contact wiring layer 620. The recess 610C may be provided on each of the first and second upper surfaces of the insulating layer 610.

[0145] The recess 610C provided on the first upper surface of the insulating layer 610 can be filled with a protective layer 650, and the recess 610C provided on the second upper surface of the insulating layer 610 can be filled with a wiring layer 620.

[0146] For example, a protrusion 650P that fills the recess 610C provided on the first upper surface of the insulating layer 610 can be provided on the lower surface of the protective layer 650. The protrusion 650P provided on the lower surface of the protective layer 650 can have a curvature and / or thickness corresponding to the curvature and / or depth of the recess 610C provided on the first upper surface of the insulating layer 610.

[0147] The protrusion 650P disposed on the lower surface of the protective layer 650 can directly contact the upper surface of the insulating layer 610 without contacting the inorganic filler 610F embedded in the insulating layer 610, and can overlap with at least one of the inorganic fillers 610F embedded in the insulating layer 610 along the horizontal direction. Therefore, the embodiment can improve the adhesion between the insulating layer 610 and the protective layer 650, can improve rigidity to minimize the degree of thermal deformation at the interface between the insulating layer 610 and the protective layer 650 according to thermal cycling, and can correspondingly further improve mechanical reliability.

[0148] Furthermore, the protrusion 620P that fills the recess 610C disposed on the second upper surface of the insulating layer 610 can be disposed on the lower surface of the wiring layer 620, and this has been described in the previous embodiments, so its detailed description will be omitted.

[0149] Figure 7 This is a diagram illustrating a semiconductor package according to a second embodiment.

[0150] Reference Figure 7 Compared with the semiconductor package 1000 of the first embodiment, the semiconductor package 2000 of the second embodiment may have a structure that omits the connecting member 200.

[0151] The semiconductor package circuit board 2100 of the second embodiment may include an insulating layer 2110, a wiring layer 2120, a via electrode 2130, a bump layer 2140, a first protective layer 2150, and a second protective layer 2160. Furthermore, depending on the stacking direction of the multiple layers of the insulating layer 2110, recesses and / or protrusions may be provided on the upper and / or lower surfaces, and protrusions corresponding to the recesses may be provided in the wiring layer 2120 and the protective layers 2150 and 2160.

[0152] Furthermore, the recesses and / or protrusions provided in the insulating layer 2110 of the second embodiment, the protrusions provided in the wiring layer 2120, and the protrusions provided in the protective layers 2150 and 2160 are substantially the same as the recesses and / or protrusions of the semiconductor package of the first embodiment, and therefore their description will be omitted.

[0153] Furthermore, the semiconductor package includes a connection portion 2310 and a semiconductor device 2320 disposed on a bump layer 2140 of the circuit board 2100. For example, the circuit board 2100 of the semiconductor package in the second embodiment may be a 2D substrate, so at least one semiconductor device 2320 may be disposed on the circuit board 2100 without including the connection member 200 embedded in the circuit board 2100.

[0154] Figure 8 This is a diagram illustrating a semiconductor package according to a third embodiment.

[0155] Reference Figure 8 The semiconductor package in the third embodiment may differ from the semiconductor package in the first embodiment in terms of the structure of the circuit board 3100.

[0156] The semiconductor package circuit board 3100 of the third embodiment may include an insulating layer 3110, a wiring layer 3120, a via electrode 3130, a bump layer 3140, a first protective layer 3150, and a second protective layer 3160. Furthermore, recesses and / or protrusions may be formed on the surface of the insulating layer 3100; therefore, protrusions may be formed in the protective layers 3150 and 3160 and the wiring layer 3120. The characteristics of the recesses and protrusions formed on the surface of the insulating layer 3110 of the third embodiment, and the protrusions formed in the protective layers 3150 and 3160 and the wiring layer 3120, are substantially the same as those of the semiconductor package of the first embodiment, and therefore their description will be omitted. However, unlike the insulating layer of the first embodiment, the insulating layer 3110 of the circuit board 3100 of the third embodiment has a structure where the uppermost insulating layer is stacked only in one direction; therefore, recesses may be formed on the lower surface of each insulating layer stacked along the vertical direction.

[0157] Furthermore, the semiconductor package includes a connection portion 3310 and a semiconductor device 3320 disposed on a bump layer 3140 of the circuit board 3100. Additionally, the semiconductor package includes a connection member 3200 embedded in an insulating layer 3110 of the substrate 3100. Furthermore, the semiconductor package also includes a second connection portion 3230, which is embedded in the insulating layer 3110 and electrically connects the pad portion 3210 of the connection member 3200 to the wiring layer 3120.

[0158] For example, Figure 1 The circuit board in the first embodiment can be a core circuit board, and Figure 8 The circuit board can be a coreless circuit board. Additionally, it is set... Figure 1 In the first embodiment, each of the uppermost and lowermost wiring layers in the circuit board can protrude above and below the insulating layer 110, respectively. Conversely, [the following is not explicitly stated:] ... Figure 8 Either the uppermost or lowermost wiring layer in the circuit board of the third embodiment may have a structure embedded in the insulating layer 3110. For example, the circuit board 3100 may have an embedded trace substrate (ETS) structure.

[0159] The embodiments can improve the physical and / or electrical reliability of the circuit board and the semiconductor package including the circuit board.

[0160] Specifically, the embodiment includes an insulating layer. The insulating layer includes a resin and an inorganic filler embedded in the resin. In this case, a plurality of recesses are provided on the upper surface of the insulating layer. Furthermore, each of the plurality of recesses provided on the upper surface of the insulating layer may have a curvature different from that of the inorganic filler. For example, the inorganic filler embedded in the insulating layer is not exposed through the recesses provided on the upper surface of the insulating layer.

[0161] Therefore, the embodiments can provide multiple recesses on the upper surface of the insulating layer while preventing the inorganic filler embedded in the insulating layer from being exposed to the outside of the insulating layer. Thus, the embodiments can solve the problem of physical and / or electrical reliability caused by the exposure of the inorganic filler of the insulating layer to the outside during the process of providing a certain level of surface roughness on the upper surface of the insulating layer.

[0162] Specifically, when inorganic fillers are exposed to the outside of the insulation layer, the adhesion between the insulation layer and the wiring layer may be reduced. That is, the adhesion between the inorganic filler of the insulation layer and the wiring layer is lower than the adhesion between the resin of the insulation layer and the wiring layer. Therefore, the adhesion between the insulation layer and the wiring layer in the area where the inorganic filler is exposed may be reduced, which may lead to delamination of the wiring layer from the insulation layer.

[0163] In contrast, this embodiment allows for the transfer of recesses to the upper surface of the insulating layer, corresponding to protrusions in the metal layer, instead of using a decontamination process. This provides recesses of uniform depth on the upper surface of the insulating layer. Therefore, this embodiment prevents inorganic fillers from being exposed to the outside of the insulating layer. As a result, this embodiment allows wiring layers disposed on the same layer to have a uniform thickness and further improves the adhesion between the insulating layer and the wiring layer.

[0164] Furthermore, in conventional techniques using a decontamination process, spaces are formed in the insulating layer where exposed inorganic fillers have detached. In this case, the depth of these detachment spaces in the vertical direction can be greater than the depth of other portions. Therefore, when an electroless copper plating process for forming wiring layers is performed in these detachment spaces, voids are formed because electroless copper plating is not performed in at least a portion of the detachment spaces. Additionally, stress applied to the insulating layer may concentrate in the detachment spaces of the reinforcing members, which have relatively large depths, potentially reducing the physical and / or electrical reliability of the semiconductor package.

[0165] In contrast, this embodiment can eliminate voids by forming uniform recesses on the surface of the insulating layer, thereby further improving the physical and electrical reliability of the semiconductor package. Furthermore, when stress is applied to the insulating layer, this embodiment can prevent stress concentration in specific areas of the insulating layer by providing uniform recesses on the upper surface of the insulating layer, and can further distribute the stress uniformly as a whole, thereby improving the physical and electrical reliability of the semiconductor package.

[0166] In addition, the embodiments can prevent the inorganic filler embedded in the insulating layer from detaching during the process of forming the recess on the surface of the insulating layer, and can prevent the change in the dielectric constant of the insulating layer that may occur due to the detachment of the inorganic filler, thereby further improving the electrical characteristics of the circuit board and semiconductor package.

[0167] Furthermore, the embodiment includes a wiring layer disposed on an insulating layer, and the wiring layer may include protrusions projecting toward the insulating layer. These protrusions may correspond to recesses disposed in the insulating layer. In this case, the protrusions of the wiring layer may overlap, along a horizontal direction, at least one of a plurality of inorganic fillers embedded in the insulating layer. Therefore, the embodiment can improve the rigidity of the circuit board and further enhance mechanical reliability by minimizing the degree of thermal deformation occurring at the interface between the insulating layer and the wiring layer due to thermal cycling by using inorganic fillers overlapping in the horizontal direction as described above.

[0168] Furthermore, the embodiment includes a protective layer disposed on the insulating layer, and the protective layer may include protrusions projecting toward the insulating layer. The protrusions of the protective layer may correspond to recesses disposed in the insulating layer. In this case, the protrusions of the protective layer may overlap, along a horizontal direction, at least one of a plurality of inorganic fillers embedded in the insulating layer. Therefore, the embodiment can improve the rigidity of the circuit board and further improve mechanical reliability by minimizing the degree of thermal deformation occurring at the interface between the insulating layer and the protective layer due to thermal cycling by using inorganic fillers overlapping in the horizontal direction as described above. Furthermore, the embodiment can prevent stress caused by thermal cycling from being transmitted to the bump layer through the protective layer, and thus can prevent cracking in the bump layer due to stress. Therefore, the embodiment can stably mount semiconductor devices on the bump layer, and thus allow the semiconductor package to operate stably.

[0169] Figures 9 to 15 Manufacturing is shown in the order of processes. Figure 1 A diagram illustrating a semiconductor packaging method.

[0170] Reference Figure 9 The embodiments may include the steps of preparing a core layer, forming a cavity in the core layer, setting a connecting member in the cavity of the core layer, and stacking a portion of an upper stacked insulating layer and a portion of a lower stacked insulating layer on the upper and lower parts of the core layer, respectively, to embed the connecting member.

[0171] Next, refer to Figure 10 The process of forming a metal layer on the insulating layer 110 is performed. For example, in an embodiment, a first metal layer 700 including protrusions 710 is formed on the insulating layer 110. Furthermore, in an embodiment, a second metal layer 720 including protrusions 730 is formed below the insulating layer 110.

[0172] Next, refer to Figure 11 In one embodiment, the process of pressing and attaching the first metal layer 700 and the second metal layer 720 to the insulating layer 110 is performed.

[0173] Next, refer to Figure 12 In this embodiment, a process of removing the first metal layer 700 and the second metal layer 720 by etching is performed. Therefore, the insulating layer 110 is provided with recesses 110C corresponding to the protrusions 710 and 730 of the first metal layer 700 and the second metal layer 720.

[0174] Next, refer to Figure 13 In this embodiment, the process of forming wiring layer 120 is performed.

[0175] Next, refer to Figure 14In this embodiment, a step of forming a first protective layer 150 on the insulating layer 110 is performed. Furthermore, in this embodiment, a step of forming a second protective layer 160 below the insulating layer 110 is performed. Additionally, in this embodiment, a step of forming a bump layer 140 penetrating the first protective layer 150 is performed.

[0176] Next, refer to Figure 15 In one embodiment, a process of disposing the connection portion 310 on the bump layer 140 is performed. Subsequently, in another embodiment, a process of mounting semiconductor devices 320 and 330 on the connection portion 310 is performed.

[0177] Furthermore, when a circuit board having the features of this disclosure is used in IT equipment or home appliances (such as smartphones, server computers, or televisions), it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of this disclosure performs semiconductor packaging functions, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical disconnection of terminals supplying power to the semiconductor chip. In addition, when performing signal transmission functions, noise problems can be solved. Therefore, a circuit board having the features of this disclosure enables the stable functioning of IT equipment or home appliances, thus enabling functional integrity and technical interoperability of the entire product and circuit board using this disclosure.

[0178] When a circuit board having the features of this disclosure described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or can safely protect the semiconductor chip controlling the transportation device from external influences, and solve problems such as leakage current, electrical short circuits between terminals, or electrical disconnection of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and circuit board to which this disclosure is applied can achieve functional integrity or technical interoperability with each other.

[0179] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, even with respect to other embodiments, those skilled in the art to which the embodiments pertain can combine or modify the features, structures, and effects shown in each embodiment. Therefore, it should be understood that content related to such combinations and modifications is included within the scope of the embodiments.

[0180] This description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: An insulating layer, with multiple inorganic fillers embedded in the insulating layer; A wiring layer disposed on the insulating layer; as well as A protective layer is disposed on the wiring layer. The wiring layer includes a plurality of protrusions projecting toward the insulating layer, and The protrusion does not contact the plurality of inorganic fillers, and the protrusion overlaps with at least one of the plurality of inorganic fillers in the horizontal direction.

2. The circuit board according to claim 1, wherein, The protective layer includes a plurality of protrusions that project toward the insulating layer.

3. The circuit board according to claim 2, wherein, The protrusions of the protective layer do not contact the plurality of inorganic fillers, and the protrusions of the protective layer overlap with at least one of the plurality of inorganic fillers along the horizontal direction.

4. The circuit board according to claim 3, wherein, At least one of the protrusions of the wiring layer and the protrusions of the protective layer is in direct contact with the insulating layer.

5. The circuit board according to claim 2, wherein, The protrusions of the protective layer overlap with the protrusions of the wiring layer along the horizontal direction.

6. The circuit board according to claim 1, wherein, The thickness of at least one of the plurality of protrusions in the wiring layer is different from the thickness of at least another protrusion in the plurality of protrusions in the wiring layer.

7. The circuit board according to claim 1, wherein, The upper surface of the insulating layer is provided with a recess corresponding to the protrusion of the wiring layer, and The lower surface of the insulating layer is provided with multiple protrusions.

8. The circuit board according to claim 1, further comprising: Connecting members embedded in the insulating layer The connecting member overlaps with at least one of the plurality of protrusions in the vertical direction.

9. The circuit board according to claim 1, wherein, The curvature of the protrusion is different from the curvature of the inorganic filler.

10. The circuit board according to claim 1, further comprising: A via electrode, the via electrode penetrating at least a portion of the insulating layer in a vertical direction and connecting to the wiring layer, and At least one of the plurality of inorganic fillers contacts the side surface of the through-hole electrode.

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