Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor with improved high-temperature reliability by suppressing the entrainment of the electric field in the electrode discontinuity formed in the counter electrode portion of the internal electrode layer. [Solution] A multilayer ceramic capacitor 1 comprising an inner layer in which an inner dielectric layer and an inner electrode layer are alternately stacked, wherein the inner electrode layer has an electrode discontinuity FR at the opposing electrode portions 311 and 321 where the inner electrode layer is discontinuous, and when viewed in a cross section parallel to the stacking direction and the length direction, the ratio of the total area of ​​pores AH with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuity FR is such that the end portion EE of the opposing electrode portions 311 and 321 is 15 percent points or more lower than the central portion of the opposing electrode portions 311 and 321.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately laminated, and further, dielectric layers are laminated on the upper and lower surfaces thereof, and a pair of external electrodes formed on both end faces of the laminate. The internal electrode layer is formed by a counter electrode portion that forms capacitance and a lead-out electrode portion that extends from the counter electrode portion toward the external electrode.

[0003] In recent years, with the progress of electronics technology, by reducing the thickness of the dielectric layer and the internal electrode layer, the number of dielectric layers and internal electrode layers to be laminated is increased, and miniaturization and high capacitance of the multilayer ceramic capacitor have been promoted.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the counter electrode portion of the internal electrode layer, there is an electrode discontinuous portion where the internal electrode layer is discontinuous. In this electrode discontinuous portion, electric field entrainment occurs, resulting in electric field concentration and shortening the life of the multilayer ceramic capacitor. In particular, when the thickness of the internal electrode layer is reduced, an electrode discontinuous portion is likely to be formed at the end of the counter electrode portion, and the high-temperature reliability of the multilayer ceramic capacitor is reduced.

[0006] The present invention aims to provide a multilayer ceramic capacitor with improved high-temperature reliability by suppressing the entrainment of electric fields in electrode discontinuities formed in the counter electrode portion of the internal electrode layer. [Means for solving the problem]

[0007] The inventors have discovered that the high-temperature reliability of a multilayer ceramic capacitor can be improved by adjusting the ratio of the total area of ​​pores of a predetermined size to the total area of ​​electrode discontinuities, or the ratio of the total area of ​​regions where a predetermined element is segregated to the total area of ​​electrode discontinuities, in the central and end portions of the opposing electrode portion of the internal electrode layer, and have completed the present invention.

[0008] In other words, the present invention provides a laminate comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction; and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction; two side surfaces opposite to each other in the width direction perpendicular to the stacking direction; and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction. A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The internal electrode layer has an electrode discontinuity portion where the internal electrode layer is discontinuous in the opposing electrode portion where adjacent internal electrode layers face each other in the stacking direction. When viewing a cross-section parallel to the stacking direction and the length direction, In a multilayer ceramic capacitor, the ratio of the total area of ​​pores with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuity is such that the end of the counter electrode portion is 15 percentage points or more lower than the central portion of the counter electrode portion.

[0009] Furthermore, the present invention includes an inner layer portion comprising a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate comprising two main surfaces facing each other in the stacking direction, two side surfaces facing each other in the width direction perpendicular to the stacking direction, and two end surfaces facing each other in the length direction perpendicular to the stacking direction and the width direction. A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The internal electrode layer has an electrode discontinuity portion where the internal electrode layer is discontinuous in the opposing electrode portion where adjacent internal electrode layers face each other in the stacking direction. When viewing a cross-section parallel to the stacking direction and the length direction, In a multilayer ceramic capacitor, the ratio of the total area of ​​the region where Y is segregated to the total area of ​​the electrode discontinuity is such that the end of the counter electrode portion is 20 percent points or more lower than the central portion of the counter electrode portion. [Effects of the Invention]

[0010] According to the present invention, it is possible to suppress the entrainment of the electric field in the electrode discontinuity formed in the counter electrode portion of the internal electrode layer, thereby providing a multilayer ceramic capacitor with improved high-temperature reliability. [Brief explanation of the drawing]

[0011] [Figure 1] This is a perspective view showing a multilayer ceramic capacitor. [Figure 2] Figure 1 shows a cross-sectional view (LT section) of a multilayer ceramic capacitor along line II-II. [Figure 3] Figure 1 shows a cross-sectional view (WT section) of a multilayer ceramic capacitor along line III-III. [Figure 4] Figure 1 is a schematic diagram showing the structure of the inner layer of a multilayer ceramic capacitor. [Figure 5] This is an enlarged view (LT section) of the electrode discontinuity at the end of the opposing electrode. [Figure 6]It is an enlarged view (LT cross-section) of the electrode discontinuity portion at the center of the counter electrode portion. [Figure 7] It is an enlarged view (LT cross-section) of the electrode discontinuity portion at the end of the counter electrode portion. [Figure 8] It is an enlarged view (LT cross-section) of the electrode discontinuity portion at the center of the counter electrode portion.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. In addition, the drawings may be schematically simplified for the purpose of explaining the content of the invention, and the ratio of the drawn components or the dimensions between the components may not match the ratios of those dimensions described in the specification. Also, there may be cases where the components described in the specification are omitted in the drawings or where the number is omitted in the drawing.

[0013] (Multilayer Ceramic Capacitor) FIG. 1 is a perspective view showing a multilayer ceramic capacitor, FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1. FIG. 4 is a schematic view showing the structure of the inner layer portion of the multilayer ceramic capacitor shown in FIG. 1. The multilayer ceramic capacitor 1 shown in FIGS. 1 to 4 includes a laminate 10 and an external electrode 40. The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0014] In FIGS. 1 to 3, an XYZ orthogonal coordinate system is shown. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Accordingly, the cross-section shown in FIG. 2 is also referred to as an LT cross-section, and the cross-section shown in FIG. 3 is also referred to as a WT cross-section. Note that the length direction L, the width direction W, and the stacking direction T do not necessarily have a mutually orthogonal relationship, and may have a mutually intersecting relationship.

[0015] The size of the multilayer ceramic capacitor is preferably such that the dimension in the length direction L is 0.2 mm or more and 10 mm or less, the dimension in the width direction W is 0.1 mm or more and 10 mm or less, and the dimension in the stacking direction T is 0.1 mm or more and 10 mm or less.

[0016] (Stacked body) The stacked body 10 has a substantially rectangular parallelepiped shape, and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. The surfaces of each surface are provided with irregularities or may be rough. Note that when there is no need to particularly distinguish and explain between the first main surface TS1 and the second main surface TS2, they are collectively referred to as the main surface TS. When there is no need to particularly distinguish and explain between the first end surface LS1 and the second end surface LS2, they are collectively referred to as the end surface LS. When there is no need to particularly distinguish and explain between the first side surface WS1 and the second side surface WS2, they are collectively referred to as the side surface WS for explanation.

[0017] It is preferable that the corners and ridge lines of the stacked body 10 are rounded. A corner is a portion where three surfaces of the stacked body 10 intersect, and a ridge line portion is a portion where two surfaces of the stacked body 10 intersect.

[0018] As shown in FIGS. 2 and 3, the stacked body 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in the stacking direction T. Further, in the stacking direction T, the stacked body 10 has an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged so as to sandwich the inner layer portion 100.

[0019] The inner dielectric layer 20i constituting the inner layer 100 and the outer dielectric layer 20o constituting the outer layer 200 may have different component compositions because the functions required for the inner layer 100 and the outer layer 200 are different. For example, the inner dielectric layer 20i is required to have a high dielectric constant, while the outer dielectric layer 20o is required to have high moisture resistance, weather resistance, and strength. Therefore, the dielectric layer constituting the inner layer 100 will be described as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer 200 will be described as the outer dielectric layer 20o. However, when there is no need to distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be described together as the dielectric layer 20.

[0020] (Inner layer) Figure 4 schematically shows the structure of the inner layer 100. The inner layer 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer 100, the plurality of internal electrode layers 30 are arranged opposite each other via the inner dielectric layers 20i. The inner layer 100 is the part that generates capacitance and functions substantially as a capacitor.

[0021] Multiple dielectric layers 20 are composed of dielectric materials. The dielectric material contains at least one of Ca, Zr, and Sr, and includes a material having a perovskite-type structure. More specifically, the dielectric material is a temperature-compensated dielectric material with a small capacitance change rate due to temperature, and contains at least one of Ca, Zr, and Sr as the main component of the dielectric material. For example, in the dielectric material, at least one of Ca and Sr constitutes the A site of the perovskite-type structure (ABO3), and at least one of Zr, Ti, and Hf constitutes the B site of the perovskite structure.

[0022] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably, for example, 0.2 μm or more and 15 μm or less. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0023] (outer layer) The first outer layer 201 is located on the side of the first main surface TS1 of the laminate 10, and the second outer layer 202 is located on the side of the second main surface TS2 of the laminate 10. More specifically, the first outer layer 201 is located between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1, and the second outer layer 202 is located between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2. The first outer layer 201 and the second outer layer 202 do not include the internal electrode layers 30.

[0024] The outer layer 200 is formed of an insulating material. The first outer layer 201 and the second outer layer 202 can each be composed of multiple outer dielectric layers 20o, or they may be composed of a single outer dielectric layer 20o. Furthermore, the outer dielectric layer 20o can be composed of the same dielectric material as the inner dielectric layer 20i, but it may contain different components from the inner dielectric layer 20i depending on the desired function.

[0025] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0026] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

[0027] The opposing electrode portion 311 and the opposing electrode portion 321 face each other in the stacking direction T of the laminate 10 via the inner dielectric layer 20i. The shape of the opposing electrode portion 311 and the opposing electrode portion 321 is not particularly limited and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are parts that generate capacitance and function substantially as capacitors.

[0028] The lead-out electrode portion 312 extends from the counter electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead-out electrode portion 322 extends from the counter electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The widthwise lengths W of the counter electrode portion 311 and the lead-out electrode portion 312 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed first end face LS1. The widthwise lengths W of the counter electrode portion 321 and the lead-out electrode portion 322 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed second end face LS2.

[0029] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0030] The first internal electrode layer 31 and the second internal electrode layer 32 mainly contain metallic Ni. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also mainly contain at least one metal selected from, for example, Cu, Ag, Pd, Sn, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy, or may contain other components. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition system as the ceramic contained in the inner dielectric layer 20i as components other than the main component. In this specification, the main component metal refers to the metal component with the highest weight percentage.

[0031] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited.

[0032] Furthermore, a method for measuring the thickness of the inner dielectric layer 20i and the inner electrode layer 30 is, for example, to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction, or further, the average of measurements taken at multiple locations in the stacking direction.

[0033] As shown in Figure 3, the laminate 10 has, in the width direction W, an electrode-facing portion W30 on which the internal electrode layer 30 faces, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode-facing portion W30. The first side gap portion WG1 is located between the electrode-facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode-facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but include only the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also referred to as W gaps.

[0034] As shown in Figure 2, the laminate 10 has, in the longitudinal direction L, an electrode-facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode-facing portion L30 and the first end face LS1, and the second end gap portion LG2 is located between the electrode-facing portion L30 and the second end face LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap portion LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the inner dielectric layer 20i, and the second end gap portion LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap portion LG1 functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap portion LG2 functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap portion LG1 and the second end gap portion LG2 are also called L gaps.

[0035] The electrode opposing portion L30 is located where the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32 are located. The leading electrode portion 312 of the first internal electrode layer 31 is located where the first end gap portion LG1 is located, and the leading electrode portion 322 of the second internal electrode layer 32 is located where the second end gap portion LG2 is located.

[0036] One method for measuring the thickness of the laminate 10 is to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing, or the WT cross-section near the center in the length direction of the laminate exposed by polishing, using a scanning electron microscope. Alternatively, each value may be the average of measurements taken at multiple locations in the length or width direction. Similarly, a method for measuring the length of the laminate 10 is, for example, to observe the LT cross-section near the center in the width direction of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction. Similarly, a method for measuring the width of the laminate 10 is, for example, to observe the WT cross-section near the center in the longitudinal direction of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction.

[0037] (external electrode) The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0038] The first external electrode 41 is positioned on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second external electrode 42 is positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may consist only of the plating layer 416, and the second external electrode 42 may consist only of the plating layer 426.

[0041] The base electrode layer 415 and the base electrode layer 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. In addition, the metal may mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0042] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0043] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-described firing layer, or it may be formed directly on the laminate without forming a firing layer.

[0044] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, the resin layer may consist of multiple layers.

[0045] The thickness of each layer of the base electrode layer 415 and base electrode layer 425, which are fired layers or resin layers, is not particularly limited and may be 2 μm or more and 220 μm or less.

[0046] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.

[0047] The plating layer 416 covers at least a portion of the underlying electrode layer 415, and the plating layer 426 covers at least a portion of the underlying electrode layer 425. The plating layers 416 and 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0048] The plating layers 416 and 426 may each be formed from multiple layers. Preferably, they are a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The plating layers 416 and 426 can also be a three-layer structure by laminating Cu plating, Ni plating, and Sn plating, respectively. The outermost layer may be Au plating.

[0049] The thickness of each layer of plating layer 416 and plating layer 426 is not particularly limited and may be 1 μm or more and 10 μm or less.

[0050] (First Embodiment) A first embodiment of the multilayer ceramic capacitor according to the present invention will be described below. In the first embodiment, the distribution state of pores AH with a circumscribed circle diameter of 500 nm or more in the electrode discontinuity FR of the internal electrode layer 30 is adjusted. The circumscribed circle diameter refers to the diameter of a virtual circle that circumscribes the pore AH in a cross-section parallel to the stacking direction T and the length direction L.

[0051] (Area of ​​stomata) The internal electrode layer 30 has electrode discontinuities FR where the internal electrode layer 30 is discontinuous in the opposing electrode portions 311 and 321 where adjacent internal electrode layers 30 face each other in the stacking direction T. When viewing a cross section parallel to the stacking direction T and the length direction L, i.e., the LT cross section, the ratio of the total area of ​​pores AH with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuities FR is more than 15 percentage points lower at the ends EE of the opposing electrode portions 311 and 321 than at the central portion EC of the opposing electrode portions 311 and 321 (Figures 5 and 6).

[0052] The end EE of the counter electrode portions 311 and 321 refers to the portion extending from the end of the counter electrode portion 311 or 321 toward the center in the longitudinal direction L, within a length of 50 μm (Figure 5). Furthermore, the central portion EC of the counter electrode portions 311 and 321 refers to the portion of the counter electrode portions 311 and 321 that is centered on the midpoint of the length L, with a length L of 50 μm (Figure 6).

[0053] If pores AH with a circumscribed circle diameter of 500 nm or more exist in the electrode discontinuity FR at the end EE of the counter electrode portions 311 and 321 of the internal electrode layer 30, the effective thickness of the dielectric layer 20 that bears the winding electric field becomes thinner. As a result, the electric field strength applied to the dielectric layer in the electrode discontinuity FR increases, and high-temperature reliability decreases. The multilayer ceramic capacitor 1 of the present invention improves high-temperature reliability by suppressing the proportion of area in which pores AH with a circumscribed circle diameter of 500 nm or more exist in the electrode discontinuity FR at the end EE of the counter electrode portions 311 and 321 of the internal electrode layer 30.

[0054] (Second embodiment) Next, a second embodiment of the multilayer ceramic capacitor according to the present invention will be described. In the second embodiment, the segregation state of a predetermined element in the electrode discontinuity FR of the internal electrode layer 30 is adjusted.

[0055] (segregation) The internal electrode layer 30 has electrode discontinuities FR where the internal electrode layer 30 is discontinuous in the opposing electrode portions 311 and 321 where adjacent internal electrode layers 30 face each other in the stacking direction T. When viewing a cross section parallel to the stacking direction T and the length direction L, i.e., an LT cross section, the ratio of the total area of ​​the region GS where Y (yttrium) segregates to the total area of ​​the electrode discontinuities FR is more than 20 percentage points lower at the EE ends of the opposing electrode portions 311 and 321 than at the central EC of the opposing electrode portions 311 and 321 (Figures 7 and 8).

[0056] The end EE of the counter electrode portions 311 and 321 refers to the portion extending from the end of the counter electrode portion 311 or 321 toward the center in the longitudinal direction L, within a length of 50 μm (Figure 7). Furthermore, the central portion EC of the counter electrode portions 311 and 321 refers to the portion of the counter electrode portions 311 and 321 that is centered on the midpoint of the length L in the length direction, and whose length L is within a range of 50 μm (Figure 8).

[0057] Y has a lower resistivity than the dielectric forming the dielectric layer 20. Therefore, if segregation containing Y exists in the electrode discontinuity FR at the end EE of the counter electrode portions 311 and 321 of the internal electrode layer 30, the electric field portion of the winding electric field that is distributed to the segregation becomes low, and the electric field strength distributed to the region of the dielectric layer other than the segregation in the stacking direction T becomes high, resulting in a decrease in high-temperature reliability. The multilayer ceramic capacitor 1 of the present invention improves high-temperature reliability by suppressing Y segregation in the electrode discontinuity FR at the end EE of the counter electrode portions 311 and 321 of the internal electrode layer 30.

[0058] (Manufacturing of multilayer ceramic capacitors) Next, we will explain an example of a manufacturing method for multilayer ceramic capacitors.

[0059] First, a ceramic green sheet for forming the dielectric layer and a conductive paste for the internal electrodes are prepared. The conductive paste for the internal electrodes contains a binder and a solvent, but known organic binders and organic solvents can be used. The conductive paste for the internal electrodes forms the internal electrodes 53.

[0060] Next, a conductive paste for internal electrodes is printed onto the ceramic green sheet in a predetermined pattern, for example, by screen printing or gravure printing, thereby forming the internal electrode pattern.

[0061] Next, a predetermined number of outer layer ceramic green sheets without internal electrode patterns are stacked, followed by sequentially stacking ceramic green sheets with internal electrodes formed on top, and then a predetermined number of outer layer ceramic green sheets are stacked on top of those to create a laminated sheet. The ceramic green sheets form the dielectric layer 20 that constitutes the multilayer ceramic capacitor 1.

[0062] The resulting laminated sheet is pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block. Next, the laminated block is cut to a predetermined size, and laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other means.

[0063] Furthermore, the laminated body 10 is fabricated by firing the laminated chips. The firing temperature at this time depends on the dielectric and internal electrode materials, but is preferably between 900°C and 1300°C.

[0064] The distribution of regions GS in which pores AH and Y with a circumscribed circle diameter of 500 nm or more are segregated in the electrode discontinuity FR formed at the end EE and central EC of the opposing electrode portions 311 and 321 of the internal electrode layer can all be controlled by adjusting the oxygen partial pressure during the firing process of the laminated chip.

[0065] Next, the conductive paste for the base electrode layer 415 is applied to the first end face LS1 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Similarly, the conductive paste for the base electrode layer 425 is applied to the second end face LS2 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Subsequently, the base electrode layers 415 and 425, which are fired layers, are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0066] As described above, the base electrode layers 415 and 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing it, or the base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0067] Subsequently, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through these steps, a multilayer ceramic capacitor 1 is obtained. [Examples]

[0068] (Postomata and high-temperature load reliability) An evaluation test performed on the multilayer ceramic capacitor 1 according to the first embodiment will now be described. Multilayer ceramic capacitors with the following specifications were used as samples, and samples with adjusted pore distribution were manufactured in batches. Samples within each batch were manufactured under the same manufacturing conditions. For each example and comparative example, five samples (n=5) for measuring the distribution of pores (AH) with a circumscribed diameter of 500 nm or more, and seventy-seven samples (n=77) for high-temperature load testing were taken from the same batch. For the measurement of the distribution of pores (AH) with a circumscribed diameter of 500 nm or more, the average value of the measurement results was used for evaluation.

[0069] (specification) • Dimensions of the multilayer ceramic capacitor: (L dimension) 3.15mm, (W dimension) 1.65mm, (T dimension) 1.65mm • Ceramic material: (Ba,Sr,Ca)ZrO3 ·Capacity: 0.01μF ·Internal electrode layer: Ni

[0070] (Measurement of stomata) After impregnating the peripheral area of ​​the sample with epoxy resin and allowing it to harden, the sample was polished together with the epoxy resin to half its width. The LT cross-sections of the end portions EE of the counter electrode portions 311 and 321 of the internal electrode layer 30, and the LT cross-sections of the central portion EC of the counter electrode portions 311 and 321 of the internal electrode layer 30 were observed using a field emission scanning electron microscope (FE-SEM) to obtain a compositional image (backscattered electron compositional image) due to backscattered electrons. The observation conditions were a measurement target area of ​​50 μm × 50 μm, an acceleration voltage of 15 kV, and an image size of 240 × 240 pixels.

[0071] The obtained backscattered electron composition image is binarized using image analysis software to determine the number of pixels in the area occupied by the electrode discontinuity FR and the number of pixels in the area occupied by pores AH with a circumscribed circle diameter of 500 nm or more at the end EE and central EC of the opposing electrode portions 311 and 321 of the internal electrode layer 30. From the ratio of these pixel counts, the ratio of the total area of ​​pores AH with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuity FR is calculated.

[0072] The method for measuring the circumscribed circle diameter of stomata involves using image analysis software to binarize the compositional image obtained from backscattered electrons (backscattered electron compositional image), determining the circumscribed circle for the stomata (dark area), calculating the diameter of this circumscribed circle, and defining this as the circumscribed circle diameter.

[0073] (Evaluation of high-temperature load reliability) • Applied voltage: 756V (×1.2WV) ·Temperature: 125℃ • Evaluation criteria: For the sample that failed first, if the time until the failure occurred was less than 2000 hours, it was marked as × (fail), and if it was 2000 hours or more, it was marked as ○ (pass).

[0074] [Table 1]

[0075] Regarding the ratio of the total area of ​​pores AH with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuity FR, it was confirmed that good results were obtained when the end EE of the counter electrode was 15 percent points or more lower than the central EC of the counter electrode.

[0076] (Segregation of Y and high-temperature load reliability) The evaluation test performed on the multilayer ceramic capacitor 1 according to the second embodiment will now be described. Using multilayer ceramic capacitors with the above specifications as samples, samples with adjusted Y segregation states were manufactured in batches. Each batch of samples was manufactured under identical conditions. For each example and comparative example, 5 samples (n=5) for segregation state measurement and 77 samples (n=77) for high-temperature load testing were prepared from the same batch. The average value of the measurement results was used for evaluation of the segregation state.

[0077] (Measurement of segregation) The region where Y segregates can be defined by the number of X-ray photons per unit time, or cps (counts per second), obtained by WDX. Specifically, from the elemental mapping of FE-WDX, cells where the Y count is greater than or equal to a predetermined value (unit: cps) are defined as the Y segregation region GS. The criterion for the number of counts required to define a region where Y segregates is 30 cps or higher.

[0078] The area of ​​the Y segregation region GS can be represented by the number of cells showing 30 cps or more. Furthermore, the area of ​​the electrode discontinuity region FR can be represented by the number of cells in the region corresponding to the electrode discontinuity region FR. This allows for the calculation of the ratio of the total area of ​​the Y segregation region GS to the total area of ​​the electrode discontinuity region FR.

[0079] The specific measurement method is as follows: • Impregnate the area around the measurement sample with epoxy resin and allow it to harden. The sample, including the epoxy resin, is polished in a way that allows observation of a cross-section parallel to the width direction W, the length direction L, and the lamination direction T, up to the center in the width direction W. Elemental mapping will be performed using FE-WDX (device name: EPMA-8050G (product name)). The observation conditions were 3300x magnification, 15kV acceleration voltage, 240x240 pixels image size, 45ms / pixel integration time, and 50nA beam current. The Y count (cps) was quantified for each cell.

[0080] (Evaluation of high-temperature load reliability) • Applied voltage: 756V (×1.2WV) ·Temperature: 125℃ • Evaluation criteria: For the sample that failed first, if the time until the failure occurred was less than 2000 hours, it was marked as × (fail), and if it was 2000 hours or more, it was marked as ○ (pass).

[0081] [Table 2]

[0082] We confirmed that a good result in the evaluation of high-temperature reliability is obtained when the ratio of the total area of ​​Y segregation to the total area of ​​the electrode discontinuity FR is 20 percentage points or more lower at the end EE of the counter electrode portions 311 and 321 than at the central EC of the counter electrode portions 311 and 321.

[0083] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention. [Explanation of symbols]

[0084] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Counter electrode section 312 Extraction electrode section 32 Second internal electrode layer 321 Counter electrode section 322 Extraction electrode section 40 External electrode 41 First external electrode 415 Base electrode layer 416 Plating layer 42 Second external electrode 425 Base electrode layer 426 Plating layer 100 Inner layer 200 Outer layer 201 First outer layer 202 Second outer layer AH Pores with a circumscribed circle diameter of 500 nm or more EC Counter electrode section (central part) End portion of the EE counter electrode FR electrode discontinuity GS segregation region L30 Electrode facing part LG1 First end gap section LG2 Second end gap section W30 Electrode facing part WG1 First side gap section WG2 Second side gap section L (Length direction) T Stacking direction W (width direction) LS end face LS1 First end face LS2 Second end face TS Main Surface TS1 First main surface TS2 Second main surface WS side WS1 First Aspect WS2 Second Aspect

Claims

1. A laminate comprising an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction perpendicular to the stacking direction, and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The internal electrode layer has an electrode discontinuity portion where the internal electrode layer is discontinuous in the opposing electrode portion where adjacent internal electrode layers face each other in the stacking direction. When viewing a cross-section parallel to the stacking direction and the length direction, A multilayer ceramic capacitor in which the ratio of the total area of ​​pores with a circumscribed circle diameter of 500 nm or more to the total area of ​​the electrode discontinuity is such that the end of the counter electrode portion is 15 percentage points or more lower than the central portion of the counter electrode portion.

2. A laminate comprising an inner layer portion including a plurality of inner dielectric layers and a plurality of inner electrode layers stacked alternately in the stacking direction, and an outer layer portion sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposite to each other in the stacking direction, two side surfaces opposite to each other in the width direction perpendicular to the stacking direction, and two end surfaces opposite to each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes connected to the internal electrode layer are provided on the two end faces, Equipped with, The internal electrode layer has an electrode discontinuity portion where the internal electrode layer is discontinuous in the opposing electrode portion where adjacent internal electrode layers face each other in the stacking direction. When viewing a cross-section parallel to the stacking direction and the length direction, In a multilayer ceramic capacitor, the ratio of the total area of ​​the region where Y is segregated to the total area of ​​the electrode discontinuity is such that the end of the counter electrode portion is 20 percentage points or more lower than the central portion of the counter electrode portion.

Images