Semiconductor package structure
By setting electrically connected capacitor elements and chip pads in the semiconductor package structure, the problem of insufficient performance of external capacitors in high-frequency, highly integrated semiconductors is solved, thereby reducing parasitic inductance and resistance, increasing integration, and improving signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU LINK-IC CO LTD
- Filing Date
- 2025-08-19
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, external discrete capacitors are difficult to meet performance requirements in high-frequency, high-integration, and miniaturized semiconductor packages, resulting in increased parasitic inductance and resistance, larger footprint, increased layout design difficulty, poor reliability, and high maintenance costs. Furthermore, they increase signal transmission loss and frequency band shift in radio frequency scenarios.
A chip with exposed pads is placed on a lead frame, and a silicon-based capacitor, electrolytic capacitor, or ceramic capacitor is placed above the chip. The chip is electrically connected to the pads through an electrical connection part. The lead frame, chip, capacitor element, and electrical connection part are encapsulated together, and the package is located around the capacitor element.
It reduces parasitic inductance and resistance, improves integration, simplifies layout design, enhances capacitor reliability and signal transmission efficiency, improves RF link transmit power and anti-interference capability, and reduces maintenance costs.
Smart Images
Figure CN224386023U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Technology
[0002] In existing technologies, external discrete capacitors (such as electrolytic capacitors and ceramic capacitors) are typically electrically connected to the packaged chip via traces on the PCB substrate. Previously, due to the relatively coarse manufacturing process (micrometer level), low operating frequency (MHz level), and limited integration (few transistors), the instantaneous current requirement of the power supply was small. At this time, even though the external discrete capacitors were far from the chip, their parasitic inductance (nH level) and response speed (microsecond level) were sufficient for basic filtering and decoupling requirements. However, as semiconductors have entered an era of high frequency (GHz to tens of GHz), high integration (hundreds of millions of transistors), and miniaturization (millimeter-level dimensions), external discrete capacitors can no longer meet performance requirements, specifically as follows:
[0003] (1) The external capacitor is connected to the chip power supply pin through PCB traces. The physical distance is usually on the order of millimeters (far greater than the micrometer level inside the package), which leads to a significant increase in parasitic inductance (ESL) and parasitic resistance (ESR).
[0004] (2) It occupies the area of the PCB substrate, hinders the miniaturization of the device, results in low integration, and increases the difficulty of layout design;
[0005] (3) Exposed to the external environment, it is significantly affected by environmental and mechanical stress, resulting in poor reliability. Furthermore, if the capacitor fails, it will increase maintenance costs.
[0006] (4) In radio frequency chips (such as 5G base stations and millimeter-wave radar), if the distance between the external filter capacitor and the radio frequency pin is too far, the "insertion loss" on the signal transmission path will increase, and the filter frequency band will shift (due to parasitic parameter interference), which will not effectively suppress spurious signals and ultimately affect the transmit power, receive sensitivity and anti-interference capability of the radio frequency link. Utility Model Content
[0007] The technical problem solved by this utility model is to provide a semiconductor packaging structure that reduces parasitic inductance and parasitic resistance, increases integration, reduces layout design difficulty, improves capacitor reliability, reduces maintenance costs, and improves signal integrity in radio frequency scenarios.
[0008] To address the aforementioned technical problems, this utility model provides a semiconductor packaging structure, comprising: a lead frame; a chip disposed on the lead frame, wherein a passivation layer on the top surface of the chip exposes the chip's pads; a capacitor element disposed above the chip, the capacitor element being a silicon-based capacitor, an electrolytic capacitor, or a ceramic capacitor; an electrical connection portion electrically connected to both the capacitor element and the pads; and a package body encapsulating the lead frame, the chip, the capacitor element, and the electrical connection portion, the package body being located around the capacitor element.
[0009] Optionally, the capacitor element is a positively mounted silicon-based capacitor stacked on the top surface of the chip, and the two ends of the electrical connection portion are electrically connected to the silicon-based capacitor and the pad, respectively.
[0010] Optionally, if the capacitor element is a silicon-based capacitor, the capacitor element is a flip-chip silicon-based capacitor with its bottom surface facing the top surface of the chip, and the electrical connection portion is located between the flip-chip silicon-based capacitor and the pad to separate the flip-chip silicon-based capacitor from the chip.
[0011] Optionally, the electrical connection portion is a bonding wire.
[0012] Optionally, the electrical connection portion is a copper pillar or a solder ball grown on the bottom surface of the silicon-based capacitor.
[0013] Optionally, the capacitor element is an electrolytic capacitor or a ceramic capacitor, and the capacitor element is surface-mount soldered to the top surface of the chip.
[0014] Optionally, the projection of the capacitor element is located within the area of the top surface of the chip on the plane containing the top surface of the chip.
[0015] Optionally, the spacing between the capacitor element and the chip is in the range of 30 micrometers to 80 micrometers.
[0016] Optionally, the package may not be used to form the capacitor element.
[0017] Compared with the prior art, the technical solution of this utility model has the following beneficial effects:
[0018] In the semiconductor packaging structure provided by the technical solution of this utility model, since a chip with exposed pads is set on the lead frame, and a capacitor element, such as a silicon-based capacitor, an electrolytic capacitor, or a ceramic capacitor, is set above the chip, there is an electrical connection between the capacitor element and the pad that enables them to be electrically connected. Furthermore, the package is located around the capacitor element, that is to say, the package is not used to constitute the capacitor element (for example, the package is not used to constitute the capacitor dielectric of the capacitor element), but the lead frame, chip, capacitor element, and electrical connection are jointly packaged by the package. Therefore, it has the following advantages: (1) The distance between the capacitor element and the chip is extremely close, thereby reducing parasitic inductance and parasitic resistance and improving performance. Transmission efficiency is improved, the filter frequency band offset is reduced, and the spurious signal is reduced, thereby improving the transmit power, receive sensitivity and anti-interference capability of the RF link. Especially on the high-frequency signal transmission PIN, the transmission rate of IO can be improved; (2) The capacitor does not occupy the area of the PCB substrate, thereby improving the integration and reducing the difficulty of layout design; (3) The capacitor is protected by the plastic package, thereby being less affected by environmental and mechanical stress, with good reliability and low maintenance cost; (4) The capacitor is placed outside the chip, which can improve the wafer utilization rate, reduce the cost, and reduce the voltage withstand requirement of the device, thereby increasing the working range of the chip or significantly reducing the development cost of the chip under the same application conditions. Attached Figure Description
[0019] Figure 1 This is a top view schematic diagram of the semiconductor packaging structure according to the first embodiment of this utility model;
[0020] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along the A1-A2 direction;
[0021] Figure 3 This is a top view schematic diagram of the semiconductor packaging structure according to the second embodiment of this utility model;
[0022] Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the A1-A2 direction;
[0023] Figure 5 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of the present invention.
[0024] Explanation of reference numerals in the attached figures:
[0025] 10, 100 - Lead frame; 20, 200 - Chip; 30, 31, 300 - Capacitor element; 31 - Finished capacitor; 40, 400 - Electrical connection part. Detailed Implementation
[0026] As described in the background section, existing external discrete capacitors are no longer sufficient to meet performance requirements.
[0027] To solve the above-mentioned technical problems, the present invention provides a semiconductor packaging structure. Since a chip with exposed pads is disposed on the lead frame, and a capacitor element (silicon-based capacitor, electrolytic capacitor, or ceramic capacitor) is disposed above the chip, and there is an electrical connection between the capacitor element and the pads that enables electrical connection between them, and the package is located around the capacitor element, the lead frame, chip, capacitor element, and electrical connection are all packaged together by the package. Therefore, it has the following advantages: (1) The distance between the capacitor element and the chip is extremely close, thereby reducing parasitic inductance and parasitic resistance, improving transmission efficiency, improving filter frequency band offset, and reducing... (1) Reduced spurious signals improve the transmit power, receive sensitivity and anti-interference capability of the RF link, especially on high-frequency signal transmission pins, which can improve the transmission rate of IO; (2) Capacitors do not occupy additional PCB substrate area, thereby improving integration and reducing layout design difficulty; (3) Capacitors are protected by plastic encapsulation, thus being less affected by environmental and mechanical stress, having good reliability and low maintenance cost; (4) Capacitors are placed outside the chip, which can improve wafer utilization, reduce cost, and reduce the voltage withstand requirement of the device, thereby increasing the chip's operating range or significantly reducing the chip's development cost under the same application conditions.
[0028] To make the above-mentioned objectives, features, and beneficial effects of this utility model more apparent and understandable, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0029] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.
[0030] [First Embodiment]
[0031] Figure 1 This is a top view schematic diagram of the semiconductor packaging structure according to the first embodiment of this utility model. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along the A1-A2 direction.
[0032] Please refer to Figure 1 and Figure 2 The semiconductor package structure includes: a lead frame 10, a chip 20, a capacitor element 30, an electrical connection portion 40, and a package body (not shown).
[0033] Chip 20 is mounted on lead frame 10.
[0034] The passivation layer on the top surface of chip 20 exposes the pads of chip 20.
[0035] Capacitor element 30 is positioned above chip 20. Capacitor element 30 is a silicon-based capacitor, an electrolytic capacitor, or a ceramic capacitor.
[0036] In this embodiment, the capacitor element 30 is further a standard-mount silicon capacitor. This standard-mount silicon capacitor is stacked on the top surface of the chip 20. This further improves the integration density.
[0037] Preferably, on the plane where the top surface of the chip 20 is located, the projection of the capacitor element 30, that is, the positively mounted silicon-based capacitor, is located within the range of the top surface of the chip 20.
[0038] The electrical connection part 40 is electrically connected to the capacitor element 30 and the solder pad respectively.
[0039] In this embodiment, the two ends of the electrical connection portion 40 are electrically connected to a positive-mount silicon-based capacitor and a bonding pad, respectively. Specifically, the electrical connection portion 40 is a bonding wire.
[0040] The package encapsulates the lead frame 10, chip 20, capacitor element 30, and electrical connection portion 40. The package is located around the capacitor element 30; that is, the package does not constitute the capacitor element 30.
[0041] In another embodiment, such as Figure 5 As shown, capacitor element 31 can also be an electrolytic capacitor or a ceramic capacitor that is surface-mount soldered to the top surface of chip 20. Specifically, the two electrodes of capacitor element 31 are soldered to the top surface of chip 20.
[0042] Preferably, the projection of the capacitor element 31 is located within the area of the top surface of the chip 20 on the plane containing the top surface of the chip 20.
[0043] [Second Embodiment]
[0044] Figure 3 This is a top view schematic diagram of the semiconductor packaging structure according to the second embodiment of the present invention. Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the A1-A2 direction.
[0045] Please refer to Figure 3 and Figure 4 The semiconductor package structure includes: a lead frame 100, a chip 200, a capacitor element 300, an electrical connection portion 400, and a package body (not shown).
[0046] Chip 200 is mounted on lead frame 100.
[0047] The passivation layer on the top surface of chip 200 exposes the pads of chip 200.
[0048] Capacitor element 300 is positioned above chip 200.
[0049] Furthermore, the spacing H1 between the capacitor element 300 and the chip 200 ranges from 30 micrometers to 80 micrometers.
[0050] In this embodiment, the capacitor element 300 is further a flip-chip silicon capacitor. The bottom surface of the flip-chip silicon capacitor faces the top surface of the chip 200.
[0051] Preferably, on the plane where the top surface of the chip 200 is located, the projection of the capacitor element 300, that is, the positively mounted silicon-based capacitor, is located within the range of the top surface of the chip 200.
[0052] The electrical connection part 400 is electrically connected to the capacitor element 300 and the solder pad respectively.
[0053] In this embodiment, the electrical connection portion 400 is located between the flip-chip silicon capacitor and the pad, thus separating the flip-chip silicon capacitor from the chip 200. Because the electrical connection portion 400 is located between the flip-chip silicon capacitor and the pad, the connection distance between the capacitor element and the chip is further reduced. This helps to further reduce parasitic inductance and parasitic resistance, improve transmission efficiency, improve filter frequency band offset, reduce spurious signals, and thus improve the transmit power, receive sensitivity, and anti-interference capability of the RF link. Furthermore, since the flip-chip silicon capacitor is separated from the chip 200, the thermal impact between them is reduced.
[0054] Furthermore, the electrical connection portion 400 is a copper pillar grown on the bottom surface of the silicon-based capacitor, or the electrical connection portion 400 is a solder ball connected to the bottom surface of the silicon-based capacitor. Thus, the ground bounce effect caused by the parasitic inductance of the wire bonding method can be reduced on high-frequency, high-current pins.
[0055] The package encapsulates the lead frame 100, chip 200, capacitor element 300, and electrical connection portion 400. The package is located around the capacitor element 300, meaning that the package is not used to constitute the capacitor element 300 (for example, the package is not used to constitute the capacitor dielectric of the capacitor element 300).
[0056] In this embodiment of the invention, since a chip with exposed pads is disposed on the lead frame, a capacitor element is disposed above the chip, and an electrical connection portion enabling electrical connection between the capacitor and the pads is provided, and the lead frame, chip, capacitor, and electrical connection portion are jointly packaged by a package, the following advantages are achieved:
[0057] (1) The distance between the capacitor element and the chip is extremely close, thereby reducing parasitic inductance and parasitic resistance, improving transmission efficiency, improving filter frequency band offset, reducing spurious signals and improving the transmit power, receive sensitivity and anti-interference capability of the RF link. Especially on high-frequency signal transmission pins, the transmission rate of IO can be improved.
[0058] (2) Capacitors do not occupy additional PCB substrate area, thereby improving integration and reducing layout design difficulty;
[0059] (3) The capacitor element is protected by the plastic encapsulation, thus it is less affected by environmental and mechanical stress, has good reliability, and low maintenance cost;
[0060] (4) The capacitor is placed outside the chip, which can improve the wafer utilization rate, reduce the cost, and reduce the voltage withstand requirement of the device, which can increase the working range of the chip or significantly reduce the development cost of the chip under the same application conditions.
[0061] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor packaging structure, characterized in that, include: Lead frame; A chip disposed on the lead frame, wherein the passivation layer on the top surface of the chip exposes the pads of the chip; The capacitor element disposed above the chip is a silicon-based capacitor, an electrolytic capacitor, or a ceramic capacitor. The electrical connection portion is electrically connected to both the capacitor element and the solder pad. The package encapsulates the lead frame, the chip, the capacitor element, and the electrical connection portion, with the package located around the capacitor element.
2. The semiconductor packaging structure according to claim 1, characterized in that, The capacitor element is a positively mounted silicon-based capacitor stacked on the top surface of the chip, and the two ends of the electrical connection portion are respectively electrically connected to the silicon-based capacitor and the pad.
3. The semiconductor packaging structure according to claim 1, characterized in that, When the capacitor element is a silicon-based capacitor, the capacitor element is a flip-chip silicon-based capacitor with its bottom surface facing the top surface of the chip, and the electrical connection portion is located between the flip-chip silicon-based capacitor and the pad to separate the flip-chip silicon-based capacitor from the chip.
4. The semiconductor packaging structure according to claim 1, wherein the electrical connection portion is a bonding wire.
5. The semiconductor packaging structure according to claim 1, characterized in that, The electrical connection portion is a copper pillar or a solder ball grown on the bottom surface of the silicon-based capacitor.
6. The semiconductor packaging structure according to claim 1, characterized in that, The capacitor element is an electrolytic capacitor or a ceramic capacitor, and the capacitor element is soldered to the top surface of the chip by surface mount soldering.
7. The semiconductor packaging structure according to claim 1, characterized in that, On the plane containing the top surface of the chip, the projection of the capacitor element lies within the area of the top surface of the chip.
8. The semiconductor packaging structure according to claim 1, characterized in that, The spacing between the capacitor element and the chip ranges from 30 micrometers to 80 micrometers.
9. The semiconductor packaging structure according to claim 1, characterized in that, The package is not used to form the capacitor element.