Integrated Circuit Design Methods

Abstract

To provide a novel method for designing integrated circuits. [Solution] A method for designing an integrated circuit (IC) includes, for a first plurality of routing layers of the IC design, performing an NPD routing operation to define non-preferred direction (NPD) paths on the first plurality of routing layers, and for a second plurality of routing layers of the IC design above the first plurality of routing layers, performing a preferred direction (PD) routing operation to define PD paths on the second plurality of routing layers.

Description

Technical Field

[0001] An integrated circuit (IC) is a device that includes many electronic components such as transistors, resistors, and diodes. These components are often defined on a semiconductor substrate and interconnected by metal wiring and vias to form a plurality of circuit components such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC typically includes a plurality of layers of wiring and vias that interconnect its electronic and circuit components.

Summary of the Invention

[0002] Some embodiments of the present invention provide an integrated circuit (IC) having a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers having no preferred wiring direction and a second set of one or more wiring layers having a preferred wiring direction. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, and the second set of wiring layers includes metal layers above the fifth having consecutive adjacent layers having different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes the third wiring layer but not the fourth wiring layer, and in these embodiments, there is a preferred wiring direction. Also, in some embodiments, the first and second wiring layers belong to the first set, and in other embodiments, the first and second wiring layers belong to the second set.

[0003] In some embodiments, each preferred routing direction is the Manhattan direction (i.e., horizontal or vertical), and the preferred routing directions of different adjacent layers alternate between horizontal and vertical. In other embodiments, the preferred routing directions include other routing directions (e.g., 45-degree or 60-degree routing directions), and consecutive adjacent layers have different preferred routing directions. In some embodiments, the preferred routing direction on each layer is the direction that includes at least a specific threshold amount (e.g., 90% or 95%) of the routing on that layer. In some embodiments, the non-preferred routing on each layer of a first set of routing layers includes interconnect routing (also called routing connections) that traverses eight or more directions.

[0004] In some embodiments, each layer of a first set of wiring layers includes straight wires (i.e., wires having only straight segments) and curved wires (i.e., wires having at least one curved segment). In some embodiments, the first set of wiring layers of the IC is used for wire connections shorter than those defined on a second set of wiring layers. In some embodiments, the first set of wiring layers in some embodiments is used for short local connections, and the second set of wiring layers is used for longer connections.

[0005] In some embodiments, electronic design automation (EDA) tools (e.g., routers and compactors) that define the IC design define paths resulting in metal traces on these layers, while considering preferred and non-preferential directions on each trace layer. In some embodiments, when the first set of trace layers includes a third and / or fourth trace layer, the EDA tool defines NPD curved paths for the third and / or fourth trace layer, but also defines NPD curved paths for the first and second trace layers. However, in some of these embodiments, the first and second trace layers have preferred direction traces in some of their regions, such as regions used for connections required to form electronic components (e.g., transistors) and circuit blocks (e.g., IP blocks) defined on the IC substrate in the locations below these regions. In some embodiments, the EDA tool uses unused space on the first and second trace layers to define NPD straight and / or curved paths, resulting in NPD straight / curved traces being formed on the corresponding layers of the manufactured IC. The NPD straight / curved wiring on the first and second layers reinforces the NPD straight / curved wiring on the third and / or fourth wiring layer.

[0006] In some embodiments, a first set of wiring layers of an IC is used to connect any nets that can be connected via wires on the first set of wiring layers, and a second set of wiring layers is used to connect any nets that cannot be fully connected via wires on the first set of wiring layers. In some of these embodiments, the IC design is based on straight and curved paths defined on the first N layers (where N is an integer greater than 2), but on straight paths only on the next M layers (where M is any integer) of the IC. In some embodiments, the IC design allows for straight and curved paths not only on some of the lower wiring layers, but also on some of the upper wiring layers (e.g., all of the wiring layers, or one or two of the first some lower and upper wiring layers). In some embodiments, a straight path is a path having only one or more straight segments, and a curved path is a path having at least one curved segment.

[0007] In some embodiments, interconnections on a first set of wiring layers are defined using NPD curved first routers, and interconnections on a second set of wiring layers are defined by preferred direction (PD) second routers (e.g., Manhattan routers). The NPD first router generates paths on each layer of the first set of wiring layers that traverse eight or more different directions on that layer. In some embodiments, the first router also generates curved paths on the first set of wiring layers. The PD second router generates paths on each layer of the second set of wiring layers that are primarily aligned with the preferred routing direction of that layer.

[0008] In some embodiments, the NPD first router defines a first set of straight and curved paths that traverse a first set of wiring layers to connect a first set of node pairs that are within a threshold distance of each other, while the PD second router defines a second set of straight paths that traverse a second set of wiring layers to connect a second set of node pairs that are beyond a threshold distance of each other. In some embodiments, the first router may define both straight and curved paths, but in these embodiments, the second router does not generate any curved paths, for example, any paths having at least one curved edge (i.e., a curved edge that is not straight).

[0009] Some embodiments first define routes for a first set of wiring layers in the IC design, and then define routes for a second set of upper wiring layers in the IC design. For example, some embodiments perform NPD detail routing for the first set of wiring layers without first performing global routing for these layers. These embodiments then perform global routing for the second set of wiring layers, and after the global routing, perform detail routing for the second set of wiring layers.

[0010] In some embodiments, NPD detail routing for a first set of wiring layers does not use any preferred wiring direction. This NPD detail routing generates curved paths because it allows all angles of a direction to be explored during the routing pathfinding operation, and then allows curved edges to be used to define paths based on the completed pathfinding. In other embodiments, NPD detail routing generates only straight paths in a large finite number of wiring directions, such as nine or more wiring directions, and does not generate a design with curved path segments. This is because, in these embodiments, the routing operation pathfinding only explores extended paths along a finite number of wiring directions, and then uses only straight edges along these wiring directions to define paths based on the completed pathfinding.

[0011] In some embodiments, the NPD detail router generates curved paths on a subset of layers within a first set of wiring layers (e.g., on the first and second wiring layers) between areas on these layers that have predefined PD straight paths (e.g., on areas on layers 1 and 2 used for routing IP blocks). Thus, in these embodiments, these subsets of the lower wiring layers have areas with predefined PD straight paths and areas between these areas that have NPD straight and curved paths.

[0012] In some embodiments, global and detailed routing for PD wiring layers use the Manhattan preferred direction, while in other embodiments, global and detailed routing for PD wiring layers use other preferred routing directions (e.g., 45-degree or 60-degree routing) in conjunction with or as an alternative to the horizontal and vertical routing directions. In some embodiments, NPD wiring layers are a first set of wiring layers in the IC design, and PD wiring layers are a second set of wiring layers in the IC design. In other embodiments, NPD wiring layers include the first two metal layers, the first three metal layers, or the first four metal layers in the IC design. In yet another embodiment, NPD wiring layers include additional metal layers as described above.

[0013] In some embodiments, the first set of NPDs for the wiring layer includes first and second subsets of the layer. In these embodiments, the method first performs a first detail routing operation on the first subset of the layer (e.g., the first or third wiring layer), and then, after completing the first detail routing operation, performs a second detail routing operation on the second subset of the layer (e.g., the second or fourth wiring layer). In some embodiments, the method performs the first and second detail routing operations by performing the first detail routing operation using an NPD detail router, and then recursively calling the NPD detail router to perform the second detail routing operation.

[0014] The above "Summary of the Invention" is intended to serve as a brief introduction to some embodiments of the present invention. It is not intended to be an introduction or summary of all the subject matter of the invention disclosed herein. The following "Modes for Carrying Out the Invention" and the "Drawings" referenced therein further illustrate not only the embodiments described in the "Summary of the Invention" but also other embodiments. Therefore, in order to understand all the embodiments described herein, it is necessary to carefully consider the "Summary of the Invention," "Modes for Carrying Out the Invention," "Drawings," and "Claims." Furthermore, the subject matter claimed is not limited by the illustrative details in the "Summary of the Invention," "Modes for Carrying Out the Invention," and "Drawings."

[0015] Novel features of the present invention are described in the appended claims. However, for illustrative purposes, some embodiments of the present invention are shown in the following figures. [Brief explanation of the drawing]

[0016] [Figure 1] Several embodiments of ICs having novel non-priority directional routing architectures are shown. [Figure 2] Examples of curved wires defined on the first and second layers of the IC, as well as horizontal and vertical wires defined on the third, fourth, and fifth wiring layers of the IC, are shown in some embodiments. [Figure 3] Here is another example of an IC using a novel NPD wiring architecture in several embodiments. [Figure 4] An example of wires on the first two layers that can only be traversed in 16 possible linear directions is shown. [Figure 5] This shows an IC that uses 45-degree PD wiring on the sixth and seventh metal layers of the IC. [Figure 6A] An example of an IC having primarily short-circuited wires on the first and second metal layers, and primarily longer wires on the fifth metal layer, is shown. [Figure 6B]An example of an IC having NPD curve wiring on the first, second, and third metal layers and having PD wiring on the fourth and fifth metal layers is shown. [Figure 6C] An example of an IC having NPD curve wiring on the first, second, third, and fourth metal layers and having PD wiring on the fifth and higher metal layers is shown. [Figure 6D] An example of an IC having NPD straight and curve wiring on the third and fourth wiring layers and, in addition, having straight and curve wiring in areas not occupied for PD wiring on the first and second wiring layers is shown. [Figure 7] An example of an IC in which all of its metal layers are NPD metal layers having full-width straight and curve wiring is shown. [Figure 8] A routing process for defining a path for connecting a netlist associated with the design of an IC is shown. [Figure 9] Routing processes of several embodiments are shown, which use only detailed routing to define a path for the NPD wiring layer and then use global routing and detailed routing to define a path for the PD wiring layer. [Figure 10] NPD detailed routing processes of several embodiments are shown. [Figure 11] Two boundary crossings for the same net defined by two different detailed router instances for defining NPD paths for two adjacent partitions are shown. [Figure 12] An example of a defined constraint is shown. [Figure 13] An example of another approach used by several embodiments is shown, which uses the path crossing data specified by one detailed router of one partition together with the detailed routers of adjacent partitions. [Figure 14] Another NPD detailed routing process of several embodiments is shown. [Figure 15] A process for manufacturing an IC having a curved path according to several embodiments is shown. [Figure 16]An example of five wiring layers of an IC design generated by one or more physical design tools of some embodiments is shown. [Figure 17] Another example of a metal layer of an IC design defined to have curved path segments is shown. [Figure 18] Examples of two routing processes for defining a curved NPD router to reduce the number of vias are shown. [Figure 19] Examples of two routing processes for defining a curved NPD router to reduce the number of vias are shown. [Figure 20] An example of a set of nets that need to be connected via a path is shown. [Figure 21] An example of a conventional Manhattan path on metal layers 3 and 4 connecting the pins of each of some nets shown in FIG. 20 is shown. [Figure 22] An example of a curved NPD path on metal layers 3 and 4 connecting the pins of each of some nets shown in FIG. 20 is shown. [Figure 23] An example of an NPD router of some embodiments is shown. [Figure 24] An example of a geometric router in some embodiments is shown where a topology router uses a machine learning engine to identify a geometric path for a set of nets that identify topology paths. [Figure 25] An example of a topology router that mosaics a partition into 64 rectangular cells and then uses it to define topology paths is shown. [Figure 26] Two alternative processes for defining a partition size related to the amount of computing resources and memory resources of a computer are shown. [Figure 27] Two alternative processes for defining a partition size related to the amount of computing resources and memory resources of a computer are shown. [Figure 28] An electronic system in which some embodiments of the present invention are implemented is conceptually shown.

Mode for Carrying Out the Invention

[0017] The following detailed description of the present invention includes and illustrates numerous details, examples, and embodiments of the invention. However, it will be apparent to those skilled in the art that the invention is not limited to the embodiments described and that the invention may be carried out without some of the specific details and examples described.

[0018] Some embodiments of the present invention provide an integrated circuit (IC) having a novel non-preferential direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers that do not have a preferred wiring direction and a second set of one or more wiring layers that have a preferred wiring direction. In some embodiments, the first set of wiring layers includes third and fourth wiring layers, and the second set of wiring layers includes a fifth or more metal layer having consecutive adjacent layers with different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes a third wiring layer but does not include a fourth wiring layer, and in these embodiments, there is a preferred wiring direction. Also, in some embodiments, the first and second wiring layers belong to the first set, and in other embodiments, the first and second wiring layers belong to the second set.

[0019] In some embodiments, each preferred routing direction is the Manhattan direction (i.e., horizontal or vertical), and the preferred routing directions (PDs) of different adjacent layers alternate between horizontal and vertical. In other embodiments, the preferred routing directions include other routing directions (e.g., 45-degree or 60-degree routing directions), and consecutive adjacent layers have different preferred routing directions.

[0020] In some embodiments, the preferred routing direction on each layer is the direction that includes at least a specific threshold amount (e.g., 90% or 95%) of the routing on that layer. In some embodiments, the non-preferential routing on each layer of a first set of routing layers includes routing (hereinafter also referred to as interconnects, interconnect lines, wires, or wire segments) that traverses along eight or more directions. In some embodiments, each layer of a first set of routing layers includes curved wires, i.e., wires having at least one curved segment. A curved segment is a segment that is curved rather than straight.

[0021] In some embodiments, electronic design automation (EDA) tools (e.g., routers and compactors) that define the IC design define the paths resulting in metal traces on each trace layer, while considering the preferred and non-preferred directions on those layers. Some embodiments employ both PD and NPD EDA routers. In some embodiments, the PD EDA router does not penalize path segments that traverse along the preferred trace direction on a particular trace layer, while penalizing path segments that traverse along the non-preferred trace direction on a particular trace layer (e.g., it evaluates wire length cost for path segments that traverse along the preferred trace direction, while evaluating wire length cost and penalty cost for path segments that traverse along the non-preferred trace direction). By penalizing path segments that traverse along the non-preferred direction, the EDA router ensures that more than a threshold amount (e.g., 90% or 95%) of paths on a PD trace layer are aligned along the preferred trace direction of that layer.

[0022] In some embodiments, the NPD router defines routes on a first set of wiring layers in an IC design. Unlike the PD router, the NPD router in some embodiments does not penalize routing in any particular direction on the wiring layers within the first set, and therefore does not produce a design in which more than a threshold amount (e.g., 90% or 95%) of routes on the NPD wiring layers are aligned with either a preferred routing direction. In other words, the NPD router in some embodiments does not penalize routes aligned with either a linear or curved direction in order to generate a bias toward eight or fewer preferred routing directions on a layer.

[0023] In some embodiments, an NPD router does not penalize routing along a specific set of nine or more wiring directions, but does penalize routing along one or more wiring directions that are not in the set of wiring directions that are not penalized. In some embodiments, an NPD router (or NPD routing operation) defines curved and / or straight paths that traverse more than eight wiring directions on the wiring layer, while a PD router (or PD routing operation) defines no curved paths at all, and only straight paths. Some examples of such PD routers and NPD routers and routing operations are described further below.

[0024] In some embodiments, a straight path is a path having only one or more straight segments (also called straight edges), and a curved path is a path having at least one curved segment (also called a curved edge). In some embodiments, a preferred direction (PD) straight path is a path having its straight segments on each layer that traverses along the PD of that layer. In other embodiments, a PD straight path is a path having most of its straight segments on each layer that traverses along the PD of that layer.

[0025] Figure 1 shows an IC 100 having a novel non-preferential directional routing architecture in several embodiments. As shown, the IC 100 includes a substrate 105 and a plurality of wiring layers (also called metal layers). The wiring layers include a first wiring layer 102 and a second wiring layer 104 which do not have a preferred routing direction, and a third wiring layer 106, a fourth wiring layer 108, and a fifth wiring layer 110 which have first, second, and third preferred directions (PDs), respectively. Thus, the first and second layers have no wire segments that traverse mainly along one direction (e.g., no more than 90% of the wire segments that traverse mainly along one direction), while the third, fourth, and fifth layers have their wire segments that traverse mainly along the respective preferred routing directions of these layers (i.e., 90% or more of their wires that traverse).

[0026] In Figure 1, the preferred routing directions of different adjacent PD wiring layers alternate between horizontal and vertical directions, i.e., the third wiring layer 106 has a horizontal preferred routing direction, the fourth wiring layer 108 has a vertical preferred routing direction, and the fifth wiring layer 110 has horizontal preferred routing. In some embodiments, IC 100 further includes a metal layer 0, as well as a plurality of other metal layers (e.g., the sixth, seventh, and eighth metal layers). In some embodiments, the metal layer 0 is a substrate layer, or in other embodiments, a first layer on top of the substrate layer.

[0027] Figure 2 shows examples of curved wires 200 defined on the first layer 102 and the second layer 104 of IC 100, as well as horizontal wires 205 and vertical wires 210 defined on the third wiring layer 106, the fourth wiring layer 108, and the fifth wiring layer 110 of the IC. In some embodiments, a number of electronic components (e.g., active components such as transistors and diodes, or passive components such as resistors and capacitors) are defined on the IC substrate, and these electronic components are connected to each other via interconnection wiring (e.g., wires 200, 205, and 210) on wiring layers (e.g., layers 102-110 of IC 100) to form a number of microcircuits (e.g., Boolean gates) and / or larger circuits (e.g., functional blocks).

[0028] Therefore, wires 200, 205, and 210 on metal layers 102-110 are defined to electrically connect circuit nodes (e.g., points, contacts, terminals, or regions of a circuit element, or between two circuit elements of a circuit) to form electrical components (e.g., transistors, diodes, etc.) and circuits. Wires on different metal layers are connected via one or more vias (not shown) to establish a continuous electrical connection for connecting two different nodes via wires that traverse different metal layers. Such a continuous electrical connection can be seen as a multilayer wire or interconnect traversing multiple wiring layers to connect two different electrical nodes of an IC.

[0029] As shown in Figure 2, the first metal layer 102 and the second metal layer 104 have straight wires 201 and curved wires 200 that traverse in any possible direction. In some embodiments, wires on these layers can traverse at any possible angle because these layers do not have a preferred wiring direction. Also, as shown by the curved wire 200a on the first metal layer, a single curved wire can be formed by one or more straight wire segments and one or more curved wire segments on the metal layer. In some embodiments, the curved wire segment is a segment having a shape defined by a nonlinear equation. Also, in some embodiments, the curved wire segment is a continuously smooth wire segment that bends without using acute angles.

[0030] Unlike the first metal layer 102 and the second metal layer 104, the third metal layer 106, the fourth metal layer 108, and the fifth metal layer 110 have a preferred wiring direction and have wiring interconnects that primarily traverse their preferred wiring direction. For example, the third metal layer mainly has horizontal wires, the fourth metal layer mainly has vertical wires, and the fifth metal layer mainly has horizontal wires. PD wiring layers may have wires that traverse non-preferential directions. Thus, as shown in Figure 2 and other figures described below, each PD wiring layer is shown to have a small amount of wires that traverse non-preferential directions. These NPD wire segments on the PD wiring layers are shown in Figure 2 and other figures as small diagonal lines or Manhattan jogs on these layers in the non-preferential direction. These jogs may occur at wire ends on the metal layer or between two other wire segments on the metal layer. Manhattan jogs, as defined in IC design, can result in curved segments on the PD wiring layer of a manufactured IC as a result of manufacturing limitations.

[0031] Figure 3 shows another example of IC300 using a novel NPD routing architecture in several embodiments. Similar to IC100 in Figure 1, IC300 has NPD routing on the first layer 302 and the second layer 304, and conventional Manhattan PD routing on its third layer 306, fourth layer 308, and fifth layer 310. However, unlike IC100, IC300 has only straight wires defined on its first two layers 302 and 304. In other words, the EDA tool defining the routing on these two layers did not define curved wires on these layers, but instead defined only straight wires traversing these layers 302 and 304. Due to manufacturing constraints, small curved segments may be inadvertently formed at angled joints between wire segments, but the EDA tool intentionally does not define such curved segments.

[0032] In this example, the wires on the first two layers 302 and 304 traverse all possible linear directions (i.e., at any angle from 0 to 360 degrees). In other embodiments, the wires on NPD wiring layers (such as the first and second layers in Figure 3) do not traverse all possible linear directions, but rather traverse a number of linear directions (e.g., 10, 16, 20, or more). For example, Figure 4 shows IC400, which is similar to IC300 in Figure 3, except that the wires on the first two layers 402 and 404 can traverse only 16 possible linear directions (i.e., 0, 30, 45, 60, 90, 120, 135, 150, 180, 210, 225, 240, 270, 315, 330, and 360 degrees).

[0033] Other embodiments use other preferred directions for PD wiring layers, such as the third, fourth, and fifth wiring layers in Figures 1-4. Figure 5 shows IC500, which is similar to IC100 in Figure 1, except that it uses 45-degree PD wiring on the sixth metal layer 502 and the seventh metal layer 504 of the IC. The sixth layer 502 has 45-degree PD wiring, and the seventh layer 504 has -45-degree PD wiring. Yet another embodiment uses other preferred directions on the metal layers with PD wiring (e.g., using 60-degree wiring). In some embodiments, the NPD wiring layers of the IC (e.g., the first wiring layer 102 and the second wiring layer 104 of IC100) are used primarily for short local connections, while the PD wiring layers (e.g., the third wiring layer 106, the fourth wiring layer 108, and / or the fifth wiring layer 110) are used primarily for longer connections.

[0034] Figure 6A shows an example of IC600, which has primarily shorter wires on the first and second wiring layers 102 and 104 to facilitate local connections between underlying circuit nodes, and primarily longer wires on the fifth wiring layer 110 for longer connections between circuit nodes. In this example, the third and fourth wiring layers 106 and 108 have a combination of shorter, medium-length, and longer wires. The shorter wires on these layers 106 and 108 are used to connect nearby circuit nodes that cannot be connected via wiring on these layers due to congestion on the NPD wiring layers 102 and 104. Wires on one metal layer (e.g., shorter wires on the third layer 106) are connected via vias to wires on other metal layers (e.g., wires on the first and second layers 102 and 104) to form continuous electrical connections for connecting circuit nodes.

[0035] In some embodiments, the router defining the wiring on the metal layers of the IC600 defines straight and curved wires for the first and second wiring layers of the IC600's EDA design. For all other metal layers, the router defines only straight paths, which may occasionally have Manhattan or diagonal jogs that appear as curved jogs when manufactured. Despite these occasional unintended curved jogs, the IC600 does not have as many curved wire segments on and over metal layer 3 as it does on metal layers 1 and 2.

[0036] This is not true in other embodiments. For example, in some embodiments, the router uses a routing model in which the third routing layer is a routing layer that primarily uses NPD curve routing. Figure 6B shows an example of IC625 whose design is defined by an EDA tool (e.g., a router) using NPD curve routing on the first routing layer 102, the second routing layer 104, and the third routing layer 606. In other embodiments, the router uses a routing model in which the third and fourth routing layers are routing layers that primarily use NPD curve routing. Figure 6C shows an example of IC650 whose design is defined by an EDA tool (e.g., a router) using NPD curve routing on the first routing layer 102, the second routing layer 104, the third routing layer 606, and the fourth routing layer 608.

[0037] For both scenarios shown in Figures 6B and 6C, routers in some embodiments define straight and curved NPD paths on the first and second wiring layers, as well as on the third wiring layer, or on the third and fourth wiring layers. However, in some embodiments, the first and second wiring layers are completely open during the routing of straight or curved NPD paths.

[0038] In other embodiments, the first and second wiring layers are not completely open during the routing of straight or curved NPD paths. For example, in some embodiments, the first two wiring layers have areas used for straight or diagonal PD routing. These areas include, for example, areas used by wires connecting circuit blocks (e.g., IP blocks), which are typically defined on the substrate in positions below these areas. Thus, in such embodiments, the NPD router not only defines straight and curved NPD paths on a third wiring layer or third and fourth wiring layers, but also opportunistically defines straight and curved NPD paths in unused space on the first and second wiring layers that are not used for PD routing necessary to define circuit blocks of ICs (e.g., IP blocks).

[0039] In yet another embodiment, the first and second wiring layers have only PD wiring because they are routed only by the PD router. In these embodiments, the only wiring layer that is an NPD wiring layer is the layer above the first and second wiring layers. For example, in some embodiments, the third and fourth wiring layers are NPD wiring layers having NPD straight and curved wires, and all other layers are PD wiring layers having PD straight wires. In addition to the third and fourth wiring layers, the IC and IC design of other embodiments have one or more other upper wiring layers as NPD wiring layers having NPD straight and curved wires.

[0040] Figure 6D shows one such example. This figure shows IC675 having NPD straight and curved routing on the third and fourth wiring layers 624 and 626, which were designed using NPD routing for the entirety of the third and fourth wiring layers. In addition to these NPD wiring layers, IC675 has NPD straight and curved routing on the first and second wiring layers 620 and 622 in areas not occupied by PD routing on these layers. As shown, the first wiring layer 620 has three areas 680, 682, and 684 with PD routing, and the second wiring layer 622 has two areas 686 and 688 with PD routing. Further as shown, IC675 has NPD straight and curved routing in the remaining areas on the first and second wiring layers 622 outside areas 680-688. In some embodiments, the NPD router that defines NPD routes on the third wiring layer 624 and the fourth wiring layer 626 also opportunistically defines straight and curved NPD routes in areas on the first wiring layer 620 and the second wiring layer 622 that are not used for PD routing of the IC's circuit blocks.

[0041] In some embodiments, the NPD router primarily uses the lower NPD wiring layers (i.e., the first to fourth wiring layers) for short local connections and the upper PD wiring layers (i.e., the fifth and subsequent wiring layers) primarily for longer connections. In some of these embodiments, the NPD router uses the first and second wiring layers for very short connections that can begin and end in one contiguous unused space on one or both of these wiring layers, and then uses the third and fourth wiring layers for short connections that cannot be made by using one contiguous unused space on the first and second wiring layers. In some embodiments, the first and second wiring layers have more PD wiring areas than shown in Figure 6D because the IC has more IP blocks that use such PD wiring on the lower wiring layers of the IC. Also in some embodiments, the IP blocks use PD wiring on other metal layers (e.g., the third and / or fourth metal layers).

[0042] In Figures 6A to 6D, the IC has PD wiring on the top metal layer such that all subsequent metal layers have PD wiring after the last NPD metal layer. This is not the case in other embodiments. For example, in some embodiments, the IC has one or more of its top metal layers and one or more of its bottom metal layers as NPD metal layers, while having PD metal layers between these top and bottom NPD metal layers. In some embodiments, the NPD metal wiring on these top and bottom metal layers is manufactured based on NPD straight or curved paths defined by an NPD router on the wiring layers (of the EDA design) corresponding to these metal layers. In one such embodiment, the IC has external pins defined on its last metal layer, and the top NPD metal layer uses NPD straight and curved wiring (defined based on straight and curved NPD paths) as optimal interconnects (e.g., shortest length and / or shortest delay wiring) for connecting the external pins to via locations on the top layer, allowing signals to quickly traverse the metal layers down or up from pin to pin.

[0043] Figure 7 shows another example of an IC having an NPD metal layer beyond the first to fourth metal layers. In this figure, IC700 is similar to IC600 except that all of its metal layers are NPD metal layers with full-angle straight and curved wiring. Similar to IC600 in Figure 6A, IC700 has shorter wires on the first wiring layer 102 and the second wiring layer 104, mainly to facilitate local connections between the underlying circuit nodes, and longer wires on its third wiring layer 706, fourth wiring layer 708, and fifth wiring layer 710. The fifth wiring layer 710 has longer wires, and the third wiring layer 706 and the fourth wiring layer 708 have a combination of shorter, medium-length, and longer wires.

[0044] In Figure 7, shorter wires on the third and fourth layers are used to connect nearby circuit nodes that cannot be connected via wiring on the first wiring layer 102 and the second wiring layer 104 due to congestion on these layers. Additionally, wires on one metal layer (e.g., shorter wires on the third layer 706) are connected via vias to wires on other metal layers (e.g., wires on the first layer 102 and the second layer 104) to form continuous electrical connections for connecting circuit nodes.

[0045] As described above, some embodiments use several EDA tools to define the IC design that results in the ICs shown in Figures 1 to 7 when manufactured. These EDA tools operate on a routing model that defines straight and / or curved routing of PDs and / or NPDs for each routing layer of the IC design. In some embodiments, the routing models shown for the ICs in Figures 1 to 7 correspond to the routing models that the EDA tools use when designing the IC.

[0046] In some embodiments, the IC includes several multilayer interconnect junctions to allow interconnect wiring to traverse from lower curved non-preferential routing layers (e.g., first and second routing layers) to upper preferential routing layers (e.g., third and fourth routing layers). In some embodiments, the multilayer interconnect junctions are arranged on the IC according to a specific configuration, such as an array. In some embodiments, each multilayer interconnect junction includes several vias connecting a curved non-preferential routing layer (e.g., one of the first and second layers) to a preferential routing layer (e.g., one of the third and fourth layers). In some embodiments, each such junction also includes vias connecting two curved non-preferential routing layers and / or two preferential routing layers.

[0047] In some embodiments, the IC includes several buffers defined within a threshold distance from each of several multilayer interconnect junctions. These buffers are used to drive signals on longer interconnects on preferred directional wiring layers (e.g., third and fourth wiring layers). In some embodiments, the IC also includes several buses on the first and / or second wiring layers, each bus allowing interconnects on the first and second wiring layers to bypass at least one multilayer interconnect junction.

[0048] In some embodiments, wiring connections on lower NPD wiring layers (such as the third and fourth layers, or the first to fourth layers) are defined using an NPD first router, and wiring connections on upper PD wiring layers (such as layer 5 and above) are defined by a PD second router (e.g., a Manhattan router). The NPD first router generates paths on each of the lower layers, traversing eight or more different directions on each of these layers. In some embodiments, the first router also generates curved paths on the lower wiring layers. The use of such routers will be discussed further below.

[0049] Figure 8 shows a routing process 800 that defines routes for connecting a netlist associated with an IC design. The netlist identifies several nets, each corresponding to two or more nodes in the IC design that need to be connected by one or more routes. As illustrated, process 800 uses a first non-preferential directional router (in 805) to define routes on a first set of lower wiring layers, and uses a second preferential directional router (in 810) to define routes on a second set of upper wiring layers. In some embodiments, the second router (used in 810) is one of the commercially available routers sold today, for example, a router sold by Cadence, Inc. or Synopsys, Inc.

[0050] In some embodiments, a first set of wiring layers includes first and second wiring layers, and a second set of one or more wiring layers includes third to seventh wiring layers. In other embodiments, a first set of wiring layers includes first to third wiring layers, and a second set includes fourth to seventh wiring layers. In yet another embodiment, a first set of wiring layers includes first to fourth wiring layers, and a second set includes fifth to seventh wiring layers.

[0051] As described above, in some embodiments, the first and second wiring layers include PD wiring (e.g., Manhattan wiring) for circuit blocks (e.g., IP blocks) used in IC design. In these embodiments, the NPD router uses the space available on the first and second wiring layers to define NPD paths (e.g., straight or curved NPD paths), and also uses a third metal layer, and a fourth metal layer if a fourth layer is available for NPD wiring, to define NPD paths.

[0052] In other embodiments, the first set of wiring layers includes only the third wiring layer, or includes the third and fourth wiring layers but does not include the first and second wiring layers. In some embodiments, only one or more of the lower wiring layers are used to define the NPD straight or curved path. On the other hand, in other embodiments, as further described above, one or more of the upper wiring layers can be used to define the NPD path.

[0053] Furthermore, in some embodiments, the first router (as used in 805) is formed by two routing components: a topology router and a geometric router. In some embodiments, the topology router mosaics each IC design layer into several polygons (also called faces) and then defines topology paths (for connecting the net) by referencing the edges of the mosaicked layers. A particular topology path has its position defined by its relative position to other topology paths along the edges where the particular topology path intersects. In some embodiments, the topology router also models vias between wiring layers traversed by topology paths using nodes associated with the faces of the polygons. In these embodiments, topology paths are defined not only by edges but also by face nodes and their relative positions to each other by referencing these edges and face nodes.

[0054] In some embodiments, each particular topology path is also defined by the coordinates of a pair of nodes (in the netlist) connected by the topology path, or simply by referring to a pair of nodes as the start and end points of the topology path. This particular start and end point of the topology path distinguishes it from a global path. Another feature that distinguishes topology paths from global paths is that a topology path has segments associated with a specific routing layer (defined by a reference to a mosaiced edge intersection) (for example, different segments of a topology path in some embodiments may lie on different routing layers). Global paths, on the other hand, can be defined without referring to the specific routing layers on which those paths intersect.

[0055] Next, in some embodiments, the geometric router defines the geometric realization for each topology path by snapping the topology path to a grid (imposed on the wiring layer) along the wiring direction permitted for the layer. In embodiments that allow curved segments, this snapping allows the wire segment to be curved. In some embodiments, a topology path has no arbitrary width or specific coordinates for its segment other than the coordinates of the two nodes (e.g., two pins) connected by the topology path. Instead of snapping each topology path to the grid, in some embodiments, the geometric router defines the width of each topology path and then leaves it to a subsequent compactor to draw the path completely geometrically (e.g., generate a complete geometric definition of the path). In some such embodiments, the geometric router defines several intermediate coordinates for each topology path so that the geometric path it generates for a topology path has not only some width but also one or more intermediate coordinates that define two or more path segments. A single topology path can have many different geometric realizations (i.e., one topology path can be associated with many geometric paths).

[0056] In some embodiments, paths on the non-priority direction lower wiring layers traverse more than eight directions (e.g., 20, 90, 180, 360, etc.). In some embodiments, these paths on some or all of the lower layers are all straight (e.g., the first two wiring layers), while in other embodiments, paths on all of the lower layers (e.g., the first four wiring layers) include both curved and straight paths.

[0057] In some embodiments, routes defined by a first router connect node pairs that are within a threshold distance of each other, and routes defined by a second router connect node pairs that are beyond a threshold distance from each other. To connect node pairs that are beyond a threshold distance from each other, the routing process 800 uses both the first and second routers, for example, using the first router to define route segments that traverse along the lower non-preferential directional wiring layer and using the second router to define route segments that traverse along the upper preferential directional wiring layer. To facilitate the operation of the second router when the second router must complete a route that has been partially completed by the first router, in some embodiments, the first router defines one or more of its NPD route segments on a first set of wiring layers up to the locations used on those layers, up to vias to a second set of wiring layers. The second router then initiates its routing operation from these via locations to complete the route that has been partially completed by the first router.

[0058] Some embodiments first define a route traversing a first set of lower wiring layers of the IC design, and then define a route traversing the upper wiring layers of the IC design. For example, some embodiments perform global routing, then first NPD detail routing, and then second PD detail routing. Other embodiments perform NPD detail routing for the first set of lower wiring layers of the IC design without first performing global routing for these layers. These embodiments then perform PD global routing, and after the global routing, perform PD detail routing to define PD routes using a second set of upper wiring layers of the IC design.

[0059] In some embodiments, NPD detail routing does not restrict its pathfinding process to exploring only one or more preferred routing directions, nor does it restrict it to penalizing other routing directions on a first set of routing layers. In some embodiments, NPD detail routing generates curved paths on this set of routing layers, allowing its pathfinding to explore any angle for its path extension, which are then geometrically drawn using curved wire segments. In other embodiments, NPD detail routing does not generate a design with curved path segments by only exploring a large finite number of routing directions, such as nine or more routing directions.

[0060] In some embodiments, global and detailed routing for PD wiring layers use the Manhattan preferred direction, while in other embodiments, global and detailed routing for PD wiring layers use other preferred directions (e.g., 45-degree or 60-degree routing instead of, or in conjunction with, horizontal and vertical routing). In some embodiments, the first set of wiring layers includes the first two metal layers of the IC design, and the second set of wiring layers includes metal layers 3 and above of the IC design. In other embodiments, the first set of wiring layers includes more than the first two metal layers of the IC design, for example, layers 1-4.

[0061] In some embodiments, the first set of wiring layers includes first and second subsets of the layers (e.g., a third and a fourth wiring layer). In these embodiments, the method performs detail routing on the first set of wiring layers by performing a first detail routing operation on the first subset of the layers (e.g., the third wiring layer), and after completing the first detail routing operation, performing a second detail routing operation on the second subset of the layers (e.g., the fourth wiring layer). In some embodiments, the method performs the first and second detail routing operations by performing the first detail routing operation using an NPD detail router, and then recursively calling the NPD detail router to perform the second detail routing operation.

[0062] Figure 9 shows routing process 900 in several embodiments, which uses only detail routing to define NPD routes for some nets on a first set of lower wiring layers, and then uses global routing and detail routing to define PD routes for the remaining nets on the first set of lower wiring layers and a second set of upper wiring layers. As illustrated, process 900 begins (in 905) with NPD detail routing for some nets on a first set of lower wiring layers of the IC design, without first performing global routing for these nets on the first set of lower wiring layers. As will be further described below with reference to Figure 10, the NPD detail routing operation (in 905) attempts to connect as many nets as possible via wire segments on the first set of wiring layers (e.g., the first three metal layers or the first four metal layers).

[0063] To perform this NPD routing, process 900 sorts the nets based on the estimated length of the path to connect each net (i.e., based on the estimated wire length to connect each net). An example of calculating the estimated wire length of a net using a heuristic is provided below with reference to Figure 18. The sorted order is ascending, with nets having shorter estimated lengths higher in the order than nets having longer estimated lengths. Based on this order, the NPD routing process attempts to define NPD paths for the selected nets on a first set of lower wiring layers, starting from the top of the order with the shorter nets, and selecting as many nets as possible. In some embodiments, the NPD detail routing operation does not explore paths using wire segments on a second set of upper wiring layers (e.g., the fifth or higher metal layer). In some embodiments, the second set of upper wiring layers is reserved for PD detail routing performed in 915, as will be further described below.

[0064] In some embodiments, NPD detail routing does not use any preferred routing direction and therefore explores all angles of the routing direction. On the first two layers, NPD detail routing, in some embodiments, explores all angles of routing in the space not occupied on these layers for circuit blocks with default routing, such as IP blocks with default PD routing.

[0065] In some embodiments, NPD detail routing generates curved paths when exploring curved directions during its pathfinding. Alternatively, in some embodiments, NPD detail routing generates curved paths because, after its topology router identifies a topology path by referencing several mosaiced edges and faces, the geometric router embeds the topology path as a geometric path having one or more straight path segments and / or curved path segments based on which is more optimal. In some embodiments, the geometric router only defines an initial geometric path for each topology path, leaving the final definition of the geometric path for subsequent post-processing operations such as compression operations. As will be further described below, post-processing operations in some embodiments define geometric paths based on one or more criteria, such as compressing the design to reduce the overall die size or widening the paths to reduce capacitive coupling between nearby wires.

[0066] In some embodiments, NPD detail routing only explores paths in a finite number of routing directions, such as nine or more routing directions, and does not generate designs with curved routing segments. In some embodiments, NPD detail routing is performed by an NPD detail router formed by topology routers and geometric routers, as described above.

[0067] After performing NPD detailed routing in 905, process 900 (in 910) performs PD global routing for the remaining unrouted nets in the IC design, and after global routing, (in 915) performs PD detailed routing for these nets. In some embodiments, the purpose of this global routing is to identify routes for nets for which routes were not identified by NPD routing in 905 (e.g., nets with nodes separated by threshold distances that are not suitable for routing through a first set of wiring layers), or nets that did not have complete routes defined by NPD detailed routing in 905.

[0068] In some embodiments, PD detail routing (in 915) performs route looking and identifies route segments (i.e., wire segments) on all available wiring layers (i.e., on first and second sets of wiring layers), but only along the preferred wiring direction it associates with each wiring layer. In other embodiments, PD detail routing (in 915) performs route looking and identifies route segments (i.e., wire segments) on a second set of upper PD wiring layers (e.g., fifth and above metal layers), but does not look for route segments on a first set of lower wiring layers. However, the route segments identified by detail routing on a second set of wiring layers often connect to route segments defined by NPD detail routing on a first set of wiring layers.

[0069] Similar to PD detail routing (in 915) in some embodiments, PD global routing (in 910) defines a global route that can partially traverse all available wiring layers, but only along the preferred wiring direction associated with each wiring layer by the global router. Alternatively, PD global routing (in 910) in other embodiments defines its global route with respect to a second set of upper wiring layers that have only PD wiring. As described above, in some embodiments, the first set of wiring layers are the first four metal layers of the IC design, and the second set of wiring layers are metal layers 5 and above of the IC design. In other embodiments, the first set of wiring layers includes only the first two or three metal layers of the IC design, or only the third and / or fourth metal layers.

[0070] In some embodiments, global routing defines global routes that traverse multiple layers, as global routes are defined by referencing a three-dimensional global routing grid. In other embodiments, global routing uses a two-dimensional grid to define two-dimensional global routes. In some of these embodiments, different edges of global routes along different preferred routing directions are associated with the routing layers associated with those directions.

[0071] In some embodiments, the global routing and detailed routing operations in 910 and 915 use Manhattan preferred direction. Examples of routers that perform the global routing and detailed routing operations in 910 and 915 include global routers and detailed routers sold by Cadence or Synopsys. In other embodiments, the global routing and detailed routing operations in 910 and 915 use other preferred direction cabling (e.g., 45-degree or 60-degree cabling in place of, or in conjunction with, horizontal and vertical cabling).

[0072] Figure 10 shows the NPD detail routing process 1000 in several embodiments. In some embodiments, this process is used (in 905) to define NPD routes on one or more sets of NPD wiring layers. As shown, the process first divides the IC design into several partitions (in 1005). Figure 11 shows an example of a portion of the IC design 1100 divided into nine partitions. Next, for each identified partition, the process (in 1010) invokes an instance of the NPD detail router to identify NPD topology routes for connecting each net to the nodes entering the identified partition.

[0073] As described above, in some embodiments, the NPD detail routing of a first set of wiring layers performs topology routing operations to identify topology paths. For each partition that must be routed, the topology NPD detail router in some embodiments first mosaics the partition into multiple shapes (e.g., polygons such as triangles), and then defines topology paths with respect to the edges of the mosaiced shapes. In some embodiments, the topology router mosaics the partition into polygons of a different shape than the polygon used to divide the IC; for example, in some embodiments, the partition is a rectangle and the mosaiced shape is a triangle. In other embodiments, the mosaiced polygon and the polygon of the partition have the same shape (e.g., a rectangle), but the mosaiced polygon is smaller so that a number of mosaiced polygons are contained within the polygon of each partition.

[0074] After topology paths are defined for each net being routed by the NPD detail router, the NPD detail router performs geometric routing operations, as further described below with reference to operation 1025 in Figure 10, to embed each defined topology path into the IC design as a geometric path.

[0075] In some embodiments, the NPD detail router defines NPD topology paths simultaneously on multiple wiring layers (for example, on the first four wiring layers simultaneously). Thus, in these embodiments, the NPD topology paths defined in 1010 can traverse any of the first set of wiring layers. As will be further described below with reference to Figure 12, in other embodiments, NPD detail routing is performed on a contiguous set of wiring layers (for example, first on the first wiring layer 102, then on the second wiring layer 104, or, if four or more wiring layers are available for NPD routing in the IC design, on the first two wiring layers, then on the next two wiring layers). In these embodiments, the NPD topology paths defined in each iteration of detail routing through 1010 traverse the set of wiring layers being routed in that iteration of detail routing. In addition to these layers, the NPD router in some of these embodiments also has, in each of its iterations, the underlying wiring layers routed in previous iterations of the NPD detail routing operation.

[0076] When a net has nodes that enter multiple partitions, in some embodiments, the topology routing of an NPD detail router that defines the topology paths of each partition identifies NPD topology paths that traverse partition boundaries, and as a result, these NPD paths can be later connected (i.e., stitched) to one or more NPD paths defined in one or more other partitions to connect to one or more nodes of a net in one or more other partitions. In some embodiments, this stitching is performed by (1) NPD detail routing for the next set of NPD wiring layers when multiple rounds of NPD detail routing are performed for multiple consecutive sets of NPD wiring layers, (2) by PD global and / or detail routing performed after NPD detail routing, and / or (3) by post-processing operations of an NPD detail router in some embodiments.

[0077] Following 1010, the process (in 1015) determines whether the detailed topology routing operation should be repeated for the identified partition in order to improve its identified NPD topology path within each partition and / or to resolve inconsistent partition boundary intersections identified by two or more NPD router instances for two or more partitions containing nodes of the same net. In some embodiments, the NPD topology routing for each partition is intended to connect as many nodes of each net entering the partition as possible, using NPD topology paths defined by referencing edges that mosaic the routed NPD wiring layer. In some embodiments, these edges include partition edges that define partitions on the NPD wiring layer (e.g., the nine partitions in Figure 11). In some embodiments, these edges also include edges that mosaic the interior of each partition.

[0078] In some embodiments, topology paths are also defined by referencing nodes defined within mosaiced polygons (called faces) defined by edges within each mosaiced partition, because these nodes are used to represent vias to other NPD wiring layers being routed simultaneously by the NPD detail routing process 1000. In some embodiments, topology detail routing defines each topology path in relation to its location along mosaiced edges and face nodes to other topology paths. In defining these paths, to ensure that too many topology paths are not defined to traverse any arbitrary location on the NPD wiring layers or any via between two routed NPD wiring layers, the topology router considers the available path capacity along each mosaiced edge and the via capacity along each mosaiced face.

[0079] Due to congestion and other issues, it may not always be possible to connect nodes within each partition using only NPD wire segments, or multiple NPD topology routing iterations may be required to identify NPD routes to connect all such nodes (e.g., after new constraints are defined after each iteration). Furthermore, two or more NPD router instances for two or more partitions containing nodes in the same net initially define separate routes for nodes entering each of those partitions. These topology routes can result in inconsistent boundary crossings for the same net. For example, Figure 11 shows two boundary crossings 1112 and 1114 for the same net defined by two different detail router instances defining NPD routes for two adjacent partitions 1105 and 1107. These two boundary crossings are problematic because they have several other topology routes (shown as dashed lines) for several other nets between them.

[0080] When such inconsistent NPD routes exist for multiple partitions connecting nodes in a single net, or when other suboptimal NPD routes are defined, process 1000 determines, in some embodiments, that it must perform additional iterations of its NPD topology routing. As process 1010 performs more iterations of its NPD topology routing, process 1000 becomes less likely, in some embodiments, to perform another iteration of its NPD detail routing. For example, in some embodiments, a penalty score is assigned to each set of inconsistencies in NPD detail routes or suboptimal NPD detail routes, and all penalty scores are aggregated in 1010 to generate an overall penalty score. As the number of iterations through 1010 increases, process 1000 requires a higher aggregate penalty score to exist before it can perform another iteration of its NPD detail routing.

[0081] If process 1000 determines (at 1015) that it must perform another iteration of its NPD topology routing, process 1000 defines one or more constraints for the next iteration of NPD topology routing at 1010 (at 1020). Alternatively, for this next iteration of NPD detail routing at 1010, process 1000 shares information (e.g., boundary crossing information) about different route segments identified by different routers for the same net between different partitions, so that the next iteration of topology routing can take these other routes into consideration when defining those next sets of routes. After 1020, the process returns to 1010 and performs this next iteration of routing.

[0082] Figure 12 shows an example of a constraint defined in 1020. To avoid two inconsistent boundary crossings 1112 and 1114 of two NPD routes defined for the common net in Figure 11, process 1000 defines a constraint that, in some embodiments, NPD detail router instances for partitions 1102 and 1104 must identify their respective routes to this net in order to cross a smaller region 1205 at this boundary. This smaller region ensures that the two NPD detail router instances are unlikely to identify other NPD routes to other nets between the two boundary crossings they identify for the common net.

[0083] In conjunction with, or alternative to, defining constraints in 1020, in some embodiments, process 1000 causes each specific NPD topology router instance that routed each specific partition in a previous iteration of 1010 to share information about the topology routes it defined with (1) each other NPD topology router instance, or (2) each NPD topology router instance that defined topology routes for partitions adjacent to a particular partition (for example, for the eight partitions adjacent to partition 1105 in Figure 11).

[0084] In some embodiments, the information provided by each specific NPD topology router instance to another NPD topology router instance includes the entire definition of each topology route defined by the specific router instance, while in other embodiments, the information includes only the partition boundary crossings (if any) of each topology route that crosses a shared partition boundary. Each NPD topology router instance then uses the information provided by the other NPD topology router instance in its next iteration through 1010. The router instance uses this information to define how the topology routes defined by the router instance in its next topology routing iteration more closely match the estimated locations of related topology routes defined by the other instance (i.e., the estimated locations of other topology routes in other partitions that must be stitched to the topology routes defined by the router instance in the next iteration).

[0085] If process 1000 determines (in 1015) that it is not necessary to perform another iteration of its NPD detail routing, the NPD detail routing process 1000 (in 1025) uses a geometric detail router to embed each defined topology path as a geometric path into the IC design. For each topology path, this embedding defines one or more geometric path segments along one or more acceptable routing directions, which in some embodiments may include one or more Manhattan routing directions and diagonal routing directions, as well as curved routing directions allowed on the NPD routing layer. In some embodiments, this geometrization snaps each topology path to one or more grid positions along one or more acceptable linear, diagonal, and curved directions. After 1025, the process terminates.

[0086] Figure 13 shows an example of another technique for several embodiments of using route crossing data specified by one detail router instance of an adjacent partition. In this technique, the IC design partition is divided into two groups, a gray group and a white group, arranged in a checkerboard pattern. Several detail router instances first perform NPD detail routing for the gray partition. The partition boundary crossings identified by these routers are then passed to NPD detail router instances that then route the white partition in detail, so that NPD routes traversing the white partition can respect the boundary crossings identified by the detail routers of the gray partition. As multiple iterations are performed for the white and gray partitions, the router instances for each set of colored partitions iteratively pass their boundary crossing information to the router instances for the next set of colored partitions until the routing iteration is complete.

[0087] Figure 14 shows another NPD detail routing process 1400 in several embodiments. This process 1400 is similar to process 1000 except that it iteratively performs NPD detail routing for one or more different sets of NPD wiring layers. To that end, process 1400 has operations 1405 and 1410 to select one or more consecutive sets of NPD wiring layers for detail routing. After selecting a consecutive set of NPD wiring layers (in 1405), process 1400 iteratively performs operations 1010-1020 in some embodiments to identify NPD paths traversing the selected set of NPD wiring layers. When identifying NPD paths on the currently selected set of NPD wiring layers, process 1400 also explores route options in one or more lower wiring layers that are part of one or more previously selected sets of NPD wiring layers in some embodiments. In other embodiments, process 1400 does not explore previously explored lower wiring layers while identifying NPD paths on the currently selected set of NPD wiring layers.

[0088] At 1410, the process determines whether it has selected the last set of NPD wiring layers. If not, the process returns to 1405 to select the next set of NPD wiring layers, and then repeats this operation until it determines that it has selected the last set of NPD wiring layers in its final iteration through 1410. In some embodiments, the selected set of NPD wiring layers includes only one wiring layer at a time. In these embodiments, process 1400 successively defines NPD paths for individual NPD wiring layers, for example, first for the first NPD wiring layer, then for the second NPD wiring layer, then for the third NPD wiring layer, and so on. In other embodiments, the selected set of NPD wiring layers includes two or more NPD wiring layers selected simultaneously at 1405 for detailed routing.

[0089] In some embodiments, process 1400 first selects the third wiring layer as its first NPD wiring layer to route, explores only the first and second wiring layers for connecting to pins on the substrate, and for opportunistic route extension when no better option is found on the third layer. In some of these embodiments, process 1400 uses the first to third wiring layers for the same reasons while identifying an NPD route for a fourth NPD wiring layer.

[0090] When two or more NPD cabling layers are routed simultaneously with another NPD cabling layer, an NPD route defined by a detailed router (which routes multiple NPD cabling layers simultaneously) can traverse multiple NPD cabling layers. To traverse different NPD cabling layers, an NPD route uses vias to connect different segments of the route on different NPD cabling layers.

[0091] Some embodiments use multi-beam mask drawing to enable curve masks, which can then be used to generate curved components on target wafers and dies. To utilize such mask drawing and wafer production, some embodiments provide physical design EDA tools that generate curve designs. An example of such a physical design tool is the aforementioned NPD detail router that generates curved paths.

[0092] To facilitate the generation of these curve designs (e.g., their curve paths), some embodiments of physical design EDA tools define their designs in the pixel domain rather than the contour domain. Pixel-based designs are also ideal for analyzing and generating curve designs by using machine learning, as machine learning processes are often optimized to handle pixel-based datasets. In fact, many machine learning applications do not handle contour-based descriptions of datasets. Therefore, by transforming physical designs (e.g., routing) to operate in the pixel domain instead of the contour domain, some embodiments make machine learning much more accessible for use by physical design tools.

[0093] Similarly, to facilitate the creation of these masks, some embodiments use the pixel region to perform the processing required to generate them, because a curved mask manipulated in the pixel region takes the same amount of time as any Manhattan design. Furthermore, this processing is often performed on the GPU in the pixel region. Since a single instruction stream can be applied uniformly to a large number of pixels, the GPU is an excellent single-instruction multiple-data (SIMD) machine in the pixel region, and therefore the immense processing power of the GPU for this type of pixel manipulation is ideal. Relying on the SIMD architecture can generate much higher computing throughput for processing physical designs and masks with curved shapes.

[0094] Contours (also called geometry) are typically represented as piecewise linear polygons, but can also be represented in infinite-resolution curve formats such as splines. Manipulating contours is the mathematical duality of manipulating pixel-based data, given resolution limits. A mathematical duality means that functionally, anything that can be done in one can be done in the other. However, when runtime performance or efficiency is considered, and given a specific precision of the result as the target, the computational behavior of one can be entirely different from that of the other.

[0095] Generally, manipulating shapes that are mostly large rectangles is fast in the contour domain (i.e., the geometry domain), while manipulating shapes that are mostly polygons or curves and have a higher vertex density is fast in the pixel domain. In the pixel domain, the pixel size is naturally defined from the resolution limit. Once the pixel size is defined, it is irrelevant whether the shape being processed is curved or straight. Both calculations take a constant amount of time. This is not true for contour-based operations, as the computation time depends on the number of piecewise linear edge counts used to represent the contour. Also, given that much of the data processing these operations is performed on high-performance GPUs, pixel-based analysis is preferred over contour-based analysis because GPUs are superior SIMD machines in the pixel domain.

[0096] To further elaborate on these points, a brief examination of IC design and manufacturing would be useful. In the past, EDA systems for both design and manufacturing have used Manhattan shapes, often extended with 45-degree edges as the basic building blocks to be calculated. A Manhattan shape is a shape with axially parallel edges having 90-degree angles. The fundamental limitation in manufacturing semiconductors with shapes other than Manhattan shapes has historically been that all precision layers on the mask have their masks written using a Variable Shaped Beam (VSB) mask writer that exposes rectangles of a specific minimum size (e.g., 1 nm to 100 nm on each side) and maximum size (e.g., 200 to 1000 nm on each side).

[0097] Since a VSB writer exposes the mask to one rectangle at a time, the mask writing time is roughly proportional to the number of rectangles that need to be written. Diagonals or curves can be approximated by a series of stepped rectangles. However, the number of rectangles is very large, making the mask writing time very long in order to obtain a sufficiently accurate approximation. To target non-Manhattan shapes on the wafer, non-Manhattan shapes on the mask are required, even including the effects of advanced forms of OPC called optical proximity correction (OPC) or inverse lithography technology (ILT).

[0098] Non-Manhattan shapes on the mask were impractical for VSB writers except in very limited applications, and therefore non-Manhattan shapes were not feasible for semiconductor design shapes that were wafer targets. The 45-degree triangle is an exception to the Manhattan limitation for VSB machines. This led to Cadence's X-Architecture, which uses 45-degree routing to reduce power consumption and improve chip performance.

[0099] VSB data preparation techniques using duplicate shots and mask-wafer mutual optimization are techniques that can be used to effectively target curved shapes on a mask using a reasonable number of VSB shots. However, such techniques are limited to 193i lithography for practical applications. EUV (extreme ultraviolet) masks have a large number of smaller shapes that need to be written with higher precision (because EUV can "see" better than 193i), and therefore these techniques are not practically viable. Thus, there is no general solution for VSB mask writing that enables curved target design on a wafer.

[0100] In recent years, multi-beam mask writers have become available for production use in leading mask shops worldwide. Multi-beam mask writers draw masks using an array of fixed-size pixels that expose the mask. Because the pixel size is fixed, the machine's writing time does not vary depending on the complexity or shape of the design, unlike VSB machines. This has made it possible to actually draw curved masks, similar to Manhattan shapes, and consequently, to design curved target shapes on wafers.

[0101] The physical design of semiconductor chips is computer-assisted, either through interactive manipulation of geometry or automated placement and routing of the design. In either case, physical verification of the design against physical rules (such as spacing and minimum width or area rules), as well as connectivity extraction and parasitic extraction of electrical parameters (such as resistance, capacitance, and inductance), are performed on the physical design. Today, the vast majority of these capabilities operate in the contour / geometry domain because VSB mask writers can only reasonably write masks to target these wafer shapes, and are therefore better optimized for rectangular designs, and indeed mostly Manhattan designs.

[0102] In contrast to these prior arts, some embodiments of the present invention use multibeam mask drawing to enable curve masks, and therefore curve design targets on wafers. To utilize such mask drawing and wafer production, some embodiments provide physical design tools that generate curve designs. A curve mask manipulated in the pixel region takes the same amount of time as any Manhattan design, just as a curve design takes the same amount of time to write on a multibeam machine.

[0103] Furthermore, when processing is performed on the GPU in the pixel domain, the advantages of the SIMD architecture become apparent due to the immense processing power of the GPU for that type of pixel manipulation, which allows a single instruction stream to be applied uniformly to all pixels, resulting in much higher computing throughput. Just as curve design takes a long time to write on a VSB machine, curve masks manipulated in the contour / geometry domain take a much longer time than typical Manhattan designs. This is because, whether the contour is represented as a piecewise linear polygon with some reasonable vertex spacing, or as a spline or some version of the NURBS format, the number of vertices required increases with increasing curvature, and the computational algorithms in the contour / geometry domain scale at runtime based on the number of vertices.

[0104] Given a specific resolution limit, it is not necessary to represent curved shapes in the contour / geometry region. In semiconductor manufacturing of curved shapes, the resolution limit is provided by the fact that these masks are written with a multi-beam mask writer. A multi-beam mask writer has a known pixel size used to print the mask. The resolution limit determined by that pixel size is a resolution limit that can be used to determine the pixel size required to manipulate any semiconductor design in the pixel region. This is a lower bound to the minimum pixel size that may be required to drive the required precision achievable in the manufacturing process.

[0105] However, other criteria may further limit the possible resolution of the output shape, and therefore the design shape. For example, ILT is calculated in terms of pixel dose. Some ILTs operate in the frequency domain (e.g., TrueMask ILT), but they also represent the mask in terms of pixel dose. It is clear that there is a physical limit to the achievable resolution of any semiconductor device, regardless of whether the resolution of the mask, and therefore the resolution of the wafer, is limited by the pixel size of the mask writer, or the pixel size of the ILT, or some other pixel size. This determines the pixel size, which is the mathematical dual of contour / geometry operations. However, the execution time of algorithms operating in the pixel domain is constant regardless of the amount of curved content, and regardless of the shape. Furthermore, with given GPU acceleration, pixel domain calculations can be parallelized at scale, which in turn significantly reduces the overall execution time.

[0106] Figure 15 shows a process 1500 for manufacturing an IC having curved paths according to several embodiments of the present invention. As shown in the figure, the process begins by defining paths in the IC design (in 1505) that are defined in pixel regions or converted to pixel regions after the routing stage. When defined in pixel regions, each path is represented with respect to the set of pixels occupied by the path in the three-dimensional space in which the IC design is defined. In some embodiments, the IC design has one or more NPD wiring layers and one or more PD wiring layers, while in other embodiments, the IC design has only NPD wiring layers. One or more paths on each NPD wiring layer can be curved paths, and a curved path is a path having one or more curved segments. On each NPD wiring layer, paths can also traverse eight or more linear directions in some embodiments.

[0107] During routing (in 1505), process 1500, in some embodiments, uses machine learning to perform its routing operations. For example, when geometrically drawing the topological path in 1025, process 1000, in some embodiments, uses machine learning to identify different estimated manufacturing wires that will be generated on the IC or IC mask for different possible geometrys of the same topological path of the net, in order to evaluate different geometrys and select one of them as the geometric path of the net.

[0108] In some embodiments, a pixel-based definition of each possible geometric path for a net is fed to a machine-trained network (e.g., a neural network), which then generates estimated manufacturing wires that are likely to be produced for the geometric paths on the IC or IC mask used to manufacture the IC. The different estimated manufacturing wires for the same net are then compared to one or more criteria (e.g., design rule checks or capacitance extraction criteria / modeling) to determine which of the geometric paths results in estimated manufacturing wires that best match the criteria or do not violate any of the criteria.

[0109] After defining the path, process 1500 then performs a compression operation (in 1510) that uses machine learning to find the optimal compression of the path. Several examples of such compression operations are described in U.S. Patent Application No. 17 / 992876, which is incorporated herein by reference. Next, in 1515, process 1500 generates the curve shape of the mask using OPC and ILT. In 1520, the process then manufactures a mask for manufacturing the IC using a multibeam mask manufacturing process. In 1525, the process manufactures the IC using the mask. After 1525, the process terminates.

[0110] In some embodiments, process 1500 is repeated several times between operations 1505 and 1515 to generate an IC design that has an optimal set of paths for producing an acceptable mask that satisfies the desired performance characteristics and / or for manufacturing the IC. These iterations are not shown in Figure 15 so as not to obscure the description of process 1500 with unnecessary details. U.S. Patent Application No. 16 / 949270 describes the iterative execution of physical design and mask manufacturing operations until an IC design having the desired characteristics is identified. U.S. Patent Application No. 16 / 949270 is incorporated herein by reference.

[0111] As mentioned above, curved wire segments can be inadvertently generated on ICs designed to have only Manhattan or 45-degree routing. This is because Manhattan and diagonal jogs on PD routing layers can result in curved jogs on these layers due to manufacturing limitations, i.e., manufacturing limitations that make it difficult to generate 45-degree or 90-degree junctions.

[0112] However, current existing EDA tools do not generate IC designs that have curved routing or NPD full-angle straight routing on the routing layers of the design. This is because the EDA tools do not generate IC designs that should be manufactured in a manufacturing process (e.g., a mask manufacturing process) that is designed to generate curved wires and NPD full-angle straight routing. Figure 16 shows an example of five routing layers 1602-1610 of an IC design generated by one or more physical design tools (e.g., one or more routers and / or compactors) of several embodiments. The first routing layer 1602 and the second routing layer 1604 are NPD curved layers having Manhattan routing segments, diagonal routing segments, and curved routing segments, while the third layer 1606, the fourth layer 1608, and the fifth layer 1610 are PD layers having alternating Manhattan PD layers.

[0113] Next, the five wiring layers 1602-1610 of the IC design in some embodiments are used to define a mask that generates the five wiring layers of IC 100 in Figure 2. Similar to the metal layers shown in Figure 16, the physical design tools in some embodiments define a similar set of metal layers for the IC design of other ICs shown in other figures above (e.g., Figures 1-7). Similar to their corresponding ICs, the wiring layers in the IC design in some embodiments have paths on NPD wiring layers that have straight (e.g., Manhattan or diagonal) segments and curved segments. Next, using the paths on these wiring layers, a mask can be generated, and then this mask can be used to manufacture an IC with NPD straight and curved wiring.

[0114] Although the first two wiring layers 1602 and 1604 are shown to be NPD curved layers, IC designs in other embodiments may have other NPD wiring layer architectures as described above. For example, in some embodiments, the third and fourth wiring layers of the IC design are NPD wiring layers, and the first and second wiring layers have blocks of PD wiring, with the areas between them free for NPD straight and curved routing.

[0115] Figure 17 shows another example of a metal layer 1700 of an IC design defined to have a curved path segment. This metal layer is the fourth metal layer of the IC design. As shown, the fourth metal layer 1700 has a preferred vertical routing direction. This layer also has a bus 1720 with a set of curved jogs 1725 that allow the bus to be repositioned on the metal layer to avoid obstacles 1750 on this layer. The curved jogs 1725 allow the bus to move to the left when moving from the bottom side of this layer to its top side.

[0116] Curved jogs in IC design are far more preferable than Manhattan or diagonal jogs. This is because curved jogs are much closer to what is fabricated on the IC and are therefore a more useful design structure for analysis for modeling IC components in design (e.g., for capacitance extraction modeling). Curved jogs are also preferable because they can be fabricated to occupy less space than horizontal or diagonal jogs defined in IC design (i.e., curved jogs can be produced more compactly than Manhattan or diagonal jogs).

[0117] Furthermore, curved wiring in IC design and within ICs offers several advantages over straight wiring. For example, curved wire jogs provide a smoother path for the flow of electricity, resulting in lower resistance than Manhattan wire jogs. Also, as mentioned above, curved jogs are more accurately modeled in IC design because they are closer to what is ultimately produced within the IC. Moreover, curved jogs are also more reliably manufacturable than Manhattan or diagonal jogs because they are closer to what is actually manufactured.

[0118] Vias can be a source of manufacturing reliability problems for ICs. Therefore, some embodiments use curved NPD routers designed to reduce the number of vias. In some embodiments, this reduction is sometimes achieved at the expense of having longer curved NPD paths on individual NPD wiring layers, but this sacrifice is acceptable due to the reliability cost of vias and the relatively small cost of slightly longer short net connections. Figures 18 and 19 show examples of two routing processes 1800 and 1900 that define curved NPD routers to reduce the number of vias. Figure 19 achieves this by routing one NPD wiring layer at a time, while Figure 18 achieves this by costing vias far more than wire length.

[0119] As illustrated, process 1800 in Figure 18 first identifies a subset of short nets (in 1805) to attempt routing on the NPD wiring layer of the IC design being routed. In some embodiments, the IC design is the design of the entire IC or a portion of the IC. In some embodiments, "short" nets are identified by using heuristics to calculate the estimated wire length of each net, sorting the nets based on the calculated estimates, and then selecting a subset of nets based on the sorted order. Examples of heuristics for each net in some embodiments include a size bounding box for the net (e.g., the area of ​​a rectangle containing all the pins of the net), the length of the Steiner tree connecting the pins of the net, and so on.

[0120] Furthermore, based on the sorted order, process 1800 selects a specific percentage of nets for NPD curve routing (e.g., 40% or 50%) in some embodiments (i.e., a specific percentage of nets with the shortest estimated wire length based on the sorted order), while in other embodiments, process 1800 makes this selection based on a different criterion (e.g., by selecting all nets with a calculated estimated wire length smaller than a threshold estimated wire length).

[0121] In 1810, process 1800 selects a set of two or more wiring layers to be routed. In its first iteration through 1810, process 1800 in some embodiments selects first and second wiring layers. In some embodiments, the first and second wiring layers have regions with default PD wiring for connecting electronic components to circuits of default circuit blocks (such as IP blocks). In such embodiments, the NPD router identifies NPD straight and curved paths in the unused space between regions with PD wiring on these layers. In these embodiments, when performing route finding to identify such paths on the first and second wiring layers, the NPD router does not penalize any routing direction. After NPD routing on one of the first two layers, wires exceeding a threshold amount (e.g., 90%) may still be aligned with the preferred direction, and as a result, once routing is complete, that layer still appears as a PD wiring layer.

[0122] In 1815, process 1800 performs its NPD routing operation to identify NPD routes traversing the NDP cabling layers selected in 1810 for many shortnets identified in 1805 for which routes have not yet been defined. The routing operation in 1815 is biased towards the use of vias, but as described above, it does not penalize any routing direction in order to bias routing in any direction.

[0123] To bias vias, in some embodiments, the routing process 1800 uses a much higher cost for vias between NPD wiring layers in the current set of layers being routed (i.e., last selected in 1810) than the wire length cost, which represents the cost associated with the length of the path on any one of the NPD wiring layers in the current set of layers being routed. Also, in some embodiments, the via cost between NPD wiring layers is higher than the via cost used later during PD routing in 1830 for vias between PD wiring layers or between NPD wiring layers and PD wiring layers.

[0124] Furthermore, in some embodiments, the cost of a via from between two layers is a multiple of the wire length cost of a planar connection on one or both of these layers. In some of these embodiments, the cost of a via from between two NPD layers is a larger multiple of the wire length cost of a planar connection on one or both of these layers than the via cost between two PD layers or between an NPD layer and a PD layer. For example, in some of these embodiments, the via cost between two NPD wiring layers, as evaluated by the NPD routing operation in 1815, is M times the wire length cost of a planar connection on one or both of the two NPD wiring layers, while the via cost between two PD wiring layers or between an NPD wiring layer and a PD wiring layer, as evaluated by the PD routing operation in 1830, is N times the wire length cost of a planar connection on one or both of the two NPD wiring layers, where M is greater than N. In some embodiments, M is several times greater than N, for example, 2 or 3 times or more.

[0125] This bias towards vias reduces the number of vias defined between NPD wiring layers in the current set of layers being routed by the routing operation in 1815. As described above, in some embodiments this reduction can be achieved at the expense of longer curved NPD paths on individual NPD wiring layers, but this sacrifice is acceptable due to the high reliability cost of vias and the relatively small cost of slightly longer short net connections.

[0126] Each path identified for each net connects the pins of the net, in some embodiments. Each identified path may also be a curved path having one or more curved edges, or a straight path having only straight edges. In some embodiments, the routing operation in 1815 typically involves multiple iterations, each iteration collaboratively routing over several processing nodes (e.g., processing cores of one or more multicore processors of a computer performing the routing) for some or all of the divided regions of the IC design. If one or more short nets span multiple partitions, it may be necessary to identify the partition intersection locations for each such short net through a series of iterations of the routing operation in 1815 for the same set of NPD wiring layers in order to determine where and how to stitch together path segments defined within different partitions for one.

[0127] Examples of connecting different route segments defined for a single net within different partitions were described above with reference to Figures 11-14. Also, as explained with reference to these figures, some embodiments perform NPD routing at 1815 by first identifying the topology paths of the routed short nets and then geometrically drawing the identified topology paths for these nets. In other embodiments, NPD routing at 1815 is purely a topology routing operation, followed by a geometric operation that identifies the topology paths for each net and, after the completion of NPD routing for all short nets (e.g., after 1825), identifies the geometric paths for the identified topology paths.

[0128] After performing a routing operation in 1815 for the currently selected set of wiring layers, there may be one or more identified “short” nets for which process 1800 has not yet identified a route. Therefore, in 1820, process 1800 adds these short nets to the list of short nets that need to be routed in the next NPD routing iteration through 1815, or in the PD routing operation in 1830. In some embodiments, process 1800 maintains only one “nets to be routed” list for all its iterations through the NPD routing operation 1815, so it is not necessary to add short nets that have not been routed for NPD routing to the unrouted list.

[0129] At 1825, process 1800 determines whether all available wiring layers available for NPD routing have been selected. If not, the process returns to 1810 to select another set of wiring layers for NPD routing, and then identifies the NPD paths on the newly selected set of wiring layers for the remaining unrouted short net. In some embodiments, the wiring layers available for NPD routing are only a subset of the wiring layers, for example, only layers 1-4 in some embodiments, and not all of the wiring layers, for example, not including wiring layers 5-7.

[0130] In some embodiments, the sets of wiring layers selected in successive iterations for NPD routing through 1810 do not overlap, but in other embodiments, they are different sets, but may overlap with one or more wiring layers common to two sets selected in two iterations through 1810. Regardless of whether successive selected sets of wiring layers overlap, the subsequently selected set of wiring layers includes at least one upper wiring layer that was not present in the previously selected set of wiring layers.

[0131] In some embodiments, when process 1800 routes all or most of the short nets on a previously selected set of wiring layers, process 1800 adds to the list of “nets to be routed” one or more “intermediate” or longer length nets to be routed on a subsequently selected set of wiring layers (i.e., the set of wiring layers selected in 1810 after the last iteration through 1825). This technique ensures that NPD routing is used as much as possible for as many nets as possible. In some embodiments, process 1800 adds longer nets to the list of “nets to be routed” based on their estimated wire lengths (calculated by one of the heuristics described above), with nets having smaller estimated wire lengths added before nets having larger estimates.

[0132] If the process determines (at 1825) that it has selected all available sets of wiring layers for NPD routing, the process then (at 1830) invokes a PD router to route the remaining unrouted net. In some embodiments where the routing operation at 1815 is purely topology routing, process 1800 uses a geometric router at 1815 to generate geometric paths to topology paths defined for one or more sets of NPD wiring layers, before invoking a PD router to route the remaining unrouted net. In some embodiments, the PD router treats the NPD paths defined by process 1800 as obstacles in its routing graph, otherwise proceeds with routing the unrouted net with PD paths defined on all wiring layers, including the NPD wiring layers routed by the NPD routing process 1800. After 1830, the process terminates.

[0133] In some embodiments, the NPD routing operations 1805–1825 of process 1800 are performed by an NPD router, and the PD routing operation 1830 is performed by a separate PD router. In other embodiments, both the NPD routing and PD routing operations are performed by a single router that performs NPD routing on a first set of wiring layers (e.g., layers 1–4) while performing PD routing on a second set of wiring layers (e.g., layer 5 and above). To ensure that NPD routing is used only for shorter nets, the routing process 1800, in some embodiments, penalizes NPD routes longer than a threshold distance or imposes constraints to prevent these routes from becoming longer than a threshold distance.

[0134] Figure 19 illustrates an NPD routing process that reduces the number of vias between NPD wiring layers by routing one NPD wiring layer at a time. This reduction can be achieved at the expense of longer curved NPD paths on individual wiring layers, but this sacrifice is acceptable due to the reliability cost of vias and the relatively small cost of longer short-net connections.

[0135] As illustrated, process 1900 first identifies a subset of short nets (in 1905) in order to attempt NPD routing on the wiring layers of the routed IC design. In some embodiments, the IC design is the design of the entire IC or a portion of the IC. In some embodiments, "short" nets are identified by using a heuristic to calculate the estimated wire length of each net, sorting the nets based on the calculated estimates, and then selecting a subset of nets based on the sorted order. An example of such a heuristic is described above by reference to Figure 18.

[0136] At 1910, process 1900 selects a specific routing layer (also called a routing layer) which is the next bottom routing layer available for NPD routing and which the process has not yet selected for NPD routing. In some embodiments, process 1900 first selects a first routing layer (at 1910) and then, in subsequent iterations through 1910, selects a step through the remaining routing layers available for NPD routing, e.g., a step through layers 2-4. In other embodiments, process 1900 first selects a third routing layer (at 1910) and then, in subsequent iterations through 1910, selects a step through the remaining routing layers available for NPD routing, e.g., a step through layer 4. In some embodiments, the routing layers available for NPD routing are only a subset of the routing layers, e.g., only layers 1-4 in some embodiments, and do not include all routing layers, e.g., do not include routing layers 5-7.

[0137] Next, in 1915, process 1900 identifies NPD paths that traverse the last selected wiring layer in 1910 for many short nets identified in 1905 for which paths have not yet been defined. Each NPD path identified for each net connects two or more nodes (e.g., two or more pins) of the net, in some embodiments. Each identified NPD path may be a curved path having one or more curved edges (along with zero or more straight edges), or a straight path having only straight edges.

[0138] During each iteration through 1915 performed for a selected specific wiring layer, process 1900 performs a route lookup to identify each NPD route to each net, identifying routes between two or more nodes of the net to be connected, and then embeds the identified routes as routes between two or more nodes. In some embodiments, this route lookup does not explore route extensions to any wiring layer above a specific NPD wiring layer in order to identify routes that traverse to upper wiring layers and then traverse back to a specific NPD wiring layer or lower layer. In some embodiments, this route lookup explores route extensions on the selected specific wiring layer and any wiring layer below the selected specific wiring layer. In other embodiments, this route lookup explores route extensions only on the selected specific wiring layer. In some of these embodiments, the route lookup of a net can identify incomplete routes for nets that terminate at via locations to upper layers. In some embodiments, subsequent iterations of NPD or PD routing performed for upper layers then perform route looksups starting from these via locations to complete the routes to these nets.

[0139] These different routing techniques in different embodiments will result in different paths being defined during the routing operation in 1915 for each specific wiring layer selected in 1910. In some embodiments, the routing operation in 1915 for a selected specific wiring layer does not use vias to any upper wiring layers not yet selected in any iteration through 1910 to identify paths that traverse to upper layers and then traverse back to the selected specific wiring layer or lower layers. Also in some embodiments, this routing operation uses only vias to connect the selected specific wiring layer to (1) a lower layer where the pins of the (routed) net are defined, or (2) a lower layer previously identified in one or more iterations prior to the current iteration through 1910 where the route segments for those nets pass through 1910.

[0140] Other embodiments implement the "no via" constraint differently. For example, to reduce or eliminate vias to an underlying wiring layer during routing of any one particular wiring layer, the routing operation for the underlying wiring layer beneath the particular wiring layer identifies via locations to traverse from the underlying wiring layer to the particular wiring layer, as described above. In conjunction with or alternatively, in some embodiments, the NPD routing process 1900 at the start of NPD routing for any one wiring layer (selected in 1910) defines expected contact locations on the selected wiring layer for connecting to an underlying layer pin or pin contact. For any given pin, such expected contact locations on the selected wiring layer are either directly above the pin or pin contact if there are no obstructions to the underlying pin or pin contact, or at an offset location above the underlying pin or pin contact, the offset location being connected to the pin or pin contact via the underlying substrate and wiring defined on the wiring layer via a path segment defined by the NPD routing process 1900 before initiating NPD routing for the selected wiring layer.

[0141] In some embodiments, the routing operation in 1915 typically involves multiple iterations, each iteration of which collaboratively routes all partitions of the IC design being routed by process 1900 across multiple processing nodes (e.g., processing cores of one or more multicore processors of a computer performing the routing). If one or more short nets span multiple partitions used to divide the routing area, the partition intersection locations are identified according to one of the methods described above with reference to Figures 11-14 and Figure 18.

[0142] Furthermore, as illustrated with reference to these figures, some embodiments perform NPD routing in 1915 by first identifying the topological paths of the routed shortnets and then geometrically drawing these nets. In other embodiments, NPD routing in 1915 is purely a topological routing operation, followed by a geometric operation that identifies the topological paths to each net and, after the completion of NPD routing for all shortnets (e.g., after 1925), identifies the geometric paths to the topologically identified paths.

[0143] After performing 1915 on the currently selected routing layer (i.e., the routing layer last selected in 1910), there may be one or more identified “short” nets for which process 1900 has not yet identified a route. Therefore, in 1920, process 1900 adds these short nets to the list of short nets that need to be routed in the next NPD routing iteration through 1915, or in the PD routing operation of 1930. In some embodiments, process 1900 maintains only one “nets to be routed” list for all its iterations through the NPD routing operation 1915, so it is not necessary to add short nets that are not routed for NPD routing to the unrouted list.

[0144] At 1925, process 1900 determines whether all available wiring layers for NPD routing have been selected. If not, the process returns to 1910 to select the next highest level wiring layer available for NPD routing, and then identifies the NPD paths on the newly selected wiring layers for the remaining unrouted short nets.

[0145] In some embodiments, when process 1900 routes all or most of the short nets on one or more previously selected NPD wiring layers, process 1900 adds to the list of “nets to be routed” one or more “intermediate” or longer length nets to be routed on the currently selected NPD wiring layers (i.e., the NPD wiring layers selected in 1910 after the last iteration through 1925). This technique ensures that NPD routing is used as much as possible for as many nets as possible. In some embodiments, process 1900 adds longer nets to the list of “nets to be routed” based on their estimated wire lengths (calculated by one of the heuristics described above), with nets having smaller estimated wire lengths added before nets having larger estimates.

[0146] If the process determines (at 1925) that it has selected all available wiring layers for NPD routing, the process then (at 1930) invokes the PD router to route the remaining unrouted net. In some embodiments where the path defined at 1915 is a topology path, process 1900 performs a geometric operation after 1925 to define a geometric path relative to the topology path, before invoking the PD router to route the remaining unrouted net. In some embodiments, the PD router treats the NPD path defined by process 1900 as an obstacle in its routing graph, otherwise proceeds with routing the unrouted net with PD paths defined on all wiring layers, including the wiring layers used by the NPD router to define the NPD path. After 1930, the process terminates.

[0147] In some embodiments, the NPD routing operations 1905–1925 of process 1900 are performed by an NPD router, and the PD routing operation 1930 is performed by a separate PD router. In other embodiments, both the NPD routing and PD routing operations are performed by a single router that performs NPD routing on a first set of wiring layers (e.g., layers 1–4) while performing PD routing on a second set of wiring layers (e.g., layer 5 and above). To ensure that NPD routing is used only for shorter nets, the routing process 1900, in some embodiments, penalizes NPD routes longer than a threshold distance or imposes constraints to prevent these routes from becoming longer than a threshold distance.

[0148] By not exploring via path extensions, or by restricting via path extensions to reach pins or pin contacts of unrouted nets, the NPD routing process 1900 significantly reduces the number of vias it defines. In some embodiments, this reduction can be achieved at the expense of longer curved NPD paths on individual NPD wiring layers, but this sacrifice is acceptable due to the relatively lower cost of longer short net connections compared to the high reliability cost of vias.

[0149] Figures 20-22 present an example demonstrating a significant reduction in the number of vias achieved by using the NPD routing process 1900 of Figure 19. Figure 20 shows a set of nets that need to be connected via a route. In this figure, the pins 2005 of each net that need to be connected are linked via one or more lines 2010. Each connected set of lines and pins effectively represents a net that needs to be connected. As described above, in some embodiments, a net is a set of pins that need to be connected.

[0150] Figure 21 shows conventional Manhattan routing on metal layers 3 and 4 connecting the pins of each of the nets shown in Figure 20. In Figure 21, solid lines are on metal layer 3 with priority horizontal routing, and dashed lines are on metal layer 4 with priority vertical routing. In some of the routes shown, each route has one or more horizontal route segments defined on horizontal PD metal layer 3 and connected to one or more vertical route segments defined on vertical PD metal layer 4. In each such route, each pair of connected horizontal and vertical segment pairs is connected via vias, resulting in a very large number (e.g., 176) vias in Figure 21.

[0151] Figure 22 shows curved NPD paths on metal layers 3 and 4 connecting the respective pins of several nets shown in Figure 20. In Figure 22, solid lines are on metal layer 3 with NPD directional wiring, and dashed lines are on metal layer 4 with NPD directional wiring. Each NPD path has one or more curved path segments defined on one or two curved NPD wiring layers. In each such path, the NPD path uses vias only to reach the NPD wiring layer in which the path is defined from the pins connected to the path, and does not use vias to connect the solid path segment on layer 3 to the dashed path segment on layer 4. This technique results in a significantly smaller number of vias (e.g., 20) in Figure 22. This technique is carried out at the expense of some of the NPD paths on a given NPD layer that are slightly longer in length, particularly when bypassing obstacles on the NPD layer. Examples of such longer NPD paths (longer to bypass obstacles) include NPD paths 2220, 2222, and 2224.

[0152] Furthermore, in the example in Figure 22, the majority of the NPD paths are defined on the third metal layer (i.e., the majority of the paths are shown as solid lines). This is because the majority of the paths can be defined on just one NPD wiring layer by allowing longer curved wires on one NPD wiring layer while avoiding vias to other NPD wiring layers. The longer lengths of the curved paths on metal layer 3 are acceptable because these paths are still relatively short (i.e., do not require buffering) and avoid vias, which are suboptimal from a manufacturing standpoint. This technique also consumes less area on metal layer 4, which can now be used to define NPD wiring for some of the intermediate-sized nets.

[0153] Figure 23 shows NPD router 2300 in several embodiments. As shown, the NPD router 2300 includes a topology router 2305, a geometric router 2310, and a post-routing optimizer 2315. In some embodiments, the topology router 2305 mosaics each NPD wiring layer or partition of each such layer in the IC design into several polygons (also called faces), and then defines topology paths (for connecting the nets) by referencing the edges of the mosaicked layers.

[0154] A particular topology path has a position defined by its relative position to other topology paths along the edges it intersects. Some embodiments also use nodes associated with polygonal faces to model vias between NPD wiring layers traversed by topology paths. In these embodiments, topology paths are defined not only by edges but also by face nodes and their relative positions to each other by referencing these edge and face nodes. In some embodiments, each particular topology path is also defined by the coordinates of pairs of nodes (in a netlist) connected by the topology path, or simply by referencing pairs of nodes as the start and end points of the topology path.

[0155] In some embodiments, the geometric router 2310 defines geometric realizations for each topology path defined by the topology router 2305. In some embodiments, the geometric router snaps each topology path to a grid (imposed on the wiring layer) along the wiring direction permitted for the layer. In embodiments that allow curved segments, this snapping allows wire segments to be curved. To generate geometric realizations of topology paths, the geometric router 2310 in some embodiments searches for straight and curved realizations of edges in the topology path, thereby generating straight and curved edges.

[0156] In some embodiments, the geometric router 2310 specifies specific geometric coordinates for the geometric paths it defines, thus specifying a particular interval between paths, whereas the topology router 2305 does not specify specific geometric coordinates for the topology paths it defines. However, in some embodiments, the topology router considers the expected wire thickness of the topology paths in order to track congestion along the mosaiced edges.

[0157] The post-routing optimizer 2315 attempts to improve the geometric path generated by the geometric router 2310 based on one or more optimization criteria. In improving the geometric path, the post-routing optimizer in some embodiments may move one or more edges of the geometric path and / or further define the geometric path by providing additional edges within the geometric path or by combining some edges within the geometric path.

[0158] In some embodiments, the optimizer 2315 is a compactor that defines a tighter compression of geometric paths. In this case, the optimization criterion reduces the size of the IC design. In other embodiments, the optimization criterion includes a timing criterion or spacing criterion that instructs the optimizer 2315 to space the geometric paths generated by the geometric router 2310 more evenly in order to improve the timing performance of signals traversing the interconnections generated based on these paths.

[0159] A more uniform distribution of geometric paths results in a reduction of parasitic capacitance due to the proximity of interconnection lines generated based on the geometric paths. In other words, by spacing the paths more evenly, the parasitic capacitance load on the wires is reduced, thereby reducing signal delay caused by parasitic capacitance. In yet another embodiment, the post-routing optimizer 2315 attempts to modify the geometric paths based on other criteria and / or multiple criteria.

[0160] As shown in the figure, the NPD router 2300 has a feedback loop from the post-routing optimizer 2315 to the geometric router 2310. The optimizer 2315 uses this feedback loop when it determines that this set of routes has suboptimal performance (e.g., the capacity load is too high or it is too long to satisfy timing constraints), and instructs the geometric router 2310 to identify a better set of one or more geometric routers for one or more nets in the IC design or partition being routed. In some embodiments, the post-routing optimizer 2315 may instruct the geometric router 2310 to identify a better set of routes over multiple iterations until an optimal set of geometric routes is identified for the set of nets.

[0161] In some embodiments, the geometric router 2310 only defines the initial geometric path for each topology path, leaving the final definition of the geometric path to the post-routing optimizer 2315, which then defines a particular geometric path based on one or more criteria, such as compressing the design to reduce the overall die size or widening the path to reduce capacitive coupling between nearby wires. For example, in some embodiments, a topology path has no arbitrary width or specific coordinates of its segment other than the coordinates of the two nodes (e.g., two pins) connected by the topology path.

[0162] Instead of snapping each topology path to a grid, in some embodiments, the geometric router defines the width of each topology path and then leaves it to the subsequent compactor to fully geometrically draw the path (e.g., generate a complete geometric definition of the path). In some such embodiments, the geometric router defines several intermediate coordinates for each topology path so that the geometric path it generates for a topology path not only has some width but also one or more intermediate coordinates that define two or more path segments. The post-routing optimizer 2315 then defines a particular geometric path based on one or more sets of criteria. In some embodiments, the post-routing optimizer 2315 comprises a compactor that uses a machine-trained network to improve the geometric path generated by the geometric router. U.S. Patent Application No. 17 / 992876, cited above, describes some examples of compactors that use a machine-trained network to improve routing in IC designs.

[0163] Figure 24 shows NPD router 2400 in several embodiments, which has a geometric router 2410 having a machine learning engine (e.g., a machine-trained neural network) that identifies geometric paths for a set of nets for which a topology router 2405 of the NPD router 2400 identifies topology paths. The figure shows a topology router 2405 that provides a set of topology paths 2402 that it identifies for a set of nets on the NPD wiring layer. Each topology path is defined by referring to an edge 2404 of a rectangular grid cell 2406 that mosaics the partitions of the NPD wiring layer. In this example, four grid cells 2406 are shown, and these grid cells contain four topology paths 2402, two of which bypass an obstacle 2408 in one of the cells. If two or more topology paths intersect an edge, each topology path intersection of that edge is defined with respect to where any other topology path intersects that same edge, for example, an edge intersection of one path is identified as being between one vertex of the edge and the edge intersection of another path.

[0164] Figure 24 also shows that the geometric router 2410 generates four geometric paths 2412 for four topology paths 2402. In some embodiments, each geometric path is defined by specific geometric coordinates associated with the pixels that define each geometric path. In some embodiments, the geometric router 2410 uses a machine-trained neural network that takes topology paths (e.g., edge intersections of each topology path) as input and generates geometric paths corresponding to the input topology paths as output. Also in some embodiments, the geometric paths generated by the geometric router are paths that mimic the expected manufactured shape of the paths.

[0165] In some embodiments, neurons in a neural network are trained by using a number of previously computed training sets, each set comprising a pair of input topological paths and their corresponding output geometric paths computed by a geometric router using one of the known EDA techniques to geometrically plot the topological paths (e.g., by snapping the topological paths to a grid). In some embodiments, the output geometric paths are the fabricated shapes of the geometric paths, which in some embodiments are generated by inspecting the actual interconnection shapes after fabrication, while in other embodiments they are generated by passing the geometric paths of each training set through a machine-trained network that generates the expected fabricated shapes of the geometric paths. Some of the training sets also include obstacles defined in the regions traversed by the topological and geometric paths.

[0166] During training, the topological paths of each training pair are fed through the neural network to generate output geometric paths, which are then compared to the geometric paths of the training pairs to generate difference values. Next, the difference values ​​of several training pairs are used to calculate the loss function value, and then the loss function value is backpropagated through the neural network to reconstruct the trainable parameters of the neural network.

[0167] In some embodiments, multiple instances of an NPD router simultaneously define paths for multiple partitions of a single NPD wiring layer in an IC design. For example, in some of these embodiments, each instance of the topology router (which defines a topology path for one partition) of the NPD router defines its topology path by mosaicing that partition into several (e.g., 16, 32, 50, 100, 128, 256) rectangular cells, and then referencing the edges of these cells intersected by the topology path. To geometrically plot each of the topology paths identified by its topology router instance, the geometric router instance in some of these embodiments iteratively (1) selects a different set of adjacent rectangular cells, and (2) uses its machine-trained neural network to geometrically plot the portion of the topology path that passes through the selected set of adjacent rectangular cells.

[0168] For example, Figure 25 shows an example where the topology router 2405 mosaics a partition into 64 rectangular cells 2502, and then uses them to define a topology path. This figure also shows that in some embodiments, the geometric router 2410 uses its machine-trained neural network four times to geometrically draw a topology path that first passes through the top-left 16 cells 2512, the top-right 16 cells 2514, the bottom-left 16 cells 2516, and the bottom-right 16 cells 2518. In some embodiments, the topology router 2405 mosaics the partition it is routing into more than 64 cells.

[0169] Some embodiments run multiple instances of an NPD router simultaneously on multiple processing cores of a computer to define routes for multiple partitions of one NPD wiring layer or a set of two or more NPD wiring layers in an IC design. This technique allows data computed by each NPD router instance for each partition to be shared with other NPD router instances that require access to this data when performing multiple iterations of its routing operation that depend on data computed by other NPD router instances. NPD router instances can share data via messaging or through a common memory they share.

[0170] For example, if the first and second NPD router instances each compute the first and second route segments of a topology path for at least one net traversing the first and second cells, then for the Nth iteration of that routing operation, the first NPD router instance defining the topology path for the first cell needs to know about the topology path computed by the second NPD router instance defining the topology path for the second cell adjacent to the first cell.

[0171] In such cases, the first NPD router instance needs to know where the second topology route segment (calculated by the second NPD router instance for a particular net) intersects the shared edge between the first and second cells. This knowledge ensures that the first NPD router instance does not define conflicting edge intersection locations for the first topology route segment it calculates that cross the same edge for a particular net. Typically, short nets enter one or two adjacent partitions, resulting in their routes traversing only one to three partitions. Note that in the case of three partitions, it typically includes a net with pins in two diagonally adjacent partitions, whereas the route would need to traverse another horizontally / vertically adjacent partition to reach the adjacent diagonally adjacent partition.

[0172] In some embodiments, the size of the partitions used to divide an NPD wiring layer or a set of two or more NPD wiring layers that are routed simultaneously by an NPD router is related to the amount of computing and memory resources of the computer used to perform simultaneous NPD routing for some or all of the partitions. Figures 26 and 27 show two alternative processes 2600 and 2700 for defining partition sizes related to the amount of computing and memory resources of the computer. In these examples, multiple NPD routers simultaneously define NPD routes (e.g., topology NPD routes) for some or all of the partitions used to divide one NPD wiring layer or a set of two or more NPD wiring layers that are being routed.

[0173] Process 2600 in Figure 26 first selects a desired partition size to divide the routing area (e.g., the NPD wiring layer of an IC design) into multiple partitions that will be routed simultaneously on multiple processing cores of a computer. Process 2600 then selects a computer with sufficient computing and memory resources (e.g., the number of cores and the amount of cache or RAM memory) to simultaneously process the NPD routing (e.g., topology routing) of all partitions on multiple NPD router instances that run concurrently and share their data in common memory.

[0174] In some embodiments, NPD router instances do not share memory but communicate data about their respective routings for adjacent partitions via messaging or some other mechanism. Also in some embodiments, each NPD router instance is allocated enough memory to allow the data that the router instance computes in each iteration of its routing for a partition to remain in memory for use in the next iteration of its routing operation (as opposed to moving the data to disk first and then back into memory).

[0175] On the other hand, process 270 in Figure 27 first selects a computer running multiple NPD router instances that will run concurrently to route some or all of the partitions of the routing area (in 2705). This computer has a certain amount of computing and memory resources (e.g., a certain number of cores and a certain amount of cache or RAM memory), and based on this, process 2700 then specifies the desired partition sizes to divide the routing area into several partitions that will be routed concurrently on multiple processing cores of the computer.

[0176] Many of the features and applications described above are implemented as software processes specified as a set of instructions recorded on a computer-readable storage medium (also called a computer-readable medium). When these instructions are executed by one or more processing units (e.g., one or more processors, processor cores, or other processing units), these instructions cause one or more processing units to perform the actions indicated by the instructions. Examples of computer-readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, and EPROMs. Computer-readable media do not include carrier waves and electronic signals transmitted wirelessly or via wired connections.

[0177] In this specification, the term “software” includes firmware residing in read-only memory or applications stored in magnetic storage devices that can be loaded into memory for processing by a processor. Furthermore, in some embodiments, multiple software inventions may be implemented as subparts of a larger program, leaving separate software inventions. In some embodiments, multiple software inventions may also be implemented as separate programs. Finally, any combination of separate programs that implement together the software inventions described herein is within the scope of the invention. In some embodiments, a software program defines one or more specific mechanical implementations that, once installed to operate on one or more electronic systems, perform and carry out the operation of the software program.

[0178] Figure 28 conceptually illustrates an electronic system 2800 in which several embodiments of the present invention are implemented. The electronic system 2800 may be a computer (e.g., a desktop computer, a personal computer, a tablet computer, a server computer, a mainframe, a blade computer, etc.) or any other type of electronic device. As shown, the electronic system includes various types of computer-readable media and interfaces for various other types of computer-readable media. Specifically, the electronic system 2800 includes a bus 2805, one or more processing units 2810, system memory 2825, read-only memory 2830, permanent storage device 2835, input device 2840, and output device 2845.

[0179] Bus 2805 collectively represents all system buses, peripheral buses, and chipset buses that communicate with a number of internal devices of the electronic system 2800. For example, bus 2805 communicates with one or more processing units 2810 to read-only memory (ROM) 2830, system memory 2825, and permanent storage device 2835. From these various memory units, one or more processing units 2810 retrieve instructions to be executed and data to be processed in order to perform the processes of the present invention. One or more processing units may be a single processor or a multi-core processor in different embodiments.

[0180] ROM 2830 stores static data and instructions required by one or more processing units 2810 and other modules of the electronic system. On the other hand, the permanent memory device 2835 is a read / write memory device. This device is a non-volatile memory unit that stores instructions and data even when the electronic system 2800 is turned off. Some embodiments of the present invention use a mass storage device (such as a magnetic or optical disk and its corresponding disk drive) as the permanent memory device 2835.

[0181] In other embodiments, a removable storage device (such as a floppy disk or flash drive) is used as the permanent storage device. Similar to the permanent storage device 2835, the system memory 2825 is a read-write memory device. However, unlike the storage device 2835, the system memory is a volatile read-write memory, such as random-access memory. The system memory stores some of the instructions and data that the processor needs at runtime. In some embodiments, the processes of the present invention are stored in the system memory 2825, the permanent storage device 2835, and / or the read-only memory 2830. From these various memory units, one or more processing units 2810 retrieve the instructions to be executed and the data to be processed in order to execute the processes of some embodiments.

[0182] Bus 2805 also connects to input device 2840 and output device 2845. The input device allows the user to communicate information to the electronic system and select commands. Input device 2840 includes an alphanumeric keyboard and a pointing device (also called a "cursor control device"). Output device 2845 displays images generated by the electronic system. The output device includes a printer and a display device such as a cathode ray tube (CRT) or liquid crystal display (LCD). Some embodiments include a device such as a touchscreen that functions as both an input and an output device.

[0183] Finally, as shown in Figure 28, bus 2805 also connects the electronic system 2800 to network 2865 via a network adapter (not shown). In this way, the computer can be part of a computer network (such as a local area network ("LAN"), a wide area network ("WAN"), or an intranet), or a network such as the Internet. Any or all components of the electronic system 2800 may be used in conjunction with the present invention.

[0184] Some embodiments include electronic components such as a microprocessor, storage, and memory that store computer program instructions in a machine-readable medium or computer-readable medium (or referred to as a computer-readable storage medium, machine-readable medium, or machine-readable storage medium). Some examples of such computer-readable media include RAM, ROM, read-only compact discs (CD-ROM), recordable compact discs (CD-R), rewritable compact discs (CD-RW), read-only digital multipurpose discs (e.g., DVD-ROM, dual-layer DVD-ROM), various recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD card, miniSD card, microSD card, etc.), magnetic and / or solid-state hard drives, read-only and recordable Blu-ray® discs, ultra-high density optical discs, any other optical or magnetic media, and floppy disks. Computer-readable media can store computer programs that are executable by at least one processing unit and contain instruction sets for performing various operations. Examples of computer programs or computer code include machine code, such as that generated by a compiler, and files containing high-level code that is executed by a computer, electronic component, or microprocessor using an interpreter.

[0185] While the above description primarily refers to a microprocessor or multicore processor running the software, some embodiments are executed by one or more integrated circuits, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored within the circuit itself.

[0186] As used herein, the terms “computer,” “server,” “processor,” and “memory” all refer to electronic devices or other technological devices. These terms exclude people or groups of people. For the purposes of this specification, the terms “display” or “display” mean to display on an electronic device. As used herein, the terms “one computer-readable medium,” “multiple computer-readable mediums,” and “machine-readable medium” are entirely limited to tangible physical objects that store information in a form readable by a computer. These terms exclude any radio signals, wired download signals, and any other transient or temporary signals.

[0187] While the present invention has been described with reference to numerous specific details, those skilled in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For example, some figures conceptually illustrate a process. The specific operations of these processes do not have to be performed in the exact order shown and described. The specific operations do not have to be performed in a single sequential series of operations, and different specific operations may be performed in different embodiments. Furthermore, a process can be implemented using several subprocesses or as part of a larger macroprocess. Accordingly, those skilled in the art will understand that the invention should not be limited by the above-mentioned exemplary details, but should be defined by the appended claims.

Claims

1. A method for designing integrated circuits (ICs), With respect to the first plurality of routing layers of the IC design, an NPD routing operation is performed to define non-preferred directions (NPD) paths on the first plurality of routing layers. With respect to the second plurality of routing layers of the IC design above the first plurality of routing layers, a preferred direction (PD) route is defined on the second plurality of routing layers using PD routing operations. A method that includes this.

2. The method according to claim 1, The PD routing operation uses one preferred routing direction on each routing layer within the second plurality of routing layers, and imposes a penalty on each route segment on each routing layer within the second plurality of routing layers that does not follow the preferred routing direction of that layer. The NPD routing operation described above is a method that does not use a single preferred routing direction on any of the routing layers among the first plurality of routing layers.

3. The method according to claim 2, wherein the NPD routing operation does not impose a penalty on any route segment along any routing direction on any of the routing layers of the first plurality of routing layers.

4. The method according to claim 2, wherein the NPD routing operation does not impose a penalty on any route segment along any one of the M routing directions on at least one of the routing layers of the first plurality of routing layers, where M is an integer greater than 8.

5. The method according to claim 2, wherein the second plurality of routing layers include at least first and second routing layers having first and second Manhattan-preferred routing directions, respectively.

6. The method according to claim 1, Performing the NPD routing operation includes defining a first set of curved paths, each of which traverses one or more of the first set of routing layers to connect at least two nodes of the IC design, and each curved path includes at least one curved segment. A method for performing the PD routing operation, comprising defining a second plurality of linear paths, each of which traverses one or more of the second plurality of routing layers to connect at least two nodes of the IC design, and each linear path having no curved paths.

7. The method according to claim 6, wherein performing the NPD routing operation includes defining a third plurality of linear paths, each of which traverses one or more of the first plurality of routing layers to connect the third plurality of nodes of the IC design.

8. The method according to claim 1, Performing the NPD routing operation includes defining a first set of paths, each of which traverses one or more of the first set of routing layers to connect at least two nodes of the IC design that are within a threshold distance of each other. A method for performing the PD routing operation, comprising defining a second plurality of paths, each of which traverses one or more of the second plurality of routing layers to connect at least two nodes of the IC design located beyond a threshold distance from each other.

9. The method according to claim 8, wherein the NPD routing operation imposes a penalty on paths longer than the threshold distance in order to bias against defining paths longer than the threshold distance.

10. The method according to claim 8, wherein the NPD routing operation uses a constraint to prevent the NPD path from becoming longer than the threshold distance.

11. The method according to claim 1, wherein the first plurality of routing layers include routing layer 3, and the second plurality of routing layers include routing layer 5 and routing layer 6.

12. The method according to claim 11, wherein the second plurality of routing layers further include routing layer 1 and routing layer 2.

13. The method according to claim 11, wherein the first plurality of routing layers further include routing layer 1 and routing layer 2.

14. The method according to claim 11, 12, or 13, wherein the first plurality of routing layers further include a routing layer 4.

15. The method according to claim 11, wherein the second plurality of routing layers further include routing layer 4.

16. The method according to claim 13, wherein each of the first plurality of routing layers has a plurality of regions having a preferred routing direction for PD paths of predefined circuit blocks on the layer, and performing the NPD routing operation includes defining a plurality of NPD paths on the first plurality of routing layers between the regions having PD paths for the predefined circuit blocks.

17. The method according to claim 2, wherein each preferred routing direction is horizontal or vertical, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between horizontal and vertical.

18. The method according to claim 2, wherein each preferred routing direction is horizontal, vertical, or diagonal, and the preferred routing directions of different adjacent layers in the second plurality of layers alternate between horizontal, vertical, and diagonal directions.

19. The method according to claim 2, wherein the preferred routing direction on each of the second plurality of layers is a direction that includes at least a threshold proportion of the route segments on the layer.

20. The method according to claim 1, wherein one router performs the NPD and PD routing operations.

21. The method according to claim 1, wherein the first router performs the NPD routing operation and the second router performs the PD routing operation.

22. A system comprising means for carrying out the method described in any one of claims 1 to 21.

23. A machine-readable medium for storing a program executed by at least one processing unit, wherein the program comprises a set of instructions for carrying out the method according to any one of claims 1 to 21.

24. It is an electronic device, A set of processing units, A machine-readable medium storing a program that, when executed by at least one processing unit, carries out the method described in any one of claims 1 to 21. An electronic device equipped with the following features.

25. A computer program that, when executed by at least one processor, causes a computer to perform the method according to any one of claims 1 to 21.

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