Approximate floating point fused dot product step to power circuit

Abstract

This invention provides an approximate floating-point fused point integral step-by-step alignment circuit, relating to the field of approximate circuit design. The invention generates two sets of effective dot product exponents based on the comparison results, and remaps the inputs of the first and second multiplication modules. The difference between the two sets of effective dot product exponents is applied step-by-step to the arithmetic shift of the approximate partial product, reducing the area of ​​the shift unit and the logic depth. A fine-grained step-by-step shift compression architecture is adopted, integrating alignment and compression operations within two processing units, avoiding large-width shifters becoming critical path bottlenecks. The processed first set of approximate partial products, the second set of approximate partial products after two compressions and shifts of the remaining partial products, and the sign compensation bit are fused and compressed, improving the efficiency of the fusion compression module and effectively reducing circuit area and delay.

Description

Technical Field

[0001] This invention relates to the field of approximate circuit design, and more particularly to an approximate floating-point fused point integration step order-aligned operation circuit. Background Technology

[0002] Compared to fixed-point numbers, floating-point numbers have a wider data representation range, making floating-point arithmetic widely used in fields with high data range requirements, such as digital signal processing, image recognition, and deep learning. However, floating-point arithmetic requires complex processing steps such as alignment, normalization, and rounding, leading to a significant increase in hardware resource overhead and computational latency. An effective optimization strategy is to decompose floating-point arithmetic steps and merge multiple floating-point operations to reduce redundant calculations and improve the overall performance of the floating-point arithmetic unit. For example, this invention combines multiplication and subsequent addition into a single operation, reducing the overhead of rounding and formatting intermediate results.

[0003] Research on fused floating-point dot product units is scarce. Current fused floating-point dot product units mainly focus on optimizing normalization, exponent comparison, or mantissa alignment logic in floating-point multiplication operations, or improving data throughput through pipeline design. However, this approach has the following problems:

[0004] (1) The implementation of the pipeline structure requires additional register cascading, which not only increases the hardware area and power consumption, but also results in a large total delay in completing a single floating-point fusion operation, making it difficult to meet the stringent time response requirements of scenarios such as real-time signal processing and low-latency inference. (2) Existing designs generate partial products through Booth encoding and adopt an overall shift alignment and compression strategy. They cannot perform differentiated approximation based on the weight differences of the partial products, resulting in a waste of hardware resources. Summary of the Invention

[0005] Purpose of the invention: For floating-point intensive applications that can tolerate moderate errors, an approximate floating-point fused point integration step alignment circuit is designed. While ensuring that the accuracy requirements of the application are met, the critical path delay, hardware area and dynamic power consumption are significantly reduced, making it suitable for multiple multiply-accumulate operation scenarios.

[0006] The present invention proposes an approximate floating-point fused point integration step order-alignment operation circuit, which includes: an extraction module, a sign integration module, an exponent comparison module, a first multiplication module, a second multiplication module, a partial product shift and compression module, a fusion compression module, and a result output module; The extraction module is used to extract the sign bit, mantissa bit, and exponent bit from four single-precision floating-point numbers conforming to the IEEE 754 standard, respectively. The symbol integration module is used to integrate the extracted sign bits and use the integrated sign bits to correct the mantissa bits to obtain the corrected mantissa bits. The index comparison module is used to calculate two sets of dot product effective indices based on the index digits, and to generate a comparison result of the two sets of dot product effective indices, the difference between the two sets of dot product effective indices, and the larger value of the two sets of dot product effective indices using the two sets of dot product effective indices. The first multiplication module is used to generate a first set of approximate partial products based on the corrected mantissa of the set of dot products with the larger effective exponent in the comparison results of the two sets of dot products. The second multiplication module is used to generate a second set of approximate partial products based on the corrected mantissa of the smaller set of dot products in the comparison of the effective exponents of the two sets of dot products. The partial product shifting and compression module performs arithmetic shifting of the last two rows of partial products on the second group of approximate partial products according to the magnitude of the second control quantity, adds sign compensation bits, and compresses the first group of approximate partial products after compression once. Then, it performs two compressions and shifts on the remaining part of the second group of approximate partial products. The fusion compression module is used to fuse and compress the processed first set of approximate partial products, the processed second set of approximate partial products, and the sign compensation bit to obtain two rows, which are denoted as the sum sequence and the carry sequence, respectively. The result output module is used to combine the sum sequence and the carry sequence with the larger of the two sets of effective exponents of the dot product to generate the dot product result.

[0007] Furthermore, the symbol integration module includes a first symbol integration unit and a second symbol integration unit; The first conformance integration unit is used to extract the first sign bit Second sign bit The first integrated symbol bit is obtained by integration. According to the first integrated symbol bit Correct the second last digit; The second symbol integration unit is used to integrate operators and the extracted third sign bit Fourth sign bit The integration process yields the second integrated symbol bit. According to the second integrated symbol bit Correct the fourth last digit; in, This represents the XOR operation. , indicates addition. =1 indicates a subtraction operation.

[0008] Furthermore, the first conformance integration unit includes: a first leading "1" extension unit, a first bit-inverting unit, a first XOR gate, and a first selector; The first leading "1" extension unit is used to respectively extend the first mantissa digits Second last digit Perform leading "1" expansion on the first mantissa. Second last digit Add three 001 bits before the highest bit to obtain the corrected first mantissa. The second mantissa, extended by the leading "1"; The first XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit. ; The first bit-inverting unit is used to add a bit before the most significant bit of the second mantissa. And except for the first integrated sign bit Invert all the bits outside the first digit to get the second bitwise reversed digit. The first selector is used to select from the second mantissa extended with leading "1" and the second mantissa bitwise reversed to obtain the corrected second mantissa. .

[0009] Furthermore, the second conformance integration unit includes: a second leading "1" extension unit, a second bit-inverting unit, a second XOR gate, a third XOR gate, and a second selector; The second leading "1" extension unit is used to respectively extend the third mantissa. and the fourth last digit Extend the leading "1" to the third mantissa. and the fourth last digit Add three 001 bits before the highest bit to obtain the corrected third mantissa. The fourth digit extended from the leading "1"; The second XOR gate is used to perform an XOR operation on the third sign bit and the fourth sign bit to obtain the third integrated sign bit; The third XOR gate is used to perform an XOR operation on the third integrated sign bit and the operator to obtain the second integrated sign bit. ; The second bitwise inversion unit is used to add a bit before the most significant bit of the fourth mantissa. And except for the second integration sign bit Invert all the bits except the first one to get the fourth bit of the reversed digits; The second selector is used to select from the fourth mantissa extended with leading "1" and the fourth mantissa bitwise reversed to obtain the corrected fourth mantissa. .

[0010] Furthermore, the calculation process for the two sets of effective exponents of the dot product is as follows:

[0011]

[0012] in, This represents the effective exponent of the first point product. Indicates the first exponent. Indicates the second exponent. This represents the effective exponent of the second point product. Indicates the third exponent. This indicates the fourth exponent.

[0013] Furthermore, the first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. The Booth encoding module is used to encode the selection result of the fourth selector to obtain the first Booth encoding; The first approximate partial product generation module is used to generate a first set of approximate partial products based on the selection result of the third selector and the first Booth encoding.

[0014] Furthermore, the second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, and a second approximate partial product generation module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, so as to obtain the corrected mantissa bits corresponding to the dot product with the smaller effective exponent; the seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding; The partial product shifting and compression module is used to perform an arithmetic right shift on the last two rows of the second group of approximate partial products by the difference between the effective exponents of the two groups of dot products. The most significant bit of the aligned approximate partial product is placed to the left of the column, and a sign compensation bit is added according to the integrated sign bit. It is then compressed a second time together with the first group of approximate partial products after the first compression. The remaining partial products are arithmetically right-shifted and a sign compensation bit is added after the two compressions.

[0015] Furthermore, if the sign bit is integrated Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if Add 0s to the left of the most significant bit of the aligned approximate partial product.

[0016] Furthermore, the result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module; The mantissa addition module is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module is used to determine whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, the summation result is inverted bitwise except for the sign bit. If the highest bit is 0, the summation result remains unchanged. Then, a leading "1" detection is performed, and the mantissa and exponent adjustment signals are output. The index adjustment module is used to adjust the index signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

[0017] Furthermore, the output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: (1) The approximate floating-point fused dot product operation circuit of the present invention generates two sets of dot product effective exponents based on the comparison results of the two sets of dot product effective exponents and remaps the inputs of the first multiplication module and the second multiplication module. The difference between the two sets of dot product effective exponents is applied to the arithmetic shift of the approximate partial product step by step, avoiding the large bit width shifter from becoming the critical path. This can effectively reduce the area of ​​the shift unit and the logic depth, and at the same time realize the close coordination between the exponent alignment and the data flow inside the multiplier. In addition, the Booth encoding module is used in the multiplication stage and approximate calculation is introduced to generate the approximate partial product to reduce the multiplication overhead.

[0019] (2) This invention adopts a fine-grained step-by-step shift and compression architecture, which integrates the alignment and compression operations into two processing units, thus avoiding large-width shifters becoming a bottleneck in the critical path. It avoids the coarse-grained alignment method of aligning all parts at once and then compressing them. Step-by-step alignment and parallel processing in groups reduce the scale of a single shift and compression, support differentiated approximation strategies, and effectively reduce circuit delay, area and power consumption.

[0020] (3) The approximate floating-point fused dot product operation circuit of the present invention fuses and compresses the processed first group of approximate partial products, the second group of approximate partial products after two compressions and shifts of the remaining partial products, and the sign compensation bits, thereby improving the efficiency of the fusion compression module and effectively reducing the circuit area and delay. In addition, during the approximate partial product shifting stage, a small amount of compensation "1" is injected according to the product sign. Without explicitly saving the complete sign extension, the result of the approximate partial product compression is equivalent to performing an arithmetic right shift on the high bits, thereby completing the sign correction with a small hardware overhead. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of an approximate floating-point fused point integration step alignment operation circuit module of the present invention.

[0022] Figure 2 This is a schematic diagram of the symbol integration module.

[0023] Figure 3 This is a schematic diagram of the overall principle of the approximate floating-point fusion point integration step alignment operation circuit of the present invention. Detailed Implementation

[0024] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0025] Existing floating-point fused dot product circuits employ a coarse-grained approach of overall shifting and alignment followed by uniform compression when performing partial product compression. This results in large-width shifters being located on the critical path, making it impossible to perform differentiated approximation based on the weight differences of the partial product. Furthermore, a single compression tree structure struggles to support differentiated approximation strategies, limiting the optimization space for accuracy and hardware overhead. In traditional solutions, shifting and compression operations are executed sequentially, failing to fully utilize parallelism and hindering fine-grained pipeline design, thus limiting improvements in throughput and energy efficiency.

[0026] Current floating-point fused dot product circuits suffer from long critical path delays, high hardware overhead, and a one-size-fits-all approach to precision processing, resulting in slightly lower energy efficiency in mobile computing and energy-intensive scenarios. To address this, this invention proposes a step-by-step, order-aligned approximate floating-point fused dot product circuit. By compressing and decomposing large shifts and multi-row partial products into smaller, parallel-processable segments, it significantly reduces latency and power consumption while maintaining application accuracy, achieving flexible and configurable optimization of accuracy, performance, and energy efficiency.

[0027] The following is combined Figures 1 to 3 The implementation examples are described in detail.

[0028] Figure 1 This is a schematic diagram of the approximate floating-point fusion point integration step alignment operation circuit of the present invention. The circuit includes: an extraction module, a sign integration module, an exponent comparison module, a first multiplication module, a second multiplication module, a partial product shift and compression module, a fusion compression module, and a result output module. The extraction module is used to extract data from four single-precision floating-point numbers conforming to the IEEE 754 standard. Extracting the sign bit mantissa and exponent The four single-precision floating-point numbers that conform to the IEEE 754 standard are all represented by 32 bits of binary. Taking A[31:0] as an example, the highest bit A

[31] is the sign bit. When A

[31] =1, it represents a negative number, and when A

[31] =0, it represents a positive number. A[30:23] is the exponent bit, and A[22:0] is the mantissa bit.

[0029] The sign integration module integrates the extracted sign bits and uses the integrated sign bits to correct the mantissa bits, obtaining the corrected mantissa bits. By integrating the sign bits in single-precision floating-point numbers and using the integrated sign bits to correct the mantissa bits, the module ensures that the two sets of dot products always perform addition operations, avoiding additional sign judgment and subtraction logic and reducing hardware overhead. Figure 2 The symbol integration module includes a first symbol integration unit and a second symbol integration unit; The first integration unit is used to extract the first symbol bit. Second sign bit The first integrated symbol bit is obtained by integration. According to the first integrated symbol bit Correct the second last digit; The second symbol integration unit is used to integrate operators and the extracted third sign bit Fourth sign bit The integration process yields the second integrated symbol bit. According to the second integrated symbol bit Correct the fourth last digit; in, This represents the XOR operation. , indicates addition. =1 indicates a subtraction operation.

[0030] In one technical solution of the present invention, the first conformance integration unit includes: a first leading "1" extension unit, a first bit-inverting unit, a first XOR gate, and a first selector; The first leading "1" extension unit is used to separate the first mantissa digits. Second last digit A leading "1" extension is performed. Considering that the subsequent Booth algorithm requires the bit width of both multipliers to be even, the first mantissa is... Second last digit Add three 001 bits before the highest bit to obtain the corrected first mantissa. The second mantissa, extended by the leading "1"; The first XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit. ; The first bitwise inversion unit is used to add a bit before the most significant bit of the second mantissa. And except for the first integrated sign bit Invert all the bits outside the first digit to get the second bitwise reversed digit. The first selector is used to select from the second mantissa extended with leading "1" and the second mantissa bitwise reversed to obtain the corrected second mantissa. The first mantissa digit of the correction was preserved through sign integration. Since the number is always positive, we only need to add bitwise inversion logic to the second mantissa, which reduces the circuit area and power consumption.

[0031] In one technical solution of the present invention, the second conforming integration unit includes: a second leading "1" extension unit, a second bit-inverting unit, a second XOR gate, a third XOR gate, and a second selector; The second leading "1" extension unit is used to separate the third mantissa digits. and the fourth last digit A leading "1" extension is performed. Considering that the subsequent Booth algorithm requires the bit width of both multipliers to be even, the extension is done in the third mantissa. and the fourth last digit Add three 001 bits before the highest bit to obtain the corrected third mantissa. The fourth digit extended from the leading "1"; The second XOR gate is used to perform an XOR operation on the third and fourth sign bits to obtain the third integrated sign bit. The third XOR gate is used to perform an XOR operation between the third integrated sign bit and the operator to obtain the second integrated sign bit. ; The second bitwise inversion unit is used to add a bit before the most significant bit of the fourth mantissa. And except for the second integration sign bit Invert all the bits except the first one to get the fourth bit of the reversed digits; The second selector is used to select from the fourth mantissa extended by a leading "1" and the fourth mantissa bit-reversed to obtain the corrected fourth mantissa. By integrating the operators representing addition and subtraction into the sign bit of the fourth mantissa, the bitwise NOT logic is reduced while ensuring that the two sets of dot products are always added, thus reducing the circuit's computational complexity and resource overhead.

[0032] The exponent comparison module is used to calculate two sets of effective exponents for the dot product based on the exponent digits, and then uses these two sets of effective exponents to generate a comparison result of the two sets of effective exponents. The difference between the two sets of effective exponents of the dot product and the larger of the two sets of effective exponents of the dot product , specifically, when hour, , , ;when hour, , , It is used for subsequent data exchange, approximate partial product shifting, and exponential adjustment.

[0033] The calculation process for the two sets of effective exponents of the dot product is as follows:

[0034]

[0035] in, This represents the effective exponent of the first point product. Indicates the first exponent. Indicates the second exponent. This represents the effective exponent of the second point product. Indicates the third exponent. This indicates the fourth exponent.

[0036] The first multiplication module is used to generate the first set of approximate partial products based on the corrected mantissa of the set of dot products with the larger effective exponent; for example... Figure 3 The first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. To reduce the resource overhead of mantissa multiplication, a Booth encoding module is introduced to encode the selection result of the fourth selector, resulting in the first Booth encoding. The first approximate partial product generation module is used to generate the first set of approximate partial products based on the selection result of the third selector and the first Booth encoding. The low-weight partial products are truncated, and only the high-weight partial product columns are generated when generating approximate partial products to reduce multiplication overhead. The specific degree of truncation can be determined according to different precision requirements.

[0037] The second multiplication module generates a second set of approximate partial products based on the smaller of the two sets of effective exponents, using the corrected mantissa bits. It then performs arithmetic shifts and adds sign compensation bits based on the difference between the two sets of effective exponents. Figure 3 The second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, and a second approximate partial product generation module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the two sets of dot product effective exponents, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, thus obtaining the corrected mantissa bits corresponding to the dot product with the smaller effective exponent. The seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. Through the second data exchange module, the operand with the smaller effective exponent is always connected to the second multiplication module, achieving close coordination between exponent alignment and the internal data flow of the multiplier.

[0038] The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding. The partial product shift and compression module is used to perform the difference between the effective exponents of the two sets of dot products on the last two rows of the second set of approximate partial products. The size is arithmetically right-shifted, and the most significant bit of the aligned approximate partial product is placed to the left. A sign compensation bit is added based on the integrated sign bit, and this is combined with the first group of approximate partial products after the first compression for a second compression. The remaining partial products are then arithmetically right-shifted after the two compressions and a sign compensation bit is added. If the integrated sign bit... Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if By adding zeros to the left of the most significant bit column of the aligned approximate partial product, and ensuring that the total number of bits for sign compensation is consistent with the number of bits in the first group of approximate partial products after truncation, the area and logic depth of the shifter are reduced, and sign correction is completed with a small hardware overhead.

[0039] This invention generates two sets of effective exponents based on the comparison results of the two sets of effective exponents of the dot product, and remaps the inputs of the first and second multiplication modules. The difference between the two sets of effective exponents of the dot product is applied step by step to the arithmetic shift of the approximate partial product, avoiding the large bit-width shifter from becoming the critical path. This effectively reduces the area of ​​the shift unit and the logic depth, while achieving close coordination between the exponent alignment and the data flow inside the multiplier. In addition, a Booth encoding module is used in the multiplication stage and approximate calculation is introduced to generate an approximate partial product to reduce the multiplication overhead.

[0040] The fusion compression module is used to fuse and compress the processed first set of approximate partial products, the processed second set of approximate partial products, and the sign compensation bit in the same compression tree, resulting in two rows denoted as the sum sequence. and carry sequence The fusion compression module uses 4:2 and 3:2 compressors, and the overall size of the fusion compression module is determined by the size of the approximate partial product matrix. By fusion compression of the processed first set of approximate partial products, the remaining partial products, and the shifted second set of approximate partial products, the efficiency of individual compressors in the fusion compression module is improved. This avoids two independent compression sets and carry propagation between multi-level groups, effectively reducing circuit area and delay. Furthermore, during the shifting stage of the second set of approximate partial products, a small amount of compensation "1" is injected according to the product sign. Without explicitly preserving the complete sign extension, the result of partial approximate product compression is equivalent to performing an arithmetic right shift on the complete product in the high-order bits, thus completing sign correction with minimal hardware overhead.

[0041] The result output module combines the sum sequence and the carry sequence with the larger of the two sets of effective exponents of the dot product to generate the dot product result. The result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module. The mantissa addition module uses a carry-lookahead adder and a carry-select adder to form a CLA-based CSA, which is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module determines whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, all bits of the summation result except the sign bit are inverted. If the highest bit is 0, the summation result remains unchanged. Then, a leading "1" is detected, and the mantissa and exponent adjustment signals are output. The index adjustment module is used to adjust the index based on the index adjustment signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

[0042] In one technical solution of the present invention, the output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An approximate floating-point fused point integration step alignment circuit, characterized in that, include: The extraction module is used to extract the sign bit, mantissa bit, and exponent bit from four single-precision floating-point numbers conforming to the IEEE 754 standard, respectively. The symbol integration module is used to integrate the extracted sign bits and use the integrated sign bits to correct the mantissa bits to obtain the corrected mantissa bits. The index comparison module is used to calculate two sets of dot product effective indices based on the index digits, and to generate a comparison result of the two sets of dot product effective indices, the difference between the two sets of dot product effective indices, and the larger value of the two sets of dot product effective indices using the two sets of dot product effective indices. The first multiplication module is used to generate a first set of approximate partial products based on the corrected mantissa of the set of dot products with the larger effective exponent in the comparison results of the two sets of dot products. The second multiplication module is used to generate a second set of approximate partial products based on the corrected mantissa of the smaller set of dot products in the comparison of the effective exponents of the two sets of dot products. The partial product shifting and compression module performs arithmetic shifting of the last two rows of partial products on the second group of approximate partial products according to the magnitude of the second control quantity, adds sign compensation bits, and compresses the first group of approximate partial products after compression once. Then, it performs two compressions and shifts on the remaining part of the second group of approximate partial products. The fusion compression module is used to fuse and compress the processed first set of approximate partial products, the processed second set of approximate partial products, and the sign compensation bit to obtain two rows, which are denoted as the sum sequence and the carry sequence, respectively. The result output module is used to combine the sum sequence and the carry sequence with the larger of the two sets of effective exponents of the dot product to generate the dot product result.

2. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The symbol integration module includes a first symbol integration unit and a second symbol integration unit; The first conformance integration unit is used to extract the first sign bit Second sign bit The first integrated symbol bit is obtained by integration. According to the first integrated symbol bit Correct the second last digit; The second symbol integration unit is used to integrate operators and the extracted third sign bit Fourth sign bit The integration process yields the second integrated symbol bit. According to the second integrated symbol bit Correct the fourth last digit; in, This represents the XOR operation. , indicates addition. =1 indicates a subtraction operation.

3. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The first conformance integration unit includes: a first leading "1" extension unit, a first bit-inverting unit, a first XOR gate, and a first selector; The first leading "1" extension unit is used to respectively extend the first mantissa digits Second last digit Perform leading "1" expansion on the first mantissa. Second last digit Add three 001 bits before the highest bit to obtain the corrected first mantissa. The second mantissa, extended by the leading "1"; The first XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit. ; The first bit-inverting unit is used to add a bit before the most significant bit of the second mantissa. And except for the first integrated sign bit Invert all the bits outside the first digit to get the second bitwise reversed digit. The first selector is used to select from the second mantissa extended with a leading "1" and the second mantissa bitwise reversed to obtain the corrected second mantissa. .

4. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The second conformal integration unit includes: a second leading "1" extension unit, a second bit-inverting unit, a second XOR gate, a third XOR gate, and a second selector; The second leading "1" extension unit is used to respectively extend the third mantissa. and the fourth last digit Perform leading "1" expansion in the third mantissa. and the fourth last digit Add three 001 bits before the highest bit to obtain the corrected third mantissa. The fourth digit extended by the leading "1"; The second XOR gate is used to perform an XOR operation on the third sign bit and the fourth sign bit to obtain the third integrated sign bit; The third XOR gate is used to perform an XOR operation on the third integrated sign bit and the operator to obtain the second integrated sign bit. ; The second bitwise inversion unit is used to add a bit before the most significant bit of the fourth mantissa. And except for the second integration sign bit Invert all the bits except the first one to get the fourth bit of the reversed digits; The second selector is used to select from the fourth mantissa extended with leading "1" and the bitwise reversed fourth mantissa to obtain the corrected fourth mantissa. .

5. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The calculation process for the two sets of effective exponents of the dot product is as follows: in, This represents the effective exponent of the first point product. Indicates the first exponent. Indicates the second exponent. This represents the effective exponent of the second point product. Indicates the third exponent. This indicates the fourth exponent.

6. The approximate floating-point fused point integration step order-alignment circuit according to claim 1, characterized in that, The first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. The Booth encoding module is used to encode the selection result of the fourth selector to obtain the first Booth encoding; The first approximate partial product generation module is used to generate a first set of approximate partial products based on the selection result of the third selector and the first Booth encoding.

7. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, and a second approximate partial product generation module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, so as to obtain the corrected mantissa bits corresponding to the dot product with the smaller effective exponent; the seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding; The partial product shifting and compression module is used to perform an arithmetic right shift on the last two rows of the second group of approximate partial products by the difference between the effective exponents of the two groups of dot products. The most significant bit of the aligned approximate partial product is placed to the left of the column, and a sign compensation bit is added according to the integrated sign bit. It is then compressed a second time together with the first group of approximate partial products after the first compression. The remaining partial products are arithmetically right-shifted and a sign compensation bit is added after the two compressions.

8. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, If the sign bit is integrated Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if Add 0s to the left of the most significant bit of the aligned approximate partial product.

9. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module; The mantissa addition module is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module is used to determine whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, the summation result is inverted bitwise except for the sign bit. If the highest bit is 0, the summation result remains unchanged. Then, a leading "1" detection is performed, and the mantissa and exponent adjustment signals are output. The index adjustment module is used to adjust the index signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

10. The approximate floating-point fused point integration step alignment circuit according to claim 1, characterized in that, The output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

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