A power-on reset circuit for an electric energy metering chip

Abstract

The application relates to a power-on reset circuit for an electric energy metering chip and belongs to the field of integrated circuit design. The circuit comprises a coarse detection module, a fine detection module and a logic combination module; a power supply voltage VDD is connected with the input ends of the coarse detection module and the fine detection module, the output ends of the coarse detection module and the fine detection module are connected with the input ends of the logic combination module, and the output end of the logic combination module outputs a signal as a system signal. The coarse detection module comprises four PMOS tubes PM0-PM3, five NMOS tubes NM0-NM4, a three-stage inverter and a transmission gate T0. The fine detection module comprises four series-connected voltage division resistors R1-R4, two operational amplifiers A0-A1 and an SR latch. The application solves the defects of a traditional power-on reset circuit in terms of detection precision, anti-interference and scene configuration, and ensures stable reset of a chip system during power-on / power-off and no abnormal starting risk.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and relates to a power-on reset circuit for chip systems, which is suitable for complex chips such as SOCs and MCUs that have high requirements for power supply stability and reset accuracy. Background Technology

[0002] In integrated circuit (IC) and electronic system design, ensuring the system can enter a predetermined initial state during power-on transients is a prerequisite for reliable system operation. The Power-on Reset (POR) circuit acts as the "gatekeeper" of system startup. Its core task is to generate a reset pulse signal of sufficient duration and defined level as the power supply voltage (VDD) rises from zero to the minimum operating voltage required to maintain normal circuit operation. This signal is used to initialize the system's internal digital logic, registers, state machine, and processor core, preventing deadlock, abnormal power consumption, or illegal operations caused by the system being in an uncertain logic state (X state) during power-on. Only when the power supply voltage reaches a stable value and all system modules are ready will the POR signal be withdrawn (released), allowing the system to begin executing the program from address zero or a specific initial state.

[0003] Currently, the industry mainly uses the following two technical approaches to implement power-on reset functionality. However, with the advancement of integrated circuit technology and the diversification of application scenarios, their respective limitations are becoming increasingly apparent: (1) External RC differentiating circuit (e.g.) Figure 1 (As shown): The structure consists of a resistor, a capacitor, and a reverse diode. The power supply VDD charges the capacitor through the resistor, generating a high-to-low delayed signal at the reset terminal. However, this structure is highly dependent on the power-up speed. If the power supply rises too slowly, the reset signal may be withdrawn before the system voltage stabilizes, causing the reset function to fail. Furthermore, the simple RC structure is easily affected by power supply noise. Moreover, off-chip RC structures are difficult to apply to most current chip designs with limited area.

[0004] (2) On-chip detection circuit based on MOSFET threshold voltage (e.g.) Figure 2 (As shown): The structure consists of resistors and a MOSFET. The resistors are connected in series to form a resistor divider circuit, generating a voltage to be detected that is proportional to the power supply voltage VDD. This voltage is then compared with the threshold voltage of the MOSFET in the next stage to obtain the reset potential. However, this structure requires a trade-off between power consumption and area. A larger resistor results in lower power consumption but a larger area. Furthermore, the MOSFET threshold voltage setting is quite strict. If it is set too high, premature reset may occur when VDD fluctuates; if it is set too low, the system may start under undervoltage conditions, leading to abnormalities.

[0005] In summary, existing POR circuit solutions struggle to achieve an ideal balance between ultra-low power consumption, small-area integration, highly reliable power-on detection, and wide-range power slope adaptation. Particularly in Internet of Things (IoT) devices and portable medical electronics, achieving accurate monitoring of power state under extremely low quiescent current and providing robust reset response has become a critical technical challenge urgently needing to be addressed in the field of integrated circuit design. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a power-on reset circuit for an energy metering chip, which solves the defects of traditional power-on reset circuits in terms of "detection accuracy, anti-interference ability, and scenario compatibility", and ensures that the chip system is stably reset during power-on / power-off and has no risk of abnormal startup.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A power-on reset circuit for an energy metering chip includes a coarse detection module, a fine detection module, and a logic combination module; the power supply voltage VDD is connected to the input terminals of the coarse detection module and the fine detection module, the output terminals of the coarse detection module and the fine detection module are connected to the input terminal of the logic combination module, and the output terminal of the logic combination module outputs a signal as a system signal.

[0008] Preferably, the coarse detection module includes four PMOS transistors, namely PM0~PM3, five NMOS transistors, namely NM0~NM4, an inverter chain (three-stage inverter), and a transmission gate T0; In this configuration, the gate of PM0 is connected to its drain, and its source is connected to the power supply voltage VDD and the source of PM1. The gates of NM0 to NM3 are connected to the power supply voltage VDD, forming the voltage detection threshold. The drain of NM0 is connected to the drain of PM0 and the input of transmission gate T0. The source of NM0 is connected to the drain of NM1, the output of transmission gate T0, and the gate of NM4. The source of NM1 is connected to the drain of NM2, the source of NM2 is connected to the drain of NM3, and the sources of NM3 and NM4 are grounded together. The drain of NM4 is connected to the input of the inverter chain and the drain of PM3. The source of PM3 is connected to the drain of PM2, the source of PM2 is connected to the drain of PM1, and the gates of PM1 to PM3 are all grounded.

[0009] In the coarse detection module, PM0 is a pull-up transistor, and NM0~NM3 are pull-down networks. The number of NMOS transistors cascaded in the access circuit is selected by the transmission gate T0. When powered on, one more NMOS transistor (NM0) is connected, and when powered off, one less NMOS transistor (NM0) is connected, forming a hysteresis threshold. The switching voltage is set by setting the width-to-length ratio of the NMOS transistors. PM1~PM3 are pull-up networks, and NM4 is a pull-down transistor, which, together with the inverter chain, realizes signal buffering and shaping.

[0010] The precise detection module includes four series-connected voltage-dividing resistors, namely R1 to R4, two operational amplifiers, namely A0 to A1, and an SR latch; R1 to R4 form a series voltage-dividing network to divide the power supply voltage VDD and output two different voltage-dividing levels; A0 and A1 are high-gain operational amplifiers to compare the external reference voltage VREF with the voltage-dividing levels; the SR latch consists of two NAND gates to latch the comparison result of the operational amplifiers.

[0011] The logic combination module includes a two-input NAND gate and a first-stage inverter; the NAND gate receives the output signals of the coarse detection module and the precise detection module; the inverter shapes the output of the NAND gate to enhance the driving ability.

[0012] The working mechanism of this circuit is divided into four stages: Stage 1: In the initial stage of power-on, the power supply voltage VDD < the coarse detection threshold; When the power supply voltage VDD in the coarse detection module (POR_Corase) is low, the gate-source voltages (VGS) of NM0 to NM3 do not reach the conduction threshold, and the pull-down network fails; PM0 conducts, and the coarse detection module (POR_Coarse) outputs a high level, and the transmission gate T0 does not conduct; In the precise detection module (POR_Fine), the voltage-dividing levels generated by the power supply voltage VDD through the voltage-dividing resistors are lower than the reference voltage VREF, the operational amplifiers A0 and A1 output low levels, and the SR latch outputs a low level; In the logic combination module, the inputs of the NAND gate are "low + low", and the output is high; the output of the inverter is low, and the system is in the reset state; Stage 2: The power supply voltage VDD reaches the coarse detection threshold, that is, the coarse detection threshold < VDD < the precise detection threshold; In the coarse detection module (POR_Corase), the power supply voltage VDD reaches the threshold voltage for the gate-source voltages VGS of NM0 to NM3 to conduct, and the pull-down network conducts, pulling the output of the coarse detection module to a high level; In the precise detection module (POR_Fine), the voltage-dividing levels of the power supply voltage VDD < the reference voltage VREF, and the SR latch still outputs a low level; the system maintains the reset state; Stage 3: The power supply voltage VDD reaches the precise detection threshold, that is, VDD ≥ the precise detection threshold; In the coarse detection module (POR_Corase), the pull-down network continues to conduct, and the output remains low; In the precise detection module (POR_Fine), the voltage-dividing levels of the power supply voltage VDD are higher than the reference voltage VREF, the operational amplifiers A0 and A1 output high levels, and the SR latch flips and latches to a high level; In the logic combination module, the NAND gate has "high + high" inputs and outputs a low level; the inverter outputs a high level, the reset signal is released, and the system starts. Phase 4: Power Failure in Power-On Scenarios, when the power supply voltage VDD drops; In the coarse detection module (POR_Corase), the pull-down network is cut off, and the output remains low. The SR latch in the fine detection module (POR_Fine) still outputs a low level; In the logic combination module, when the NAND gate input is "low + low", the output is high; when the inverter outputs a low level, the system is in a reset state.

[0013] The beneficial effects of this invention are as follows: (1) This invention adopts a graded triggering mechanism that combines coarse detection and fine detection, which improves detection accuracy and provides dual triggering protection. The coarse detection module uses a cascaded MOS transistor structure to achieve fast response and establish the basic voltage range; the fine detection module compares the voltage divider level with the external precision reference voltage through a high-gain operational amplifier. This design overcomes the shortcomings of traditional circuits that rely solely on the threshold voltage of the MOS transistor and are easily affected by process angle and temperature drift, greatly reduces the deviation of the reset and cancellation voltage, and ensures that the chip starts at the precise voltage critical point.

[0014] (2) The circuit designed in this invention constructs a "preventing false triggering" barrier in multiple dimensions, exhibiting excellent resistance to power supply glitches and noise suppression capabilities. The coarse detection module dynamically switches the number of cascaded NMOS transistors during power-on and power-off processes through the transmission gate, forming a clear hysteresis comparator structure, effectively preventing minor fluctuations or noise on the power line from causing the reset signal to "oscillate" at the critical point. The fine detection module introduces an SR latch, which can lock the comparison result at a certain level. Even if transient glitches occur in the power supply, the latching mechanism can maintain the stability of the current state, avoiding asymmetrical resets or illegal restarts caused by unclean power supplies.

[0015] (3) For complex scenarios such as "rapid power loss followed by immediate power-on" that power metering chips may face, the circuit designed in this invention has excellent scenario adaptability and power-down reliability. The collaborative working mechanism of the coarse detection module and the fine detection module ensures that the system can quickly detect voltage drops and promptly pull down the reset signal during power loss. The logic combination module interleaves the two-level signals, enabling the circuit to adapt to systems with multiple voltage levels and ensuring that a definite reset sequence can be generated under power-on conditions with different slopes, eliminating the risk of state machine deadlock caused by undervoltage start-up.

[0016] (4) The circuit designed in this invention has flexible adjustability and can perform timing matching. By adjusting the width-to-length ratio of the NMOS transistor in the coarse detection module and the voltage divider resistor ratio in the fine detection module, the designer can accurately set the hold time of the reset signal according to the specific chip requirements. The first-stage inverter at the end of the logic combination module not only plays a signal shaping role, but also enhances the driving capability of the reset signal on the large-scale digital logic array inside the chip, ensuring the consistency of global reset.

[0017] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 It is an off-chip RC differentiating circuit; Figure 2 This is an on-chip detection circuit based on the MOSFET threshold voltage; Figure 3 This is the power-on reset circuit diagram; Figure 4 This is the circuit diagram for the coarse detection module (POR_Corase); Figure 5 This is the circuit diagram for the precision detection module (POR_Fine). Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0021] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0022] Please see Figures 3-5 This invention provides a power-on reset circuit for an energy metering chip, such as... Figure 3 As shown, the circuit includes a coarse detection module (POR_Corase), a fine detection module (POR_Fine), and a logic combination module.

[0023] like Figure 4 As shown, the coarse detection module (POR_Corase) includes PMOS transistors PM0~PM3, NMOS transistors NM0~NM4, an inverter chain (three-stage inverters), and a transmission gate T0. PM0 is a pull-up transistor with its gate connected to its drain (always conducting after power-on); NM0~NM3 form a pull-down network with their gates connected to the power supply voltage VDD, constituting the voltage detection threshold; the transmission gate T0 selects the number of NMOS transistors cascaded in the circuit, adding one more NMOS transistor during power-on and removing one during power-off, forming the hysteresis threshold. The switching voltage is set by adjusting the width-to-length ratio of the NMOS transistors; PM1~PM3 form a pull-up network, and NM4 is a pull-down transistor, working with the inverter chain to achieve signal buffering and shaping.

[0024] like Figure 5 As shown, the fine detection module (POR_Fine) includes voltage dividers R1~R4, operational amplifiers A0~A1, and an SR latch. R1~R4 form a series voltage divider network that divides the power supply voltage VDD, outputting two different voltage levels. A0 and A1 are high-gain operational amplifiers that compare the external reference voltage VREF with the divided voltage levels. The SR latch consists of two NOR gates that latch the comparison result from the operational amplifiers.

[0025] like Figure 3 As shown, the logic combination module includes a two-input NAND gate and a single-stage inverter. The NAND gate receives the output signals from the coarse detection module and the fine detection module; the inverter shapes the output of the NAND gate to enhance its driving capability.

[0026] The working mechanism of this circuit is divided into four stages: Stage 1: At the initial stage of power-on (VDD < coarse detection threshold); Stage 2: VDD reaches the coarse detection threshold (coarse detection threshold < VDD < fine detection threshold); Stage 3: VDD reaches the fine detection threshold (VDD ≥ fine detection threshold); Stage 4: Power-off in the power-on scenario.

[0027] Stage 1: Coarse detection module: When the VDD voltage is low, the gate-source voltage (VGS) of NM0 - NM3 does not reach the conduction threshold, and the pull-down network is paralyzed; PM0 conducts, the coarse detection module outputs a low level, and the transmission gate T0 does not conduct.

[0028] Fine detection module: The divided voltage level generated by VDD through the voltage-dividing resistor is lower than VREF, the operational amplifiers A0 and A1 output low levels, and the SR latch outputs a low level.

[0029] In the logic combination module, the input of the NAND gate is "low + low", and the output is high level; the inverter outputs a low level, and the system is in the reset state.

[0030] Stage 2: Coarse detection module: The VDD voltage reaches the threshold voltage for VGS conduction of NM0 - NM3, the pull-down network conducts, and the output of the coarse detection module is pulled to a high level.

[0031] Fine detection module: The divided voltage level of VDD < VREF, and the SR latch still outputs a low level. The system maintains the reset state.

[0032] Stage 3: Coarse detection module: The pull-down network continues to conduct, and the output remains low.

[0033] Fine detection module: The divided voltage level of VDD is higher than VREF, the operational amplifiers A0 and A1 output high levels, and the SR latch flips and latches to a high level.

[0034] In the logic combination module, the input of the NAND gate is "high + high", and the output is low level; the inverter outputs a high level, the reset signal is released, and the system starts.

[0035] Stage 4: When VDD is powered off: Coarse detection module: The pull-down network of the coarse detection module is cut off, and the output remains low.

[0036] Fine detection module: The SR latch of the fine detection module still outputs a low level.

[0037] In the logic combination module, the input of the NAND gate is "low + low", and the output is high level; the inverter outputs a low level, and the system is in the reset state.

[0038] In summary, the advantages of the circuit designed in this embodiment compared with the traditional structure are: (1) the threshold deviation is greatly reduced and the detection accuracy is high; (2) the resistance to power supply glitches is improved; (3) it is compatible with multi-voltage systems and power-off and power-on scenarios; (4) the timing is matched and the reset signal holding time is controllable.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A power-on reset circuit for an energy metering chip, characterized in that, It includes a coarse detection module, a fine detection module and a logic combination module; the power supply voltage VDD is connected to the input ends of the coarse detection module and the fine detection module, the output ends of the coarse detection module and the fine detection module are connected to the input end of the logic combination module, and the output end of the logic combination module outputs a signal as the system signal.

2. The power-on reset circuit according to claim 1, characterized in that, The coarse detection module includes four PMOS transistors, namely PM0~PM3, five NMOS transistors, namely NM0~NM4, an inverter chain and a transmission gate T0; Among them, the gate and drain of PM0 are connected, and the source is connected to the power supply voltage VDD and the source of PM1; the gates of NM0~NM3 are connected to the power supply voltage VDD to form a voltage detection threshold; the drain of NM0 is connected to the drain of PM0 and the input of the transmission gate T0, and the source of NM0 is connected to the drain of NM1, the output of the transmission gate T0 and the gate of NM4; the source of NM1 is connected to the drain of NM2, the source of NM2 is connected to the drain of NM3, and the sources of NM3 and NM4 are grounded together; the drain of NM4 is connected to the input of the inverter chain and the drain of PM3; the source of PM3 is connected to the drain of PM2, the source of PM2 is connected to the drain of PM1, and the gates of PM1~PM3 are grounded.

3. The power-on reset circuit according to claim 1, characterized in that, In the coarse detection module, PM0 is a pull-up transistor, NM0~NM3 is a pull-down network, and the number of cascaded NMOS transistors connected to the circuit is selected through the transmission gate T0. When powering on, one more NMOS transistor, namely NM0, is connected, and when powering off, one less NMOS transistor, namely NM0, is connected, forming a hysteresis threshold, and the switching voltage is set by setting the width-to-length ratio of the NMOS transistors; PM1~PM3 is a pull-up network, and NM4 is a pull-down transistor, which cooperates with the inverter chain to realize signal buffering and shaping.

4. The power-on reset circuit according to claim 2 or 3, characterized in that, The inverter chain is a three-stage inverter.

5. The power-on reset circuit according to claim 1, characterized in that, The fine detection module includes four series-connected voltage-dividing resistors, namely R1~R4, two operational amplifiers, namely A0~A1 and an SR latch; R1~R4 is a series voltage-dividing network that divides the power supply voltage VDD and outputs two different voltage-dividing levels; A0 and A1 are high-gain operational amplifiers that compare the external reference voltage VREF with the voltage-dividing levels; the SR latch is composed of two NOR gates and latches the comparison result of the operational amplifier.

6. The power-on reset circuit according to claim 1, characterized in that, The logic combination module includes a two-input NAND gate and a first-stage inverter; the NAND gate receives the output signals of the coarse detection module and the fine detection module; the inverter shapes the output of the NAND gate.

7. The power-on reset circuit according to any one of claims 1 to 3, 5 to 6, characterized in that, The working mechanism of this circuit is divided into four stages: Stage 1: In the initial stage of power-on, the power supply voltage VDD < the coarse detection threshold; When the power supply voltage VDD in the coarse detection module is low, the gate-source voltage VGS of NM0~NM3 does not reach the conduction threshold, and the pull-down network fails; PM0 conducts, the coarse detection module outputs a high level, and the transmission gate T0 does not conduct; In the fine detection module, the voltage-dividing levels generated by the power supply voltage VDD through the voltage-dividing resistors are lower than the reference voltage VREF, the operational amplifiers A0 and A1 output low levels, and the SR latch outputs a low level; In the logic combination module, the input of the NAND gate is "low + low", and the output is high; the output of the inverter is low, and the system is in a reset state; Stage 2: The power supply voltage VDD reaches the coarse detection threshold, that is, the coarse detection threshold < VDD < the fine detection threshold; When the power supply voltage VDD in the coarse detection module reaches the threshold voltage VGS of the gate-source voltage NM0~NM3 to turn on, the pull-down network turns on and pulls the output of the coarse detection module to a high level. In the precision detection module, the voltage divider level of the power supply voltage VDD is less than the reference voltage VREF, and the SR latch still outputs a low level; the system remains in a reset state. Phase 3: The power supply voltage VDD reaches the fine detection threshold, i.e., VDD ≥ fine detection threshold; In the coarse detection module, the pull-down network remains continuously connected, and the output remains at a low level. In the precision detection module, the power supply voltage VDD is higher than the reference voltage VREF, the operational amplifiers A0 and A1 output high levels, and the SR latch flips and latches to a high level. In the logic combination module, the NAND gate has "high + high" inputs and outputs a low level; the inverter outputs a high level, the reset signal is released, and the system starts. Phase 4: Power Failure in Power-On Scenarios, when the power supply voltage VDD drops; In the coarse detection module, the pull-down network is cut off, and the output remains low. The SR latch in the precision detection module still outputs a low level; In the logic combination module, when the NAND gate input is "low + low", the output is high; when the inverter outputs a low level, the system is in a reset state.

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