Semiconductor elements and semiconductor assemblies containing them

Abstract

The present invention provides semiconductor elements and semiconductor assemblies including them. [Solution] The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is located between the first and second semiconductor structures and includes a first dopant. This semiconductor device is J_E max A / cm 2 Under the current density, the maximum external quantum efficiency E max It has %, and 0.001*(J_E max ) A / cm 2 Under the current density, the semiconductor element is E max It has an external quantum efficiency of 15% or more.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor light-emitting devices, such as light-emitting diodes. [Background technology]

[0002] Semiconductor devices have a very wide range of applications, and the development and research of related materials continues. For example, III-V semiconductor materials, including group 3 and group 5 elements, can be applied to various photoelectric semiconductor devices, such as light-emitting diodes (LEDs), laser diodes (LDs), photoelectric detectors, or solar cells, or they may be power elements for switches or rectifiers used in fields such as lighting, medical, displays, communications, sensing, and power systems. Light-emitting diodes, as one type of semiconductor light-emitting device, are widely used because they have advantages such as low power consumption and a long service life. [Overview of the project] [Problems that the invention aims to solve]

[0003] The object of the present invention is to provide a semiconductor element and a semiconductor assembly including the same. [Means for solving the problem]

[0004] According to the present invention, a semiconductor device is provided which comprises a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure comprises a first dopant. The second semiconductor structure is located on the first semiconductor structure and comprises a second dopant different from the first dopant. The active region is located between the first semiconductor structure and the second semiconductor structure and comprises a first dopant. This semiconductor device is J_E max A / cm 2 Under the current density, the maximum external quantum efficiency E max It has % of which 0.001 A / cm² 2 ≦J_E max A / cm 2≤100 A / cm 2 and, under a current density of 0.001*(J_E max ) A / cm 2 , the semiconductor device has an external quantum efficiency of 15% or more of E max %.

Brief Description of the Drawings

[0005] [Figure 1A] It is a top view of a semiconductor device in one embodiment of the present invention. [Figure 1B] It is a diagram showing a cross-sectional structure of a semiconductor device in one embodiment of the present invention. [Figure 1C] It is a partially enlarged view of a semiconductor device in one embodiment of the present invention. [Figure 1D] It is a diagram showing a cross-sectional structure of a semiconductor device in one embodiment of the present invention. [Figure 1E] It is a top view of a semiconductor device in one embodiment of the present invention. [Figure 1F] It is a diagram showing a cross-sectional structure of a semiconductor device in one embodiment of the present invention. [Figure 2A] It is a diagram showing the relationship between the current density and the internal quantum efficiency (IQE) of a semiconductor device in an embodiment of the present invention. [Figure 2B] It is a diagram showing the relationship between the current density and the external quantum efficiency (EQE) of a semiconductor device in an embodiment of the present invention. [Figure 2C] It is a diagram showing the relationship between the R value and the relative EQE ratio of a semiconductor device in an embodiment of the present invention. [Figure 2D] It is a diagram showing the relationship between the current density and the external quantum efficiency (EQE) of a semiconductor device in an embodiment of the present invention. [Figure 3] It is a diagram showing the relationship between the concentration and depth of elements in a partial region of a semiconductor device in one embodiment of the present invention. [Figure 4] It is a diagram showing the relationship between the current density and the internal quantum efficiency (IQE) of a semiconductor device in an embodiment of the present invention. [Figure 5A] It is a diagram showing a cross-sectional structure of a semiconductor assembly in one embodiment of the present invention. [Figure 5B] This is a diagram showing a cross-sectional structure of a semiconductor assembly according to an embodiment of the present invention. [Figure 6] This is a diagram showing a cross-sectional structure of a semiconductor assembly according to an embodiment of the present invention. [Figure 7] This is a top view of a semiconductor assembly according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0006] Hereinafter, several embodiments will be described to enable those skilled in the art to more easily understand the present invention. Note that these embodiments are merely illustrative and do not limit the present invention. Also, those skilled in the art may adjust the embodiments described below according to needs. For example, the order of the processes may be changed, and / or some steps may be increased or decreased.

[0007] Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0 < x0 < 1; the general formula AlInP represents Al x1 In 1-x1 P, where 0 < x1 < 1; the general formula AlGaInP represents Al x2 Ga x3 In 1-x2-x3 P, where 0 < x2 < 1, 0 < x3 < 1; the general formula InGaAsP represents In x4 Ga 1-x4 As[[ID=3�]] x5 P 1-x5 where 0 < x4 < 1, 0 < x5 < 1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6-x7 As, where 0 < x6 < 1, 0 < x7 < 1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 where 0 < x8 < 1, 0 < x9 < 1; the general formula InGaAs represents In x10 Ga 1-x10represents As, where 0 < x10 < 1; the general formula AlGaAs represents Al x11 Ga 1-x11 represents As, where 0 < x11 < 1; the general formula InGaN represents In x12 Ga 1-x12 represents N, where 0 < x12 < 1; the general formula AlGaN represents Al x13 Ga 1-x13 represents N, where 0 < x13 < 1; the general formula AlGaAsP represents Al x14 Ga 1-x14 As x15 P 1-x15 represents, where 0 < x14 < 1, 0 < x15 < 1; the general formula InGaAsN represents In x16 Ga 1-x16 As x17 N 1-x17 represents, where 0 < x16 < 1, 0 < x17 < 1; the general formula AlInGaN represents Al x18 In x19 Ga 1-x18-x19 represents N, where 0 < x18 < 1, 0 < x19 < 1. Also, the content of each element can be adjusted according to different purposes. For example, it is not limited to adjusting the magnitude of the energy level, or when the semiconductor device is a light-emitting device, the main wavelength (domain wavelength) or peak wavelength of the light-emitting device can be adjusted thereby.

[0008] The semiconductor device of the present invention is, for example, a light-emitting element (e.g., a light-emitting diode, a laser diode), a light-absorbing element (e.g., a photo-detector), or a non-emitting element. The components and dopants of each layer contained in the semiconductor device of the present invention can be obtained by analyzing them using any suitable method, for example, a secondary ion mass spectrometer (SIMS). The thickness of each layer can also be obtained by analyzing them using any suitable method, for example, a transmission electron microscope (TEM), a scanning electron microscope (SEM), etc.

[0009] Those skilled in the art should understand that other components may be added based on each embodiment described below. For example, unless otherwise specified, a statement such as "the first layer (or structure) is located on the second layer (or structure)" may include embodiments in which the first layer (or structure) is in direct contact with the second layer (or structure), or it may include embodiments in which there is another structure between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. It should also be understood that the relative positions of each layer (or structure) may change depending on the viewing direction.

[0010] Furthermore, in this invention, a description such as "a layer or structure consisting substantially of M" indicates that the main component of this layer or structure is M, but does not exclude the inclusion of dopants or unavoidable impurities.

[0011] Figure 1A is a top view of a semiconductor element 10 in one embodiment of the present invention. Figure 1B is a diagram showing the cross-sectional structure of the semiconductor element 10 in Figure 1A along the line X-X'. Figure 1C is a partially enlarged view of region R in the semiconductor element 10 shown in Figure 1B. As shown in Figure 1A, in a top view, the semiconductor element 10 may have a length L0 and a width W0. The length L0 and width W0 may each be 500 μm or less, for example, 450 μm, 400 μm, 350 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 30 μm or 10 μm or less, and may also be 1 μm or more. In a top view, the semiconductor element 10 may have a rectangular or circular shape. In one embodiment, the length L0 and width W0 of the semiconductor element 10 may be approximately equal, forming a square. In one embodiment, when viewed from above, the area (L0*W0) of the upper surface of the semiconductor element 10 is 10,000 μm². 2 For example, 1 μm 2 ~5000μm 2 Within the range (for example, 100 μm) 2 , 625μm 2 , 1250 μm 2 , 2000 μm 2 or 2500 μm 2 As shown in Figures 1A and 1B, the semiconductor device 10 includes a base 100, an epitaxial structure 102, a first electrode 110, and a second electrode 112. The epitaxial structure 102 is located on the base 100. The first electrode 110 is located on the epitaxial structure 102, and the second electrode 112 is located below the base 100.

[0012] The base 100 comprises a conductive or insulating material, the conductive material being, for example, GaAs, InP, SiC, GaP, ZnO, GaN, AlN, Ge, Si, and the insulating material being, for example, sapphire. In one embodiment, the base 100 is a growth substrate, that is, an epitaxial structure 102 can be formed on the base 100 by, for example, metal-organic chemical vapor deposition (MOCVD). In another embodiment, the base 100 is not a growth substrate but a bonding substrate, which can be bonded to the epitaxial structure 102 by an adhesive material.

[0013] As shown in Figure 1B, the epitaxial structure 102 includes a first semiconductor structure 104, a second semiconductor structure 106, and an active region 108 located between the first and second semiconductor structures 104 and 106. The first and second semiconductor structures 104 and 106 have opposing conductivity types. For example, the first semiconductor structure 104 is n-type and the second semiconductor structure 106 is p-type, or the first semiconductor structure 104 is p-type and the second semiconductor structure 106 is n-type. Thus, the first and second semiconductor structures 104 and 106 can provide electrons and holes, respectively. The first and second semiconductor structures 104, 106, and active region 108 may each contain group 3 and 5 semiconductor materials. The group 3 and 5 semiconductor materials may include Al, Ga, As, P, N, or In. In one embodiment, the first and second semiconductor structures 104, 106, and active region 108 do not need to contain N. Specifically, the above-mentioned group 3 and 5 semiconductor materials may be binary compound semiconductors (e.g., GaAs, GaP, or GaN), ternary compound semiconductors (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the active region 108 is substantially composed of a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP).

[0014] The semiconductor element 10 may include a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum well (MQW) structure. According to one embodiment, when the semiconductor element 10 is a light-emitting element and the semiconductor element 10 is operating, the active region 108 can emit a light beam. The light beam includes visible light or invisible light. The light beam emitted by the semiconductor element 10 depends on the material components of the active region 108. For example, when the material in the active region 108 includes an InGaN system, it can emit blue light, deep blue light, or green light with a peak wavelength of 400 nm to 490 nm. When the material in the active region 108 includes an AlGaN system, it can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm. When the material in the active region 108 includes an InGaAs system, an InGaAsP system, an AlGaAs system, or an AlGaInAs system, it can emit infrared light with a peak wavelength of 700 nm to 1700 nm. When the material in the active region 108 includes an InGaP system or an AlGaInP system, it can emit red light with a peak wavelength of 610 nm to 700 nm, or yellow light with a peak wavelength of 530 nm to 600 nm.

[0015] In one embodiment, the active region 108 may include a semiconductor stack layer 108c consisting of a barrier layer 108a and an adjacent well layer 108b, that is, one pair of semiconductor stack layers 108c includes one barrier layer 108a and one well layer 108b. Specifically, the active region 108 may include one pair or more pairs of semiconductor stack layers 108c. In one embodiment, the number of pairs of semiconductor stack layers 108c is two or more. In one embodiment, the number of pairs of semiconductor stack layers 108c may be 20 or less, and may also be 10 or less. The number of pairs of semiconductor stack layers 108c is, for example, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, or 19. In one embodiment, when the active region 108 includes five or fewer pairs of semiconductor stack layers 108c (i.e., five or fewer barrier layers 108a and five or fewer well layers 108b), the semiconductor device 10 has relatively high quantum efficiency, and in particular, low current density (e.g., 1 A / cm²). 2 The efficiency of the element is high when operating under the following conditions (or low current, e.g., 10mA or less). Specifically, the current density is the magnitude of the current applied to the semiconductor element 10 (unit: amperes (A)) multiplied by the upper surface area (unit: cm²) of the epitaxial structure 102. 2 It can be obtained by dividing by (which is). In one embodiment, the upper surface area of ​​the epitaxial structure 102 is 1 μm 2 ~2500μm 2 It may also be within the range of 50 μm 2 ~100μm 2 , 600 μm 2 , 1200 μm 2 , 1500μm 2 or 2000 μm 2 In a top view, when the epitaxial structure 102 has areas of multiple different sizes, the aforementioned top area refers to the largest of these areas.

[0016] The barrier layer 108a and / or the well layer 108b may contain AL (aluminum). In one embodiment, the active region 108 has n barrier layers 108a and n well layers 108b, where n is a positive integer, by including n pairs of semiconductor stack layers 108c. Each barrier layer 108a may have a primary aluminum content (percentage) (ai%, i=1, 2, ..., n), and each well layer 108b may have a secondary aluminum content (percentage) (bi%, i=1, 2, ..., n). a1% is the primary aluminum content (percentage) of the first barrier layer 108a, a2% is the primary aluminum content (percentage) of the second barrier layer 108a, and an% is the primary aluminum content (percentage) of the nth barrier layer 108a. b1% is the secondary aluminum content (percentage) of the first well layer 108b, b2% is the secondary aluminum content (percentage) of the second well layer 108b, and bn% is the secondary aluminum content (percentage) of the nth well layer 108b. In one embodiment, the primary aluminum content (percentage) of the barrier layer 108a of each layer may be the same or different. The difference in aluminum content (percentage) (Al%) between the barrier layers 108a may be between 0 and 1 atom%. In one embodiment, the secondary aluminum content (percentage) of the well layers 108b of each layer may be the same or different. The difference in aluminum content (percentage) (Al%) between the well layers 108b may be between 0 and 1 atom%.

[0017] Specifically, the first and second aluminum content (percentage) refers to the number of Al atoms (percentage) (atom%) in the barrier layer 108a and the well layer 108b, respectively, and can be obtained, for example, by measuring the barrier layer 108a and the well layer 108b, respectively, using an Energy Dispersive Spectrometer (EDX). For example, if the barrier layer 108a contains Al z1 Ga 0.5-z1 In 0.5 P (of which 0 ≤ z1 ≤ 0.5) is included, and well layer 108b is Al z2 Ga 0.5-z2 In0.5 When P (of which 0 ≤ z2 ≤ 0.5) is present, z1 and z2 can be obtained from the EDX measurement results. Here, the primary aluminum content (percentage) (ai%) of the barrier layer 108a can be defined as z1 * 100%, and the secondary aluminum content (percentage) (bi%) of the well layer 108b can be defined as z2 * 100%. That is, the aluminum content (percentage) represents the proportion of Al to the total number of atoms (percentage) of all group 3 elements. For example, when z1 = 0.3, it indicates that the primary aluminum content (percentage) is 30%. In one example, the aluminum content (percentage) of the barrier layer 108a and the well layer 108b can also be obtained by analysis using SIMS. In one example, the primary aluminum content (percentage) is greater than the secondary aluminum content (percentage). In one embodiment, the primary aluminum content (percentage) may be in the range of 15% to 50%, for example, 20%, 25%, 30%, 35%, 40%, 45%, or 50%. In one embodiment, the secondary aluminum content (percentage) may be in the range of 0% to 15%, for example, 5% or 10%. In one embodiment, when the primary aluminum content (percentage) is 25% or more, the electron confinement capability of the barrier layer 108a can be further improved, and it has a relatively good quantum efficiency (e.g., EQE or IQE). In one embodiment, when the primary aluminum content (percentage) is 35% or more, it has a better quantum efficiency.

[0018] In one embodiment, the active region 108 includes n pairs of semiconductor stack layers 108c, thereby having n barrier layers 108a and n well layers 108b, where n is a positive integer. Each barrier layer 108a may have a first thickness (t1i, i=1, 2, ..., n), and each well layer 108b may have a second thickness (t2i, i=1, 2, ..., n). The first thickness may be greater than or equal to the second thickness. t11 is the first thickness of the first barrier layer 108a, t12 is the first thickness of the second barrier layer 108a, and t1n is the first thickness of the nth barrier layer 108a. t21 is the second thickness of the first well layer 108b, t22 is the second thickness of the second well layer 108b, and t2n is the second thickness of the nth well layer 108b. In one embodiment, the first thickness of each barrier layer 108a may be the same or different, and the difference in thickness between the barrier layers 108a may be between 0 and 1 nm. In one embodiment, the second thickness of each well layer 108b may be the same or different, and the difference in thickness between the well layers 108b may be between 0 and 1 nm. The first and second thicknesses may each be 200 Å or less, for example, about 150 Å, 100 Å, 50 Å, or 10 Å, respectively. In one embodiment, the quantum efficiency of the semiconductor device 10 is good when the thicknesses of the barrier layer 108a and the well layer 108b are all 200 Å or less. In one embodiment, the ratio of the first thickness (t1i) to the second thickness (t2i) is in the range of 2:1 to 40:1. For example, the ratio of the first thickness to the second thickness (t1i / t2i) may be in the range of 10:1 to 35:1. Having a relatively large first thickness can improve the electron confinement capability of the barrier layer 108a. In one embodiment, the first thickness may be in the range of 20 Å to 4000 Å, for example, 100 Å or more and 2000 Å or less. The second thickness may be in the range of 10 Å to 200 Å, for example, 150 Å, 100 Å, or 50 Å.

[0019] As shown in Figure 1B, the first semiconductor structure 104 includes a first confinement layer 114, and the second semiconductor structure 106 includes a second confinement layer 116. In this embodiment, the first confinement layer 114 and the second confinement layer 116 are adjacent to the active region 108 and are in direct contact with the active region 108. The first confinement layer 114 and the second confinement layer 116 may each contain a group 3 or 5 semiconductor material, such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first confinement layer 114 and the second confinement layer 116 have the same material as the barrier layer 108a. The first confinement layer 114 and / or the second confinement layer 116 may contain aluminum. The first confinement layer 114 may have a tertiary aluminum content (percentage), and the second confinement layer 116 may have a quaternary aluminum content (percentage). As described above, the aluminum content (percentage) here represents the proportion of Al to the total number of atoms (percentage) of all group 3 elements. In one embodiment, both the tertiary aluminum content (percentage) and the quaternary aluminum content (percentage) are greater than the divite aluminum content (percentage). In one embodiment, both the tertiary aluminum content (percentage) and the quaternary aluminum content (percentage) are greater than or equal to the primate aluminum content (percentage). In one embodiment, the first confinement layer 114 may have a third thickness (t3), and the second confinement layer 116 may have a fourth thickness (t4). The third and fourth thicknesses may be the same or different. In one embodiment, the third thickness is greater than or equal to the second thickness, and the fourth thickness is greater than or equal to the second thickness. This improves the electron confinement capability of the first confinement layer 114 and the second confinement layer 116. In one embodiment, the ratio of the third thickness to the first or second thickness (t3 / t1i or t3 / t2i) is in the range of 1.5:1 to 10:1, for example, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, or 9:1.In one embodiment, the ratio of the fourth thickness to the first or second thickness (t4 / t1i or t4 / t2i) is in the range of 1.5:1 to 10:1, for example, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, or 9:1. In one embodiment, when t3 / t1i, t3 / t2i, t4 / t1i, or t4 / t2i is within the above range, the electron confinement capability of the first confinement layer 114 / second confinement layer 116 can be further improved.

[0020] In one embodiment, the active region 108 contains a first dopant. The first dopant has a doping concentration in the active region 108. The first dopant may be an n-type or p-type dopant with respect to the active region 108. In one embodiment, the first dopant may contain elements from Group II, Group IV, or Group VI of the periodic table. In one embodiment, the first dopant contains C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the doping concentration of the first dopant in the active region 108 is 1 x 10⁻¹⁰ 16 / cm 3 That concludes the explanation. In one embodiment, the doping concentration in the active region 108 of the first dopant was 1 x 10⁻¹⁰. 18 / cm 3 It is smaller than that. Specifically, the doping concentration at the active region 108 of the first dopant is 5 x 10⁻⁶. 15 / cm 3 ~1x10 16 / cm 3 , 5x10 16 / cm 3 , 8x10 16 / cm 3 , 1x10 17 / cm 3 or 5x10 17 / cm 3It may also be within the range. The first dopant may be distributed in the first semiconductor structure 104 and / or the second semiconductor structure 106. In one embodiment, the doping concentration of the first dopant in the first semiconductor structure 104 is higher than the doping concentration in the active region 108 of the first dopant. In one embodiment, the first dopant is distributed at least in the first confinement layer 114 and the active region 108. In one embodiment, the first dopant is continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108, and 1x10 16 / cm 3 or higher doping concentration. "Continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108" means that when analyzing the first confinement layer 114 and the active region 108 by SIMS, signals of the first dopant can be obtained at each depth position in the first confinement layer 114 and the active region 108. Specifically, in one embodiment, when analyzing the first dopant using SIMS, the first dopant exists at least between the surface of the first confinement layer 114 away from the active region 108 side to the interface between the active region 108 and the second confinement layer 116, and exists in each barrier layer 108a and each well layer 108b of the active region 108.

[0021] In one embodiment, in the semiconductor stack layer 108c of the active region 108 closest to the first confinement layer 114, the doping concentration of the first dopant is 1x10 16 / cm 3 or higher and 1x10 18 / cm 3 or lower. In one embodiment, in the semiconductor stack layer 108c of the active region 108 closest to the second confinement layer 116, the doping concentration of the first dopant is 1x10 16 / cm 3 or higher and 1x10 17 / cm 3The following may also apply: In one embodiment, the doping concentration of the first dopant in the semiconductor stack layer 108c of the active region 108 closest to the first confinement layer 114 is equal to or greater than the doping concentration of the first dopant in the semiconductor stack layer 108c of the active region 108 closest to the second confinement layer 116. In one embodiment, the first dopant is distributed in at least the first confinement layer 114, the second confinement layer 116, and the active region 108. In one embodiment, the doping concentration of the first dopant in the first confinement layer 114 is equal to or greater than the doping concentration of the first dopant in the active region 108. In one embodiment, the doping concentration of the first dopant in the active region 108 is equal to or greater than the doping concentration of the first dopant in the second confinement layer 116. In one embodiment, the doping concentration of the first dopant gradually decreases from the first confinement layer 114 to the second confinement layer 116. Specifically, in one embodiment, the first dopant in the first confinement layer 114 may have a minimum doping concentration c1, the first dopant in the second confinement layer 116 may have a minimum doping concentration c2, and the first dopant in the active region 108 may have a minimum doping concentration c3, where c1 ≥ c3 ≥ c2. The minimum doping concentrations c1, c2, and c3 may be the minimum values ​​of the first dopant doping concentration in the first confinement layer 114, the second confinement layer 116, and the active region 108, respectively. When analyzing the first dopant using SIMS, the above minimum values ​​may correspond to the lowest dips in the first dopant concentration curve in the SIMS analysis results in the first confinement layer 114, the second confinement layer 116, and the active region 108 (or, in the case of no clear dips, the minimum detectable concentration).

[0022] The first semiconductor structure 104 may further include a first coating layer 118 located below the first confinement layer 114. The first coating layer 118 may include a group 3 or 5 semiconductor material, such as a ternary semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first coating layer 118 also contains the first dopant. In one embodiment, the doping concentration of the first dopant in the first coating layer 118 is equal to or greater than the doping concentration of the first dopant in the first confinement layer 114.

[0023] In one embodiment, the first semiconductor structure 104 may further optionally include a first window layer (not shown) located below the first coating layer 118. The first window layer may include a group 3 or 5 semiconductor material, such as a ternary semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). The material of the first window layer may be different from the material of the first coating layer 118. In one embodiment, the thickness of the first window layer is greater than the thickness of the first coating layer 118. In one embodiment, the first window layer also contains a first dopant. In one embodiment, the doping concentration of the first dopant in the first window layer is equal to or greater than the doping concentration of the first dopant in the first coating layer 118 or the first confinement layer 114. In one embodiment, the doping concentration of the first dopant in the first coating layer 118 and / or the first window layer is 1 x 10⁻¹⁰ 19 / cm 3 The following, for example, 5x10 17 / cm 3 ~1x10 18 / cm 3 , 2x10 18 / cm 3 or 3x10 18 / cm 3 It is within the range.

[0024] In one embodiment, the second semiconductor structure 106 further includes a second coating layer 119 located above the second confinement layer 116. The second coating layer 119 may include a group 3, 5 semiconductor material, such as a ternary semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the second coating layer 119 includes a second dopant different from the first dopant. In one embodiment, the second dopant may include a group II, group IV, or group VI element in the periodic table. In one embodiment, the second dopant includes C, Zn, Si, Ge, Sn, Se, Mg, or Te. The second dopant may also be distributed in the active region 108 and / or the second confinement layer 116. In one embodiment, the first dopant and the second dopant may be present simultaneously in the second containment layer 116 and / or the second coating layer 119. In one embodiment, the second dopant in the second containment layer 116 and / or the second coating layer 119 is 1 x 10 16 / cm 3 The above doping concentrations are acceptable.

[0025] In one embodiment, the first semiconductor structure 104 may contain a third dopant different from the first and second dopants. In one embodiment, the third dopant is distributed in the first coating layer 118 and / or the first window layer. In one embodiment, the first dopant is distributed in the first coating layer 118, the first confinement layer 114 and the active region 108, and the third dopant is mainly distributed in the first window layer. In one embodiment, the first and third dopants are not simultaneously present in the first confinement layer 114, the active region 108, the first coating layer 118 or the first window layer, for example, in the first confinement layer 114, the active region 108, the first coating layer 118 or the first window layer, the minimum doping concentration of one of the first and third dopants is 1 x 10⁻¹⁶. 16 / cm 3It is lower than. In one embodiment, the third dopant may contain an element from Group II, Group IV, or Group VI of the periodic table. In one embodiment, the third dopant contains C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the atomic radius of the third dopant is smaller than the atomic radius of the first or second dopant. In one embodiment, with respect to the first semiconductor structure 104, the first and third dopants are dopants of the same conductivity type, and the second dopant is a dopant of the opposite conductivity type. For example, with respect to the first semiconductor structure 104, the first and third dopants are p-type dopants and the second dopant is an n-type dopant, or the first and third dopants are n-type dopants and the second dopant is a p-type dopant. In one embodiment, the first dopant is continuously and seamlessly distributed in the first coating layer 118 to the second confinement layer 116. For example, when analyzing the first coating layer 118 to the second confinement layer 116 with SIMS, the signal of the first dopant can be obtained at every depth position in the first coating layer 118 to the second confinement layer 116. In one embodiment, the second dopant is continuously and seamlessly distributed in the second coating layer 119. For example, when analyzing the second coating layer 119 with SIMS, the signal of the second dopant can be obtained at every depth position in the second coating layer 119. In one embodiment, the third dopant is continuously and seamlessly distributed in the first window layer. For example, when analyzing the first window layer with SIMS, the signal of the third dopant can be obtained at every depth position in the first window layer. In one embodiment, the doping concentration of the second dopant in the second confinement layer 116 may be slightly lower than the doping concentration of the second dopant in the second coating layer 119. In one embodiment, the doping concentration of the third dopant in the first window layer may be greater than the doping concentration of the third dopant in the first coating layer 118. In one embodiment, the first dopant and the third dopant can be present simultaneously at the interface between the first window layer and the first coating layer 118.

[0026] The first electrode 110 and the second electrode 112 are used to electrically connect to an external power source. The materials of the first electrode 110 and the second electrode 112 may be the same or different, and may include, for example, a metal oxide material, a metal, or an alloy, respectively. Metal oxide materials include ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, IZO, etc. Metals may include, for example, Ge, Be, Zn, Au, Pt, Ti, Al, Ni, Cu, etc. Alloys may include at least two selected from the group consisting of these metals, for example, GeAuNi, BeAu, GeAu, ZnAu, etc. As shown in Figure 1A, the first electrode 110 may include an electrode pad 110a and a stretched electrode 110b connected to the electrode pad 110a. In this embodiment, the stretched electrode 110b includes a first stretched portion 110b1 and a second stretched portion 110b2. The first extended portion 110b1 may be in direct contact with the electrode pad 110a, and the second extended portion 110b2 may be in direct contact with the first extended portion 110b1 and may be extended in a direction perpendicular to the first extended portion 110b1. In one embodiment, the semiconductor element 10 may have only the electrode pad 110a, but is not limited thereto.

[0027] Figure 1D shows a cross-sectional structure of a semiconductor element 20 in one embodiment of the present invention. The main difference between the semiconductor element 20 of this embodiment and the semiconductor element 10 is that the semiconductor element 20 further includes an insulating layer 120, a conductive layer 122, a reflective layer 124, and a junction structure 128. The insulating layer 120, conductive layer 122, reflective layer 124, and junction structure 128 are located between the epitaxial structure 102 and the base 100. In this embodiment, the insulating layer 120 is in contact with the second semiconductor structure 106, the first electrode 110 is located on the first semiconductor structure 104, and is in contact with and electrically connected to the first semiconductor structure 104. The conductive layer 122 covers the insulating layer 120, the reflective layer 124 covers the conductive layer 122, and the junction structure 128 is located between the base 100 and the reflective layer 124.

[0028] The insulating layer 120 may be a patterned dielectric material layer, for example, an insulating material with a refractive index less than 2, such as SiN. x AlOx SiO x MgF x Or a combination thereof may be included. In one embodiment, x = 1.5 or 2. As shown in Figure 1D, the insulating layer 120 has a plurality of pores 126, and the conductive layer 122 can cover the insulating layer 120 and fill the pores 126, so that the conductive layer 122 and the epitaxial structure 102 can form contact regions at the pores 126. This allows the conductive layer 122 to be electrically connected to the epitaxial structure 102. The conductive layer 122 may contain a metal or a metal oxide. The metal may include Ag, Ge, Au, Ni or a combination thereof. The metal oxide may include ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, IZO or a combination of these materials.

[0029] The reflective layer 124 can reflect the light beam emitted from the active region 108 and direct it outwards toward the first electrode 110. The reflective layer 124 may contain a semiconductor material, a metal, or an alloy. The semiconductor material may include group 3, 5 semiconductor materials, such as binary, ternary, or quaternary group 3, 5 semiconductor materials. The metal may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, W, etc. The alloy may contain at least two selected from the group consisting of these metals. In one embodiment, the reflective layer 124 may include a distributed Bragg reflector structure (DBR). The Bragg reflector structure may be formed by alternately stacking (stacking) two or more semiconductor materials with different refractive indices, for example, AlAs / GaAs, AlGaAs / GaAs, or InGaP / GaAs.

[0030] The bonding structure 128 is connected to the base 100 and the reflective layer 124. In one embodiment, the bonding structure 128 may be a single layer or multiple layers (not shown). The material of the bonding structure 128 may include a transparent conductive material, a metal, or an alloy. The transparent conductive material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, GaP, ICO, IWO, ITiO, IZO, IGO, GAZO, graphene, or a combination of these materials. The metal may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, W, etc. The alloy may include at least two selected from the group consisting of these metals.

[0031] In Figure 1D, the first semiconductor structure 104 is located above the active region 108, and the second semiconductor structure 106 is located below the active region 108. However, in another embodiment, the following configuration may also exist: the first semiconductor structure 104 is located below the active region 108 and is in contact with the insulating layer 120 and the conductive layer 122, while the second semiconductor structure 106 is located above the active region 108 and is in contact with the first electrode 110. Note that the positions, relative relationships, material components, and structural modifications of the other layers or structures in this embodiment have all been described in detail in the previous embodiment, so a detailed explanation is omitted here.

[0032] Figure 1E is a top view of a semiconductor element 40 in one embodiment of the present invention. Figure 1F is a diagram showing the cross-sectional structure of the semiconductor element 40 in Figure 1E along the Y-Y' line. The main difference between the semiconductor element 40 in this embodiment and the semiconductor element 10 is that in the semiconductor element 40, the first electrode 110 and the second electrode 112 are located on the same side of the base 100, while in the semiconductor element 10, the first electrode 110 and the second electrode 112 are located on opposite sides of the base 100. In this embodiment, the epitaxial structure 102 is located on the base 100, and the first electrode 110 and the second electrode 112 are located on the epitaxial structure 102. The first electrode 110 can contact the second semiconductor structure 106, and the second electrode 112 can contact the first semiconductor structure 104. In this embodiment, the first semiconductor structure 104 and the active region 108 have a width smaller than the width of the second semiconductor structure 106. In Figure 1F, the first semiconductor structure 104 is located above the active region 108, and the second semiconductor structure 106 is located below the active region 108. However, in another embodiment, the first semiconductor structure 104 may be located below the active region 108 and in contact with the base 100, while the second semiconductor structure 106 may be located above the active region 108 and in contact with the second electrode 112. Similarly, the insulating layer 120, conductive layer 122, reflective layer 124, or junction structure 128 described in the previous embodiment may be located between the second semiconductor structure 106 and the base 100. The junction structure 128 may contain conductive or nonconductive materials. Note that the positions, relative relationships, material components, and structural modifications of each other layer or structure in this embodiment have all been described in detail in the previous embodiment, so a detailed explanation is omitted here.

[0033] Figure 2A shows the relationship between the current density and internal quantum efficiency (IQE) of a semiconductor device in an embodiment of the present invention. Specifically, Figure 2A shows the IQE curves obtained by performing simulations on the semiconductor device using the simulation software APSYS (Crosslight Software Inc.). The semiconductor device corresponding to curve C1 has an undoped structure in the active region 108, and the semiconductor device corresponding to curve C2 has approximately 1 x 10⁻¹⁶ IQE in the active region 108. 16 / cm 3 The structure includes a primary dopant with a doping concentration of [value missing]. As shown in Figure 2A, both have a current density of approximately 30 A / cm². 2 It has the maximum IQE value at this point. Also, 1 A / cm 2 Within the following low current density range, semiconductor devices having the first dopant in the active region 108 have a relatively higher IQE value compared to semiconductor devices that are not doped in the active region 108. Therefore, the presence of the first dopant in the active region can help improve the IQE value, especially in low current density environments (e.g., 1 A / cm²). 2 The IQE score can be significantly improved (see below).

[0034] Figure 2B shows the relationship between the current density and external quantum efficiency (EQE) of a semiconductor device in an embodiment of the invention. The semiconductor device corresponding to curve F1 has an undoped structure in the active region 108, and the semiconductor device corresponding to curve F2 includes a structure having a first dopant in the active region 108. As shown in Figure 2B, 1 A / cm 2 Within the following low current density range (e.g., 0.001 to 1 A / cm²) 2 In this case, a semiconductor device having the first dopant in the active region 108 has a relatively high external quantum efficiency.

[0035] Figure 2C shows the relationship between the R value and relative EQE ratio of semiconductor devices in embodiments of the present invention. The semiconductor device corresponding to curve G1 has a structure that is not doped in the active region 108, and the semiconductor device corresponding to curve G2 includes a structure that has a first dopant in the active region 108. The semiconductor devices corresponding to curves G1 and G2 have a ratio of 0.001 A / cm². 2 ~100A / cm 2 When measured within the current density range, within this current density range, the semiconductor device exhibits a maximum external quantum efficiency E max It can have %, and the current density corresponding to this maximum external quantum efficiency is J_E max A / cm 2 This is defined as follows. In Figure 2C, a value of R = 1 means that the current density is 1 * (J_ Emax ) A / cm2 This corresponds to the result, and Figure 2C is 0.001*(J_E max ) A / cm 2 ~1*(J_E max ) A / cm 2 This shows the relative EQE ratio within the current density range. In other words, this relative EQE ratio is E max Set the percentage to 100%, and the EQE value obtained under different current densities is E max This is obtained by calculating the percentage within the %. As shown in Figure 2C, the semiconductor device having the first dopant in the active region 108 is J_E max All have relatively good EQE within a current density range lower than 0.001*(J_E max ) A / cm 2 Under this current density, a semiconductor device having the first dopant in the active region 108 is far superior to a semiconductor device that is not doped in the active region 108.

[0036] Figure 2D shows the relationship between the current density and external quantum efficiency (EQE) of a semiconductor device in an embodiment of the present invention. The difference between the semiconductor devices in curves Q1 to Q3 lies in the aluminum content (percentage) in the barrier layer. In the semiconductor device corresponding to curve Q1, the aluminum content (percentage) of each barrier layer 108a is approximately 17.5%, in the semiconductor device corresponding to curve Q2, the aluminum content (percentage) of each barrier layer 108a is approximately 35%, and in the semiconductor device corresponding to curve Q3, the aluminum content (percentage) of each barrier layer 108a is approximately 50%. As can be seen from Figure 2D, the current density is 1 A / cm². 2 When the following conditions are met, increasing the aluminum content (percentage) of the barrier layer 108a can help improve the EQE of the semiconductor device.

[0037] Figure 3 shows the relationship between element concentration and depth within a certain region of a semiconductor device in one embodiment of the present invention. Specifically, Figure 3 shows the results of analyzing a part of the structure of a semiconductor device 10 containing a first dopant and a second dopant using SIMS. As shown in Figure 3, the semiconductor device 10 of this embodiment includes, in order, a second coating layer 119, a second confinement layer 116, an active region 108, a first confinement layer 114, a first coating layer 118, and a first window layer 130. In this embodiment, the second coating layer 119 contains AlInP, the second confinement layer 116 contains AlGaInP, the active region 108 contains 16 pairs of semiconductor stack layers 108c (16 barrier layers 108a and 16 well layers 108b), and both the barrier layers 108a and well layers 108b all contain AlGaInP, the first confinement layer 114 contains AlGaInP, the first coating layer 118 contains AlInP, and the first window layer 130 contains AlGaInP. In Figure 3, curve D1 represents the dopant concentration of the first dopant, and curve D2 represents the dopant concentration of the second dopant. In this embodiment, the first dopant is distributed at least within the range from the first window layer 130 to the second containment layer 116, while the second dopant is mainly distributed in the second coating layer 119 and the second containment layer 116. As shown in Figure 3, the doping concentration of the second dopant in the second containment layer 116 is clearly lower than the doping concentration of the second dopant in the second coating layer 119.

[0038] Figure 4 shows the relationship between the current density and internal quantum efficiency (IQE) of a semiconductor device in an embodiment of the present invention. Specifically, Figure 4 shows the IQE curves obtained by performing simulations on the semiconductor device using the simulation software APSYS (Crosslight Software Inc.). The difference between each semiconductor device lies in the first dopant having different doping concentrations in the active region 108. More specifically, the semiconductor device corresponding to curve E0 has a structure that is not doped in the active region 108, while curves E1 to E5 each have a first dopant doping concentration of approximately 1 x 10⁻¹⁶ in the active region 108. 16 / cm 3 , 5x1016 / cm 3 , 1x10 17 / cm 3 , 5x10 17 / cm 3 , 1x10 18 / cm 3 This corresponds to the structure shown in Figure 4. In this embodiment, 1 A / cm 2 Under the following low current densities, the doping concentration of the first dopant is approximately 1 x 10⁻¹⁰ 16 / cm 3 ~1x10 17 / cm 3 The IQE of all structures within the range (curves E1 to E3) is significantly better than that of the undoped structure (curve E0) in the active region 108. In this example, the doping concentration of the first dopant is 1 x 10⁻¹⁰. 17 / cm 3 When it increases to 1 A / cm 2 The maximum IQE value is obtained in the following case: when the doping concentration of the first dopant is 5 x 10⁻¹⁰ 17 / cm 3 or 1x10 18 / cm 3 As the current density increases (curves E4-E5), within some current density ranges, the IQE is still better than that of the undoped structure in the active region 108 (curve E0). As can be seen from Figure 4, in this embodiment, the presence of a first dopant within a specific doping concentration range in the active region 108 allows for maintaining maximum quantum efficiency while keeping the current density low (e.g., 1 A / cm²). 2 The quantum efficiency can be improved in the following environments.

[0039] Figure 5A shows a cross-sectional structure of a semiconductor assembly 200 in one embodiment of the present invention. As shown in Figure 5A, the semiconductor assembly 200 includes a mounting substrate 22, an adhesive layer 24 located on the mounting substrate 22, and a plurality of semiconductor elements 10' located on the adhesive layer 24. In this embodiment, the semiconductor elements 10' do not include a base, and each semiconductor element 10' includes the epitaxial structure 102 described in each embodiment, and a first electrode 110 and a second electrode 112 located on both sides of the epitaxial structure 102, respectively. The mounting substrate 22 is in contact with the semiconductor elements 10' by the adhesive layer 24. The mounting substrate 22 may include conductive or insulating materials, such as sapphire, glass, GaAs, InP, SiC, GaP, ZnO, GaN, AlN, Ge, Si, etc. The adhesive layer 24 may contain polymer materials such as benzocyclobutene (BCB), epoxy resin, polyimide, silicone resin, or SOG (Spin On Glass). Note that the positions, relative relationships, material components, and structural variations of the other layers or structures in this embodiment have been described in detail in previous embodiments, so a detailed explanation is omitted here.

[0040] Figure 5B shows a cross-sectional structure of a semiconductor assembly 400 in one embodiment of the present invention. As shown in Figure 5B, the semiconductor assembly 400 includes a mounting substrate 42, an adhesive layer 44 located on the mounting substrate 42, and a plurality of semiconductor elements 40' located on the adhesive layer 44. In this embodiment, the semiconductor elements 40' do not include a base, and the semiconductor elements 40' may include an epitaxial structure 102 as described in the previous embodiment, and a first electrode 110 and a second electrode 112 located on one side of the epitaxial structure 102. The semiconductor elements 40' further include a first contact structure 140a located between the first electrode 110 and the epitaxial structure 102, and a second contact structure 140b located between the second electrode 112 and the epitaxial structure 102. The first contact structure 140a and the second contact structure 140b may each include a group 3, 5 semiconductor material, a metal, or an alloy. The semiconductor element 40' further includes a dielectric material layer 160 that covers the epitaxial structure 102 and has openings. As shown in Figure 5B, the first electrode 110 and the second electrode 112 can be electrically connected to the first contact structure 140a and the second contact structure 140b, respectively, by filling the openings in the dielectric material layer 160. For the mounting substrate 42 and the adhesive layer 44, please refer to the descriptions of the mounting substrate 22 and the adhesive layer 24, respectively. Furthermore, the positions, relative relationships, material components, and other details of each layer or structure in this embodiment, as well as variations in the structure, have been described in detail in previous embodiments, so a detailed explanation is omitted here.

[0041] Figure 6 shows a cross-sectional structure of a semiconductor assembly 600 in one embodiment of the present invention. Referring to Figure 6, the semiconductor assembly 600 includes a semiconductor element 60, a package substrate 61, a carrier 63, a junction line 65, a contact structure 66, and a package layer 68. The package substrate 61 may include a ceramic or glass material. The package substrate 61 has a plurality of through holes 62. Filling the through holes 62 with a conductive material, such as a metal, can help with conductivity and / or heat dissipation. The carrier 63 is located on one side surface of the package substrate 61 and may include a conductive material, such as a metal. The contact structure 66 is located on the other side surface of the package substrate 61. In this embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b can be electrically connected to the carrier 63 by the through holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), which is located, for example, between the first contact pad 66a and the second contact pad 66b.

[0042] The semiconductor element 60 is located on the carrier 63. The semiconductor element 60 may be any of the semiconductor elements described in any embodiment of the present invention (e.g., semiconductor elements 10, 10', 20, 40, 40'). In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 by a junction line 65. The material of the junction line 65 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of these elements. The package layer 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the package layer 68 may include a resin material, such as epoxy resin or silicone resin. The package layer 68 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted from the semiconductor element 60 into a second light. The wavelength of the second light is longer than the wavelength of the first light.

[0043] Figure 7 is a top view of a semiconductor assembly 800 in one embodiment of the present invention. The semiconductor assembly 800 in this embodiment is, for example, a display unit. As shown in Figure 7, the semiconductor assembly 800 includes a carrier 80 and a plurality of pixel units 82 located on the carrier 80. The plurality of pixel units 82 are arranged in an array in directions parallel to the x and y axes and are arranged with a spacing d in the direction parallel to the x axis. The number of pixel units 82 may be adjusted according to the needs. For example, in one embodiment, the plurality of pixel units 82 included in the semiconductor assembly 800 can provide a resolution of 1920 x 1080 pixels. In one embodiment, the spacing d is less than 1.4 mm, for example, the spacing d is between 0.2 mm and 1.3 mm, specifically, for example, 0.75 mm, 0.8 mm, 1 mm, and 1.25 mm. As shown in Figure 7, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86, and a third semiconductor element 88 arranged in the direction parallel to the y axis. One or more of the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 may be semiconductor elements described in any embodiment of the present invention (for example, semiconductor elements 10, 10', 20, 40, 40'). In one embodiment, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 are all light-emitting elements and are capable of emitting red light, green light, and blue light, respectively. In one embodiment, the arrangement order of these light-emitting elements may also be adjusted according to the needs; for example, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 may emit red light, blue light, and green light, respectively. Each pixel unit 82 is electrically connected to a circuit (not shown) on the surface of the carrier 80 so that the light-emitting elements within it receive an external signal and emit light based on the external signal. The carrier 80 may have a single-layer or multi-layer structure. The material of carrier 80 may include polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenol resins (PF), or glass fiber epoxy resin (FR4).In one embodiment, the carrier 80 can be bent and, for example, can withstand a radius of curvature smaller than 50 mm, such as 25 mm or 32 mm.

[0044] As can be seen from the above, the length L0 and width W0 of the semiconductor device are within the aforementioned range (500 μm or less), and the operating current of the semiconductor device is between 0.001 mA and 100 mA and / or the current density is 0.001 A / cm². 2 and 100A / cm 2 When in between, the number of pairs of semiconductor stack layers 108c in the active region 108, and / or the first aluminum content (percentage), and / or the thickness of the barrier layer 108a and the well layer 108b, and / or the thickness of the first or second confinement layer, and / or the aluminum content of the first or second confinement layer, and / or the concentration of the first dopant in the active region 108, can all affect the quantum efficiency of the semiconductor device.

[0045] Specifically, in one embodiment, the operating current is between 0.01 mA and 5 mA and / or the current density is 0.01 A / cm². 2 and 5A / cm 2 When the following conditions are met, an epitaxial structure or semiconductor device that satisfies any one or any combination of the following conditions (i) to (vi) has relatively high quantum efficiency, namely, (i) the primary aluminum content (percentage) is 25% or more; (ii) the ratio of the primary thickness to the secondary thickness is in the range of 2:1 to 40:1; (iii) the number of pairs of semiconductor stack layers 108c in the active region 108 is 10 pairs or less; (iv) the tertiary / quaternary aluminum content (percentage) is greater than the secondary aluminum content (percentage); (v) the third thickness is greater than or equal to the second thickness, and the fourth thickness is greater than or equal to the second thickness; and (vi) the primary dopant is included in the active region 108. Furthermore, the length L0 of the semiconductor device 10 is less than 200 μm, the width W0 is less than 200 μm, and / or the top surface area of ​​the epitaxial structure 102 is 50 μm 2 ~2000μm 2When within the range, an epitaxial structure or semiconductor device that satisfies any one or any combination of the above conditions (i) to (vi) is more significantly improved in terms of quantum efficiency.

[0046] According to one embodiment, under different current densities (for example, 0.001 to 100 A / cm²), 2 It falls within the range of, for example, 0.001~0.01, 0.1, 1, 5, 10, or 50 A / cm². 2 When measuring the external quantum efficiency (e.g., in units of %) of an epitaxial structure or semiconductor device, an epitaxial structure or semiconductor device that satisfies any one or any combination of the above conditions (i) to (vi) has the maximum external quantum efficiency E within the above current density range. 1max It has a % and the maximum external quantum efficiency E 1max The current density corresponding to % is J_E 1max A / cm 2 It is defined as follows. The external quantum efficiency can be obtained, for example, by measuring it using an integrating sphere system. 0.1*(J_E 1max ) A / cm 2 Under the current density, the aforementioned epitaxial structure or semiconductor device is E 1max It has an external quantum efficiency of 80% or more, and preferably E 1max It can have an external quantum efficiency of 85% or 90% or more. 0.01*(J_E 1max ) A / cm 2 Under the current density, the aforementioned epitaxial structure or semiconductor device is E 1max It has an external quantum efficiency of 50% or more, and preferably, E 1max It can have an external quantum efficiency of 60% or 70% or more. 0.001*(J_E 1max ) A / cm 2 Under the current density, the aforementioned epitaxial structure or semiconductor device is E 1max It has an external quantum efficiency of 15% or more, and preferably, E 1max It can have an external quantum efficiency of 20%, 25%, 30%, or 40% or more.

[0047] According to one embodiment, when measuring the external quantum efficiency (e.g., in units of %) of an epitaxial structure or semiconductor device under different current intensities (e.g., within the range of 0.001 to 100 mA, e.g., 0.001 to 0.01, 0.1, 1, 5, 10, 20, 30, 40, or 50 mA), an epitaxial structure or semiconductor device that satisfies any one or any combination of the above conditions (i) to (vi) has the maximum external quantum efficiency E within the above current range. 2max It has a % and the maximum external quantum efficiency E 2max The current density corresponding to % is C_E 2max It is defined as mA. External quantum efficiency can be obtained, for example, by measuring it using an integrating sphere system. 2max The percentage is 80% or more, and preferably E 2max The percentage can be 85% or 90% or higher. 0.01*(C_E 2max Under a current of )mA, the aforementioned epitaxial structure or semiconductor device is E 2max It has an external quantum efficiency of 50% or more, and preferably, E 2max It may have an external quantum efficiency of 60% or 70% or more. 0.001*(C_E 2max Under a current of )mA, the aforementioned epitaxial structure or semiconductor device is E 2max It has an external quantum efficiency of 15% or more, and preferably, E 2max It can have an external quantum efficiency of 20%, 25%, 30%, or 40% or more.

[0048] According to one embodiment, an epitaxial structure or semiconductor device that satisfies any one or any combination of two or more of the above conditions (i) to (vi) has a first optical output value O1 (e.g., in units of lumens (lm)) at a first temperature and a second optical output value O2 at a second temperature, wherein the second temperature is lower than the first temperature. The first and second temperatures are, for example, different ambient temperatures for testing or operating the epitaxial structure and / or semiconductor device. The ratio of the first optical output value O1 to the second optical output value O2 may be 30% or more, for example, 40%, 50%, 60%, 70%, 80%, or 90%. The ratio of the first optical output value O1 to the second optical output value O2 may be 100% or less. The difference between the first and second temperatures may be 30°C or more, for example, about 40°C, 50°C, 60°C, 70°C, or 80°C. In one embodiment, the second temperature is room temperature (e.g., about 25°C), and the first temperature is about 85°C. That is, the optical output value of an epitaxial structure or semiconductor device that satisfies any one or any combination of two or more of the above conditions (i) to (vi) can have a relatively small effect of temperature changes and a relatively low temperature dependence.

[0049] From the above, according to embodiments of the present invention, it is possible to provide epitaxial structures, semiconductor elements, or semiconductor assemblies, and to further improve characteristics such as internal or external quantum efficiency, in particular, low current (e.g., 10 mA or less) or low current density (e.g., 1 A / cm²). 2The present invention can be applied when the operation and / or miniaturization of the following are required. More specifically, the epitaxial structure, semiconductor element, or semiconductor assembly of the present invention can be improved in terms of surface recombination velocity (SRV), temperature dependence, current spread, and operational efficiency degradation (droop). Specifically, the epitaxial structure, semiconductor element, and semiconductor assembly of the present invention can be applied to products in fields such as lighting, medical, display, communication, sensing, and power supply systems, such as lighting fixtures, monitors, mobile phones, tablet computers, in-vehicle instrument panels, televisions, computers, wearable devices (e.g., watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical equipment.

[0050] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and any modification to the present invention, as long as it does not deviate from the spirit of the invention, falls within the technical scope of the present invention. [Explanation of Symbols]

[0051] 10, 10', 20, 40, 40': Semiconductor elements 22, 42: Mounting board 24, 44: Adhesive layer 200, 400, 600, 800: Semiconductor Assembly 61: Package substrate 62: Through hole 63: Career 63a:First part 63b:Second part 65:Join line 66: Contact structure 66a: First contact pad 66b: Second contact pad 68: Packaging layer 80: Career 82: Pixel Unit 84: First Semiconductor Devices 86: Second Semiconductor Device 88: Third Semiconductor Element 100: Bass 102: Epitaxial structure 104: First Semiconductor Structure 106: Second Semiconductor Structure 108: Active area 108a: Barrier layer 108b: Well layer 108c: Semiconductor stack layer 110:First electrode 110a: Electrode pads 110b: Stretched electrode 110b1: First extension part 110b2:Second extension part 112:Second electrode 114: First confinement layer 116: Second confinement layer 118:First coating layer 119:Second coating layer 130: First window layer 140a: First contact structure 140b:Second contact structure 160: Dielectric material layer 120: Insulating layer 122: Conductive layer 124: Reflective layer 126: Pore 128:Joint structure R:Region L0: Length W0: Width C1, C2, D1, D2, E0, E1, E2, E3, E4, E5, F1, F2, G1, G2, Q1, Q2, Q3: Curve X-X', Y-Y': line

Claims

1. A semiconductor device, It includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first confinement layer and a first coating layer, and the first confinement layer and the first coating layer include a first dopant. The second semiconductor structure includes a second confinement layer and a second dopant different from the first dopant. The active region is located between the first semiconductor structure and the second semiconductor structure and includes a plurality of pairs of semiconductor stack layers, each of which includes a barrier layer and a well layer. A semiconductor device wherein the active region does not contain N, the first confinement layer and the second confinement layer are in direct contact with the active region, the first coating layer further contains a third dopant different from the first dopant and the second dopant, and the first confinement layer does not contain the third dopant.

2. A semiconductor device according to claim 1, A semiconductor device in which the atomic radius of the third dopant is smaller than the atomic radius of the first dopant or the second dopant.

3. A semiconductor device according to claim 1, A semiconductor device in which the first dopant and the third dopant are dopants of the same conductivity type.

4. A semiconductor device according to claim 1, The third dopant is a semiconductor device comprising C, Zn, Si, Ge, Sn, Se, Mg, or Te.

5. A semiconductor device according to claim 1, A semiconductor device wherein the active region includes the first dopant, and the doping concentration of the first dopant in the first confinement layer is equal to or greater than the doping concentration in the active region.

6. A semiconductor device according to claim 5, The doping concentration of the third dopant in the active region is 1 × 10⁻⁶ １６ / cm ３ A semiconductor element with a lower level of performance.

7. A semiconductor device according to claim 5, A semiconductor device wherein the second confinement layer contains the first dopant, and the doping concentration of the first dopant in the active region is equal to or greater than the doping concentration in the second confinement layer.

8. A semiconductor device according to claim 7, The doping concentration of the first dopant in the second containment layer is 1 × 10⁻¹⁶ １６ / cm ３ from 1 x 10 １７ / cm ３ A semiconductor element located between them.

9. A semiconductor device according to claim 1, Including the base, The base is a semiconductor device in which the second semiconductor structure is located on one side away from the active region.

10. A semiconductor device according to claim 9, Further comprising an insulating layer and a reflective layer, The insulating layer is located between the second semiconductor structure and the base. The reflective layer is located between the insulating layer and the base, forming a semiconductor element.

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