Gettering capability evaluation method and gettering capability evaluation sample

Abstract

This invention provides a method for evaluating the gettering ability of silicon wafers to heavy metals, even under low-temperature heat treatment conditions, and a sample for evaluating the gettering ability. [Solution] The present invention provides a method for evaluating the gettering ability of a silicon wafer 210, comprising the steps of: forming a silicon oxide film 215 with a thickness of 2.0 nm to 10 nm on the surface of a silicon wafer 210; forming a heavy metal-containing film 220 on the surface of the silicon oxide film 215 to obtain a silicon wafer sample 200; performing a heat treatment to diffuse heavy metals from the heavy metal-containing film 220 to the silicon wafer 210; determining the heavy metal concentration in the silicon wafer by Secondary Ion Mass Spectrometry (SIMS) analysis after the heat treatment; and evaluating the gettering ability of the silicon wafer based on the heavy metal concentration profile obtained by SIMS analysis.

Description

[Technical Field]

[0001] The present invention relates to a method for evaluating gettering capability and a sample for evaluating gettering capability, and more particularly to a method for evaluating the gettering capability of a silicon wafer. [Background technology]

[0002] To stabilize the yield of semiconductor devices, heavy metal gettering technology using silicon wafers has been developed. Heavy metal atoms are mainly introduced from equipment components used in device manufacturing. These introduced heavy metal atoms diffuse into the wafer due to high-temperature heat treatment associated with the formation of device components such as oxide films, wells, sources, and drains. Gettering sinks created by heavy metal gettering technology capture these diffused heavy metal atoms, preventing deterioration of device characteristics.

[0003] Non-patent document 1 discloses the behavior of copper, a heavy metal, directly diffusing onto the silicon surface and the behavior of copper diffusing onto the silicon surface via a silicon oxide film. Patent document 1 also discloses a method for confirming the gettering ability of a silicon wafer by heat-treating a silicon wafer that has been pre-contaminated with metal impurities at a high temperature of 800°C or higher.

[0004] In recent years, three-dimensional integration technology has attracted attention as an alternative to two-dimensional integrated semiconductor devices, aiming to improve the performance and functionality of semiconductor devices. In three-dimensional integrated semiconductor devices, multiple semiconductor substrates are stacked vertically, and through-silicon electrodes and electrode materials composed of heavy metal elements such as copper are used. Three-dimensional integrated semiconductor devices utilize heavy metal electrode materials with a higher density than conventional two-dimensional integrated semiconductor devices, resulting in greater variation in the thickness of the diffusion barrier layer around the electrodes. Furthermore, the manufacturing process for three-dimensional integrated semiconductor devices involves heat treatment at lower temperatures than that used for conventional two-dimensional integrated semiconductor devices. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] P. Bai et al., "Intrinsic Cu gettering at a thermally grown SiO2 / Si interface", J. Appl. Phys. 68, 3313 (1990). [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2005-303094 [Overview of the project] [Problems that the invention aims to solve]

[0007] The method described in Patent Document 1 is a technique applicable when the heat treatment temperature in the semiconductor device manufacturing process is high, such as in the manufacturing process for two-dimensional integrated semiconductor devices. On the other hand, in the manufacturing process for three-dimensional integrated semiconductor devices, as mentioned above, the heat treatment temperature is generally low and the device structure is complex. Therefore, the method described in Patent Document 1 cannot evaluate whether the silicon wafer under evaluation has appropriate gettering capability for three-dimensional integrated semiconductor device applications. In particular, when manufacturing three-dimensional integrated semiconductor devices, it is necessary to prevent deterioration of device characteristics due to heavy metal contamination from electrode materials associated with low-temperature heat treatment, but a method for evaluating gettering capability that takes into account heavy metal diffusion associated with such low-temperature heat treatment has not been established to date.

[0008] Therefore, the present invention aims to provide a gettering ability evaluation method that can evaluate the gettering ability of a silicon wafer to heavy metals even under low-temperature heat treatment conditions. [Means for solving the problem]

[0009] The inventors diligently studied to solve the above problems. As a result, the inventors conceived of a method in which a silicon oxide film of sufficient thickness to allow heavy metals to penetrate the surface layer of a silicon wafer is formed on the silicon wafer, and then a heavy metal-containing film is provided and thermal diffusion occurs, and the diffusion behavior of the heavy metal is observed. The gist of the silicon wafer gettering capability evaluation method and the silicon wafer sample for gettering capability evaluation of the present invention is as follows.

[0010] In other words, the present invention encompasses the following embodiments. [1] A step of forming a silicon oxide film with a thickness of 2.0 nm or more and 10 nm or less on the surface of a silicon wafer, A step of forming a heavy metal-containing film on the surface of the silicon oxide film, A step of performing a heat treatment to diffuse the heavy metal from the heavy metal-containing film to the silicon wafer, The process involves determining the heavy metal concentration profile in the silicon wafer by SIMS analysis after the heat treatment, A step of evaluating the gettering ability of the silicon wafer based on the heavy metal concentration profile obtained by the SIMS analysis, A method for evaluating gettering ability, including the method described above. [2] The evaluation method according to [1], wherein the silicon wafer is a silicon wafer in which a gettering layer is formed on the surface of the silicon wafer by implanting monomer ions or cluster ions. [3] The evaluation method according to [1] or [2], wherein the silicon wafer is an epitaxial silicon wafer having a silicon epitaxial layer on the surface of a silicon substrate. [4] The evaluation method according to any one of [1] to [3], wherein a silicon oxide film with a thickness of 2.0 nm or more and 5.0 nm or less is formed on the surface of the silicon wafer. [5] The evaluation method according to any one of [1] to [4], wherein the silicon oxide film is formed by thermal oxidation. [6] The evaluation method according to any one of [1] to [5], wherein the heavy metal-containing film contains copper. [7] The evaluation method according to any one of [1] to [6], wherein the heavy metal-containing film is formed by a sputtering method. [8] The evaluation method according to any one of [1] to [7], wherein the heat treatment is performed at 300°C or higher and 600°C or lower. [9] A silicon wafer provided with a gettering site, A silicon oxide film having a thickness of 2.0 nm or more and 10 nm or less provided on the surface of the silicon wafer, A heavy metal-containing film provided on the surface of the silicon oxide film, A sample for evaluating gettering ability, which has the above.

[10] The evaluation sample according to [9], wherein the gettering site is a gettering layer.

[11] The evaluation sample according to [9] or

[10] , wherein the thickness of the silicon oxide film is 2.0 nm or more and 5.0 nm or less.

[12] The evaluation sample according to any one of [9] to

[11] , wherein a silicon epitaxial layer is provided on the surface portion of the silicon wafer. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a gettering ability evaluation method capable of evaluating the gettering ability of a silicon wafer with respect to heavy metals even under low-temperature heat treatment conditions. [Brief Description of the Drawings]

[0012] [Figure 1A] It is a diagram for explaining the outline of the silicon wafer samples according to Experimental Examples 1-1 to 1-3 in Preliminary Experiment 1. [Figure 1B] It is a diagram for explaining the outline of the silicon wafer samples according to Experimental Examples 1-4 to 1-6 in Preliminary Experiment 1. [Figure 2A] It is a graph showing the copper concentration profile in the depth direction of the silicon wafer samples according to Experimental Examples 1-1 to 1-3 in Preliminary Experiment 1. [Figure 2B]A graph showing the copper concentration profile in the depth direction of the silicon wafer samples according to Experimental Examples 1-4 to 1-6 in Preliminary Experiment 1. [Figure 3] STEM observation images before and after heat treatment of the interface between the silicon wafer and the copper film of the silicon wafer samples according to Experimental Examples 1-1, 1-2, 1-4, and 1-5 in Preliminary Experiment 1. [Figure 4A] A graph showing the copper concentration profile in the depth direction of the silicon wafer samples according to Experimental Examples 2-1 to 2-5 in Preliminary Experiment 2. [Figure 4B] A graph showing the copper concentration profile in the depth direction of the silicon wafer samples according to Experimental Examples 2-6 to 2-9 in Preliminary Experiment 2. [Figure 4C] A graph showing the copper concentration profile in the depth direction of the silicon wafer samples according to Experimental Examples 2-10 to 2-12 in Preliminary Experiment 2. [Figure 5] A diagram showing an example of the silicon wafer sample according to the present invention. [Embodiments of the Invention]

[0013] Prior to the detailed description of the embodiments, first, the experiments that led to the completion of the present invention will be described. According to the aforementioned Non-Patent Document 1, when copper silicide is formed, the diffusion of copper beyond the copper silicide into the wafer is suppressed. On the other hand, even when a silicon oxide film with a thickness of 1500 Å is provided, copper cannot diffuse into the wafer. Therefore, the inventor considered the hypothesis that if a diffusion suppression layer that can gently diffuse copper, a heavy metal, onto the surface of the silicon wafer while suppressing the formation of copper silicide is formed, the diffusion behavior of copper during low-temperature heat treatment can be grasped. Therefore, in this experiment, a silicon wafer with the sample structure shown in FIG. 1 was prepared. In FIG. 1A, a copper film was directly provided on the surface of the silicon wafer. In FIG. 1B, a silicon oxide film was provided on the surface of the silicon wafer, and a copper film was provided on the surface of the silicon oxide film.

[0014] [Preliminary Experiment 1] In preliminary experiment 1, a p-type silicon wafer 10 (diameter: 200 mm, thickness: 775 μm, dopant: boron (B), dopant concentration: 1 × 10) obtained from a CZ single-crystal silicon ingot was used. 15 atoms / cm 3 ) was used. Below, the details of the experiments in Experimental Examples 1-1 to 1-6 will be explained with reference to Figure 1.

[0015] (Experimental Example 1-1) Refer to Figure 1A. In Experimental Example 1-1, a copper film 120 was formed on a silicon wafer 110 by magnetron sputtering to obtain the silicon wafer sample 100 for Experimental Example 1-1. No heat treatment was performed thereafter.

[0016] (Experimental Examples 1-2) In Experimental Example 1-1, no heat treatment was performed after the formation of the copper film 120. In Experimental Example 1-2, the silicon wafer sample 100 was obtained in the same manner as in Experimental Example 1-1, except that the silicon wafer sample after the formation of the copper film 120 was heat-treated by holding it at 300°C for 1 hour.

[0017] (Experimental Examples 1-3) In Experimental Example 1-2, a heat treatment at 300°C was performed after copper film formation, and in Experimental Example 1-3, a heat treatment at 600°C was performed after copper film formation. The silicon wafer sample 100 was obtained in the same manner as in Experimental Example 1-2, except that the process was the same.

[0018] (Experimental Examples 1-4) In Experimental Example 1-4, as shown in Figure 1B, a silicon wafer 210 was transported into a thermal oxidation apparatus (manufactured by Samco Corporation), and an oxygen atmosphere heat treatment was performed in the apparatus at an oxygen concentration of 100% and a temperature of 900°C for 1 hour to form a 5.0 nm silicon oxide film 215 on the silicon wafer 210. Subsequently, a copper film 220 was formed on the surface of the silicon oxide film 215 by magnetron sputtering under the same conditions as in Experimental Example 1-1 to obtain the silicon wafer sample 200 related to Experimental Example 1-4.

[0019] (Experimental Examples 1-5) In Experimental Examples 1-4, no heat treatment was performed after the formation of the copper film 220. In Experimental Example 1-5, the silicon wafer sample 200 was obtained in the same manner as in Experimental Examples 1-4, except that the silicon wafer sample after the formation of the copper film 220 was heat-treated by holding it at 300°C for 1 hour.

[0020] (Experimental Examples 1-6) In Experimental Examples 1-5, a heat treatment at 300°C was performed after copper film formation, while in Experimental Example 1-6, a heat treatment was performed on the silicon wafer sample after copper film formation by holding it at 600°C for 1 hour. The silicon wafer sample 200 was obtained in the same manner as in Experimental Examples 1-5.

[0021] For the silicon wafer samples obtained for Experimental Examples 1-1 to 1-6, the copper concentration distribution in the depth direction of the silicon wafer samples was measured by SIMS (Secondary Ion Mass Spectrometry). Figure 2A shows the copper concentration profile of silicon wafer sample 100 for Experimental Examples 1-1 to 1-3, and Figure 2B shows the copper concentration profile of silicon wafer sample 200 for Experimental Examples 1-4 to 1-6.

[0022] In addition, STEM (Scanning Transmission Electron Microscope) images of the vicinity of the interface between the silicon wafer and the copper film were observed for the silicon wafer samples related to Experimental Examples 1-1, 1-2, 1-4, and 1-5, and the observed images are shown in Figure 3.

[0023] From the results in Figure 2A, it was found that in the silicon wafer samples related to Experimental Examples 1-1 to 1-3, regardless of whether heat treatment was performed or not, copper was unevenly distributed in the region less than 500 nm deep from the silicon wafer surface at the interface with the copper film, and the copper concentration decreased uniformly in the region greater than 500 nm deep. On the other hand, from the results in Figure 2B, it was found that in the silicon wafer samples related to Experimental Examples 1-4 to 1-6, in which a 5.0 nm silicon oxide film was placed between the copper film and the silicon wafer, diffusion of copper from the copper film to the silicon wafer occurred even in the region greater than 500 nm deep from the silicon wafer surface. From this, the inventors considered that if a gettering layer is provided on the silicon wafer, the gettering behavior during low-temperature heat treatment can be observed by providing a silicon oxide film between it and the copper film.

[0024] Furthermore, STEM observations in Figure 3 revealed that in silicon wafer sample 100 related to Experimental Example 1-2 after heat treatment, copper silicide (Cu4Si) was formed at the interface between the heat-treated copper film and the silicon wafer. On the other hand, in silicon wafer sample 200 related to Experimental Example 1-4, where a silicon oxide film was placed between the copper film and the silicon wafer, and in Experimental Example 1-5 after heat treatment, no copper silicide was observed. Considering the reasons for these results, it is thought that the free energy of the silicon oxide film (SiO2) is lower and more stable than that of copper silicide (Cu4Si). Therefore, it is considered that the copper on the silicon oxide film diffused into the silicon oxide film without forming copper silicide.

[0025] [Preliminary Experiment 2] Next, in preliminary experiment 2, in order to confirm the diffusion effect of copper on a silicon wafer, we investigated the effects of the thickness of the silicon oxide film placed between the silicon wafer and the copper film and the heat treatment temperature. A p-type silicon wafer, the same as in preliminary experiment 1, was used for the experiment. The details of the experiment are explained in the following experimental examples 2-1 to 2-12.

[0026] (Experimental Example 2-1) In Experimental Example 2-1, a silicon wafer 210 was transported into a thermal oxidation apparatus (manufactured by Samco Corporation), and a 5.0 nm silicon oxide film 215 was formed on the silicon wafer 210 by performing an oxygen atmosphere heat treatment for 1 hour under the conditions of 100% oxygen concentration and a temperature of 900°C. Subsequently, a copper film 220 was formed on the surface of the silicon oxide film 215 by magnetron sputtering to obtain the silicon wafer sample 200 related to Experimental Example 2-1. The silicon wafer sample related to Experimental Example 2-1 was made using a silicon wafer from the same lot as used in Preliminary Experiment 2, and the manufacturing method was the same as in Experimental Example 1-4.

[0027] (Experimental Examples 2-2 to 2-5) In Experimental Example 2-1, no heat treatment was performed after forming the copper film 220. In Experimental Examples 2-2 to 2-5, silicon wafer samples 200 were obtained in the same manner as in Experimental Example 2-1, except that heat treatment was performed according to the conditions in Table 1 below. (Experimental Examples 2-6) In Experimental Example 2-6, a silicon wafer sample 200 was obtained in the same manner as in Experimental Example 2-1, except that a 20 nm silicon oxide film 215 was formed on the silicon wafer 210.

[0028] (Experimental Examples 2-7 to 2-9) In Experimental Example 2-6, no heat treatment was performed after forming the copper film 220. In Experimental Examples 2-7 to 2-9, silicon wafer samples 200 were obtained in the same manner as in Experimental Example 2-6, except that heat treatment was performed according to the conditions in Table 1 below.

[0029] (Experimental Examples 2-10) In Experimental Example 2-10, a silicon wafer sample 200 was obtained in the same manner as in Experimental Example 2-1, except that an 80 nm silicon oxide film 215 was formed on a silicon wafer 210.

[0030] (Experimental Examples 2-11 and 2-12) In Experimental Example 2-10, no heat treatment was performed after forming the copper film 220. In Experimental Examples 2-11 and 2-12, silicon wafer samples 200 were obtained in the same manner as in Experimental Example 2-10, except that heat treatment was performed according to the conditions in Table 1 below.

[0031] For the silicon wafer samples 200 obtained for Experimental Examples 2-1 to 2-12, the copper concentration distribution in the depth direction of the silicon wafer samples 200 was measured by SIMS (Secondary Ion Mass Spectrometry). Figure 4A shows the copper concentration profiles of the silicon wafer samples 200 for Experimental Examples 2-1 to 2-5, Figure 4B shows the profiles for Experimental Examples 2-6 to 2-9, and Figure 4C shows the profiles for Experimental Examples 2-10 to 2-12.

[0032] In the silicon wafer samples used in Experimental Examples 2-1 to 2-5, where a silicon oxide film with a thickness of 5.0 nm was placed between the silicon wafer and the copper film, the diffusion of copper into the silicon wafer was confirmed at all temperatures from 300°C to 600°C. Furthermore, in the silicon wafer samples used in Experimental Examples 2-6 to 2-12, where a silicon oxide film with a thickness of 20 nm or more was placed, it was found that copper was unevenly distributed only near the interface between the copper film and the silicon wafer at all temperatures, and the copper concentration decreased at depths beyond that. In addition, since copper captured in the gettering layer is generally at a relatively high concentration, the detection limit of copper in silicon in SIMS analysis (5.0 × 10⁻¹⁰) was observed at the typical depth where the gettering layer is formed. 16 atoms / cm 3 If copper is diffused at a concentration of ) or higher, it is considered that it can be used to evaluate the gettering ability. From this, the inventors considered that if a gettering layer is provided on a silicon wafer, the gettering behavior during low-temperature heat treatment can be observed by providing a silicon oxide film with a thickness of less than 20 nm between it and the copper film. Table 1 below shows whether the gettering ability evaluation can be applied to the fabrication conditions of each silicon wafer sample.

[0033] [Table 1]

[0034] [Preliminary Experiment 3] Furthermore, in preliminary experiment 3, in order to confirm the diffusion effect of copper on the silicon wafer, we investigated the effects of the silicon oxide film thickness between the silicon wafer and the copper film in more detail. The same silicon wafer 210 as in preliminary experiment 1 was used for the experiment. The details of the experiment are explained in the following experimental examples 3-1 to 3-8.

[0035] (Experimental Example 3-1) In Experimental Example 3-1, a silicon wafer 210 was transported into a thermal oxidation apparatus (manufactured by Samco Corporation), and a 1.0 nm silicon oxide film was formed on the silicon wafer 210 by performing an oxygen atmosphere heat treatment for 1 hour under the conditions of 100% oxygen concentration and a temperature of 900°C. Subsequently, a copper film 220 was formed on the surface of the silicon oxide film by magnetron sputtering, and then a silicon wafer sample 200 related to Experimental Example 3-1 was obtained by performing a heat treatment at 400°C for 1 hour.

[0036] (Experimental Examples 3-2 to 3-6) In Experimental Example 3-1, a 1.0 nm silicon oxide film was formed on silicon wafer 210. In Experimental Examples 3-2 to 3-6, silicon wafer samples 200 were obtained in the same manner as in Experimental Example 3-1, except that the thickness of the silicon oxide film was changed according to the conditions in Table 2 below.

[0037] (Experimental Examples 3-7) In Experimental Example 3-7, a silicon wafer sample 200 was obtained in the same manner as in Experimental Example 3-1, except that a silicon wafer 210 was transported into a thermal oxidation apparatus (manufactured by Samco Corporation) and subjected to an oxygen atmosphere heat treatment for 1 hour under the conditions of 100% oxygen concentration and a temperature of 900°C in the apparatus, thereby forming a 20 nm silicon oxide film 215 on the silicon wafer 210.

[0038] (Experimental Examples 3-8) In Experimental Example 3-7, when a 20-nm silicon oxide film was formed on the silicon wafer 210, in Experimental Example 3-8, a silicon wafer sample 200 was obtained in the same manner as in Experimental Example 3-7, except that the film thickness of the silicon oxide film was changed as shown in Table 2 below.

[0039] Regarding the obtained silicon wafer samples 200 according to Experimental Examples 3-1 to 3-8, the concentration distribution of copper in the depth direction of the silicon wafer sample 200 was measured by SIMS (Secondary Ion Mass Spectrometry). Table 2 below shows the copper concentration at a depth of 1 μm from the surface of the silicon wafer in each silicon wafer sample.

[0040]

Table 2

[0041] From the results of Preliminary Experiment 3, it was found that copper had diffused into the silicon wafer in the silicon wafer samples according to Experimental Examples 3-2 to 3-6 in which a silicon oxide film 215 with a thickness of 2.0 nm or more and 10 nm or less was provided between the silicon wafer 210 and the copper film 220. Specifically, when the silicon oxide film had a thickness of 2.0 nm or more and 10 nm or less, the copper concentration at a depth of 1 μm from the surface of the silicon wafer was 5.0×10 16 atoms / cm 3 or more, and when the thickness was 2.0 nm or more and 5.0 nm or less, it was 5.0×10 17 atoms / cm 3 or more. Also, in the silicon wafer samples 200 according to Experimental Example 3-1 in which a silicon oxide film 220 with a thickness of 1.0 nm was provided, and Experimental Examples 3-7 and 3-8 in which a silicon oxide film 220 with a thickness of 20 nm or more was provided, in each case, the copper concentration at a depth of 1 μm from the surface of the silicon wafer was 5.0×10 16 atoms / cm 3 or less.

[0042] Based on the above results, the inventors believe that if gettering sites are provided on a silicon wafer, the capture behavior of heavy metals by the gettering sites during low-temperature heat treatment can be observed by forming a silicon oxide film with a thickness of 2.0 nm to 10 nm between it and a copper film, and then performing low-temperature heat treatment.

[0043] (Method for evaluating gettering ability) Based on the experimental results described above, a method for evaluating the gettering capability of a silicon wafer according to one embodiment of the present invention will be explained with reference to Figure 5.

[0044] A method for evaluating the gettering ability of a silicon wafer according to one embodiment of the present invention includes at least the steps of: forming a silicon oxide film 515 on the surface of a silicon wafer 510; forming a heavy metal-containing film 520 on the surface of the silicon oxide film 515; performing a heat treatment; determining the heavy metal concentration in the silicon wafer after the heat treatment; and evaluating the gettering ability of the silicon wafer based on the heavy metal concentration profile. Details of each step will be described below.

[0045] <Silicon oxide film formation process> In the process of forming the silicon oxide film 515, a silicon oxide film 515 with a thickness of 2.0 nm to 10 nm is formed on the surface of the silicon wafer 510. As can be seen from preliminary experiments, if the thickness of the silicon oxide film 515 is less than 2.0 nm or greater than 10 nm, heavy metals will not diffuse into the silicon wafer 510 when heat treatment is performed at a low temperature of 300°C to 600°C. From a similar viewpoint, since more heavy metals will diffuse into the silicon wafer 510, it is preferable to form a silicon oxide film 515 with a thickness of 2.0 nm to 5.0 nm on the surface of the silicon wafer 510, and more preferably a silicon oxide film 515 with a thickness of 2.0 nm to 3.0 nm. The silicon oxide film 515 can be formed by any method such as thermal oxidation, but it is preferable to form it by dry oxidation among thermal oxidation methods because it is simple and the oxide film thickness can be controlled on the order of nanometers.

[0046] <Heavy metal-containing film formation process> In the process of forming the heavy metal-containing film, the heavy metal-containing film 520 is formed on the surface of the silicon oxide film 515. As confirmed in preliminary experiments, the reaction between the heavy metal and silicon is suppressed because the heavy metal-containing film 520 is in direct contact with the silicon oxide film 515, and the heavy metal diffuses into the silicon wafer 510 via the silicon oxide film 515. Furthermore, since this is intended for use in a three-dimensional stacked semiconductor device, the heavy metal-containing film 520 preferably contains copper, and may also contain iron, nickel, or ruthenium as the heavy metal. The heavy metal-containing film 520 can be formed by any method, but since it is preferable to simulate the situation in an actual three-dimensional stacked semiconductor device, it is preferably formed by sputtering, and more preferably by magnetron sputtering.

[0047] <Heat treatment process> In the heat treatment process, the silicon wafer having the aforementioned silicon oxide film and heavy metal-containing film is heat-treated to diffuse the heavy metal from the heavy metal-containing film into the silicon wafer. Furthermore, since the heat treatment in this process is a low-temperature heat treatment intended for use in silicon wafers in three-dimensional stacked semiconductor devices, the heat treatment temperature is preferably 300°C to 600°C, more preferably 300°C to 500°C, and even more preferably 300°C to 400°C.

[0048] <Heavy metal concentration evaluation process> In the process of determining heavy metal concentration, the heavy metal concentration in the silicon wafer is determined by secondary ion mass spectrometry (SIMS) analysis. By obtaining a heavy metal concentration profile in the depth direction within the silicon wafer through SIMS analysis, the quantitative heavy metal concentration at each depth can be confirmed. The measurement range is not particularly limited, but since the evaluation is performed on the region where the gettering layer is formed, it is preferable to evaluate up to a depth of 1 μm or more from the silicon wafer surface, more preferably to a depth of 5 μm or more, and even more preferably to a depth of 10 μm or more. The actual gettering layer is 1 μm to 5 μm thick when formed by monomer ion implantation, and less than 1 μm when formed by molecular ions.

[0049] <Process for evaluating gettering capability> In the process of evaluating gettering ability, the gettering ability of the silicon wafer is evaluated based on the heavy metal concentration profile obtained by SIMS analysis. Based on the results of the experimental example described above, if a silicon oxide film of appropriate thickness is formed at the interface between heavy metals such as copper and the silicon wafer, heavy metals such as copper can be diffused into the silicon wafer by low-temperature heat treatment, and the depth-direction profile of the heavy metal concentration can be confirmed by SIMS analysis. If the heavy metal concentration profile can be confirmed by SIMS analysis, it can be applied not only to determining whether or not the silicon wafer has gettering ability, but also to designing the depth (dGS) of the gettering layer in the silicon wafer.

[0050] Furthermore, in the method for evaluating gettering capability according to the present invention, it is preferable that a gettering layer 512 is formed on the silicon wafer 510. The gettering layer 512 is preferably formed by implanting monomer ions or cluster ions, and may also be formed by BMD (Bulk Micro Defect) or the like, and the formation method is not particularly limited. In addition, considering the embodiment in which it is actually used in semiconductor devices, it is preferable that it is an epitaxial silicon wafer having a silicon epitaxial layer 512 on the surface of the silicon substrate.

[0051] (Sample for evaluating gettering capability) The sample for evaluating gettering capability according to this embodiment is a silicon wafer sample, comprising a silicon wafer, a silicon oxide film, and a heavy metal-containing film provided on the surface of the silicon oxide film. The silicon wafer has gettering sites, and a silicon oxide film with a thickness of 2.0 nm to 10 nm is formed on the surface of the silicon wafer. By providing a silicon oxide film of this thickness, heavy metals can diffuse into the silicon wafer even under low-temperature heat treatment conditions, so it is possible to evaluate whether heavy metals are captured at the gettering sites. Here, the gettering sites are preferably gettering layers, a silicon oxide film with a thickness of 2.0 nm to 5.0 nm is preferably formed on the surface of the silicon wafer, and a silicon epitaxial layer is preferably provided on the surface of the silicon wafer. This is because a configuration closer to that of an actual semiconductor device allows for more reliable evaluation. [Industrial applicability]

[0052] The present invention provides a method for evaluating the gettering ability of a silicon wafer to heavy metals, even under low-temperature heat treatment conditions.

[0053] [Contribution to the United Nations-led Sustainable Development Goals (SDGs)] This invention can be used to evaluate silicon wafers for state-of-the-art 3D stacked CMOS image sensors (CIS). CIS enables high-precision environmental recognition in, for example, autonomous vehicles and advanced driver-assistance systems (ADAS), contributing to a reduction in traffic accidents. In the medical field, it can provide high-resolution images in medical cameras and diagnostic equipment, contributing to early diagnosis and improved treatment accuracy, thus contributing to the promotion of public health. It can also contribute to the development of appropriate medical care systems and the strengthening of governance in medical institutions. In this way, CIS makes a significant contribution to society, and this invention supports these contributions while also contributing to sustainable development in line with the SDGs and ESG from the perspectives of environmental considerations, social value enhancement, and proper governance. [Explanation of Symbols]

[0054] 100, 200, 500 silicon wafer samples 110, 210, 510 silicon wafers 215, 515 Silicon oxide film 120, 220, 520 copper film

Claims

1. A step of forming a silicon oxide film with a thickness of 2.0 nm or more and 10 nm or less on the surface of a silicon wafer, A step of forming a heavy metal-containing film on the surface of the silicon oxide film, A step of performing a heat treatment to diffuse the heavy metal from the heavy metal-containing film to the silicon wafer, After the heat treatment, a step is taken to determine the heavy metal concentration profile in the silicon wafer by SIMS analysis, A step of evaluating the gettering ability of the silicon wafer based on the heavy metal concentration profile obtained by the SIMS analysis, A method for evaluating gettering ability, including the method described above.

2. The evaluation method according to claim 1, wherein the silicon wafer is a silicon wafer in which a gettering layer is formed on the surface of the silicon wafer by implanting monomer ions or cluster ions.

3. The evaluation method according to claim 1, wherein the silicon wafer is an epitaxial silicon wafer having a silicon epitaxial layer on the surface of a silicon substrate.

4. The evaluation method according to claim 1, wherein a silicon oxide film with a thickness of 2.0 nm or more and 5.0 nm or less is formed on the surface of the silicon wafer.

5. The evaluation method according to claim 1, wherein the silicon oxide film is formed by thermal oxidation.

6. The evaluation method according to claim 1, wherein the heavy metal-containing film contains copper.

7. The evaluation method according to claim 1, wherein the heavy metal-containing film is formed by a sputtering method.

8. The evaluation method according to claim 1, wherein the heat treatment is performed at a temperature of 300°C or higher and 600°C or lower.

9. A silicon wafer equipped with a gettering site, A silicon oxide film with a thickness of 2.0 nm or more and 10 nm or less is provided on the surface of the silicon wafer, A heavy metal-containing film provided on the surface of the silicon oxide film, A sample for evaluating gettering ability, having the following characteristics.

10. The evaluation sample according to claim 9, wherein the gettering site is a gettering layer.

11. The evaluation sample according to claim 9, wherein the thickness of the silicon oxide film is 2.0 nm or more and 5.0 nm or less.

12. The evaluation sample according to claim 9, wherein a silicon epitaxial layer is provided on the surface of the silicon wafer.

Images