Semiconductor wafer manufacturing method

Abstract

Provided is a semiconductor wafer manufacturing method comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace. The single-wafer heat treatment furnace includes: a plurality of lift pins; and a susceptor having, in a semiconductor wafer placement region, a plurality of through-holes into which the lift pins can be respectively inserted. The manufacturing method comprises: supporting the semiconductor wafer with the plurality of lift pins by raising the susceptor and the plurality of lift pins and bringing the plurality of lift pins into contact with a rear surface of the semiconductor wafer in a state in which the plurality of lift pins are respectively inserted into the plurality of through-holes and each of the plurality of lift pins protrudes upward from the plurality of through-holes; placing the semiconductor wafer, supported with the plurality of lift pins, on the semiconductor wafer placement region of the susceptor by raising only the susceptor; and heat-treating the semiconductor wafer placed on the semiconductor wafer placement region of the susceptor. In a period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer placement region of the susceptor, a period in which the rise of the susceptor is stopped is included.

Description

Method for manufacturing a semiconductor wafer Cross-reference to related applications

[0001] This application claims the priority of Japanese Patent Application No. 2024-221312 filed on December 18, 2024, the entire description of which is incorporated herein by specific reference.

[0002] The present invention relates to a method for manufacturing a semiconductor wafer. Specifically, the present invention relates to a method for manufacturing a semiconductor wafer including heat-treating the semiconductor wafer (for example, forming an epitaxial layer).

[0003] As an example of the processes performed during the manufacturing process of a semiconductor wafer such as a silicon wafer, various heat-treatments such as formation of an epitaxial layer, annealing, and formation of a thermal oxide film can be mentioned. During such heat-treatments, usually, the susceptor in the heat-treatment furnace is raised and lowered to place the semiconductor wafer on the susceptor (see, for example, WO2013 / 005481A1, the entire description of which is incorporated herein by specific reference).

[0004] For the heat-treatment of a semiconductor wafer (also simply referred to as a "wafer"), a single-wafer heat-treatment furnace is widely used. The heat-treatment of a semiconductor wafer in a single-wafer heat-treatment furnace (also simply referred to as a "heat-treatment furnace") is performed, for example, as follows. When a semiconductor wafer is carried into the process chamber of the heat-treatment furnace by a conveying means, the lift pins rise upward in a state of protruding from the through-holes of the susceptor to receive and support the semiconductor wafer. Further, as the susceptor rises, the semiconductor wafer is placed on the susceptor and heat-treatment is performed. When the heat-treatment is completed, the lift pins protrude upward again from the through-holes of the susceptor to support the semiconductor wafer. The semiconductor wafer supported by the lift pins is transferred onto the conveying means and discharged outside the process chamber.

[0005] When heat-treating multiple semiconductor wafers using a single-wafer heat treatment furnace, wafer placement on the susceptor and heat treatment are performed sequentially for each wafer within the furnace. If the wafer placement position on the susceptor is misaligned from the target position (also referred to as "wafer placement misalignment"), the outer edge thickness shape of the heat-treated wafer may not be the desired shape. When such a phenomenon occurs, for example, the heat-treated wafer may not meet the desired outer edge flatness quality. Therefore, it is desirable to suppress the occurrence of wafer placement misalignment on the susceptor during wafer heat treatment in a single-wafer heat treatment furnace.

[0006] One aspect of the present invention suppresses the occurrence of wafer placement misalignment on a susceptor in a single-wafer heat treatment furnace.

[0007] Through diligent research, the inventors have concluded that the cause of wafer misalignment lies in wafer warping resulting from the temperature difference between the front and back surfaces of the wafer. Based on this conclusion, further diligent research has led the inventors to discover that wafer misalignment can be suppressed by temporarily stopping the rise of the susceptor during the period when only the susceptor is raised to place a semiconductor wafer on it. The inventors surmise that this is because the temperature difference between the front and back surfaces of the wafer caused by radiant heat from the susceptor can be reduced by providing the above-mentioned stopping period, thereby mitigating the wafer warping caused by this temperature difference. However, the present invention is not limited to the conclusions described herein.

[0008] One aspect of the present invention is as follows: [1] A method for manufacturing a semiconductor wafer, comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace, wherein the single-wafer heat treatment furnace comprises a plurality of lift pins and a susceptor having a plurality of through holes in a semiconductor wafer mounting area through which each of the lift pins can be inserted, and includes: inserting each of the plurality of lift pins into each of the plurality of through holes so that each of the plurality of lift pins protrudes above the plurality of through holes, raising the susceptor and the plurality of lift pins so that the plurality of lift pins come into contact with the back surface of the semiconductor wafer and the semiconductor wafer is supported by the plurality of lift pins; raising only the susceptor so that the semiconductor wafer supported by the plurality of lift pins is placed on the semiconductor wafer mounting area of ​​the susceptor; and heat-treating the semiconductor wafer placed on the semiconductor wafer mounting area of ​​the susceptor. A method for manufacturing a semiconductor wafer, comprising: [2] A method for manufacturing a semiconductor wafer, comprising: a period during which the susceptor is raised while only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor, and a period during which the susceptor is stopped from rising.[4] The method for manufacturing a semiconductor wafer according to [3], during the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins make contact with the back surface of the semiconductor wafer, the method includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed, wherein the period in which the raising of the susceptor and the plurality of lift pins is stopped is included in the second raising period. [5] The method for manufacturing a semiconductor wafer according to [2], during the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins make contact with the back surface of the semiconductor wafer, the method includes a period in which the raising of the susceptor and the plurality of lift pins is stopped. [6] The method for manufacturing a semiconductor wafer according to [5], wherein the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, the method includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed, and the period in which the raising of the susceptor and the plurality of lift pins is stopped is included in the second raising period. [7] The method for manufacturing a semiconductor wafer according to any one of [1] to [6], wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the heat treatment is the formation of an epitaxial layer.

[0009] According to one aspect of the present invention, a method for manufacturing a semiconductor wafer can be provided, which includes suppressing the occurrence of wafer placement misalignment on a susceptor and heat-treating a semiconductor wafer in a single-wafer heat treatment furnace.

[0010] This is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. This is a flowchart illustrating the operation of the lift pin and susceptor in the single-wafer epitaxial growth furnace shown in Figure 1. For each of the levels 1 to 7 described later, the placement position of the wafer center on the susceptor in state S6 of Figure 2 is shown (two-dimensional coordinate system). Figure 3 shows the results of graphing the wafer center placement position data for each level shown in a single-location graph.

[0011] The above manufacturing method will be explained in more detail below.

[0012] <Semiconductor Wafers> Examples of semiconductor wafers heat-treated in a single-wafer heat treatment furnace include various types of semiconductor wafers such as silicon wafers. For example, a wafer cut from an ingot of semiconductor material grown by a known method (for example, a silicon single-crystal wafer cut from a silicon single-crystal ingot) can be subjected to one or more processing treatments such as planarization, polishing such as mirror polishing, chamfering, and cleaning before being placed in a heat treatment furnace for heat treatment. The conductivity type of the semiconductor wafer may be p-type or n-type.

[0013] <Single-wafer heat treatment furnaces> Examples of single-wafer heat treatment furnaces include epitaxial growth furnaces for forming an epitaxial layer on a semiconductor wafer, annealing furnaces for annealing a semiconductor wafer, and thermal oxidation furnaces for forming a thermal oxide film on a semiconductor wafer. The configurations of these heat treatment furnaces are well known.

[0014] In a single-wafer heat treatment furnace, semiconductor wafers are placed on a susceptor installed in the furnace, and heat treatment is performed inside the furnace.

[0015] Figure 1 is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. The epitaxial growth furnace 1 shown in Figure 1 is equipped with a process chamber 10 in which the epitaxial layer is formed. A reaction gas is introduced into the quartz glass process chamber 10, and the susceptor 12 and preheating ring 17 are heated from the outside of the process chamber 10 by a lamp 19 to form an epitaxial layer on the surface of the semiconductor wafer W. The semiconductor wafer W is transported into the process chamber 10 by a transfer blade 18, which is a transport means, and after the formation of the epitaxial layer is completed, it is transported out of the process chamber 10 by the transfer blade 18. The susceptor 12 has a plurality of through holes in the semiconductor wafer mounting area through which lift pins 11 can be inserted, and a plurality of lift pins 11 are inserted into each of these through holes. The lift pins 11 are connected to a lift assembly 16 via a lift shaft 14 and a lift arm 15. The susceptor 12 is connected to the lift assembly 16 via a susceptor support shaft 13. Although Figure 1 shows two lift pins 11 as an example, in the single-wafer heat treatment furnace used in the above manufacturing method, the number of lift pins can be multiple (i.e., two or more), and is not limited to the number shown in the drawing.

[0016] Figure 2 is a flowchart illustrating the operation of the lift pin and susceptor in the single-wafer epitaxial growth furnace shown in Figure 1. Some of the various components of the single-wafer epitaxial growth furnace shown in Figure 1 are omitted in Figure 2. The operation shown in Figure 2 will be described below. The semiconductor wafer W is loaded into the process chamber (see Figure 1) by the transfer blade 18 (S1). The susceptor 12 and lift pin 11 are raised by the lift assembly (see Figure 1) with the lift pin 11 protruding upward from the through hole of the susceptor 12 (S2-S4). As the susceptor 12 and lift pin 11 rise while maintaining the state in which the lift pin 11 protrudes upward from the through hole of the susceptor 12, the lift pin 11 comes into contact with the back surface of the semiconductor wafer W on the transfer blade 18 (S3). Furthermore, as the lift pin 11 maintains a state in which it protrudes upward from the through hole of the susceptor 12, the susceptor and lift pin 11 rise, releasing contact between the semiconductor wafer W and the transfer blade 18 (S4). Subsequently, the transfer blade 18 exits the process chamber. During the period until the transfer blade 18 exits the process chamber, the rising of the susceptor 12 and lift pin 11 is stopped. After the transfer blade 18 exits the process chamber, the susceptor support shaft (see Figure 1) is driven, causing only the susceptor 12 to rise (S5, S6), and the semiconductor wafer W supported by the lift pin 11 is placed on the semiconductor wafer mounting area of ​​the susceptor 12 (S6). Specifically, the semiconductor wafer W is housed in the recess of the semiconductor wafer mounting area of ​​the susceptor 12 (S6). In the present invention and this specification, during the period when "only the susceptor is rising", the drive of the lift assembly for raising and lowering the lift pin inserted through the through hole of the susceptor is stopped. Thereafter, the susceptor 12 on which the semiconductor wafer W is placed is further raised to the film deposition position while holding the lift pin 11 (S7). After forming an epitaxial layer at the film deposition position, steps S1 to S6 are performed in reverse order, that is, in the order of S6, S5, S4, S3, S2, S1, and then the semiconductor wafer W is transported out of the process chamber by the transfer blade 18.

[0017] <Specific Examples and Comparative Examples of Lift Pin and Susceptor Operation> Table 1 shows specific examples and comparative examples of lift pin and susceptor operation.

[0018]

[0019] In Table 1, "a seconds" in the "S1→S2" column indicates that the time required to transition from state S1 to state S2 in the flow diagram shown in Figure 2 is a seconds. The same applies to the "S2→S3", "S3→S4", "S4→S5", "S5→S6", and "S6→S7" columns. Unless otherwise specified, the lift pin rises at a constant speed and does not stop rising after it starts rising, and the susceptor rises at a constant speed and does not stop rising after it starts rising. In the present invention and this specification, "constant speed" includes cases where the speed is completely the same and cases where the speed fluctuates unintentionally due to equipment or other reasons. In Table 1, the period "S1→S2→S3" is the period during which the susceptor and lift pin are raised until the lift pin and the back surface of the semiconductor wafer come into contact. Subsequently, during the period from S3 to S4, the susceptor and lift pins rise further, releasing the semiconductor wafer from the transfer blade's support, and the semiconductor wafer is supported only by the lift pins (S4). Although not shown in Figure 2, after the semiconductor wafer is supported only by the lift pins in the S4 state, the transfer blade is removed from the process chamber. As previously described, the rising of the susceptor and lift pins is stopped during the period until the transfer blade is removed from the process chamber. The period from when the susceptor alone begins to rise after the transfer blade has been removed from the process chamber until S6 is the "period during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor". This period is the period from S4 to S5 to S6 in Table 1. For details, as described in "Note 1" in the margin of Table 2, S4 to S5 is the period from when the susceptor alone begins to rise after the transfer blade has been removed from the process chamber until S5. In Table 1, "Specific Example" includes a period during which the susceptor rise is stopped while only the "S4→S5→S6" susceptor is raised. "Comparative Example" does not include a period during which the susceptor rise is stopped while only the "S4→S5→S6" susceptor is raised. The details of each level shown in Table 1 are explained below.During the period in which the susceptor and lift pin are rising, the rising speed of the susceptor and the rising speed of the lift pin are the same. This ensures that the lift pin remains above the through-hole of the susceptor throughout the period in which the susceptor and lift pin are rising. In this invention and specification, "same speed" includes cases where the speeds are exactly the same, and cases where there is an unintentional difference in speed due to device-related causes, etc. Hereafter, the rising speed of the susceptor and lift pin will also be referred to as "rising speed (susceptor + lift pin)". The rising speed of the susceptor alone will also be referred to as "susceptor rising speed".

[0020] (Level 1: Comparative Example) During the entire period of "S1→S2→S3" (i.e., the period during which the susceptor and lift pin are raised until the lift pin and the back surface of the semiconductor wafer come into contact), the rising speed (susceptor + lift pin) is constant. During the entire period of "S4→S5→S6" (i.e., the period during which only the susceptor is raised), the susceptor rising speed is constant.

[0021] (Level 2: Comparative Example) During the period "S1→S2→S3", the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. For the period "S4→S5→S6", as in Level 1, the susceptor ascent rate is constant throughout the entire period.

[0022] (Level 3: Comparative Example) For the period "S1→S2→S3", the ascent rate (susceptor + lift pin) is constant throughout the entire period, just like in Level 1. During the period "S4→S5→S6", the susceptor ascent rate in the "S5→S6" period is slower than the susceptor ascent rate in the "S4→S5" period.

[0023] (Level 4: Specific comparative examples) During the period "S1→S2→S3", the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. During the period "S4→S5→S6", the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period.

[0024] (Level 5: Specific Example) During the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. Furthermore, the "S2→S3" period includes a period during which the ascent of the susceptor and lift pin is stopped. In Table 1, "Stop p seconds" in the "S2→S3" column indicates that the ascent of the susceptor and lift pin is stopped for p seconds during the "S2→S3" period (total ascent time (susceptor + lift pin) before and after the stop: n seconds). During the "S4→S5→S6" period, the susceptor ascent rate during the "S5→S6" period is slower than the susceptor ascent rate during the "S4→S5" period. Furthermore, the "S5→S6" period includes a period during which the ascent of the susceptor is stopped. In Table 1, the "Stop r seconds" listed in the "S5→S6" column indicates that the susceptor's upward movement is stopped for r seconds during the "S5→S6" period (total time the susceptor is moving before and after the stop: q seconds).

[0025] (Level 6: Comparative Example) During the "S1→S2→S3" period, the ascent rate (susceptor + lift pin) during the "S2→S3" period is slower than the ascent rate (susceptor + lift pin) during the "S1→S2" period. Furthermore, the "S2→S3" period includes a period during which the ascent of the susceptor and lift pin is stopped. In Table 1, the "stop p seconds" listed in the "S2→S3" column indicates that the ascent of the susceptor and lift pin is stopped for p seconds during the "S2→S3" period (total ascent time (susceptor + lift pin) before and after the stop: n seconds). For the "S4→S5→S6" period, as in Level 1, the susceptor ascent rate is constant throughout the entire period.

[0026] (Level 7: Specific Example) For the period "S1→S2→S3", the lifting speed (susceptor + lift pin) is constant throughout the entire period, just like in Level 1. During the period "S4→S5→S6", the susceptor lifting speed in the "S5→S6" period is slower than the susceptor lifting speed in the "S4→S5" period. Furthermore, the "S5→S6" period includes a period during which the susceptor lifting is stopped. In Table 1, "Stop r seconds" in the "S5→S6" column indicates that the susceptor lifting is stopped for r seconds during the "S5→S6" period (total time the susceptor is lifting before and after the stop: q seconds).

[0027] Levels 5 and 7 include a period during which the susceptor's ascent is stopped during the period in which only the susceptor is raised. As previously mentioned, including such a period can help suppress the occurrence of wafer placement misalignment by reducing the temperature difference between the front and back surfaces of the wafer caused by the radiant heat of the susceptor. Furthermore, Level 5 includes a period during the "S1→S2→S3" period, that is, the period during which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer, during which the susceptor and lift pin are raised. The inventors surmise that including such a period helps reduce the temperature difference between the front and back surfaces of the wafer caused by the radiant heat of the lift pin and susceptor. The inventors believe that reducing the temperature difference between the front and back surfaces of the wafer in this way helps suppress timing discrepancies in contact with the back surface of the wafer among multiple lift pins, which in turn leads to stable support of the semiconductor wafer by the lift pins. Furthermore, the inventors surmise that by stably supporting the semiconductor wafer with lift pins, the occurrence of wafer placement misalignment can be further suppressed.

[0028] Furthermore, the inventors surmise that, from the viewpoint of further suppressing wafer placement misalignment, it is even more preferable to adopt one or both of the following embodiments (1) and (2).

[0029] (1) During the period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor, there is a first susceptor raising period in which the susceptor is raised at the first susceptor raising rate, followed by a second susceptor raising period in which the susceptor is raised at a second susceptor raising rate that is slower than the first susceptor raising rate. In "Level 5" and "Level 7" shown in Table 1, during the period "S4→S5→S6", the period "S5→S6" is the "second susceptor raising period", and the period "S4→S5" is the "first susceptor raising period". Raising the susceptor at a slow speed is preferable from the viewpoint of suppressing the rapid occurrence of a temperature difference between the front and back surfaces of the wafer due to radiant heat from the susceptor. On the other hand, raising the susceptor at a high speed is preferable from the viewpoint of increasing productivity by shortening the processing time in the heat treatment furnace. Embodiment (1) is preferable from the viewpoint of improving productivity and reducing the effects of radiant heat from the susceptor, because the susceptor is raised at high speed until it is close to the wafer, and the period during which the susceptor is raised at a low speed when the wafer is close to the wafer and the wafer is more susceptible to the effects of radiant heat from the susceptor is thus preferable. From both of these viewpoints, it is more preferable to include a period during which the raising of the susceptor is stopped in the second susceptor raising period.

[0030] (2) During the period in which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer, the process includes a first raising period in which the susceptor and lift pin are raised at a first raising rate, followed by a second raising period in which the susceptor and lift pin are raised at a second raising rate that is slower than the first raising rate. In "Level 5" shown in Table 1, during the period "S1→S2→S3", the period "S2→S3" is the "second raising period", and the period "S1→S2" is the "first raising period". Raising the susceptor and lift pin at a slower speed is preferable from the viewpoint of suppressing the rapid occurrence of a temperature difference between the front and back surfaces of the wafer due to radiant heat from the lift pin and susceptor. On the other hand, raising the susceptor and lift pin at a faster speed is preferable from the viewpoint of increasing productivity by shortening the processing time in the heat treatment furnace. Embodiment (2) is preferable from the viewpoint of improving productivity and reducing the effects of radiant heat from the lift pin and susceptor, because the susceptor and lift pin are raised at high speed until the lift pin approaches the wafer, and the period during which the susceptor and lift pin are raised at a low speed when the wafer is more susceptible to the effects of radiant heat from the lift pin and susceptor due to the proximity of the lift pin to the wafer. From both of these viewpoints, it is more preferable to include a period during which the raising of the susceptor and lift pin is stopped during the second raising period.

[0031] The susceptor raising speed during the period when the susceptor is raised after the semiconductor wafer is placed on the wafer mounting area of ​​the susceptor (the period from "S6" to "S7" in Table 1), and the raising speed (susceptor + lift pin) during the period when the susceptor and lift pin are raised after the lift pin contacts the back surface of the semiconductor wafer (the period from "S3" to "S4" in Table 1), are not particularly limited.

[0032] During the period when only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor, a longer period during which the susceptor's rise is stopped is preferable from the viewpoint of reducing the effect of radiant heat from the susceptor, while a shorter period during which the susceptor's rise is stopped is preferable from the viewpoint of improving productivity. From both of these viewpoints, if the total time during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor is taken as 100%, then the period during which the susceptor's rise is stopped is preferably 40% to 60%. Note that when the susceptor's rise is stopped, the above total period (100%) also includes the period during which the susceptor's rise is stopped.

[0033] During the period in which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer, a longer period during which the susceptor and lift pin are stopped rising is preferable from the viewpoint of reducing the effect of radiant heat from the lift pin and susceptor, while a shorter period during which the susceptor and lift pin are stopped rising is preferable from the viewpoint of improving productivity. From both of these viewpoints, if the total time during which the susceptor and lift pin are raised until the lift pin contacts the back surface of the semiconductor wafer is taken as 100%, then the period during which the susceptor and lift pin are stopped rising is preferably 40% to 60%. Note that when the susceptor and lift pin are stopped rising, the above total time (100%) also includes the period during which the susceptor and lift pin are stopped rising.

[0034] As described above, according to one embodiment of the present invention, a semiconductor wafer manufacturing method can suppress the occurrence of wafer placement misalignment on the susceptor and allow semiconductor wafers to be heat-treated in a single-wafer heat treatment furnace.

[0035] The present invention will be further described below based on examples. However, the present invention is not limited to the embodiments shown in the examples.

[0036] Heat treatments were performed using each of the levels 1 to 7 shown in Table 1. In the heat treatment using each level, epitaxial layers were formed on a total of 200 or more semiconductor wafers (silicon single crystal wafers) in a single-wafer epitaxial growth furnace shown in Figure 1. In levels 5 and 7, the total time spent raising only the susceptor until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor was set to 100%, and the period during which the susceptor stopped rising was set to a range of 40% to 60%. In levels 5 and 6, the total time spent raising the susceptor and lift pins until the lift pins contact the back surface of the semiconductor wafer was set to 100%, and the period during which the susceptor and lift pins stopped rising was set to a range of 40% to 60%.

[0037] Figure 3 shows the placement position (two-dimensional coordinate system) of the wafer center on the susceptor in state S6 of Figure 2 for each of levels 1 to 7. The "center of gravity" is the center of the wafer placement area of ​​the susceptor. The positional relationship between the wafer center and the center of gravity was confirmed by the bias of the flatness measurement data in the outer peripheral direction. In the figure, when the X axis is 0 mm and the Y axis is 0 mm, the wafer center is located on the center of gravity.

[0038] Figure 4 shows the results of graphing the wafer center placement data at each level shown in Figure 3 into a single-location graph.

[0039] Table 2 shows the average (arithmetic mean) of the discrepancy between the wafer center and the center of gravity (placement position deviation) at each level shown in Figure 3.

[0040]

[0041] The results shown in Table 2 confirm that by adopting "Level 5" and "Level 7," the misalignment between the wafer center and the center of gravity (mounting position misalignment) is smaller compared to when other levels are adopted. From these results, it can be confirmed that including a period during which the susceptor stops rising in the period during which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor contributes to suppressing the occurrence of wafer mounting position misalignment on the susceptor. Furthermore, comparing "Level 5" and "Level 7" in the results shown in Table 2, the misalignment between the wafer center and the center of gravity (mounting position misalignment) is smaller in Level 5. From these results, it can be confirmed that including a period during which the susceptor and lift pin stop rising in the period during which the susceptor and lift pin are raised until the lift pin and the back surface of the semiconductor wafer come into contact can further suppress the occurrence of wafer mounting position misalignment on the susceptor.

[0042] One aspect of the present invention is useful in the manufacturing field of various semiconductor wafers. For example, according to one aspect of the present invention, it becomes possible to manufacture semiconductor wafers with excellent flatness quality. High-performance semiconductors containing semiconductor wafers with excellent flatness quality as substrates can play an important role in the development and industrialization of advanced industrial products. For example, semiconductors are used in control systems for various products such as automobiles, home appliances, and medical devices, and improving the performance of semiconductors is important for improving the quality and reliability of these products. Furthermore, high-performance semiconductors enable high-speed processing of large amounts of data in data centers, which are essential for providing digital services such as the internet and cloud services. This enables high-speed communication with network terminal devices. Thus, one aspect of the present invention can promote the development of many industrial fields such as the medical, healthcare, energy, transportation infrastructure, and information and communication industries through semiconductor devices, and can contribute to solving the SDGs (Sustainable Development Goals) by solving various social and environmental issues.

Claims

1. A method for manufacturing a semiconductor wafer, comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace, wherein the single-wafer heat treatment furnace comprises a plurality of lift pins and a susceptor having a plurality of through holes in a semiconductor wafer mounting area through which each of the lift pins can be inserted, and includes: raising the susceptor and the plurality of lift pins so that each of the plurality of lift pins is inserted through each of the plurality of through holes and each of the plurality of lift pins protrudes above the plurality of through holes, thereby bringing the plurality of lift pins into contact with the back surface of the semiconductor wafer and supporting the semiconductor wafer with the plurality of lift pins; raising only the susceptor so that the semiconductor wafer supported by the plurality of lift pins is placed on the semiconductor wafer mounting area of ​​the susceptor; and heat-treating the semiconductor wafer placed on the semiconductor wafer mounting area of ​​the susceptor. A method for manufacturing a semiconductor wafer, comprising a period during which the raising of the susceptor is stopped while only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting region of the susceptor.

2. The method for manufacturing a semiconductor wafer according to claim 1, wherein, during the period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer mounting area of ​​the susceptor, the method includes a first susceptor raising period in which the susceptor is raised at a first susceptor raising rate, followed by a second susceptor raising period in which the susceptor is raised at a second susceptor raising rate slower than the first susceptor raising rate, and the period in which the raising of the susceptor is stopped is included in the second susceptor raising period.

3. The method for manufacturing a semiconductor wafer according to claim 1, further comprising a period during which the raising of the susceptor and the plurality of lift pins is stopped while the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer.

4. The method for manufacturing a semiconductor wafer according to claim 3, wherein, during the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, the method includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed, and the period in which the raising of the susceptor and the plurality of lift pins is stopped is included in the second raising period.

5. The method for manufacturing a semiconductor wafer according to claim 2, further comprising a period during which the raising of the susceptor and the plurality of lift pins is stopped while the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer.

6. The method for manufacturing a semiconductor wafer according to claim 5, wherein, during the period in which the susceptor and the plurality of lift pins are raised until the plurality of lift pins come into contact with the back surface of the semiconductor wafer, the method includes a first raising period in which the susceptor and the plurality of lift pins are raised at a first raising speed, followed by a second raising period in which the susceptor and the plurality of lift pins are raised at a second raising speed lower than the first raising speed, and the period in which the raising of the susceptor and the plurality of lift pins is stopped is included in the second raising period.

7. The method for manufacturing a semiconductor wafer according to any one of claims 1 to 6, wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the heat treatment is the formation of an epitaxial layer.

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