Indication device

Abstract

The present invention provides a display device having a data line arrangement structure that enables bezel reduction. [Solution] The display device includes a substrate that includes a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate. The substrate includes first to fifth areas that are sequentially located in a first direction. The display area includes the first to fifth display areas, each contained within the first to fifth areas. The third area includes a third display area, a first non-display area on one side of the third display area, and a second non-display area on the other side of the third display area. The N data lines include M1 data lines passing through the first non-display area within the third area, M2 data lines passing through the second non-display area within the third area, and M3 data lines passing through the third display area within the third area. N is a natural number greater than or equal to 3, and M1, M2, and M3 are each natural numbers greater than or equal to 1, so N = M1 + M2 + M3.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] Recently, a display panel of a display device can include a display area where an image is displayed and a non-display area where an image is not displayed. Here, the non-display area may sometimes be referred to as a bezel. The smaller the size of the non-display area of the display panel, the easier it may be to increase the size of the display area, realize the display device in various shapes, and apply it to various uses. Reducing the size of the non-display area is not easy due to the shape of the display device and the signal wiring arranged on the display panel.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure can provide a display device having a data line arrangement structure capable of reducing a bezel.

[0004] Embodiments of the present disclosure can provide a display device having a data line arrangement structure capable of improving data driving efficiency.

[0005] Embodiments of the present disclosure can provide a display device having a data line arrangement structure capable of reducing a bezel by using a metal layer structure of a display panel.

[0006] Embodiments of the present disclosure can provide a display device of a heterogeneous integrated display type having a data line arrangement structure capable of reducing a bezel.

[0007] Embodiments of this disclosure can provide a display device as a wearable device having a data line arrangement structure that enables bezel reduction. Here, the wearable device may include virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, or extended reality (XR) devices.

[0008] The problems of the embodiments of this disclosure are not limited to those mentioned herein, and other problems not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to an embodiment of the present disclosure may include a substrate including a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate. The substrate may include first to fifth regions sequentially located in a first direction. The display area may include first to fifth display areas contained within the first to fifth regions, respectively. The third region may include a third display area, a first non-display area on one side of the third display area, and a second non-display area on the other side of the third display area.

[0010] N data lines may include M1 data lines passing through a first hidden area in the third region, M2 data lines passing through a second hidden area in the third region, and M3 data lines passing through a third visible area in the third region. Here, N is a natural number greater than or equal to 3, and M1, M2, and M3 are each natural numbers greater than or equal to 1, and the sum of M1, M2, and M3 may correspond to N.

[0011] A display device according to an embodiment of the present disclosure may include a substrate including a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate. The substrate may include first to fifth regions sequentially located in a first direction, and the display area may include first to fifth display areas, each contained within the first to fifth regions.

[0012] In the third region, one edge of the substrate may be concave or curved inward.

[0013] Of the N data lines, the first data line may be bent or curved in one direction in the second display area, and may be bent or curved in the other direction in the fourth display area.

[0014] According to embodiments of this disclosure, a display device having a data line arrangement structure that enables bezel reduction can be provided.

[0015] According to embodiments of this disclosure, a display device can be provided that has a data line arrangement structure that does not require data rendering, thereby improving data driving efficiency. This enables low-power operation.

[0016] According to embodiments of this disclosure, a display device having a data line arrangement structure that enables bezel reduction can be provided by utilizing the metal layer structure of the display panel. This makes process optimization possible.

[0017] According to embodiments of this disclosure, it is possible to provide a heterogeneous integrated display type display device having a data line arrangement structure that enables bezel reduction.

[0018] According to embodiments of this disclosure, a display device as a wearable device can be provided that has a data line arrangement structure that enables bezel reduction.

[0019] The effects of the embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Brief Description of the Drawings

[0020] The content of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings. The detailed description and the accompanying drawings are provided for illustrative purposes only and do not limit the content of the present disclosure. [Figure 1] A display device according to an embodiment of the present disclosure is shown. [Figure 2] An equivalent circuit of sub-pixels of a display panel according to an embodiment of the present disclosure is shown. [Figure 3] An arrangement structure of data lines of a display panel according to an embodiment of the present disclosure is shown. [Figure 4] A detailed area included in a waist area of a display panel according to an embodiment of the present disclosure is shown. [Figure 5] A cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 6] An arrangement structure of data lines capable of reducing bezels of a display panel according to an embodiment of the present disclosure is shown. [Figure 7] An arrangement structure of data lines capable of reducing bezels of a display panel according to an embodiment of the present disclosure is shown. [Figure 8] In a display panel according to an embodiment of the present disclosure, a light-emitting area of a second display area and a light-emitting area of a fourth display area are shown. [Figure 9] In a display panel according to an embodiment of the present disclosure, a light-emitting area of a second display area and a light-emitting area of a fourth display area are shown. [Figure 10] In a display panel according to an embodiment of the present disclosure, a wiring arrangement structure of a second display area and a wiring arrangement structure of a fourth display area are shown. [Figure 11] In a display panel according to an embodiment of the present disclosure, a wiring arrangement structure of a second display area and a wiring arrangement structure of a fourth display area are shown. [Figure 12]In the display panel according to an embodiment of the present disclosure, it is a cross-sectional view of the second display area and the fourth display area. [Figure 13] In the display panel according to an embodiment of the present disclosure, it is a cross-sectional view of the second display area and the fourth display area.

Mode for Carrying Out the Invention

[0021] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, the same numerals may be used as much as possible. In the description of the present disclosure, when it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality, unless there are specific descriptions.

[0022] Also, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0023] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "joined", it should be understood that two or more components can be directly "connected", "coupled", or "joined", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "joined". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.

[0024] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0025] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0026] Figure 1 shows a display device 100 according to an embodiment of the present disclosure.

[0027] The display device 100 according to the embodiments of this disclosure may include a display panel 110 and a drive circuit 120, etc.

[0028] The display panel 110 may include a substrate 111 and a plurality of subpixels SP formed on the substrate 111.

[0029] The substrate 111 may include a display area DA on which video can be displayed and a non-display area NDA on which video cannot be displayed. The display area DA and the non-display area NDA may be areas of the display panel 110. That is, the display panel 110 may include a display area DA and a non-display area NDA. Here, the non-display area NDA is also called a bezel.

[0030] The substrate 111 can be divided into multiple regions. For example, the substrate 111 can include an upper region TOP, a lower region BOT, and an intermediate region MID. The upper region TOP can include a pad region PA. The lower region BOT can be located furthest from the pad region PA among the first to third regions A1, A2, and A3. The intermediate region MID can be located between the upper region TOP and the lower region BOT.

[0031] The display area DA may include the upper display area DA_TOP contained within the upper area TOP, the lower display area DA_BOT contained within the lower area BOT, and the intermediate display area DA_MID contained within the intermediate area MID. That is, the substrate 111 may include the upper area TOP containing the upper display area DA_TOP, the lower area BOT containing the lower display area DA_BOT, and the intermediate area MID containing the intermediate display area DA_MID. The upper area TOP may include the pad area PA.

[0032] The non-display area (NDA) is an outer area of ​​the display area (DA) and may include a pad area (PA) adjacent to the upper display area (DA_TOP) rather than the intermediate display area (DA_MID).

[0033] The substrate 111 may be a flexible substrate.

[0034] The substrate 111 may have an upper edge line TEL, a lower edge line BEL, a first boundary line BL1, and a second boundary line BL2.

[0035] The upper edge line TEL and the lower edge line BEL may be cutting lines of the substrate 111. The upper edge line TEL may be the edge line of the substrate 111 near the pad area PA, and the lower edge line BEL may be the edge line of the substrate 111 on the opposite side of the upper edge line TEL.

[0036] The substrate 111 can be bent near the upper edge line TEL. Therefore, the pad area PA and the components connected to it (drive circuit 120, flexible printed circuit board 130, printed circuit board 140) can be located beneath the substrate 111.

[0037] The first boundary line BL1 may be a virtual line indicating the boundary between the upper display area DA_TOP and the intermediate display area DA_MID, and the second boundary line BL2 may be a virtual line indicating the boundary between the lower display area DA_BOT and the intermediate display area DA_MID.

[0038] Multiple subpixels SP can be placed in the display area DA. Multiple subpixels SP can be placed in each of the upper display area DA_TOP, the middle display area DA_MID, and the lower display area DA_BOT.

[0039] In the display device 100 according to the embodiment of the present disclosure, the intermediate region MID may include an inwardly recessed waist region WA. This allows the intermediate region MID to have a width smaller than the upper display region DA_TOP and / or the lower display region DA_BOT.

[0040] Within the intermediate region MID, the waist region WA can represent the region between the valley line Lv and the edge EDG of the substrate 111. The valley line Lv may be a virtual line extending in a first direction through the point where the substrate 111 is most deeply indented (Pv, hereinafter referred to as the "valley point").

[0041] For example, at the first boundary line BL1 between the upper display area DA_TOP and the intermediate display area DA_MID, the width of the intermediate display area DA_MID may narrow as you approach its center. Similarly, at the second boundary line BL2 between the lower display area DA_BOT and the intermediate display area DA_MID, the width of the intermediate display area DA_MID may narrow as you approach its center. Here, width can refer to the length in the first direction.

[0042] For example, the maximum width of the intermediate display area DA_MID may be smaller than the maximum width of the upper display area DA_TOP and the maximum width of the lower display area DA_BOT.

[0043] In the display device 100 according to the embodiments of this disclosure, the drive circuit 120 can be electrically connected to the pad area PA within the non-display area NDA. For example, the drive circuit 120 is mounted on a flexible printed circuit board 130, and one side of the flexible printed circuit board 130 can be connected to the pad area PA of the substrate 111. Here, the flexible printed circuit board 130 may also be called a flexible printed circuit or circuit film. A printed circuit board 140 may be connected to the other side of the flexible printed circuit board 130.

[0044] The drive circuit 120 can be implemented as an integrated circuit. The drive circuit 120 may include a data drive circuit that supplies data signals corresponding to the video signal to the subpixels SP in the display panel 110.

[0045] The display device 100 according to embodiments of this disclosure may further include a gate drive circuit that supplies gate signals to subpixels SP in the display panel 110. In one example, the gate drive circuit may be located outside the display panel 110. In another example, the gate drive circuit may be located inside the display panel 110. A gate drive circuit located inside the display panel 110 is called a gate-in-panel (GIP) type and can be located on a substrate 111. A gate drive circuit located inside the display panel 110 can also be called a gate-in-panel circuit. For example, a gate-in-panel circuit can be located in a non-display area (NDA).

[0046] If the gate drive circuit is located outside the display panel 110, the gate drive circuit may be included in the drive circuit 120, or it may exist separately from the drive circuit 120.

[0047] The display device 100 according to the embodiments of this disclosure may further include a controller for controlling the drive circuit 120 and the gate drive circuit. For example, the controller may be mounted on a printed circuit board 140.

[0048] The display device 100 according to the embodiments of this disclosure may further include a non-display area (NDA) of the display panel 110 and a case member that covers the circuit configuration (e.g., a drive circuit 120, a flexible printed circuit board 130, and a printed circuit board 140). For example, the case member may include a mounting member that can be worn on the user's face (e.g., eyeglass temples, a headband, etc.).

[0049] On the other hand, for example, the display device 100 according to the embodiment of the present disclosure may have the shape of eyeglasses. For example, the display device 100 according to the embodiment of the present disclosure may be a heterogeneous integrated display device or an eyeglass-type wearable device. If the display device 100 according to the embodiment of the present disclosure is an eyeglass-type wearable device, the user can wear the display device 100 like eyeglasses. As a result, the waist region WA of the display device 100 can correspond to the position of the user's nose, and the upper edge line TEL of the upper region TOP and the lower edge line BEL of the lower region BOT can be adjacent to both of the user's ears.

[0050] For example, the display device 100 according to the embodiments of this disclosure may be at least one wearable device from among virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, and extended reality (XR) devices. For example, if the display device 100 is a wearable device that can be worn on a user's face, the surface on which the image is displayed among the two surfaces of the display device 100 may be the surface opposite to the surface closer to the user wearing the display device 100. In this case, the image displayed on the display device 100 worn by the user can be shown to other users in the vicinity of the wearer. As another example, if the display device 100 is a wearable device that can be worn on a user's face, the surface on which the image is displayed among the two surfaces of the display device 100 may be the surface closer to the user wearing the display device 100. As another example, if the display device 100 is a wearable device that can be worn on the user's face, then of the two surfaces of the display device 100, the surface on which the image is displayed can be both the surface closer to the user wearing the display device 100 and the surface on the opposite side.

[0051] Figure 2 shows the equivalent circuit of a subpixel SP of the display panel 110 according to an embodiment of the present disclosure.

[0052] Each subpixel SP of the display device 100 according to the embodiments of this disclosure may include a light-emitting element ED and a subpixel circuit SPC for driving the light-emitting element ED.

[0053] The light-emitting element (ED) may be an organic-based organic light-emitting diode (OLED), an inorganic-based light-emitting diode (LED), or a quantum dot light-emitting element, but is not limited to these. For the sake of explanation, the following description will use the case where the light-emitting element (ED) is an organic light-emitting diode (OLED) as an example.

[0054] The subpixel circuit SPC may include multiple transistors for driving the light-emitting element ED and at least one capacitor. The subpixel circuit SPC can drive the light-emitting element ED by supplying a drive current to the light-emitting element ED at predetermined timings. The light-emitting element ED can emit light when driven by the drive current.

[0055] Multiple transistors included in the subpixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED and a scan transistor ST that is turned on or off in response to a scan signal SC.

[0056] The drive transistor DT can supply drive current to the light-emitting element ED. The scan transistor ST can be configured to control the electrical state of the corresponding node in the subpixel circuit SPC, or to control the state or operation of the drive transistor DT. At least one capacitor may include a storage capacitor Cst to maintain a constant voltage between frames.

[0057] To drive the subpixel SP, a video signal such as the data signal Vdata and a type of gate signal such as the scan signal SC can be applied to the subpixel SP. Furthermore, a common drive signal, including the drive voltage VDD and base voltage VSS, can be applied to the subpixel SP.

[0058] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL can be placed between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE may be an electrode placed in each subpixel SP, and the common electrode CE may be an electrode commonly placed in multiple subpixels SP. As an example, the pixel electrode PE may be the anode electrode and the common electrode CE may be the cathode electrode. As another example, the pixel electrode PE may be the cathode electrode and the common electrode CE may be the anode electrode. In the following explanation, for convenience, we will use the case where the pixel electrode PE is the anode electrode and the common electrode CE is the cathode electrode as an example.

[0059] If the light-emitting element ED is an organic light-emitting element, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 together can be called the common intermediate layer EL_COM.

[0060] The light-emitting layer (EML) can be placed for each subpixel SP, or it can be placed in common across multiple subpixel SPs, and the common intermediate layer (EL_COM) can also be placed in common across multiple subpixel SPs. However, it is not limited to these arrangements.

[0061] The light-emitting layer (EML) can be placed in each light-emitting region or in common across multiple light-emitting regions, and the common intermediate layer (EL_COM) can be placed in common across multiple light-emitting and non-light-emitting regions. However, it is not limited to these arrangements.

[0062] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), an electron blocking layer (EBL), and a hole transfer layer (HTL), and the second common intermediate layer COM2 may include an electron transfer layer (ETL), a hole blocking layer (HBL), and an electron injection layer (EIL), but is not limited thereto. The hole injection layer HIL injects holes from the pixel electrode PE to the hole transfer layer HTL, the hole transfer layer HTL transports holes to the light-emitting layer EML, the electron injection layer EIL injects electrons from the common electrode CE to the electron transfer layer ETL, and the electron transfer layer ETL transports electrons to the light-emitting layer EML.

[0063] For example, the common electrode CE can be electrically connected to the base voltage wiring VSSL. A base voltage VSS, which is a type of common voltage, can be applied to the common electrode CE via the base voltage wiring VSSL. The pixel electrode PE can be electrically connected directly or indirectly (via other transistors) to the first node Na of the drive transistor DT of each subpixel SP. In this disclosure, the base voltage VSS may also be referred to as the first common voltage, low potential power supply voltage, or low potential voltage, and the base voltage wiring VSSL may also be referred to as the first common voltage wiring, low potential power supply voltage line, or low potential voltage line.

[0064] Each light-emitting element ED can be composed of the superposition of a pixel electrode PE, an emissive layer EML within the intermediate layer EL, and a common electrode CE. Each light-emitting element ED can form a predetermined light-emitting region. For example, the light-emitting region of each light-emitting element ED may include the superposition of the pixel electrode PE, the emissive layer EML within the intermediate layer EL, and the common electrode CE.

[0065] The drive transistor DT may be a drive transistor for supplying drive current to the light-emitting element ED. The drive transistor DT may be connected between the drive voltage wiring VDDL and the light-emitting element ED.

[0066] The drive transistor DT may include a first node Na, a second node Nb, and a third node Nc. The first node Na may be electrically connected to the light-emitting element ED, the second node Nb may be to which a data signal Vdata is applied, and the third node Nc may be to which a drive voltage VDD, which is another type of common voltage, is applied from the drive voltage wiring VDDL. The drive transistor DT may be connected to the first node Na and the third node Nc. In this disclosure, the drive voltage VDD may also be referred to as the second common voltage, high potential power supply voltage, or high potential voltage, and the drive voltage wiring VDDL may also be referred to as the second common voltage wiring, low potential power supply voltage line, or low potential voltage line.

[0067] In a drive transistor DT, the second node Nb is the gate node, the first node Na is either the source node or the drain node, and the third node Nc may be either the drain node or the source node. For the sake of explanation, in the following, in a drive transistor DT, the second node Nb may be the gate node, the first node Na may be the source node, and the third node Nc may be the drain node. However, it is not limited to this.

[0068] The scan transistor ST included in the subpixel circuit SPC shown in Figure 2 may be a switching transistor that transmits the data signal Vdata, which is the video signal, to the second node Nb, which is the gate node of the drive transistor DT.

[0069] The scan transistor ST is controlled on / off by a scan signal SC, which is a type of gate signal applied via a scan line SCL, which is a type of gate line GL, and can control the electrical connection between the second node Nb of the drive transistor DT and the data line DL. The drain or source electrode of the scan transistor ST may be electrically connected to the data line DL, the source or drain electrode of the scan transistor ST may be electrically connected to the second node Nb of the drive transistor DT, and the gate electrode of the scan transistor ST may be electrically connected to the scan line SCL.

[0070] The storage capacitor Cst may be electrically connected between the first node Na and the second node Nb of the drive transistor DT. The storage capacitor Cst may include at least one capacitor electrode electrically connected to or corresponding to the first node Na of the drive transistor DT, and at least one capacitor electrode electrically connected to or corresponding to the second node Nb of the drive transistor DT.

[0071] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node Na and the second node Nb of the drive transistor DT. However, it is not limited to this.

[0072] The drive transistor DT and the scan transistor ST may each be either an n-type or p-type transistor, but are not limited to this. For example, one of the drive transistor DT and scan transistor ST may be either an n-type or a p-type transistor.

[0073] The display panel 110 may have a top-emission structure or a bottom-emission structure. When the display panel 110 has a top-emission structure, at least a portion of the subpixel circuit SPC can overlap with at least a portion of the light-emitting element ED in the vertical direction. This can increase the area of ​​the light-emitting region and improve the aperture ratio. When the display panel 110 has a bottom-emission structure, the subpixel circuit SPC does not need to overlap with the light-emitting element ED in the vertical direction.

[0074] The subpixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure, as shown in Figure 2, which includes two transistors DT and ST and one capacitor Cst, and may optionally include one or more transistors or one or more capacitors.

[0075] The structure of the subpixel circuit SPC can affect the type and number of gate lines supplied to the subpixel SP. Furthermore, the structure of the subpixel circuit SPC can affect the type and number of common drive signals supplied to the subpixel SP.

[0076] Since the circuit elements within each subpixel SP (e.g., light-emitting elements ED, which are realized with organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture and oxygen, the display panel 110 may further include a sealing layer placed on the light-emitting elements ED. The sealing layer can prevent external moisture and oxygen from penetrating the circuit elements (e.g., light-emitting elements ED). The sealing layer can be configured in various forms to prevent the light-emitting elements ED from coming into contact with moisture and oxygen. For example, the sealing layer may consist of two or more layers in which organic and inorganic films are alternately stacked. However, it is not limited to this.

[0077] The display device 100 may further include a touch sensor layer on which a touch sensor is formed, and a touch sensing circuit that senses the touch sensor formed on the touch sensor layer and determines whether or not a touch is present or the touch coordinates, in order to provide a touch sensing function.

[0078] Figure 3 shows the data line arrangement structure of the display panel 110 according to an embodiment of the present disclosure. However, in the following description, Figures 1 and 2 will also be referred to.

[0079] The display panel 110 may include an upper region TOP, a lower region BOT, and an intermediate region MID between the upper region TOP and the lower region BOT. The upper region TOP may be the region to which circuit configurations (e.g., a drive circuit 120, a flexible printed circuit board 130, and a printed circuit board 140) are connected. The width BTW of the portion of the upper region TOP corresponding to the upper edge line TEL may be smaller than that of other portions.

[0080] The display panel 110 may include multiple data lines DL for transmitting data signals Vdata to multiple subpixels SP. Multiple data lines DL may be arranged in the display area DA.

[0081] Depending on the shape of the substrate 111 of the display panel 110 (for example, the shape of eyeglasses), the multiple data lines DL may include a plurality of first data lines DL1 that do not pass through the waist region WA, and a plurality of second data lines DL2 that pass through the waist region WA.

[0082] Each of the multiple first data lines DL1 can be connected to a first data link line DLL1 that extends from the pad area PA through the upper edge line TEL to the upper display area DA_TOP, and can be positioned extending in a first direction within the upper display area DA_TOP.

[0083] Each of the multiple first data lines DL1 can extend in the first direction and be positioned without curving in all of the upper display area DA_TOP, the middle display area DA_MID, and the lower display area DA_BOT.

[0084] Each of the multiple second data lines DL2 can be connected to a second data link line DLL2 that extends from the pad area PA through the upper edge line TEL to the upper display area DA_TOP, and can be positioned extending in the first direction within the upper display area DA_TOP.

[0085] However, each of the multiple second data lines DL2 can be positioned curved inward so that it is positioned on the inwardly recessed substrate 111 when passing through the waist region WA within the intermediate display region DA_MID.

[0086] If each of the multiple second data lines DL2 curves as it passes through the waist region WA, it can pass through the hidden region NDA contained within the waist region WA. As a result, each of the multiple second data lines DL2 may include an upper data line DL2_DA_TOP located in the upper display region DA_TOP, a lower data line DL2_DA_BOT located in the lower display region DA_BOT, and a bypass data line DL2_NDA that connects the upper data line DL1_DA_TOP and the lower data line DL2_DA_BOT and is located in the hidden region NDA.

[0087] As mentioned above, each of the multiple second data lines DL2 is positioned in a curved manner within the waist region WA, and as each of the bypass data lines DL2_NDA of the multiple second data lines DL2 is positioned within the hidden region NDA, the size of the hidden region NDA included in the waist region WA can increase.

[0088] Consequently, if the display device 100 according to the embodiment of this disclosure is a glasses-type wearable device, an increase in the size of the non-display area NDA included in the waist area WA may result in a decrease in the design quality of the display device 100 or make it inconvenient to wear the display device 100.

[0089] Figure 4 shows the detail area included in the waist area WA of the display panel 110 according to the embodiment of the present disclosure.

[0090] The hidden area NDA included in the waist area WA may include a data link area DLLA where multiple bypass data lines DL2_NDA of multiple second data lines DL2 are located, a drive power wiring area PLA where drive power wiring is located, a gate-in-panel circuit area GIPA where a gate-in-panel circuit, which is a gate-in-panel type gate drive circuit, is located, a base voltage wiring area VSSA where base voltage wiring VSSL is located, and a crack stopper area CSA where crack stopper structures are located.

[0091] The drive power supply wiring area PLA can accommodate gate drive-related link wiring connected to the gate in-panel circuit, and drive power supply wiring for transmitting various drive power supplies (e.g., initialization voltage, reference voltage, etc.) to the subpixel SP.

[0092] The non-display area NDA included in the waist area WA may further include a connection area CLA where the drive power wiring located in the drive power wiring area PLA is extended and gate lines are located to transmit gate signals output from the gate-in-panel circuit to the subpixel SP.

[0093] The non-display area NDA included in the waist area WA may further include a first empty space FA1 between the base voltage wiring area VSSA and the crack stopper area CSA, and a second empty space FA2 between the crack stopper area CSA and the trimming line. Here, the trimming line may correspond to the cutting line of the substrate 111.

[0094] As mentioned above, each of the multiple second data lines DL2 is positioned curvingly in the waist region WA, and as the bypass data line DL2_NDA of each of the multiple second data lines DL2 is positioned in the hidden region NDA, the hidden region NDA contained in the waist region WA can contain a larger data link region DLLA.

[0095] Figure 5 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view taken along the XY lines of Figure 3.

[0096] The display panel 110 according to the embodiments of this disclosure may include a display area DA and a non-display area NDA.

[0097] The display panel 110 according to the embodiments of this disclosure may include a substrate 111, a buffer layer 520 disposed on the substrate 111, a gate insulating layer 530 disposed on the buffer layer 520, an interlayer insulating layer 540 disposed on the gate insulating layer 530, a planarizing layer 550 disposed on the interlayer insulating layer 540, a light-emitting element ED disposed on the planarizing layer 550 and located in the display area DA, and a sealing layer 580 disposed on the light-emitting element ED.

[0098] The substrate 111 may be single-layer or multilayer. If the substrate 111 is multilayer, it may include a first substrate 301, an intermediate substrate layer 302, and a second substrate 303. The intermediate substrate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, the first substrate 301 and the second substrate 303 may each be polyimide (PI) layers, but are not limited thereto. The intermediate substrate layer 302 may also be an inorganic insulating layer, but are not limited thereto. The intermediate substrate layer 302 can block the charge from affecting the transistors located on the second substrate 303 via the polyimide layer of the second substrate 303 when the first substrate 301, which is a polyimide layer, is charged.

[0099] Furthermore, the intermediate substrate layer 302 can block moisture components from penetrating the first substrate 301 and permeating to the upper layer. For example, the intermediate substrate layer 302 can consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), or it can be formed from a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx). However, it is not limited to these.

[0100] The buffer layer 520 may be single-layer or multi-layer, but is not limited to this. If the buffer layer 520 is multi-layer, it may include a first buffer layer 521 and a second buffer layer 522.

[0101] The display panel 110 may further include a transistor TFT and a storage capacitor Cst, which are arranged on the buffer layer 520. The transistor TFT may include an active layer ACT, a gate electrode G, a source electrode S, and a drain electrode D. The storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0102] The active layer ACT of the transistor TFT is placed on the buffer layer 520, and the gate insulating layer 530 may be placed on the active layer ACT of the transistor TFT.

[0103] The gate electrode G of the transistor TFT is located on the gate insulating layer 530 and can overlap with at least a portion of the active layer ACT.

[0104] The interlayer insulating layer 540 may include a first interlayer insulating layer 541 and a second interlayer insulating layer 542. The first interlayer insulating layer 541 may be placed on the gate electrode G of a transistor TFT. The second interlayer insulating layer 542 may be placed on the first interlayer insulating layer 541.

[0105] The source electrode S and drain electrode D of the transistor TFT can be placed on the second interlayer insulating layer 542. The source electrode S of the transistor TFT can be connected to a portion of the active layer ACT through holes in the second interlayer insulating layer 542 and the first interlayer insulating layer 541, and the drain electrode D of the transistor TFT can be connected to another portion of the active layer ACT of the transistor TFT through other holes in the second interlayer insulating layer 542 and the first interlayer insulating layer 541.

[0106] The first capacitor electrode CAPE1 can be placed on the gate insulating layer 530, and the second capacitor electrode CAPE2 can be placed on the first interlayer insulating layer 541 and superimposed on the first capacitor electrode CAPE1.

[0107] The first capacitor electrode CAPE1 can be placed in the same metal layer as the gate electrode G of the transistor TFT, and the second capacitor electrode CAPE2 can be placed between the gate electrode G of the transistor TFT and the source electrode S / drain electrode D.

[0108] The planarization layer 550 can be placed on the second interlayer insulating layer 542.

[0109] The light-emitting element ED can be placed on the planarization layer 550 and may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0110] The pixel electrode PE is placed on the planarization layer 550 and can be electrically connected to the source electrode S or drain electrode D of the transistor TFT through holes in the planarization layer 550.

[0111] Bank 560 is positioned on the planarization layer 550 and the pixel electrode PE, but may have light-emitting holes EH that expose a portion of the pixel electrode PE. The light-emitting holes EH of bank 560 may correspond to the light-emitting region of the light-emitting element ED.

[0112] The intermediate layer EL can be positioned on bank 560, in contact with the upper surface of the pixel electrode PE within the light-emitting hole EH of bank 560.

[0113] The common electrode CE can be placed on the intermediate layer EL.

[0114] The sealing layer 580 can be placed on the common electrode CE. The sealing layer 580 may include a first sealing layer 581, a second sealing layer 582, and a third sealing layer 583. The first sealing layer 581 and the third sealing layer 583 may be inorganic layers, and the second sealing layer 582 may be an organic layer.

[0115] The display panel 110 may further include a first dam DAM1 positioned outside the second sealing layer 582. For example, the first dam DAM1 may include a plurality of dam constituent layers 550a, 560a, and 570a. For example, the plurality of dam constituent layers 550a, 560a, and 570a may include a first dam constituent layer 550a, a second dam constituent layer 560a, and a third dam constituent layer 570a. The first dam constituent layer 550a may contain the same organic insulating material as the flattening layer 550, the second dam constituent layer 560a may contain the same organic insulating material as the bank 560, and the third dam constituent layer 570a may contain the same organic insulating material as the spacer that can be placed on the bank 560.

[0116] The display panel 110 may further include a second dam DAM2 located outside the first dam DAM1. For example, the second dam DAM2 may include multiple dam layers 550a, 560a, and 570a, similar to the first dam DAM1.

[0117] The first sealing layer 581 is positioned on the common electrode CE, but may extend beyond the top of the first dam DAM1 and the second dam DAM2 to the outside of the second dam DAM2.

[0118] The third sealing layer 583 is positioned on the second sealing layer 582, but extends outward beyond the second sealing layer 582, and together with the first sealing layer 581, can extend over the tops of the first dam DAM1 and the second dam DAM2, extending to the outside of the second dam DAM2. As a result, the second sealing layer 582 is absent on the first dam DAM1 and the second dam DAM2, and the first sealing layer 581 and the third sealing layer 583 can be positioned on the structures of the first dam DAM1 and the second dam DAM2 in contact with each other.

[0119] The display panel 110 may further include a base voltage wiring VSSL to which the base voltage VSS is applied, and a connection pattern CP that electrically connects the common electrode CE and the base voltage wiring VSSL.

[0120] The base voltage wiring VSSL can be placed between the second interlayer insulation layer 542 and the planarization layer 550. The base voltage wiring VSSL can be placed below the planarization layer 550 and can extend below the first dam DAM1.

[0121] The connection pattern CP can be positioned between bank 560 and planarization layer 550. For example, the connection pattern CP can be located in a non-display area NDA. The connection pattern CP can extend from the top surface of planarization layer 550 along the side surface of planarization layer 550 and be electrically connected to the base voltage wiring VSSL.

[0122] Bank 560 may have additional connection holes CH. For example, the connection holes CH of Bank 560 may be located in a hidden area NDA.

[0123] The common electrode CE can be extended from the display area DA to a portion of the non-display area NDA. In the non-display area NDA, the common electrode CE can be electrically connected to the upper surface of the connection pattern CP via the connection hole CH of bank 560.

[0124] The display panel 110 may further include a lower shielding metal BSM that overlaps with the active layer ACT of the transistor TFT. The lower shielding metal BSM may be located between the substrate 111 and the buffer layer 520, or between the first buffer layer 521 and the second buffer layer 522.

[0125] The display panel 110 can include various metal layers. For example, the display panel 110 can include a lower shield metal layer BSML on which the lower shield metal BSM is located, a gate metal layer GML on which the gate electrode G of the transistor TFT and the first capacitor electrode CAPE1 of the storage capacitor Cst are located, a capacitor electrode metal layer TML on which the second capacitor electrode CAPE2 of the storage capacitor Cst is located, a source-drain metal layer SDML on which the source electrode S and drain electrode D of the transistor TFT are located, a pixel electrode metal layer PEML on which the pixel electrode PE is located, and a common electrode metal layer CEML on which the common electrode CE is located.

[0126] On the other hand, as described above with reference to Figures 3 and 4, the shape of the display panel 110 allows the size of the non-display area NDA included in the waist area WA to increase as data lines (bypass data lines) to which data signals are applied are arranged. As a result, if the display device 100 according to the embodiment of this disclosure is a glasses-type wearable device, the design quality of the display device 100 may be reduced or the display device 100 may become inconvenient to wear.

[0127] Therefore, embodiments of the present disclosure can provide a "bezel-reducing data link structure" that can reduce the size of the non-display area NDA included in the waist area WA of the display panel 110. Embodiments of the present disclosure can provide a power wiring structure that can improve display driving performance. Embodiments of the present disclosure can provide a power wiring structure linked to the bezel-reducing data link structure.

[0128] The following describes a signal structure that enables bezel reduction according to embodiments of the present disclosure. However, the following description will also refer to Figures 1 to 5.

[0129] Figures 6 and 7 show a data line arrangement structure that enables bezel reduction of the display panel 110 according to an embodiment of the present disclosure.

[0130] Referring to Figures 6 and 7, the display panel 110 according to the embodiment of the present disclosure may include a substrate 111 that includes a display area DA capable of displaying video and a non-display area NDA outside the display area DA, and N data lines arranged on the substrate 111.

[0131] For example, the substrate 111 may include first to fifth regions A1, A2, A3, A4, and A5 that are sequentially located in the first direction.

[0132] For example, display area DA can include the first to fifth display areas DA1, DA2, DA3, DA4, and DA5, which are contained within the first to fifth areas A1, A2, A3, A4, and A5, respectively. That is, the first area A1 can include the first display area DA1, the second area A2 can include the second display area DA2, the third area A3 can include the third display area DA3, the fourth area A4 can include the fourth display area DA4, and the fifth area A5 can include the fifth display area DA5.

[0133] The first to fifth regions A1, A2, A3, A4, and A5 can exist between the upper edge line TEL and the lower edge line BEL.

[0134] The first region A1 may be the region between the upper edge line TEL and the first boundary line BL12. The first boundary line BL12 may be the boundary between the first region A1 and the second region A2. The first region A1 may be the region that includes the pad region PA.

[0135] The second region A2 may be the region between the first boundary line BL12 and the second boundary line BL23. The second boundary line BL23 may be the boundary between the second region A2 and the third region A3.

[0136] The third region A3 may be the region between the second boundary line BL23 and the third boundary line BL34. The third boundary line BL34 may be the boundary between the third region A3 and the fourth region A4.

[0137] The fourth region A4 may be the region between the third boundary line BL34 and the fourth boundary line BL45. The fourth boundary line BL45 may be the boundary between the fourth region A4 and the fifth region A5.

[0138] The fifth region A5 may be the region between the fourth boundary line BL45 and the lower edge line BEL.

[0139] The third region A3 may include the third display region DA3, the first non-display region NDA1 on one side of the third display region DA3, and the second non-display region NDA2 on the other side of the third display region DA3. The third region A3 may include a waist area (WA) that is indented inward on one side.

[0140] At the second boundary line BL23 between the second region A2 and the third region A3, the width of the third region A3 may narrow as it approaches the center of the third region A3. Similarly, at the third boundary line BL34 between the fourth region A4 and the third region A3, the width of the third region A3 may narrow as it approaches the center of the third region A3.

[0141] One side of the third region A3 may include a waist area (WA) where the edge line of the substrate 111 is recessed inward. The other side of the third region A3 is opposite the waist area WA and may include a back area (BA) where the edge line of the substrate 111 is convex or flat.

[0142] The waist region WA may include a third display region DA3 and a first non-display region NDA1 outside of it (e.g., left outer), and the back region BA may include a third display region DA3 and a second non-display region NDA2 outside of it (e.g., right outer).

[0143] Referring to Figure 6, each of the N data lines can pass through all of the first to fifth regions A1, A2, A3, A4, and A5. As a result, each of the first to fifth regions A1, A2, A3, A4, and A5 can contain N data lines.

[0144] For example, in the first region A1, all N data lines can pass through the first display region DA1. In the fifth region A5, all N data lines can pass through the fifth display region DA5.

[0145] In one example, in the second region A2, all N data lines can pass through the second display region DA2. In another example, in the second region A2, some of the N data lines can pass through the second display region DA2, while others can pass through the hidden region NDA outside the second display region DA2 (for example, to the right).

[0146] In one example, in the fourth region A4, all N data lines can pass through the fourth display region DA4. In another example, in the fourth region A4, some of the N data lines can pass through the fourth display region DA4, while the other parts can pass through the non-display region NDA outside the fourth display region DA4 (for example, to the right).

[0147] For example, in the third region A3, some of the N data lines (e.g., M3 data lines) can pass through the third display region DA3, another portion (e.g., M1 data lines) can pass through the first non-display region NDA1 outside the third display region DA3 (e.g., left outer), and yet another portion (e.g., M2 data lines) can pass through the second non-display region NDA2 outside the third display region DA3 (e.g., right outer).

[0148] For example, N data lines may include M1 data lines passing through the first hidden area NDA1 within the third area A3, M2 data lines passing through the second hidden area NDA2 within the third area A3, and M3 data lines passing through the third visible area DA3 within the third area A3.

[0149] M3 data lines can pass only through the third display area DA3 within the third area A3, without passing through the first non-display area NDA1 and the second non-display area NDA2, which are included in the third area A3.

[0150] According to the display panel 110 of the embodiment of this disclosure, N is the total number of data lines arranged on the display panel 110 and may be a natural number of 3 or more. M1 is the total number of data lines passing through the first non-display area NDA1 in the third area A3 and may be a natural number of 1 or more. M2 is the total number of data lines passing through the second non-display area NDA2 in the third area A3 and may be a natural number of 1 or more. M3 is the total number of data lines passing through only the third display area DA3 among the first non-display area NDA1, the third display area DA3, and the second non-display area NDA2 included in the third area A3 and may be a natural number of 1 or more.

[0151] According to the display panel 110 in the embodiment of this disclosure, the sum of M1, M2, and M3 may correspond to N.

[0152] Due to the shape of the display device 100 according to the embodiment of this disclosure (for example, the shape of eyeglasses), the third region A3 has a narrower width (maximum width) than the first, second, fourth, and fifth regions A1, A2, A4, and A5, so that all N (N=M1+M2+M3) data lines cannot be placed in the third display region DA3 within the third region A3.

[0153] For example, depending on the shape of the display device 100 according to the embodiment of this disclosure (e.g., the shape of eyeglasses), out of N (N=M1+M2+M3) data lines, only M3 data lines can pass through the third display area DA3 within the third area A3, and (M1+M2) data lines cannot pass through the third display area DA3 within the third area A3.

[0154] In this case, if all (M1+M2) data lines that cannot pass through the third display area DA3 within the third area A3 pass through the first hidden area NDA1 within the third area A3, the size of the first hidden area NDA1 can only increase.

[0155] However, according to the display device 100 of the embodiment of this disclosure, a portion of the (M1+M2) data lines (M1 data lines) can pass through the first non-display area NDA1 in the third area A3, and the other portion (M2 data lines) can pass through the second non-display area NDA2 in the third area A3, thereby preventing the size of the first non-display area NDA1 from becoming excessively large.

[0156] The display panel 110 may further include multiple subpixels SP arranged in the display area DA. Figure 7 illustrates an example where five data lines DL1, DL2, DL3, DL4, and DL5 are arranged in the display panel 110, and of the five data lines DL1, DL2, DL3, DL4, and DL5, the first data line DL1 passes through the first non-display area NDA1 in the third area A3, the fifth data line DL5 passes through the second non-display area NDA2 in the third area A3, and the second to fourth data lines DL2, DL3, and DL4 pass through the third display area DA3 in the third area A3 (i.e., N=5, M1=1, M2=1, M3=3).

[0157] Multiple subpixels SP are arranged in the first display area DA1 within the first region A1 and connected to the first gate line GL1, consisting of N1 subpixels (e.g., SP1_1, SP1_2, SP1_3, SP1_4, SP1_5), in the second display area DA2 within the second region A2 and connected to the second gate line GL2, and in the third display area DA3 within the third region A3. It may include N3 subpixels connected to the third gate line GL3 (e.g., SP3_2, SP3_3, SP3_4), N4 subpixels located in the fourth display area DA4 within the fourth region A4 and connected to the fourth gate line GL4 (e.g., SP4_1, SP4_2, SP4_3, SP4_4), and N5 subpixels located in the fifth display area DA5 within the fifth region A5 and connected to the fifth gate line GL5 (e.g., SP5_1, SP5_2, SP5_3, SP5_4, SP5_5).

[0158] In the display panel 110 according to the embodiment of this disclosure, N3 may be the minimum value among N1, N2, N3, N4, and N5. N3 may be a natural number of 1 or more. As a result, the number of pixels in the third display area DA3 may be small.

[0159] According to the display panel 110 of the embodiment of this disclosure, N1 and N5 may each be the same as N (N1=N5=N). N2 and N4 may each be less than or equal to N (N2≦N, N4≦N). N3 may be less than or equal to N2 or N4 (N3≦N2, or N3≦N4).

[0160] According to the display panel 110 of the embodiment of this disclosure, N3 may be the same as M3, and (N1~N3) may be (M1+M2).

[0161] Referring to Figure 7, M1 data lines passing through the first hidden area NDA1 within the third area A3 may include the first data line DL1.

[0162] N1 subpixels may include a first subpixel SP1_1 connected to the first data line DL1. N2 subpixels may include a second subpixel SP2_1 located diagonally to the right (down-right diagonally) from the first subpixel SP1_1 and connected to the first data line DL1. N4 subpixels may include a fourth subpixel SP4_1 connected to the first data line DL1. N5 subpixels may include a fifth subpixel SP5_1 located diagonally to the left (down-left diagonally) from the fourth subpixel SP4_1 and connected to the first data line DL1.

[0163] Referring to Figures 6 and 7, the second region A2 may be a right-shifted region where the data transmission path is shifted away from the waist region WA (to the right in the example of Figures 6 and 7). The fourth region A4 may be a left-shifted region where the data transmission path is shifted towards the waist region WA (to the left in the example of Figures 6 and 7).

[0164] Referring to Figure 7, the first data line DL1 can be bent or curved in the second display area DA2 within the second area A2. The first data line DL1 can be bent or curved in the fourth display area DA4 within the fourth area A4. For example, in the third area A3, one edge of the substrate 111 is recessed inward, and the first data line DL1 may be bent or curved in one direction (e.g., to the right) in the second display area DA2 within the second area A2, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area DA4 within the fourth area A4.

[0165] The first data line DL1 can be positioned along the inwardly recessed edge of the substrate 111 as it passes through the first non-display area NDA1 within the third area A3.

[0166] The first subpixel SP1_1, the second subpixel SP2_1, the fourth subpixel SP4_1, and the fifth subpixel SP5_1 can all be connected to the first data line DL1. However, the second and fourth subpixels SP2_1 and SP4_1 located in the second and fourth display areas DA2 and DA4 may be located in different columns than the first and fifth subpixels SP1_1 and SP5_1 located in the first and fifth display areas DA1 and DA5.

[0167] The first subpixel SP1_1, the second subpixel SP2_1, the fourth subpixel SP4_1, and the fifth subpixel SP5_1 can all emit light of the same color. As mentioned above, since data signals are sequentially supplied to subpixels emitting light of the same color via the first data line DL1, data rendering, which requires adjusting data for each color, is not necessary. This improves data driving efficiency.

[0168] Referring to Figure 7, the M3 data lines passing through the third display area DA3 within the third area A3 can include the second to fourth data lines DL2, DL3, and DL4. Below, the arrangement structure and subpixel connection structure of the second to fourth data lines DL2, DL3, and DL4 will be described as representatively using the arrangement structure and subpixel connection structure of the second data line DL2.

[0169] N1 subpixels can include a sixth subpixel SP1_2 connected to the second data line DL2. N2 subpixels can include a seventh subpixel SP2_2 located diagonally to the right (down-right diagonally) from the sixth subpixel SP1_2 and connected to the second data line DL2. N3 subpixels can include an eighth subpixel SP3_2 located in the first direction from the seventh subpixel SP2_2 and connected to the second data line DL2. N4 subpixels can include a ninth subpixel SP4_2 located in the first direction from the eighth subpixel SP3_2 and connected to the second data line DL2. N5 subpixels can include a tenth subpixel SP5_2 located diagonally to the left (down-left diagonally) from the ninth subpixel SP4_2 and connected to the second data line DL2.

[0170] The second data line DL2 may be bent or curved in the second display area DA2 within the second area A2. The second data line DL2 may be bent or curved in the fourth display area DA4 within the fourth area A4. For example, in the third area A3, one edge of the substrate 111 is recessed inward, and the second data line DL2 may be bent or curved in one direction (e.g., to the right) in the second display area DA2 within the second area A2, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area DA4 within the fourth area A4.

[0171] The second data line DL2 can pass through the third display area DA3 within the third area A3 in the first direction.

[0172] The sixth subpixel SP1_2, the seventh subpixel SP2_2, the eighth subpixel SP3_2, the ninth subpixel SP4_2, and the tenth subpixel SP5_2 can all be connected to the second data line DL2. However, the seventh to ninth subpixels SP2_2, SP3_2, and SP4_2 located in the second to fourth display areas DA2, DA3, and DA4 may be located in different columns from the sixth and tenth subpixels SP1_2 and SP5_2 located in the first and fifth display areas DA1 and DA5.

[0173] The sixth subpixel SP1_2, the seventh subpixel SP2_2, the eighth subpixel SP3_2, the ninth subpixel SP4_2, and the tenth subpixel SP5_2 can all emit light of the same color. As mentioned above, since data signals are sequentially supplied to subpixels that emit light of the same color via the second data line DL2, data rendering, which requires adjusting data for each color, is not necessary. This improves data driving efficiency.

[0174] Referring to Figure 7, the M2 data lines passing through the second hidden area NDA2 within the third area A3 may include a fifth data line DL5.

[0175] The fifth data line DL5 may be bent or curved in the second display area DA2 within the second area A2, and may be bent or curved in the fourth display area DA4 within the fourth area A4. For example, in the third area A3, one edge of the substrate 111 is recessed inward, and the fifth data line DL5 may be bent or curved in one direction (e.g., to the right) in the second display area DA2 within the second area A2, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area DA4 within the fourth area A4.

[0176] N1 subpixels can include an eleventh subpixel SP1_5 connected to the fifth data line DL5. N5 subpixels can include a fifteenth subpixel SP5_5 connected to the fifth data line DL5.

[0177] The fifth data line DL5 can be positioned along the edge of the substrate 111 as it passes through the second non-display area NDA2 within the third area A3.

[0178] Both the 11th subpixel SP1_5 and the 15th subpixel SP5_5 can be connected to the 5th data line DL5.

[0179] Both the 11th subpixel SP1_5 and the 15th subpixel SP5_5 can emit light of the same color. Since data signals are sequentially supplied to the subpixels SP1_5 and SP5_5 that emit light of the same color via the 5th data line DL5, data rendering, which requires adjusting color-specific data, is not necessary. This improves data driving efficiency.

[0180] On the other hand, the first region A1 in Figures 6 and 7 may be included in the upper region TOP of Figure 1, the third region A3 in Figures 6 and 7 may be included in the middle region MID of Figure 1, and the fifth region A5 in Figures 6 and 7 may be included in the lower region BOT of Figure 1.

[0181] As an example, the second region A2 in Figures 6 and 7 may be included in the upper region TOP or the intermediate region MID of Figure 1. As another example, part of the second region A2 in Figures 6 and 7 may be included in the upper region TOP of Figure 1, while other parts may be included in the intermediate region MID of Figure 1.

[0182] For example, the fourth region A4 in Figures 6 and 7 may be included in the intermediate region MID or the lower region BOT of Figure 1. As another example, part of the fourth region A4 in Figures 6 and 7 may be included in the intermediate region MID of Figure 1, while other parts may be included in the lower region BOT of Figure 1.

[0183] The display device 100 according to the embodiments of this disclosure may be a glasses-type wearable device or a heterogeneous integrated display device. In this case, when a user wears the display device 100, one side of the third region A3 of the display device 100 (corresponding to the waist region WA) can be positioned in conjunction with the user's nose.

[0184] Figures 8 and 9 show the light-emitting regions EA1 to EA12 of the second display region DA2 and the light-emitting regions EA13 to EA24 of the fourth display region DA4 in the display panel 110 according to an embodiment of the present disclosure. Figure 2 will be referenced together with the above description.

[0185] Referring to Figure 8, in the second display area DA2 within the second area A2, each data line can be arranged in a bent or curved direction toward the lower right. Depending on the arrangement trajectory of such data lines, a data delivery path can be formed in the lower right direction within the second display area DA2 within the second area A2.

[0186] Referring to Figure 9, in the fourth display area DA4 within the fourth area A4, each data line can be arranged in a bent or curved direction toward the lower left. Depending on the arrangement trajectory of these data lines, a data delivery path can be formed in the lower left direction within the fourth display area DA4 within the fourth area A4.

[0187] The arrangement trajectory of the data lines in the second display area DA2 and the fourth display area DA4 described above can change the shape of the pixel electrode contained in each subpixel, and the connection position between the pixel electrode PE contained in each subpixel SP and the subpixel circuit SPC can also change.

[0188] Each of the multiple subpixels SP located in the multiple display area DA may include a light-emitting element ED and a subpixel circuit SPC. The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and the subpixel circuit SPC may be connected to the pixel electrode PE.

[0189] Multiple subpixels SP located in multiple display areas DA may include multiple first subpixels emitting a first color of light, multiple second subpixels emitting a second color of light, and multiple third subpixels emitting a third color of light.

[0190] Each of the multiple first subpixels can form an emission region EA_R from which a first color of light is emitted, each of the multiple second subpixels can form an emission region EA_G from which a second color of light is emitted, and each of the multiple third subpixels can form an emission region EA_B from which a third color of light is emitted.

[0191] Each of the plurality of first subpixels may include a first light-emitting element including a first pixel electrode and a first subpixel circuit connected to the first light-emitting element. Each of the plurality of second subpixels may include a second light-emitting element including a second pixel electrode and a second subpixel circuit connected to the second light-emitting element.

[0192] Referring to Figure 8, the second display area DA2 may include light-emitting regions EA3, EA6, EA8, and EA11 that emit the first color of light, light-emitting regions EA1, EA4, EA9, and EA12 that emit the second color of light, and light-emitting regions EA2, EA5, EA7, and EA10 that emit the third color of light.

[0193] Referring to Figure 8, in the second display area DA2, each of the plurality of first subpixels may include a first light-emitting element including first pixel electrodes PE3, PE6, PE8, and PE11, and a first subpixel circuit connected to the first light-emitting element. Each of the plurality of second subpixels may include a second light-emitting element including second pixel electrodes PE1, PE4, PE9, and PE12, and a second subpixel circuit connected to the second light-emitting element. Each of the plurality of third subpixels may include a third light-emitting element including third pixel electrodes PE2, PE5, PE7, and PE10, and a third subpixel circuit connected to the third light-emitting element.

[0194] Referring to Figure 9, the fourth display area DA4 may include light-emitting regions EA15, EA18, EA20, and EA23 that emit the first color of light, light-emitting regions EA13, EA16, EA21, and EA24 that emit the second color of light, and light-emitting regions EA14, EA17, EA19, and EA22 that emit the third color of light.

[0195] Referring to Figure 9, in the fourth display area DA4, each of the plurality of first subpixels may include a first light-emitting element including first pixel electrodes PE15, PE18, PE20, PE23 and a first subpixel circuit connected to the first light-emitting element. Each of the plurality of second subpixels may include a second light-emitting element including second pixel electrodes PE13, PE16, PE21, PE24 and a second subpixel circuit connected to the second light-emitting element. Each of the plurality of third subpixels may include a third light-emitting element including third pixel electrodes PE14, PE17, PE19, PE22 and a third subpixel circuit connected to the third light-emitting element.

[0196] Referring to Figures 8 and 9, in each of the multiple first subpixels from which a first color of light is emitted, the first pixel electrodes PE3, PE6, PE8, PE11; PE15, PE18, PE20, PE23 of the first light-emitting element may include first connection portions CNT3, CNT6, CNT8, CNT11; CNT15, CNT18, CNT20, CNT23, which are protrusions connected to the first subpixel circuit via a contact hole CTH.

[0197] In each of the multiple second subpixels from which a second color of light is emitted, the second pixel electrodes PE1, PE4, PE9, PE12; PE13, PE16, PE21, PE24 of the second light-emitting element may include second connectors CNT1, CNT4, CNT9, CNT12; CNT13, CNT16, CNT21, CNT24, which are protrusions connected to the second subpixel circuit via a contact hole CTH.

[0198] In each of the multiple third subpixels from which a third color of light is emitted, the third pixel electrodes PE2, PE5, PE7, PE10; PE14, PE17, PE19, PE22 of the third light-emitting element may include third connectors CNT2, CNT5, CNT7, CNT10; CNT14, CNT17, CNT19, CNT22, which are protrusions connected to the third subpixel circuit via a contact hole CTH.

[0199] Referring to Figures 8 and 9, in the second display region DA2 and the fourth display region DA4 of the first to fifth display regions DA1, DA2, DA3, DA4, DA5, at least some of the multiple first connection parts CNT3, CNT6, CNT8, CNT11; CNT15, CNT18, CNT20, CNT23 included in the multiple first subpixels from which the first color of light is emitted may differ from the rest in at least one of the size, shape, and position, and may be included in the multiple second subpixels from which the second color of light is emitted. At least some of the multiple second connection parts CNT1, CNT4, CNT9, CNT12; CNT13, CNT16, CNT21, CNT24 that are present may differ from the rest in at least one of size, shape, and position, and at least some of the multiple third connection parts CNT2, CNT5, CNT7, CNT10; CNT14, CNT17, CNT19, CNT22 that are present in the multiple third subpixels from which third color light is emitted may differ from the rest in at least one of size, shape, and position.

[0200] Figures 10 and 11 show the wiring arrangement structure of the second display area DA2 and the wiring arrangement structure of the fourth display area DA4 in the display panel 110 according to an embodiment of the present disclosure.

[0201] Referring to Figure 10, in the second display area DA2 within the second region A2, each data line DL1, DL2, and DL3 can be arranged in a bent or curved direction toward the lower right. Depending on the arrangement trajectory of these data lines DL1, DL2, and DL3, a data transmission path (shown as a dotted line) can be formed in the lower right direction within the second display area DA2 within the second region A2.

[0202] Referring to Figure 11, in the fourth display area DA4 within the fourth area A4, each data line DL1, DL2, and DL3 can be arranged in a bent or curved direction toward the lower left. Depending on the arrangement trajectory of these data lines DL1, DL2, and DL3, a data transmission path (shown as a dotted line) can be formed in the lower left direction within the fourth display area DA4 within the fourth area A4.

[0203] Referring to Figure 10, among the N data lines, the first data line DL1 may include a first line part DL1a located in the second region A2 and extending in a first direction, and a second line part DL1b located in the second region A2, electrically connected to the first line part DL1a, and extending from the first line part DL1a in a second direction (e.g., to the right lateral direction).

[0204] Referring to Figure 10, the first data line DL1 may further include a third line part DL1c located in the second region A2, electrically connected to the second line part DL1b, and extending in the first direction from the second line part DL1b.

[0205] Referring to Figure 10, the first data line DL1 may further include a fourth line part DL1d located in the second region A2 and electrically connected to the third line part DL1c, extending from the third line part DL1c in a second direction (e.g., the right lateral direction).

[0206] Referring to Figure 11, the first data line DL1 may further include a fifth line part DL1e located in the fourth region A4 and extending in a first direction (e.g., longitudinally), and a sixth line part DL1f located in the fourth region A4, electrically connected to the fifth line part DL1e, and extending from the fifth line part DL1e in a second direction (e.g., left transversely). Here, the fifth line part DL1e may be electrically connected to the fourth line part DL1d.

[0207] Referring to Figure 11, the first data line DL1 is located in the fourth region A4 and is electrically connected to the sixth line part DL1f, and may further include a seventh line part DL1g extending in the first direction from the sixth line part DL1f.

[0208] Referring to Figure 11, the first data line DL1 is located in the fourth region A4 and is electrically connected to the seventh line part DL1g, and may further include an eighth line part DL1h extending in the first direction from the seventh line part DL1g.

[0209] Referring to Figures 10 and 11, the first, third, fifth, and seventh line parts DL1a, DL1c, DL1e, and DL1g of the first data line DL1 are first-direction wirings extending in the first direction (vertical direction), while the second, fourth, sixth, and eighth line parts DL1b, DL1d, DL1f, and DL1h of the first data line DL1 are second-direction wirings extending in the second direction (rightward direction).

[0210] For example, the first, third, fifth, and seventh line parts DL1a, DL1c, DL1e, and DL1g of the first data line DL1 are wiring in the first direction and can be located within the first metal layer. The second, fourth, sixth, and eighth line parts DL1b, DL1d, DL1f, and DL1h of the first data line DL1 are wiring in the second direction and can be located within a second metal layer different from the first metal layer.

[0211] Referring to Figure 10, among the N data lines, the second data line DL2 may include a first line part DL2a located in the second region A2 and extending in a first direction, and a second line part DL2b located in the second region A2, electrically connected to the first line part DL2a, and extending from the first line part DL2a in a second direction (e.g., to the right lateral direction).

[0212] Referring to Figure 10, the second data line DL2 may further include a third line part DL2c located in the second region A2, electrically connected to the second line part DL2b, and extending in the first direction from the second line part DL2b.

[0213] Referring to Figure 10, the second data line DL2 may further include a fourth line part DL2d located in the second region A2, electrically connected to the third line part DL2c, and extending from the third line part DL2c in a second direction (e.g., the right lateral direction).

[0214] Referring to Figure 11, the second data line DL2 may further include a fifth line part DL2e located in the fourth region A4 and extending in a first direction (e.g., longitudinal), and a sixth line part DL2f located in the fourth region A4, electrically connected to the fifth line part DL2e, and extending from the fifth line part DL2e in a second direction (e.g., left transverse). Here, the fifth line part DL2e may be electrically connected to the fourth line part DL2d.

[0215] Referring to Figure 11, the second data line DL2 is located in the fourth region A4 and is electrically connected to the sixth line part DL2f, and may further include a seventh line part DL2g extending in the first direction from the sixth line part DL2f.

[0216] Referring to Figure 11, the second data line DL2 is located in the fourth region A4 and is electrically connected to the seventh line part DL2g, and may further include an eighth line part DL2h extending in the first direction from the seventh line part DL2g.

[0217] Referring to Figures 10 and 11, the first, third, fifth, and seventh line parts DL2a, DL2c, DL2e, and DL2g of the second data line DL2 are first-direction wirings extending in the first direction (vertical direction), while the second, fourth, sixth, and eighth line parts DL2b, DL2d, DL2f, and DL2h of the second data line DL2 are second-direction wirings extending in the second direction (rightward direction).

[0218] For example, the first, third, fifth, and seventh line parts DL2a, DL2c, DL2e, and DL2g of the second data line DL2 are wiring in the first direction and can be located within the first metal layer. The second, fourth, sixth, and eighth line parts DL2b, DL2d, DL2f, and DL2h of the second data line DL2 are wiring in the second direction and can be located within a second metal layer different from the first metal layer.

[0219] Referring to Figure 10, among the N data lines, the third data line DL3 may include a first line part DL3a located in the second region A2 and extending in a first direction, and a second line part DL3b located in the second region A2, electrically connected to the first line part DL3a, and extending from the first line part DL3a in a second direction (e.g., the right lateral direction). Referring to Figure 11, the third data line DL3 may further include a fifth line part DL3e located in the fourth region A4 and extending in a first direction (e.g., the vertical direction), and a sixth line part DL3f located in the fourth region A4, electrically connected to the fifth line part DL3e, and extending from the fifth line part DL3e in a second direction (e.g., the left lateral direction). Here, the fifth line part DL3e may be electrically connected to the second line part DL3b.

[0220] Referring to Figures 10 and 11, the first and fifth line parts DL3a and DL3e of the third data line DL3 are first-direction wirings extending in the first direction (vertical direction), and the second and sixth line parts DL3b and DL3f of the third data line DL3 are second-direction wirings extending in the second direction (rightward direction).

[0221] For example, the first and fifth line parts DL3a and DL3e of the third data line DL3 are wiring in the first direction and can be located within the first metal layer. The second and sixth line parts DL3b and DL3f of the third data line DL3 are wiring in the second direction and can be located within a second metal layer different from the first metal layer.

[0222] Referring to Figures 10 and 11, the display panel 110 according to embodiments of the present disclosure may further include a plurality of power supply wirings PL arranged within a first metal layer. For example, the plurality of power supply wirings PL may include a drive voltage wiring VDDL, a base voltage wiring VSSL, a first power supply wiring PL1, and a second power supply wiring PL2, etc. Here, the drive voltage wiring VDDL may also be called a high-potential voltage wiring or a first common voltage wiring, and the base voltage wiring VSSL may also be called a low-potential voltage wiring or a second common voltage wiring. The type of each of the first power supply wiring PL1 and the second power supply wiring PL2 may vary depending on the structure of the subpixel SP. For example, each of the first power supply wiring PL1 and the second power supply wiring PL2 may be an initialization voltage wiring for transmitting an initialization voltage to any node in the subpixel SP, or a reset voltage wiring for transmitting a reset voltage to a pixel electrode PE in the subpixel SP.

[0223] At least one of the multiple power supply lines PL is positioned alongside the line part corresponding to the first direction of data lines DL1, DL2, and DL3, and can intersect and overlap with the line part corresponding to the second direction of data lines DL1, DL2, and DL3.

[0224] At least one power supply cable may have a wider wire width than the first-direction wiring of data lines DL1, DL2, and DL3.

[0225] For example, of the first metal layer on which wiring in the first direction is arranged and the second metal layer on which wiring in the second direction is arranged, one may be a source-drain metal layer on which the source electrode or drain electrode of a transistor in the display area DA is arranged, and the other may be a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting a storage capacitor in the display area DA is arranged.

[0226] In this case, as an example, the first metal layer on which the wiring in the first direction is arranged may be a source-drain metal layer on which the source electrode or drain electrode of a transistor in the display area DA is arranged, and the second metal layer on which the wiring in the second direction is arranged may be a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting a storage capacitor in the display area DA is arranged. As another example, the first metal layer on which the wiring in the first direction is arranged may be a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting a storage capacitor in the display area DA is arranged, and the second metal layer on which the wiring in the second direction is arranged may be a source-drain metal layer on which the source electrode or drain electrode of a transistor in the display area DA is arranged.

[0227] As another example, of the first metal layer on which wiring in the first direction is arranged and the second metal layer on which wiring in the second direction is arranged, one may be a source-drain metal layer on which the source electrode or drain electrode of the transistor in the display region DA is arranged, and the other may be a gate metal layer on which the gate electrode of the transistor in the display region DA is arranged.

[0228] In this case, as an example, the first metal layer on which the wiring in the first direction is located may be a source-drain metal layer on which the source electrode or drain electrode of the transistor in the display area DA is located, and the second metal layer on which the wiring in the second direction is located may be a gate metal layer on which the gate electrode of the transistor in the display area DA is located. As another example, the first metal layer on which the wiring in the first direction is located may be a gate metal layer on which the gate electrode of the transistor in the display area DA is located, and the second metal layer on which the wiring in the second direction is located may be a source-drain metal layer on which the source electrode or drain electrode of the transistor in the display area DA is located.

[0229] Figures 12 and 13 are cross-sectional views of the second display area DA2 and the fourth display area DA4 in the display panel 110 according to an embodiment of this disclosure. However, the laminated structure in the cross-sectional views of Figures 12 and 13 is the same as the laminated structure in the cross-sectional view of Figure 5. Therefore, redundant explanations are omitted.

[0230] Referring to Figure 12, according to the data line arrangement structure of the embodiment of this disclosure, in the second display area DA2 within the second area A2, one first data line DL1 can be composed of two metal layers ML1 and ML2.

[0231] Referring to Figure 13, according to the data line arrangement structure of the embodiment of this disclosure, in the fourth display area DA4 within the fourth area A4, one first data line DL1 can also be composed of two metal layers. Here, the two metal layers may include a first metal layer ML1 and a second metal layer ML2.

[0232] According to the data line arrangement structure of the embodiments of this disclosure, in the first display area DA1 within the first area A1, the third display area DA3 within the third area A3, and the fifth display area DA5 within the fifth area A5, one first data line DL1 can be composed of one metal layer. Here, the one metal layer may be a first metal layer ML1 or a second metal layer ML2.

[0233] Referring to Figure 12, in the second display area DA2 within the second area A2, the first data line DL1 may include a first line part DL1a, a second line part DL1b, a third line part DL1c, and a fourth line part DL1d.

[0234] The first line part DL1a and the third line part DL1c of the first data line DL1 are first-direction wirings extending in a first direction (e.g., longitudinal direction), and the second line part DL1b and the fourth line part DL1d of the first data line DL1 may be second-direction wirings extending in a second direction (e.g., right-lateral direction).

[0235] Wiring in the first direction can be placed within the first metal layer ML1. Wiring in the second direction can be placed within the second metal layer ML2. For example, the first metal layer ML1 may be a source-drain metal layer SDML on which the source or drain electrode of a transistor in the display region DA is placed, and the second metal layer ML2 may be a capacitor electrode metal layer TML on which one of two or more capacitor electrodes constituting a storage capacitor in the display region DA is placed.

[0236] For example, the source-drain metal layer (SDML) may be a metal layer placed between the interlayer insulating layer 540 and the planarization layer 550. The capacitor electrode metal layer (TML) may be a metal layer placed between the first interlayer insulating layer 541 and the second interlayer insulating layer 542.

[0237] Referring to Figure 13, in the fourth display area DA4 within the fourth area A4, the first data line DL1 may include a fifth line part DL1e, a sixth line part DL1f, a seventh line part DL1g, and an eighth line part DL1h.

[0238] The fifth line part DL1e and the seventh line part DL1g of the first data line DL1 are first-direction wirings extending in a first direction (e.g., longitudinal direction), and the sixth line part DL1f and the eighth line part DL1h of the first data line DL1 may be second-direction wirings extending in a second direction (e.g., right-lateral direction).

[0239] Wiring in the first direction can be placed within the first metal layer ML1. Wiring in the second direction can be placed within the second metal layer ML2. For example, the first metal layer ML1 may be a source-drain metal layer SDML on which the source or drain electrode of a transistor in the display region DA is placed, and the second metal layer ML2 may be a capacitor electrode metal layer TML on which one of two or more capacitor electrodes constituting a storage capacitor in the display region DA is placed.

[0240] Referring to Figures 12 and 13, multiple power supply lines PL can be arranged within the first metal layer ML1. For example, the multiple power supply lines PL may include a drive voltage line VDDL, a base voltage line VSSL, a first power supply line PL1, and a second power supply line PL2. Here, the drive voltage line VDDL may also be called a high-potential voltage line or a first common voltage line, and the base voltage line VSSL may also be called a low-potential voltage line or a second common voltage line. The type of the first power supply line PL1 and the second power supply line PL2 may vary depending on the structure of the subpixel SP. For example, the first power supply line PL1 and the second power supply line PL2 may each be an initialization voltage line for transmitting an initialization voltage to any node in the subpixel SP, or a reset voltage line for transmitting a reset voltage to a pixel electrode PE in the subpixel SP.

[0241] Referring to Figures 12 and 13, multiple power supply lines PL can be arranged within the first metal layer ML1 together with line parts DL1a, DL1c, DL1e, DL1g corresponding to the wiring in the first direction of the first data line DL1.

[0242] At least one of the multiple power supply lines PL can intersect and superimpose line parts DL1b, DL1d, DL1f, DL1h corresponding to the wiring in the second direction of the first data line DL1.

[0243] The display panel 110 may further include a second metal pattern located within a second metal layer ML2, along with line parts DL1b, DL1d, DL1f, and DL1h corresponding to the wiring of the first data line DL1 in a second direction. The second metal pattern is a pattern extending in a second direction and may be located within a capacitor electrode metal layer TML.

[0244] The second metal pattern can be superimposed on the line parts DL1a, DL1c, DL1e, and DL1g, which correspond to the routing of the first data line DL1 in the first direction.

[0245] The display device according to the embodiment of this disclosure can be described as follows.

[0246] A display device according to an embodiment of the present disclosure may include a substrate including a display area capable of displaying video and a non-display area outside the display area, and N data lines arranged on the substrate.

[0247] The substrate may include at least three regions located sequentially in a first direction. The display region may include at least three regions, each contained within the at least three regions.

[0248] The intermediate region, among at least three regions, may include an intermediate display region, a first non-display region on one side of the intermediate display region, and a second non-display region on the other side of the intermediate display region.

[0249] The N data lines may include M1 data lines passing through the first hidden area, M2 data lines passing through the second hidden area, and M3 data lines passing through the intermediate display area.

[0250] N is a natural number greater than or equal to 3, M1, M2, and M3 are each natural numbers greater than or equal to 1, and the sum of M1, M2, and M3 can correspond to N.

[0251] Of the three regions, the width of the intermediate region may narrow as you move closer to it from the first or second region.

[0252] Of at least three regions, the width of the intermediate region can narrow as you approach it from the fifth or fourth region.

[0253] In the intermediate region, one edge of the substrate may be concave inward or curved.

[0254] The substrate may include first to fifth regions located sequentially in a first direction. The display region may include first to fifth display regions, each contained within the first to fifth regions. The third region is an intermediate region, and the third display region may be an intermediate display region.

[0255] Of the N data lines, the first data line may be bent or curved in one direction in the second display area, and may be bent or curved in the other direction in the fourth display area.

[0256] The display device according to the embodiments of this disclosure is a glasses-type wearable device or a heterogeneous integrated display device, wherein one side of the intermediate region may correspond to the position of the user's nose.

[0257] A display device according to an embodiment of the present disclosure may include a substrate including a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate. The substrate may include first to fifth regions sequentially located in a first direction. The display area may include first to fifth display areas, each contained within the first to fifth regions.

[0258] The third region may include a third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region.

[0259] N data lines may include M1 data lines passing through a first hidden area in the third region, M2 data lines passing through a second hidden area in the third region, and M3 data lines passing through a third visible area in the third region. Here, N is a natural number greater than or equal to 3, and M1, M2, and M3 are each natural numbers greater than or equal to 1, and the sum of M1, M2, and M3 may correspond to N.

[0260] At the boundary between the second and third regions, the closer you get to the center of the third region, the narrower the width of the third region may become, and at the boundary between the fourth and third regions, the closer you get to the center of the third region, the narrower the width of the third region may become.

[0261] One side of the third region may be concave inward.

[0262] The subpixels arranged in the display area may include N1 subpixels arranged in a first display area within a first area and connected to a first gate line, N2 subpixels arranged in a second display area within a second area and connected to a second gate line, N3 subpixels arranged in a third display area within a third area and connected to a third gate line, N4 subpixels arranged in a fourth display area within a fourth area and connected to a fourth gate line, and N5 subpixels arranged in a fifth display area within a fifth area and connected to a fifth gate line.

[0263] Here, among N1, N2, N3, N4, and N5, N3 can be the smallest value. N3 can be a natural number greater than or equal to 1. N1 and N5 are each the same as N, and N2 and N4 can each be less than or equal to N. N3 can be less than or equal to N2 or N4.

[0264] M1 data lines can include a first data line. N1 subpixels can include a first subpixel connected to the first data line. N2 subpixels can include a second subpixel located diagonally to the right of the first subpixel and connected to the first data line. N4 subpixels can include a fourth subpixel connected to the first data line. N5 subpixels can include a fifth subpixel located diagonally to the left of the fourth subpixel and connected to the first data line.

[0265] The first data line is bent or curved in the second region, the first data line is bent or curved in the fourth region, and the first data line can be positioned along an inwardly recessed edge of the substrate as it passes through the first non-display region within the third region.

[0266] The first subpixel, the second subpixel, the fourth subpixel, and the fifth subpixel can all emit light of the same color.

[0267] M3 data lines can include the second to fourth data lines. N1 subpixels can include the sixth subpixel connected to the second data line. N2 subpixels can include the seventh subpixel located diagonally to the right of the sixth subpixel and connected to the second data line. N3 subpixels can include the eighth subpixel located in the first direction from the seventh subpixel and connected to the second data line. N4 subpixels can include the ninth subpixel located in the first direction from the eighth subpixel and connected to the second data line. N5 subpixels can include the tenth subpixel located diagonally to the left of the ninth subpixel and connected to the second data line.

[0268] The second data line is bent or curved in the second region, the second data line is bent or curved in the fourth region, and the second data line can pass through the third display region within the third region in the first direction.

[0269] The sixth, seventh, eighth, ninth, and tenth subpixels can all emit light of the same color.

[0270] M2 data lines can include a fifth data line. N1 subpixels can include an eleventh subpixel connected to the fifth data line. N5 subpixels can include a fifteenth subpixel connected to the fifth data line.

[0271] The fifth data line can be positioned along the edge of the substrate as it passes through the second non-display area within the third area.

[0272] Both the 11th subpixel and the 15th subpixel can emit light of the same color.

[0273] Multiple subpixels located in multiple display areas may include multiple first subpixels emitting a first color of light, multiple second subpixels emitting a second color of light, and multiple third subpixels emitting a third color of light.

[0274] Each of the plurality of first subpixels may include a first light-emitting element including a first pixel electrode and a first subpixel circuit connected to the first light-emitting element. Each of the plurality of second subpixels may include a second light-emitting element including a second pixel electrode and a second subpixel circuit connected to the second light-emitting element. Each of the plurality of third subpixels may include a third light-emitting element including a third pixel electrode and a third subpixel circuit connected to the third light-emitting element.

[0275] In each of the plurality of first subpixels, the first pixel electrode of the first light-emitting element may include a first connector for connecting to the first subpixel circuit. In each of the plurality of second subpixels, the second pixel electrode of the second light-emitting element may include a second connector for connecting to the second subpixel circuit. In each of the plurality of third subpixels, the third pixel electrode of the third light-emitting element may include a third connector for connecting to the third subpixel circuit.

[0276] In the second and fourth display regions of the first to fifth display regions, at least a portion of the plurality of first connection portions included in the plurality of first subpixels from which the first color of light is emitted may differ from the rest in at least one of size, shape, and position; at least a portion of the plurality of second connection portions included in the plurality of second subpixels from which the second color of light is emitted may differ from the rest in at least one of size, shape, and position; and at least a portion of the plurality of third connection portions included in the plurality of third subpixels from which the third color of light is emitted may differ from the rest in at least one of size, shape, and position.

[0277] Of the N data lines, the first data line may include a first-direction wiring located in a second region and extending in a first direction, and a second-direction wiring located in the second region, electrically connected to the first-direction wiring, and extending from the first-direction line in a second direction different from the first direction.

[0278] The wiring in the first direction may be arranged within a first metal layer, and the wiring in the second direction may be arranged within a second metal layer different from the first metal layer.

[0279] Of the first and second metal layers, one may be a source-drain metal layer on which the source or drain electrode of a transistor in the display area is placed, and the other may be a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting a storage capacitor in the display area is placed.

[0280] The display device according to the embodiments of the present disclosure may further include a plurality of power wirings arranged within a first metal layer. At least one of the plurality of power wirings may be arranged alongside the wiring in a first direction and may intersect and overlap with the wiring in a second direction.

[0281] At least one power supply cable may have a wider wire width than the first-direction cable.

[0282] Among the N data lines, the first data line can include a wiring in the first direction that is located in the fourth region and extends in the first direction, and a wiring in the second direction that is located in the fourth region, electrically connected to the wiring in the first direction, and extends in a second direction different from the first direction. Here, the wiring in the first direction may be disposed in the first metal layer, and the wiring in the second direction may be disposed in a second metal layer different from the first metal layer.

[0283] The display device according to an embodiment of the present disclosure can be a wearable device that a user can wear on the face.

[0284] Of the two surfaces of the display device according to an embodiment of the present disclosure, the surface on which an image is displayed can correspond to the surface on the opposite side of the surface close to the user wearing the display device.

[0285] The display device according to an embodiment of the present disclosure can include a substrate including a display area capable of displaying an image and a non-display area outside the display area, N data lines disposed on the substrate, and a plurality of sub-pixels disposed in the display area. The substrate can include first to fifth regions sequentially positioned in the first direction. The display area can include first to fifth display areas respectively included in the first to fifth regions.

[0286] <​​

[0287] The third region can include a third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region.

[0288] The N data lines can include M1 data lines passing through the first non-display region within the third region, M2 data lines passing through the second non-display region within the third region, and M3 data lines passing through the third display region within the third region. Here, N can be a natural number of 3 or more. M1, M2, and M3 can each be a natural number of 1 or more. The total value of M1, M2, and M3 can correspond to N.

[0289] Among the N data lines, the first data line can include a first-direction wiring located in the second region and extending in the first direction, and a second-direction wiring located in the second region and electrically connected to the first-direction wiring and extending in a second direction different from the first direction.

[0290] The first-direction wiring can be disposed within the first metal layer. The second-direction wiring can be disposed within a second metal layer different from the first metal layer.

[0291] A display device according to an embodiment of the present disclosure can include a substrate including a display region capable of video display and a non-display region outside the display region, and N data lines disposed on the substrate. The substrate includes first to fifth regions sequentially positioned in the first direction, and the display region can include first to fifth display regions respectively included in the first to fifth regions. The third region can include a third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region.

[0292] In the third region, an edge on one side of the substrate (for example, the left edge) may be recessed inward.

[0293] Of the N data lines, the first data line may be bent or curved in one direction (e.g., to the right) in the second display area, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area.

[0294] The first data line can pass through the first hidden area within the third area.

[0295] The display includes the second to fourth data lines among the N data lines, wherein the second data line may be bent or curved in one direction (e.g., to the right) in the second display area, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area.

[0296] The second data line can pass through the third hidden area within the third area.

[0297] Of the N data lines, the fifth data line may be bent or curved in one direction (e.g., to the right) in the second display area, and may be bent or curved in the other direction (e.g., to the left) in the fourth display area.

[0298] The fifth data line can pass through the second hidden area within the third area.

[0299] According to the embodiments of the present disclosure described above, it is possible to provide a display device having a data line arrangement structure that enables bezel reduction.

[0300] According to embodiments of this disclosure, a display device can be provided that has a data line arrangement structure that does not require data rendering, thereby improving data driving efficiency. This enables low-power operation.

[0301] According to embodiments of this disclosure, a display device having a data line arrangement structure that enables bezel reduction can be provided by utilizing the metal layer structure of the display panel. This makes process optimization possible.

[0302] According to an embodiment of the present disclosure, it is possible to provide a display device of a heterogeneous integrated display type having a data line arrangement structure capable of reducing bezels.

[0303] According to an embodiment of the present disclosure, it is possible to provide a display device as a wearable device having a data line arrangement structure capable of reducing bezels.

[0304] The above description merely exemplarily explains the technical idea of the present disclosure. Those having ordinary knowledge in the technical field to which the present disclosure pertains can make various modifications and variations without departing from the essential characteristics of the present disclosure. Also, the embodiments shown in the present disclosure do not limit the technical idea of the present disclosure but are for explanatory purposes. Therefore, the scope of the technical idea of the present disclosure is not limited by these embodiments.

Description of Reference Numerals

[0305] 100: Display device 110: Display panel 111: Substrate 120: Driving circuit 130: Flexible printed circuit board 140: Printed circuit board WA: Waist region BA: Back region A1: First region A2: Second region A3: Third region A4: Fourth region <00—0970>A5: Fifth region DA1: First display region DA2: Second display region DA3: Third display region DA4: Fourth display region DA5: Fifth display region

Claims

1. A substrate including a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate Includes, The substrate includes at least three regions sequentially located in a first direction, and the display region includes at least three regions each contained within the at least three regions. The intermediate region among the at least three regions includes the intermediate display region, the first non-display region on one side of the intermediate display region, and the second non-display region on the other side of the intermediate display region. The N data lines include M1 data lines passing through the first non-display area, M2 data lines passing through the second non-display area, and M3 data lines passing through the intermediate display area. A display device in which N is a natural number greater than or equal to 3, M1, M2, and M3 are each natural numbers greater than or equal to 1, and the sum of M1, M2, and M3 corresponds to N.

2. Of the three regions mentioned above, the width of the intermediate region narrows as you move from the first or second region towards the intermediate region. The display device according to claim 1, wherein, of the at least three regions, the width of the intermediate region narrows as it approaches the fifth or fourth region.

3. The display device according to claim 1, wherein in the intermediate region, one edge of the substrate is recessed inward or curved.

4. The substrate includes first, second, third, fourth, and fifth regions located sequentially in the first direction, The aforementioned display area includes the first, second, third, fourth, and fifth display areas which are respectively contained within the first, second, third, fourth, and fifth areas. The third region is the intermediate region, and the third display region is the intermediate display region, The display device according to claim 1, wherein, of the N data lines, the first data line is bent or curved in one direction in the second display area, or bent or curved in the other direction in the fourth display area.

5. The display area further includes a plurality of subpixels arranged in the aforementioned display area, The aforementioned subpixels are N1 subpixels arranged in the first display area within the first region and connected to the first gate line; N2 subpixels arranged in the second display area within the second region and connected to the second gate line, N3 subpixels arranged in the third display area within the third region and connected to the third gate line, N4 subpixels arranged in the fourth display area within the fourth region and connected to the fourth gate line, and It includes N5 subpixels arranged in the fifth display area within the fifth region and connected to the fifth gate line, Of the aforementioned N1, N2, N3, N4, and N5, N3 is the smallest value, and N3 is a natural number greater than or equal to 1. The aforementioned N1 and N5 are the same as the aforementioned N, The display device according to claim 4, wherein N2 and N4 are each less than or equal to N, and N3 is less than or equal to N2 or N4.

6. The M1 data lines include a first data line, The N1 subpixels include a first subpixel connected to the first data line, The N2 subpixels include a second subpixel located diagonally to the right of the first subpixel and connected to the first data line. The N4 subpixels include a fourth subpixel connected to the first data line. The N5 subpixels include a fifth subpixel located diagonally to the left from the fourth subpixel and connected to the first data line. The first data line is bent or curved in the second region. The first data line is bent or curved in the fourth region. The display device according to claim 5, wherein the first data line is positioned along an inwardly recessed or curved edge of the substrate when passing through the first non-display area within the third area.

7. The display device according to claim 6, wherein the first subpixel, the second subpixel, the fourth subpixel, and the fifth subpixel all emit light of the same color.

8. The aforementioned M3 data lines include the second to fourth data lines, The N1 subpixels include a sixth subpixel connected to the second data line, The N2 subpixels include a seventh subpixel located diagonally to the right of the sixth subpixel and connected to the second data line. The N3 subpixels include an eighth subpixel located in the first direction from the seventh subpixel and connected to the second data line. The N4 subpixels include a ninth subpixel located in the first direction from the eighth subpixel and connected to the second data line, The N5 subpixels include a 10th subpixel located diagonally to the left from the 9th subpixel and connected to the second data line. The second data line is bent or curved in the second region. The second data line is bent or curved in the fourth region. The display device according to claim 5, wherein the second data line passes through the third display area within the third area in the first direction.

9. The display device according to claim 8, wherein the sixth subpixel, the seventh subpixel, the eighth subpixel, the ninth subpixel, and the tenth subpixel all emit light of the same color.

10. The aforementioned M2 data lines include a fifth data line, The N1 subpixels include an eleventh subpixel connected to the fifth data line, The N5 subpixels include a 15th subpixel connected to the 5th data line. The display device according to claim 5, wherein the fifth data line is arranged along the edge of the substrate as it passes through the second non-display area within the third area.

11. The display device according to claim 10, wherein both the 11th subpixel and the 15th subpixel emit light of the same color.

12. Further including a plurality of subpixels located in a plurality of the display areas, The aforementioned subpixels are Multiple first subpixels from which the first color of light is emitted, Multiple second subpixels from which a second color of light is emitted, and It includes multiple third subpixels from which a third color of light is emitted, Each of the plurality of first subpixels includes a first light-emitting element including a first pixel electrode and a first subpixel circuit connected to the first light-emitting element. Each of the plurality of second subpixels includes a second light-emitting element including a second pixel electrode and a second subpixel circuit connected to the second light-emitting element. Each of the plurality of third subpixels includes a third light-emitting element including a third pixel electrode and a third subpixel circuit connected to the third light-emitting element. In each of the plurality of first subpixels, the first pixel electrode of the first light-emitting element includes a first connection portion for connecting to the first subpixel circuit. In each of the plurality of second subpixels, the second pixel electrode of the second light-emitting element includes a second connection portion for connecting to the second subpixel circuit. In each of the plurality of third subpixels, the third pixel electrode of the third light-emitting element includes a third connection portion for connecting to the third subpixel circuit. Of the first, second, third, fourth, and fifth display areas, in the second and fourth display areas, At least some of the plurality of first connection portions included in the plurality of first subpixels from which the first color of light is emitted differ from the remaining first connection portions in at least one of the following ways: size, shape, and position. At least some of the plurality of second connection portions included in the plurality of second subpixels from which the second color of light is emitted differ from the remaining second connection portions in at least one of the following ways: size, shape, and position. The display device according to claim 4, wherein at least some of the plurality of third connection portions included in the plurality of third subpixels from which the third color light is emitted differ from the remaining third connection portions in at least one of size, shape, and position.

13. Of the N data lines mentioned above, the first data line is: A wiring in the first direction located in the second region and extending in the first direction, and Located in the second region, electrically connected to the wiring in the first direction, and including wiring in the second direction that extends from the line in the first direction in a second direction different from the first direction, The wiring in the first direction is arranged within the first metal layer. The display device according to claim 4, wherein the wiring in the second direction is arranged in a second metal layer different from the first metal layer.

14. Of the first metal layer and the second metal layer, One is a source-drain metal layer on which the source electrode or drain electrode of the transistor within the display area is arranged. The other is a metal layer of a capacitor electrode on which one of two or more capacitor electrodes constituting the storage capacitor in the display area is arranged, according to claim 13.

15. The invention further includes a plurality of power wirings arranged within the first metal layer, The display device according to claim 13, wherein at least one of the plurality of power supply wires is arranged alongside the wiring in the first direction and intersects and overlaps with the wiring in the second direction.

16. The display device according to claim 15, wherein the at least one power supply wiring has a wider line width than the wiring in the first direction.

17. Of the N data lines mentioned above, the first data line is: A first-direction wiring located in the fourth region and extending in the first direction; and The fourth region includes a second direction of wiring located in the fourth region, electrically connected to the first direction wiring, and extending from the first direction wiring in a second direction different from the first direction, The wiring in the first direction is arranged within the first metal layer. The display device according to claim 4, wherein the wiring in the second direction is arranged in a second metal layer different from the first metal layer.

18. The display device according to claim 1, wherein the display device is a glasses-type wearable device or a heterogeneous integrated display device, and one side of the intermediate region corresponds to the position of the user's nose.

19. A substrate including a display area capable of displaying images and a non-display area outside the display area, and N data lines arranged on the substrate Includes, The substrate includes first, second, third, fourth, and fifth regions located sequentially in the first direction, and the display region includes first, second, third, fourth, and fifth display regions which are respectively contained within the first, second, third, fourth, and fifth regions. In the third region, one edge of the substrate is recessed inward or curved. Of the N data lines mentioned above, the first data line is: The second display area is bent or curved in one direction, and A display device in which the fourth display area is bent or curved in another direction.

20. The third region includes the third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region. The display device according to claim 19, wherein the first data line passes through the first non-display area within the third area.

21. The third region includes the third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region. The aforementioned N data lines include a second, third, and fourth data line. The second data line is, The second display area is bent or curved in one direction, The fourth display area is bent or curved in the other direction, and The display device according to claim 19, which passes through the first non-display area within the third area.

22. The third region includes the third display region, a first non-display region on one side of the third display region, and a second non-display region on the other side of the third display region. Of the N data lines mentioned above, the fifth data line is: The second display area is bent or curved in one direction, The fourth display area is bent or curved in the other direction, and The display device according to claim 19, which passes through the second non-display area within the third area.

Images