Manufacturing method for semiconductor devices

Abstract

To improve the reliability of semiconductor devices and suppress yield degradation. [Solution] A trench TR is formed in the semiconductor substrate SUB. A gate electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1, and a well region NW1 are formed in the semiconductor substrate SUB. A source region NS is formed in the body region PB. An n-type source region and an n-type drain region are formed in the well region PW1. A p-type source region and a p-type drain region are formed in the well region NW1. Heat treatment is performed on the source region NS, the n-type source region, the n-type drain region, the p-type source region, and the p-type drain region. After the above heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located beneath the body region PB.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a trench gate type MOSFET.

Background Art

[0002] In semiconductor devices that require high breakdown voltage, semiconductor elements such as trench gate type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in which gate electrodes are embedded inside trenches are applied. Further, semiconductor devices have been developed in which a trench gate type MOSFET is used as an output circuit and a planar type MOSFET is used as a control circuit for controlling the gate potential of the output circuit. Such semiconductor devices are called IPDs (Intelligent Power Devices).

[0003] As a form of the semiconductor device constituting the IPD, there is a semiconductor module in which a semiconductor chip for an output circuit and a semiconductor chip for control circuit control are mounted as one package. As another form, there is a structure in which each MOSFET constituting the output circuit and the control circuit is formed on the same semiconductor substrate and these are mixed and mounted in one semiconductor chip.

[0004] For example, Patent Documents 1 to 3 disclose semiconductor devices in which each MOSFET constituting an output circuit and a control circuit is formed on the same semiconductor substrate as an IPD. Further, the IPD of Patent Document 1 discloses a technique for forming a gate electrode of a trench gate type MOSFET and a gate electrode of a planar type MOSFET in separate manufacturing processes.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

[0006] Forming each MOSFET constituting the output circuit and control circuit on the same semiconductor substrate offers advantages in terms of reducing mounting costs and miniaturizing the semiconductor device. However, the trench-gate type MOSFET for the output circuit and the planar type MOSFET for the control circuit have different device structures and different required characteristics, which tends to complicate the manufacturing process. Therefore, defects that did not occur individually may occur in the manufacturing process of the trench-gate type MOSFET and the planar type MOSFET, leading to problems such as reduced reliability and lower yield of the semiconductor device.

[0007] The main object of this application is to provide a technology that can improve the reliability of a semiconductor device and suppress yield degradation when trench-gate type MOSFETs and planar type MOSFETs are formed on the same semiconductor substrate. Other issues and novel features will become apparent from the description herein and the accompanying drawings. [Means for solving the problem]

[0008] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0009] A method for manufacturing a semiconductor device according to one embodiment has a first region on which a first MOSFET is formed and a second region on which a second MOSFET is formed. The method for manufacturing the semiconductor device includes the steps of: preparing a semiconductor substrate of a first conductivity type having an upper surface; forming a first well region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate of the second region; forming a first hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate; forming a trench in the semiconductor substrate exposed from the first hard mask in the first region; forming a first gate insulating film inside the trench after the step of forming the trench; forming a first conductive film on the first gate insulating film and the first hard mask after the step of forming the first conductive film; and performing an anisotropic etching treatment on the first conductive film after the step of forming the first conductive film. The process includes the steps of: removing the first conductive film on the first hard mask and forming a first gate electrode inside the trench so as to fill the inside of the trench via the first gate insulating film; forming a cap film made of an insulating film on the upper surface of the first gate electrode after the step of forming the first gate electrode; removing the first hard mask after the step of forming the cap film; forming a second gate insulating film on the first well region after the step of removing the first hard mask; forming a second conductive film on the second gate insulating film and on the cap film; and forming a second gate electrode on the second gate insulating film by patterning the second conductive film with anisotropic etching. The first MOSFET includes the first gate insulating film and the first gate electrode. The second MOSFET includes the second gate insulating film and the second gate electrode. [Effects of the Invention]

[0010] According to one embodiment, the reliability of semiconductor devices can be improved and the decrease in yield can be suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] It is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] It is a cross-sectional view showing the semiconductor device in Embodiment 1. [Figure 3] It is a cross-sectional view showing the semiconductor device in Embodiment 1. [Figure 4] It is a cross-sectional view showing the semiconductor device in Embodiment 1. [Figure 5] It is a cross-sectional view showing the semiconductor device in Embodiment 1. [Figure 6] It is an enlarged plan view of a part of the semiconductor device in Embodiment 1. [Figure 7] It is a cross-sectional view showing the semiconductor device in Embodiment 1. [Figure 8] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 9] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 10] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 11] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 9. [Figure 12] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 10. [Figure 13] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 14] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 15] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 13. [Figure 16] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 14. [Figure 17] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 15. [Figure 18] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 19] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 17. [Figure 20] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 18. [Figure 21] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 19. [Figure 22] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 20. [Figure 23] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 21. [Figure 24] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 22. [Figure 25] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 23. [Figure 26] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 24. [Figure 27] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 25. [Figure 28] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 26. [Figure 29] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 27. [Figure 30] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 28. [Figure 31] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 29. [Figure 32] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 30. [Figure 33] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 31. [Figure 34] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 32. [Figure 35] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 33. [Figure 36] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 34. [Figure 37] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 35. [Figure 38] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 36. [Figure 39]This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 37. [Figure 40] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 38. [Figure 41] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 39. [Figure 42] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 40. [Figure 43] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 41. [Figure 44] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 42. [Figure 45] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 43. [Figure 46] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 44. [Figure 47] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 45. [Figure 48] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 46. [Figure 49] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 47. [Figure 50] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 48. [Figure 51] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 49. [Figure 52] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 50. [Figure 53] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 51. [Figure 54] This is a cross-sectional view of the main part showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 55] This is a cross-sectional view of the main part showing the manufacturing process of the semiconductor device in Example 1. [Figure 56] This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 54. [Figure 57] Figure 55 is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device. [Figure 58]Figure 56 is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device. [Figure 59] Figure 57 is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device. [Figure 60] This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 58. [Figure 61] Figure 59 is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device. [Figure 62] Figure 60 is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device. [Figure 63] This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 61. [Figure 64] This is a cross-sectional view of the main part showing the manufacturing process of a semiconductor device in Example 2. [Figure 65] This is a cross-sectional view of the main part showing the manufacturing process of a semiconductor device in Example 3. [Figure 66] This is an enlarged plan view of a part of the semiconductor device in Embodiment 1. [Figure 67] This is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 68] This graph shows experimental data from the present inventors. [Figure 69] This is an enlarged plan view of a part of the semiconductor device in Embodiment 1. [Figure 70] This is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 71] This is a cross-sectional view of the main part showing the manufacturing process of a semiconductor device in Embodiment 2. [Figure 72] This is a cross-sectional view of the main part showing the manufacturing process of the semiconductor device in Example 4. [Figure 73] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 2. [Figure 74] This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 73. [Figure 75] This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 74. [Figure 76]This is a cross-sectional view of the main parts showing the manufacturing process of a semiconductor device, following Figure 75. [Modes for carrying out the invention]

[0012] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0013] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of a semiconductor device> The semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 to 7. The semiconductor device 100 is an IPD (Integrated Device) in which an output circuit for driving an external load and a control circuit for controlling the gate potential of the output circuit are formed on the same semiconductor substrate SUB. The load is, for example, various electronic components mounted on a vehicle.

[0015] Figure 1 is a plan view of a semiconductor chip, which is a semiconductor device 100. As shown in Figure 1, the semiconductor device 100 has a region 1A where a MOSFET for the output circuit is formed, and regions 2A to 4A where semiconductor elements such as MOSFETs and resistors for the control circuit are formed. Note that the layout of regions 2A to 4A is not limited to the example in Figure 1 and can be freely designed as appropriate.

[0016] Figure 1 also shows multiple pads and source pads, which are part of the uppermost wiring M3. The source pads are located above region 1A and serve as output terminals for the output circuit. Multiple pads are located around regions 2A to 4A. Various signals and ground potentials from outside the semiconductor device 100 are transmitted to the control circuit via the multiple pads.

[0017] Figure 2 shows the n-type MOSFET 1Qn formed in region 1A, and the n-type MOSFET 2Qn and p-type MOSFET 2Qp formed in region 2A. MOSFET 1Qn is a trench-gate type MOSFET, while MOSFETs 2Qn and 2Qp are planar type MOSFETs. Figure 4 shows the wiring structure formed above MOSFETs 1Qn, 2Qn, and 2Qp.

[0018] Figure 3 shows the n-type MOSFET 3Qn and p-type MOSFET 3Qp formed in region 3A, and the resistive element RS formed in region 4A. MOSFETs 3Qn and 3Qp are planar MOSFETs. Figure 5 shows the wiring structure formed above MOSFETs 3Qn, 3Qp, and the resistive element RS.

[0019] Furthermore, Figure 2 shows only a representative portion of the structure of region 1A, while Figures 6 and 7 show the specific structure of region 1A. Figure 6 is a plan view showing multiple MOSFETs 1Qn. Figure 7 is a cross-sectional view along lines AA and BB shown in Figure 6.

[0020] <MOSFET 1Qn in region 1A> First, the structure of MOSFET1Qn in region 1A will be explained using Figures 2, 6, and 7.

[0021] As described below, MOSFET1Qn includes a gate insulating film GI1, a gate electrode GE1, a body region PB, a source region NS, a high-concentration diffusion region PR, a column region PC, and a cap film CP1. MOSFET1Qn also includes a drain region ND and a drift region NV (semiconductor substrate SUB in region 1A) as drains.

[0022] As shown in Figure 6, multiple trenches TR are formed in the semiconductor substrate SUB. The multiple trenches TR are formed in a stripe pattern, each extending in the Y direction and adjacent to one another in the X direction. A gate electrode GE1 is formed inside the trench TR. Multiple holes CH1 are arranged spaced apart from each other along the extending direction of the trench TR. The source electrode SE is electrically connected to the source region NS and the body region PB through the holes CH1. Holes CH2 are located on the gate electrode GE1 near the ends of the trench TR. The gate wiring GW is electrically connected to the gate electrode GE1 through the holes CH2.

[0023] As shown in Figures 2 and 7, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB is made of silicon. The semiconductor substrate SUB has a low concentration of n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In this application, a laminate consisting of such an n-type silicon substrate and an n-type semiconductor layer is also described as a semiconductor substrate SUB.

[0024] On the upper surface of the semiconductor substrate SUB, a trench TR is formed within the semiconductor substrate SUB, extending to a predetermined depth from the upper surface of the semiconductor substrate SUB. The depth of the trench TR is, for example, 0.5 μm or more and 2 μm or less. A gate insulating film GI1 is formed inside the trench TR (on the sides and bottom of the trench TR). The gate insulating film GI1 is, for example, a silicon oxide film, and has a thickness of, for example, 10 nm or more and 20 nm or less.

[0025] A gate electrode GE1 is formed inside the trench TR, filling the trench TR via the gate insulating film GI1. The gate electrode GE1 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced. A cap film CP1 is formed on the upper surface of the gate electrode GE1, covering its upper surface. The cap film CP1 is an insulating film, a silicon oxide film formed by thermal oxidation of the upper surface of the gate electrode GE1 (polycrystalline silicon film). The thickness of the cap film CP1 is greater than the thickness of the gate insulating film GI1 and the gate insulating films GI2 and GI3 described later, for example, 40 nm or more and 60 nm or less.

[0026] On the upper surface of the semiconductor substrate SUB, a p-type body region PB is formed within the semiconductor substrate SUB, such that it is shallower than the depth of the trench TR. An n-type source region NS is formed within the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0027] Within the semiconductor substrate SUB located beneath the body region PB, p-type column regions PC are formed. As shown in Figure 6, multiple column regions PC are provided at equal intervals in the direction of extension of the trench TR (Y direction). Furthermore, the multiple column regions PC are arranged in a staggered pattern. By arranging p-type column regions PC two-dimensionally within the n-type drift region NV, the area around the column regions PC can be depleted, improving the breakdown voltage. In addition, as shown in column regions PC1 to PC3, equilateral triangles are formed by lines connecting the centers of each of the multiple column regions PC. This makes it easier to homogenize the depletion layer extending from each column region PC, and to achieve sufficient depletion between each column region PC.

[0028] On the underside of the semiconductor substrate SUB, an n-type drain region ND is formed within the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. Below the underside of the semiconductor substrate SUB, a drain electrode DE is formed. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed across regions 1A to 4A.

[0029] The drain region ND and the semiconductor substrate SUB (drift region NV) constitute the drain of MOSFET 1Qn. The power supply potential is supplied as the drain potential to the drain region ND and the semiconductor substrate SUB from outside the semiconductor device 100 via the drain electrode DE.

[0030] Furthermore, if the semiconductor substrate SUB is a laminate of an n-type silicon substrate and an n-type semiconductor layer, the n-type silicon substrate may function as a drain region ND. In that case, the formation of a drain region ND is not required. In other words, the formation of a drain region ND is not essential.

[0031] On the upper surface of the semiconductor substrate SUB, a silicon nitride film SN1 and an interlayer insulating film IL1 are formed so as to cover the gate electrode GE1. The interlayer insulating film IL1 is formed on top of the silicon nitride film SN1. The thickness of the silicon nitride film SN1 is, for example, 10 nm or more and 20 nm or less. The thickness of the interlayer insulating film IL1 is, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL1 is, for example, a laminated film of a thin silicon oxide film and a thick silicon oxide film (BPSG: Boro Phospho Silicate Glass film) containing boron and phosphorus.

[0032] Pores CH1 are formed in the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB. The bottom of pore CH1 is located inside the body region PB. Near the bottom of pore CH1, a high-concentration diffusion region PR is formed in the body region PB. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. In addition, pores CH2 are formed in the interlayer insulating film IL1 and the silicon nitride film SN1, penetrating the cap film CP1 and reaching the gate electrode GE1.

[0033] A plug PG is formed inside each of holes CH1 and CH2. Multiple wirings M1 are formed on the interlayer insulating film IL1. In region 1A, some of the multiple wirings M1 function as source electrodes SE and gate wiring GW. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via the plug PG inside hole CH1. The gate wiring GW is electrically connected to the gate electrode GE1 via the plug PG inside hole CH2.

[0034] The gate wiring GW is electrically connected to semiconductor elements such as MOSFETs 2Qn, 2Qp, 3Qn, 3Qp and resistor RS via other wiring such as wiring M1 in regions 2A to 4A. Therefore, the potential supplied to the gate electrode GE1 is controlled by the control circuit in regions 2A to 4A, which includes the aforementioned semiconductor elements.

[0035] The plug PG is composed of a laminated film consisting of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0036] Furthermore, the wiring M1 is composed of a laminated film of a first barrier metal film, a conductive film formed on the first barrier metal film, and a second barrier metal film formed on the conductive film. The first barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum film or an aluminum alloy film with copper or silicon added. The second barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film.

[0037] <MOSFETs 2Qn and 2Qp in region 2A> The structures of MOSFETs 2Qn and 2Qp in region 2A are described below using Figure 2.

[0038] As described below, MOSFET2Qn includes a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, and a well region PW1. The source region and drain region of MOSFET2Qn are composed of impurity regions N1 and N2.

[0039] Furthermore, MOSFET2Qp includes a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, and a well region NW1. The source region and drain region of MOSFET2Qp are composed of impurity region P1 and impurity region P2.

[0040] p-type well regions (HPWs) are formed in the semiconductor substrate SUB in regions 2A and 3A. The well regions (HPWs) are primarily provided to separate well region NW1 in region 2A and well region NW2 in region 3A from the n-type semiconductor substrate SUB.

[0041] Within the well region HPW of region 2A, a p-type well region PW1 and an n-type well region NW1 are formed. A gate insulating film GI2 is formed on well region PW1 and well region NW1, respectively. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness of, for example, 10 nm or more and 20 nm or less. A gate electrode GE2 is formed on the gate insulating film GI2.

[0042] MOSFETs 2Qn and 2Qp in region 2A are provided for high-speed driving and are driven at a lower operating voltage than MOSFET 1Qn in region 1A. Therefore, the material contained in gate electrode GE2 is different from the material contained in gate electrode GE1 and has a lower sheet resistance than the material contained in gate electrode GE1. In addition, gate electrode GE2 is formed by a different manufacturing process than gate electrode GE1. For example, gate electrode GE2 consists of a laminated film of a polycrystalline silicon film into which n-type impurities have been introduced and a tungsten silicide film formed on the polycrystalline silicon film.

[0043] The thickness of the polycrystalline silicon film is 60 nm or more and 100 nm or less, and the thickness of the tungsten silicide film is 80 nm or more and 120 nm or less. Furthermore, the impurity concentration of the polycrystalline silicon film contained in gate electrode GE2 is the same as or higher than the impurity concentration of the polycrystalline silicon film contained in gate electrode GE1.

[0044] A capping film CP2 is formed on the upper surface of the gate electrode GE2. The capping film CP2 is an insulating film, for example, a silicon oxide film. The thickness of the capping film CP2 is, for example, 100 nm or more and 150 nm or less. A sidewall spacer SW is formed on the side surface of the gate electrode GE2. The sidewall spacer SW is, for example, a silicon oxide film.

[0045] Within the well region PW1, n-type impurity regions N1 and N2 are formed. The well region PW1, sandwiched between the pair of impurity regions N1 and located below the gate electrode GE2, becomes the channel region of MOSFET2Qn. Impurity region N2 is formed at a deeper position than impurity region N1 and has a higher impurity concentration than impurity region N1.

[0046] Within the well region NW1, two p-type impurity regions, P1 and P2, are formed. The well region NW1, sandwiched between the pair of impurity regions P1 and located below the gate electrode GE2, becomes the channel region of MOSFET2Qp. Impurity region P2 is formed at a deeper position than impurity region P1 and has a higher impurity concentration than impurity region P1.

[0047] Regions 1A to 4A are each demarcated by element isolation sections (LOCs) formed on the semiconductor substrate SUB. The element isolation section LOC is, for example, a silicon oxide film, and has a thickness of, for example, 300 nm or more and 600 nm or less. The element isolation section LOC is also formed at the boundary between MOSFET2Qn and MOSFET2Qp in region 2A, and at the boundary between MOSFET3Qn and MOSFET3Qp in region 3A.

[0048] <MOSFETs 3Qn and 3Qp in region 3A> The structures of MOSFETs 3Qn and 3Qp in region 3A are described below using Figure 3.

[0049] As described below, MOSFET3Qn includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region PW2, and an element isolation region LOC. The source region of MOSFET3Qn is composed of impurity regions N1 and N2. The drain region of MOSFET3Qn is composed of a well region NW2 and an impurity region N2.

[0050] Furthermore, MOSFET3Qp includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region NW3, and an element isolation region LOC. The source region of MOSFET3Qp is composed of impurity region P1 and impurity region P2. The drain region of MOSFET3Qp is composed of a well region PW3 and impurity region P2.

[0051] Within the well region HPW of region 3A, a p-type well region PW2 and an n-type well region NW2 are formed. A gate insulating film GI3 is formed on well region PW2 and well region NW2. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. A sidewall spacer SW is formed on the side surface of the gate electrode GE3.

[0052] Furthermore, an element isolation section (LOC) is formed in a part of the well region NW2. Part of the gate electrode GE3 is formed on the element isolation section LOC, and the end of the gate electrode GE3 on the drain region side is located on the element isolation section LOC.

[0053] MOSFETs 3Qn and 3Qp in region 3A are driven at a higher operating voltage than MOSFETs 2Qn and 2Qp in region 2A. For example, a potential of about 5V is applied to the drain region of MOSFET 2Qn in region 2A, while a potential of 10V or more is applied to the drain region of MOSFET 3Qn in region 3A. Therefore, to mitigate electric field concentration in the drain region, MOSFET 3Qn has an element isolation section (LOC) provided below the gate electrode GE3 on the drain region side.

[0054] Within well region PW2, n-type impurity regions N1 and N2 are formed. Within well region NW2, n-type impurity region N2 is formed. The well region PW2, sandwiched between impurity region N1 and well region NW2, and located below gate electrode GE3, becomes the channel region of MOSFET3Qn.

[0055] In the semiconductor substrate SUB of region 3A, n-type well region NW3 and p-type well region PW3 are formed. A gate insulating film GI3 is formed on well region NW3 and well region PW3. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. A sidewall spacer SW is formed on the side surface of the gate electrode GE3.

[0056] Furthermore, in MOSFET3Qp, an element isolation section (LOC) is formed in a part of the well region NW3 to mitigate electric field concentration in the drain region. Part of the gate electrode GE3 is formed on the element isolation section LOC, and the end of the gate electrode GE3 on the drain region side is located on the element isolation section LOC.

[0057] Within well region NW3, p-type impurity regions P1 and P2 are formed. Within well region PW3, p-type impurity region P2 is formed. The well region NW3, sandwiched between impurity region P1 and well region PW3, and located below gate electrode GE3, becomes the channel region of MOSFET3Qp.

[0058] Furthermore, the gate insulating film GI3, gate electrode GE3, cap film CP3, and sidewall spacer SW in region 3A are formed using the same manufacturing process as the gate insulating film GI2, gate electrode GE2, cap film CP2, and sidewall spacer SW in region 2A, respectively. Therefore, these materials and thicknesses are the same as those described for MOSFETs 2Qn and 2Qp in region 2A.

[0059] <Resistor element RS in region 4A> The structure of the resistive element RS in region 4A will be explained below with reference to Figure 3.

[0060] A device isolation region (LOC) is formed on the semiconductor substrate SUB in region 4A. An insulating film IF4 is formed on the device isolation region LOC. The insulating film IF4 is, for example, a silicon oxide film and has a thickness of, for example, 50 nm or more and 70 nm or less.

[0061] A resistive element RS is formed on the insulating film IF4. The resistive element RS needs to be designed to obtain a high resistance value. Therefore, the material contained in the resistive element RS has a higher sheet resistance than the material contained in the gate electrodes GE1 to GE3. Furthermore, the resistive element RS is formed by a different manufacturing process than the gate electrodes GE1 to GE3. The resistive element RS is, for example, a polycrystalline silicon film into which p-type impurities have been introduced, and has a thickness of, for example, 120 nm or more and 180 nm or less.

[0062] <Wiring structure> The wiring structure formed above MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, 3Qp and resistor RS will be described below with reference to Figures 4 and 5.

[0063] In regions 2A to 4A, a silicon nitride film SN1 and an interlayer insulating film IL1 are formed on the upper surface of the semiconductor substrate SUB, covering the gate electrodes GE2 and GE3 and the resistive element RS. The material contained in the interlayer insulating film IL1 is the same as that described in region 1A.

[0064] In MOSFETs 2Qp and 3Qp, positive charges can be trapped in the gate insulating films GI2 and GI3, potentially degrading the NBTI. By covering MOSFETs 2Qp and 3Qp with the silicon nitride film SN1, the entry of positive charges into the gate insulating films GI2 and GI3 can be suppressed, thereby improving the reliability of the semiconductor device 100.

[0065] In regions 2A to 4A, multiple pores CH3 are formed in the interlayer insulating film IL1 and the silicon nitride film SN1. A plug PG is formed inside each of the multiple pores CH3. Multiple wirings M1 are formed on the interlayer insulating film IL1. The materials contained in the plugs PG and wirings M1 are the same as those described in region 1A.

[0066] The impurity regions N2 and P2 and the resistive element RS are electrically connected to multiple wires M1 via plugs PG inside hole CH3. Although not shown in the diagram, gate electrodes GE2 and GE3 are also electrically connected to wires M1 via plugs PG inside hole CH3.

[0067] In regions 1A to 4A, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover multiple wirings M1. The interlayer insulating film IL2 is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL2 is, for example, 650 nm or more and 850 nm or less.

[0068] Multiple vias V1 connected to multiple wirings M1 are formed in the interlayer insulating film IL2. Each via V1 is constructed by embedding a laminated film of a barrier metal film and a conductive film within a contact hole formed in the interlayer insulating film IL2. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0069] Multiple wirings M2 connected to multiple vias V1 are formed on the interlayer insulating film IL2. The material contained in wiring M2 is the same as that of wiring M1. An interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the multiple wirings M2. The material contained in interlayer insulating film IL3 is the same as that of interlayer insulating film IL2. The thickness of interlayer insulating film IL3 is, for example, 650 nm or more and 850 nm or less. Multiple vias V2 connected to multiple wirings M2 are formed in the interlayer insulating film IL3. The configuration of via V2 is the same as that of via V1.

[0070] Multiple wirings M3 connected to multiple vias V2 are formed on the interlayer insulating film IL3. Each wiring M3 is composed of a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film. The conductive film is, for example, an aluminum film or an aluminum alloy film with copper or silicon added. The thickness of wirings M1 and M2 is, for example, 300 nm or more and 600 nm or less, but the thickness of wiring M3 is sufficiently thicker than the thickness of wirings M1 and M2, for example, 3 μm or more and 5 μm or less.

[0071] A protective film PVF is formed on the interlayer insulating film IL3 so as to cover multiple wirings M3. The protective film PVF is, for example, a polyimide film. The thickness of the protective film PVF is, for example, 4 μm or more and 7 μm or less.

[0072] Multiple openings OP1 and OP2 are formed in the protective PVF film on the wiring M3 so that portions of multiple wirings M3 are exposed (see Figures 67 and 70). The portions of wiring M3 exposed in opening OP1 constitute source pads PADs for connection to the external connection member BW. In addition, the portions of wiring M3 exposed in the multiple openings OP2 constitute multiple pads PADs for connection to the external connection member BW.

[0073] The external connection components BW are, for example, bonding wires made of gold or copper, or clips made of copper plates. By connecting the external connection components BW to the source pads and multiple pads, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0074] <Manufacturing method for semiconductor devices> The following describes each manufacturing process included in the manufacturing method of the semiconductor device 100, mainly using Figures 8 to 53.

[0075] As shown in Figures 8 and 9, first, an n-type semiconductor substrate SUB having an upper and lower surface is prepared. As mentioned above, in this case, the n-type semiconductor substrate SUB itself constitutes the drift region NV, but the drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate while introducing phosphorus (P) by epitaxial growth.

[0076] Next, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB, for example by thermal oxidation. Then, a silicon nitride film is formed on the silicon oxide film, for example by CVD (Chemical Vapor Deposition). Next, a hard mask HM1 that selectively covers the upper surface of the semiconductor substrate SUB is formed by patterning the silicon oxide film and the silicon nitride film. Next, a thermal oxidation treatment is performed on the semiconductor substrate SUB to form an element isolation section LOC made of silicon oxide film on the semiconductor substrate SUB exposed from the hard mask HM1. After that, the hard mask HM1 is removed by isotropic etching.

[0077] As shown in Figures 10 and 11, first, a through-film TH1 made of silicon oxide is formed on the upper surface of the semiconductor substrate SUB by thermal oxidation. Next, p-type well regions HPW are formed in the semiconductor substrate SUB in regions 2A and 3A by selective ion implantation from the upper surface side of the semiconductor substrate SUB so as to pass through the through-film TH1. In this ion implantation, for example, boron (B) is used as an impurity.

[0078] Next, the well region HPW is subjected to heat treatment. This heat treatment is carried out in a nitrogen atmosphere, for example, under conditions of 1150°C for 90 minutes. This heat treatment causes impurities contained in the well region HPW to diffuse into the semiconductor substrate SUB and become activated.

[0079] Since the heat treatment described above is performed for a relatively long time, if the heat treatment is performed after the formation of the gate insulating film GI1, stress may be generated from the gate insulating film GI1 into the semiconductor substrate SUB, and this stress may cause crystal defects to be generated in the semiconductor substrate SUB. In addition, although the hard mask HM1 and the hard mask HM2 described later contain a silicon nitride film, if the heat treatment is performed with the silicon nitride film formed on the upper surface of the semiconductor substrate SUB, the stress of the silicon nitride film may cause crystal defects to be generated in the semiconductor substrate SUB.

[0080] In other words, the above heat treatment is preferably performed before the formation of the trench TR and before the formation of the gate insulating film GI1, and is preferably performed when the silicon nitride film has not yet formed on the upper surface of the semiconductor substrate SUB.

[0081] As shown in Figures 12 and 13, first, an insulating film IF1 made of silicon nitride is formed on the through film TH1, for example by CVD. Next, an insulating film IF2 made of silicon oxide is formed on the insulating film IF1, for example by CVD. Then, a resist pattern RP1 is formed on the insulating film IF2 so as to selectively open a portion of region 1A and cover regions 2A to 4A.

[0082] As shown in Figures 14 and 15, first, the through-film TH1, insulating film IF1, and insulating film IF2 are patterned by anisotropic etching using the resist pattern RP1 as a mask. This forms a hard mask HM2. Next, the resist pattern RP1 is removed by ashing. Then, trenches TR are formed in the semiconductor substrate SUB exposed from the hard mask HM2 by anisotropic etching using the hard mask HM2 as a mask. After that, the semiconductor substrate SUB is cleaned. At this time, the insulating film IF2 is removed, but the through-film TH1 and insulating film IF1 remain as the hard mask HM2.

[0083] As shown in Figures 16 and 17, first, a gate insulating film GI1 is formed inside the trench TR by thermal oxidation. Next, a conductive film CF1 is formed on the gate insulating film GI1 and the hard mask HM2, for example by CVD. The conductive film CF1 is a polycrystalline silicon film. Next, the conductive film CF1 is converted into an n-type polycrystalline silicon film by ion implantation of impurities such as phosphorus (P).

[0084] As shown in Figures 18 and 19, the conductive film CF1 is subjected to anisotropic etching. This removes the conductive film CF1 from the hard mask HM2 and forms a gate electrode GE1 inside the trench TR, filling the inside of the trench TR via the gate insulating film GI1.

[0085] As shown in Figures 20 and 21, a portion of the gate electrode GE1 is oxidized by thermal oxidation. This forms a cap film CP1 made of an insulating film on the upper surface of the gate electrode GE1. In other words, the cap film CP1 is a silicon oxide film formed by thermal oxidation of the upper surface of a polycrystalline silicon film.

[0086] As shown in Figures 22 and 23, the hard mask HM2 is removed. First, the insulating film IF1 is removed by isotropic etching using an aqueous solution containing phosphoric acid. Next, the through-film TH1 is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0087] As shown in Figures 24 and 25, using photolithography and ion implantation techniques, each impurity region is selectively formed in regions 1A to 3A of the semiconductor substrate SUB on the upper surface.

[0088] In region 1A, a p-type body region PB is formed in the semiconductor substrate SUB so as to be shallower than the depth of the trench TR. In region 2A, a p-type well region PW1 and an n-type well region NW1 are formed in the semiconductor substrate SUB. Well regions PW1 and NW1 are formed within well region HPW. In region 3A, a p-type well region PW2, an n-type well region NW2, a p-type well region PW3, and an n-type well region NW3 are formed in the semiconductor substrate SUB. Well regions PW2 and NW2 are formed within well region HPW.

[0089] Although not shown in the diagram, a through-film made of silicon oxide is formed on the upper surface of the semiconductor substrate SUB prior to these ion implantations. After these ion implantations, the through-film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0090] As shown in Figures 26 and 27, first, a gate insulating film made of silicon oxide is formed on the upper surface of the semiconductor substrate SUB by thermal oxidation. Here, the gate insulating films formed on well regions PW1 and NW1 of region 2A are shown as gate insulating film GI2. Also, the gate insulating films formed on well regions PW2, NW2, PW3 and NW3 of region 3A are shown as gate insulating film GI3.

[0091] Next, a conductive film CF2 is formed on the gate insulating film GI2, the gate insulating film GI3, and the cap film CP1. The material contained in the conductive film CF2 has a higher sheet resistance than the material contained in the conductive film CF1 (gate electrode GE1). The conductive film CF2 is, for example, a laminated film of an n-type polycrystalline silicon film formed by the CVD method and a tungsten silicide film formed by the CVD method.

[0092] Next, an insulating film IF3 made of silicon oxide is formed on the conductive film CF2, for example by CVD. Then, a resist pattern RP2 is formed on the insulating film IF3 so as to selectively cover a portion of region 2A and a portion of region 3A.

[0093] As shown in Figures 28 and 29, the insulating film IF3 and conductive film CF2 are patterned by performing anisotropic etching using the resist pattern RP2 as a mask. This removes the insulating film IF3 and conductive film CF2 that are not covered by the resist pattern RP2. Then, on the upper surface of the semiconductor substrate SUB in region 2A, the gate electrode GE2 and cap film CP2 are formed via the gate insulating film GI2. Similarly, on the upper surface of the semiconductor substrate SUB in region 3A, the gate electrode GE3 and cap film CP3 are formed via the gate insulating film GI3.

[0094] Next, the resist pattern RP2 is removed by an ashing process. Subsequently, the gate insulating films GI2 and GI3 exposed from the gate electrodes GE2 and GE3 are removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0095] Here, the features of Embodiment 1 will be described in the manufacturing process shown in Figures 16 and 17 through 28 and 29. These features will be explained using Figures 54 to 65, in comparison with Study Examples 1 to 3. Note that Study Examples 1 to 3 are not prior art, but rather new findings obtained through the inventors of this application.

[0096] Figures 54 and 55 show the state immediately after the formation of the gate insulating film GI1. In Study Example 1, the gate insulating film GI1 is formed with the hard mask HM2 removed, but in Embodiment 1, the gate insulating film GI1 is formed with the hard mask HM2 remaining.

[0097] Next, as shown in Figures 56 and 57, a conductive film CF1 is formed to fill the inside of the trench TR. Then, as shown in Figures 58 and 59, anisotropic etching is performed on the conductive film CF1 to remove the conductive film CF1 on the outside of the trench TR and to recede the conductive film CF1 inside the trench TR. The conductive film CF1 remaining inside the trench TR becomes the gate electrode GE1.

[0098] At this point, the position of the upper surface of the conductive film CF1 in Study Example 1 is considerably lower than the position of the upper surface of the semiconductor substrate SUB. On the other hand, the position of the upper surface of the conductive film CF1 in Embodiment 1 is slightly lower than the position of the upper surface of the semiconductor substrate SUB, but is closer to the upper surface of the semiconductor substrate SUB due to the thickness of the hard mask HM2.

[0099] Next, as shown in Figures 60 and 61, a cap film CP1 is formed on the upper surface of the conductive film CF1 by thermal oxidation treatment. At this point, the position of the upper surface of the cap film CP1 in Study Example 1 is lower than the position of the upper surface of the semiconductor substrate SUB.

[0100] On the other hand, the upper surface of the conductive film CF1 in Embodiment 1 is lower than the upper surface of the semiconductor substrate SUB. This difference in position is indicated as height H1. Also, the upper surface of the cap film CP1 in Embodiment 1 is higher than the upper surface of the semiconductor substrate SUB. This difference in position is indicated as height H2. In other words, the upper surface of the semiconductor substrate SUB is located within the thickness range of the cap film CP1. Furthermore, the thickness of the cap film CP1 is greater than the thickness of the gate insulating film GI1.

[0101] Figures 62 and 63 show the state after removing the hard mask HM2, forming the conductive film CF2, and then performing anisotropic etching to pattern the conductive film CF2. In Study Example 1, however, because the upper surface of the cap film CP1 is located low, there is a problem in that the conductive film CF2 remains inside the trench TR as a sidewall-like residue.

[0102] Such residues can, for example, hinder the formation of holes CH2 in the gate electrode GE1, leading to the failure of holes CH2 to form properly. Furthermore, there is a risk that the residues may detach and scatter during each manufacturing process, potentially leaving them as foreign matter on the semiconductor substrate SUB. This can result in reduced reliability or decreased yield of the semiconductor device 100. In contrast, Embodiment 1 can suppress the generation of such residues.

[0103] To suppress the generation of residue, measures such as those shown in Example 2 of Figure 64 and Example 3 of Figure 65 may be considered.

[0104] In Example 2, by increasing the thickness of the gate insulating film GI1, the position of the upper surface of the gate electrode GE1 can be brought closer to the upper surface of the semiconductor substrate SUB, even if the recession amount of the conductive film CF1 remains the same. However, as the thickness of the gate insulating film GI1 increases, the on-current becomes more difficult to flow. In other words, the on-resistance increases, which degrades the performance of the semiconductor device 100.

[0105] In Example 3, by increasing the thickness of the hard mask HM2 (thickness of the insulating film IF1), the position of the upper surface of the gate electrode GE1 is higher than the position of the upper surface of the semiconductor substrate SUB, even if the amount of recession of the conductive film CF1 is the same. In this case, the generation of residue inside the trench TR can be suppressed.

[0106] However, after removing the hard mask HM2, if the conductive film CF2 is subjected to anisotropic etching, a sidewall-like residue of the conductive film CF2 remains on the side of the protruding gate electrode GE1. This residue may also become foreign matter on the semiconductor substrate SUB. Furthermore, if the residue remains on the side of the protruding gate electrode GE1, this residue may become a leak path between the gate electrode GE1 and the source region NS.

[0107] Embodiment 1 was devised considering the problems that occur in Study Examples 1 to 3, and can suppress the generation of residue caused by the conductive film CF2. Furthermore, since there is no need to adjust the thickness of the gate insulating film GI1, the increase in on-resistance can also be suppressed. In other words, according to Embodiment 1, the reliability of the semiconductor device 100 can be improved while ensuring the performance of the semiconductor device 100, and the decrease in yield can also be suppressed.

[0108] Incidentally, as mentioned above, when removing the insulating film IF1, which is a silicon nitride film, from the hard mask HM2, an isotropic etching process using an aqueous solution containing phosphoric acid is used. In this case, if the upper surface of the gate electrode GE1 is exposed, the gate electrode GE1 will be etched by the phosphoric acid. Such etching can be prevented by forming a cap film CP1 on the gate electrode GE1.

[0109] Furthermore, the cap film CP1 is formed by thermal oxidation treatment of the upper surface of the gate electrode GE1, which is made of polycrystalline silicon film. However, as shown in Figure 58, the upper part of the gate electrode GE1 has a pointed shape before the thermal oxidation treatment. Such pointed areas are prone to electric field concentration and are likely to be a cause of localized deterioration of dielectric strength.

[0110] As shown in Figure 60, by appropriately adjusting the time of the thermal oxidation treatment, the upper part of the gate electrode GE1 is rounded. This suppresses electric field concentration at the top of the gate electrode GE1. For example, by adjusting the time of the thermal oxidation treatment so that the thickness of the cap film CP1 is 40 nm or more and 60 nm or less, the upper part of the gate electrode GE1 is rounded to a degree that suppresses electric field concentration. In other words, it is preferable to perform the thermal oxidation treatment until the thickness of the cap film CP1 becomes thicker than the thickness of the gate insulating film GI1 (10 nm to 20 nm).

[0111] It is also possible to oxidize the upper surface of the gate electrode GE1 when forming the gate insulating film GI2 without forming the cap film CP1. However, since the thickness of the gate insulating film GI2 is, for example, 10 nm or more and 20 nm or less, the upper part of the gate electrode GE1 may not be sufficiently rounded. Considering this point, it is preferable to perform the above thermal oxidation treatment until the thickness of the cap film CP1 becomes thicker than the thickness of the gate insulating film GI2.

[0112] The manufacturing process is described below, following Figures 28 and 29 onward.

[0113] As shown in Figures 30 and 31, first, using photolithography and ion implantation techniques, each impurity region is selectively formed in regions 2A and 3A of the semiconductor substrate SUB on the upper surface.

[0114] In region 2A, an n-type impurity region N1 is formed in well region PW1, and a p-type impurity region P1 is formed in well region NW1. In region 3A, an n-type impurity region N1 is formed in well region PW2, and a p-type impurity region P1 is formed in well region NW3.

[0115] Although not shown in the diagram, a through-film made of silicon oxide is formed on the upper surface of the semiconductor substrate SUB prior to these ion implantations. After these ion implantations, the through-film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0116] Next, an insulating film, such as a silicon oxide film, is formed on the upper surface of the semiconductor substrate SUB in regions 1A to 4A, for example, by CVD. Then, an anisotropic etching treatment is performed on the insulating film to remove the insulating film from the upper surface of the semiconductor substrate SUB, and sidewall spacers SW are formed on the respective sides of the gate electrodes GE2 and GE3.

[0117] As shown in Figures 32 and 33, first, an insulating film IF4, made of, for example, a silicon oxide film, is formed on the upper surface of the semiconductor substrate SUB, for example, by CVD, so as to cover the gate electrodes GE1 to GE3 and the element isolation portion LOC.

[0118] Next, a conductive film CF3 is formed on the insulating film IF4, for example by CVD. The material contained in conductive film CF3 has a higher sheet resistance than the material contained in conductive films CF1 and CF2 (gate electrodes GE1~GE3). Conductive film CF3 is a polycrystalline silicon film. Next, conductive film CF3 is converted into a p-type polycrystalline silicon film by ion implantation of impurities such as boron (B). Then, a resist pattern RP3 is formed on conductive film CF3 so as to selectively cover a portion of region 4A.

[0119] As shown in Figures 34 and 35, first, the conductive film CF3 is patterned by anisotropic etching using the resist pattern RP3 as a mask. This forms the resistive element RS. Next, the resist pattern RP3 is removed by ashing. Then, the insulating film IF4 exposed from the resistive element RS is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0120] As shown in Figures 36 and 37, first, using photolithography and ion implantation techniques, each impurity region is selectively formed in regions 1A to 3A of the semiconductor substrate SUB on the upper surface.

[0121] In region 1A, an n-type source region NS is formed in the body region PB. In region 2A, an n-type impurity region N2 is formed in the well region PW1, and a p-type impurity region P2 is formed in the well region NW1. In this way, in region 2A, the source and drain regions of MOSFET2Qn containing impurity regions N1 and N2 are formed, and the source and drain regions of MOSFET2Qp containing impurity regions P1 and P2 are formed.

[0122] In region 3A, an n-type impurity region N2 is formed in well region PW2, an n-type impurity region N2 is formed in well region NW2, a p-type impurity region P2 is formed in well region NW3, and a p-type impurity region P2 is formed in well region PW3. In this way, in region 3A, the source region of MOSFET3Qn including impurity regions N1 and N2 is formed, and the drain region of MOSFET3Qn including well region NW2 and impurity region N2 is formed. Also in region 3A, the source region of MOSFET3Qp including impurity regions P1 and P2 is formed, and the drain region of MOSFET3Qp including well region PW3 and impurity region P2 is formed.

[0123] Although not shown in the diagram, a through-film made of silicon oxide is formed on the upper surface of the semiconductor substrate SUB prior to these ion implantations. After these ion implantations, the through-film may be removed by a cleaning process using an aqueous solution containing hydrofluoric acid, or it may be left in place.

[0124] Next, the source and drain regions of each MOSFET 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp are subjected to heat treatment. This heat treatment is carried out in a nitrogen atmosphere, for example, under conditions of 850°C for 20 minutes. This heat treatment activates the impurities contained in the source and drain regions of each MOSFET 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp.

[0125] Through the above manufacturing processes, the basic structures of MOSFET1Qn, 2Qn, 2Qp, 3Qn, and 3Qp can be obtained.

[0126] Next, a silicon nitride film SN1 is formed on the upper surface of the semiconductor substrate SUB in regions 1A to 4A, for example by CVD, so as to cover the gate electrodes GE1 to GE3 and the resistive element RS. The thickness of the silicon nitride film SN1 is, for example, 10 nm or more and 20 nm or less.

[0127] As shown in Figures 38 and 39, an insulating film IF5 made of a silicon oxide film, a silicon nitride film SN2, and an insulating film IF6 made of a silicon oxide film are sequentially formed on the silicon nitride film SN1, for example by CVD. The thickness of insulating film IF5 is, for example, 80 nm or more and 120 nm or less. The thickness of silicon nitride film SN2 is, for example, 120 nm or more and 160 nm or less. The thickness of insulating film IF6 is, for example, 1000 nm or more and 1400 nm or less.

[0128] As shown in Figures 40 and 41, first, a resist pattern RP4 is formed on the insulating film IF6 to selectively open a portion of region 1A. Next, an anisotropic etching process is performed using the resist pattern RP4 as a mask to form an opening OP0 in the insulating film IF6 located on the body region PB. In this process, the silicon nitride film SN2 functions as an etching stopper.

[0129] Next, ion implantation is performed inside the opening OP0, passing through the silicon nitride film SN1, the insulating film IF5, and the silicon nitride film SN2. This forms a p-type column region PC in the semiconductor substrate SUB located beneath the body region PB. In this ion implantation, boron (B), for example, is used as an impurity, and the process is carried out in multiple stages while changing the implantation energy. After that, the resist pattern RP4 is removed by ashing.

[0130] Here, it is preferable that the formation of the column region PC is performed after heat treatment to activate the impurities contained in the source and drain regions of each of MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp. If the heat treatment for activation is performed after the formation of the column region PC, the impurities contained in the column region PC may diffuse, causing the column region PC to expand. If the position of the column region PC expands too much from the design value, the on-resistance of MOSFET 1Qn may increase. In addition, since it is difficult to control the diffusion position of the column region PC due to heat treatment, there is a risk of variation in the expansion of the depletion layer, and the expected breakdown voltage may not be obtained. For this reason, in Embodiment 1, the formation of the column region PC is performed after the heat treatment for activation.

[0131] As shown in Figures 42 and 43, first, the insulating film IF6 is removed by performing an isotropic etching treatment using an aqueous solution containing hydrofluoric acid, with the silicon nitride film SN2 acting as an etching stopper. Next, the silicon nitride film SN2 is removed by performing an isotropic etching treatment using an aqueous solution containing phosphoric acid, with the insulating film IF5 acting as an etching stopper. Since the insulating film IF5 was formed between the silicon nitride film SN1 and the silicon nitride film SN2, the removal of silicon nitride film SN1 is prevented when silicon nitride film SN2 is removed.

[0132] Subsequently, the insulating film IF5 may be removed by isotropic etching using an aqueous solution containing hydrofluoric acid, or it may be left as part of the interlayer insulating film IL1. Here, we will illustrate the case where the insulating film IF5 is left.

[0133] As shown in Figures 44 and 45, an interlayer insulating film IL1 is formed on the upper surface of the semiconductor substrate SUB in regions 1A to 4A so as to cover the gate electrodes GE1 to GE3 and the resistive element RS.

[0134] First, a silicon oxide film is formed on the silicon nitride film SN1, for example by CVD. Next, a BPSG film is formed on the silicon oxide film, for example by coating. Then, the BPSG film is heat-treated. This heat treatment is carried out in a nitrogen atmosphere, for example, under conditions of 850°C for 20 minutes. This heat treatment may cause boron or phosphorus to diffuse from the BPSG film to the semiconductor substrate SUB, but such diffusion can be prevented by the silicon oxide film. Note that if the insulating film IF5 remains, the formation of the silicon oxide film is not essential.

[0135] Next, the interlayer insulating film IL1 is polished using the CMP (Chemical Mechanical Polishing) method. This flattens the upper surface of the interlayer insulating film IL1.

[0136] As shown in Figures 46 and 47, first, pores CH1 are formed in region 1A within the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB by photolithography and anisotropic etching. The bottom of the pores CH1 is located inside the body region PB.

[0137] Furthermore, during the etching of the interlayer insulating film IL1, the silicon nitride film SN1 functions as an etching stopper. Subsequently, the conditions such as the gas are changed, and the silicon nitride film SN1 and the semiconductor substrate SUB are etched sequentially. Since the etching process is stopped once by the silicon nitride film SN1, it becomes easier to make the depth of the multiple pores CH1 within the wafer surface uniform.

[0138] Next, a p-type high-concentration diffusion region PR is formed by introducing, for example, boron (B) into the body region PB at the bottom of the pore CH1 using ion implantation.

[0139] As shown in Figures 48 and 49, pores CH2 are formed in region 1A within the interlayer insulating film IL1, the silicon nitride film SN1, and the cap film CP1 by photolithography and anisotropic etching. The pores CH2 reach the gate electrode GE1. Similar to the process of creating the pores CH1, the silicon nitride film SN1 acts as an etching stopper during the etching of the interlayer insulating film IL1.

[0140] As shown in Figures 50 and 51, multiple pores CH3 are formed in the interlayer insulating film IL1 and the silicon nitride film SN1 in regions 2A to 4A by photolithography and anisotropic etching. In region 2A, the multiple pores CH3 reach the source and drain regions of MOSFETs 2Qn and 2Qp, respectively. In region 3A, the multiple pores CH3 reach the source and drain regions of MOSFETs 3Qn and 3Qp, respectively. In region 4A, the multiple pores CH3 reach the resistive element RS. Similar to the manufacturing process of pores CH1, the silicon nitride film SN1 acts as an etching stopper during the etching of the interlayer insulating film IL1.

[0141] Although not shown in the diagram, pores CH3 reaching gate electrodes GE2 and GE3 are also formed in the interlayer insulating film IL1 and the silicon nitride film SN1.

[0142] The manufacturing process for pore CH1 requires etching to a deeper location compared to the manufacturing processes for pore CH2 and pore CH3, and also requires etching of the semiconductor substrate SUB. Furthermore, after the formation of pore CH1, there is also a manufacturing process for the high-concentration diffusion region PR. Therefore, it is preferable that the manufacturing process for pore CH1, pore CH2, and pore CH3 be separate processes.

[0143] Furthermore, since etching of the cap film CP1 is performed in the manufacturing process of pore CH2, it is preferable that the manufacturing process for pore CH2 and the manufacturing process for pore CH3 are separate processes.

[0144] However, since the thickness of the cap film CP1 is relatively thin compared to the interlayer insulating film IL1, the manufacturing process for holes CH2 and CH3 may be the same, provided that the etching damage to the source and drain regions of MOSFETs 2Qn, 2Qp, 3Qn, and 3Qp is within an acceptable range. In particular, in Embodiment 1, the position of the upper surface of the gate electrode GE1 is close to the position of the upper surface of the semiconductor substrate SUB, so the time it takes for holes CH2 to reach the gate electrode GE1 can be shortened. Therefore, even if the manufacturing process for holes CH2 and CH3 is the same, the etching damage can be reduced compared to Example 1, etc.

[0145] As shown in Figures 52 and 53, plug PG is formed inside each of the holes CH1 to CH3. First, a barrier metal film is formed inside each of the holes CH1 to CH3 and on the interlayer insulating film IL1, for example by sputtering. Next, a conductive film is formed on the barrier metal film, for example by CVD, so as to fill the inside of each of the holes CH1 to CH3. Next, the barrier metal film and the conductive film formed on the outside of each of the holes CH1 to CH3 are removed, for example by anisotropic etching. This forms plug PG in the interlayer insulating film IL1. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0146] Next, a first barrier metal film, a conductive film, and a second barrier metal film are sequentially formed on the interlayer insulating film IL1, for example, by sputtering or CVD. Then, the wiring M1 for connection to the plug PG is formed on the interlayer insulating film IL1 by patterning the first barrier metal film, the conductive film, and the second barrier metal film. The first barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum film or an aluminum alloy film with copper or silicon added. The second barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film.

[0147] Subsequently, the structures shown in Figures 4 and 5 are obtained through the following manufacturing processes.

[0148] An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the wiring M1. To form the interlayer insulating film IL2, first, a first silicon oxide film is formed on the interlayer insulating film IL1, for example by a high-density plasma CVD (HDP-CVD) method. Next, a second silicon oxide film is formed on the first silicon oxide film, for example by a CVD method. Then, the first silicon oxide film and the second silicon oxide film are planarized by a polishing treatment using a CMP method. As a result, the interlayer insulating film IL2, which includes the first silicon oxide film and the second silicon oxide film, is formed.

[0149] Furthermore, a hydrogen alloy treatment may be performed after the formation of the interlayer insulating film IL2 but before the formation of the via V1 described later. This hydrogen alloy treatment is a heat treatment performed in a hydrogen atmosphere under conditions such as 400°C for 20 minutes. This hydrogen alloy treatment can terminate the dangling bonds near the top surface of the semiconductor substrate SUB and improve the variation in the threshold voltage of MOSFET1Qn.

[0150] Next, vias V1 are formed in the interlayer insulating film IL2 to connect to wiring M1. To form vias V1, first, contact holes are formed in the interlayer insulating film IL2 by photolithography and anisotropic etching. Next, a barrier metal film is formed inside the contact holes and on the interlayer insulating film IL2, for example by CVD. Next, a conductive film is formed on the barrier metal film, for example by CVD, to fill the inside of the contact holes. Finally, the barrier metal film and the conductive film formed outside the contact holes are removed, for example by anisotropic etching. This forms vias V1 in the interlayer insulating film IL2. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0151] Next, a wiring M2 is formed on the interlayer insulating film IL2 so as to connect to via V1. Then, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the wiring M2. Next, a via V2 is formed in the interlayer insulating film IL3 so as to connect to wiring M2. The manufacturing processes for wiring M2, interlayer insulating film IL3, and via V2 can be carried out using the same methods as the manufacturing processes for wiring M1, interlayer insulating film IL2, and via V1.

[0152] Furthermore, after forming the interlayer insulating film IL3 but before forming the via V2, the hydrogen alloy treatment may be performed under the same conditions as described above. The hydrogen alloy treatment may be performed only after the formation of the interlayer insulating film IL2, only after the formation of the interlayer insulating film IL3, or both.

[0153] Next, wiring M3 is formed on the interlayer insulating film IL3 to connect to via V2. To form wiring M3, first, a barrier metal film and a conductive film are sequentially formed on the interlayer insulating film IL3, for example, by sputtering or CVD. Next, wiring M3 is formed on the interlayer insulating film IL3 by patterning the barrier metal film and the conductive film. The barrier metal film is, for example, a titanium-tungsten film. The conductive film is, for example, an aluminum film or an aluminum alloy film with copper or silicon added.

[0154] Next, a protective film PVF is formed on the interlayer insulating film IL3, for example by a coating method, so as to cover the wiring M3. The protective film PVF is, for example, a polyimide film. Next, openings OP1 and OP2 are formed in the protective film PVF on the wiring M3 so that a portion of the wiring M3 is exposed (see Figures 67 and 70). The portion of the wiring M3 exposed within the openings OP1 and OP2 constitutes source pads or pads for connection to the external connection member BW.

[0155] Subsequently, the underside of the semiconductor substrate SUB is polished as needed. Next, an n-type drain region ND is formed on the underside of the semiconductor substrate SUB by introducing, for example, arsenic (As) using ion implantation. Then, a drain electrode DE is formed beneath the underside of the semiconductor substrate SUB by sputtering.

[0156] Furthermore, if the semiconductor substrate SUB is a laminate of an n-type silicon substrate and an n-type semiconductor layer, the n-type silicon substrate will be thinned by the polishing process described above. In this case, if the n-type silicon substrate remains, the remaining n-type silicon substrate can function as a drain region ND, so it is not necessary to form the drain region ND by the ion implantation method described above.

[0157] As a result, the semiconductor device 100 is manufactured.

[0158] <Pad structure> The features of the source pads and pads in Embodiment 1 will be described below with reference to Figures 66 to 70.

[0159] Figure 66 is a plan view corresponding to the enlarged area 10 enclosed by the dashed line among the source pads shown in Figure 1. Figure 67 is a cross-sectional view along the CC line in Figure 66. Although vias V1 and V2 are not actually shown in Figure 67, they are shown with dashed lines to make the hierarchical relationship of each component easier to understand.

[0160] As shown in Figures 66 and 67, in a plan view, at positions overlapping with the source pads, the wiring M2 has multiple slits SL that penetrate the wiring M2, the wiring M1 has multiple slits SL that penetrate the wiring M1, and the semiconductor substrate SUB has multiple MOSFETs 1Qn. Note that the source pads, which are part of the wiring M3, do not have such slits SL.

[0161] In wiring M1 and wiring M2, the multiple slits SL form a rectangular shape in plan view and are arranged in a matrix such that the direction of their longer sides is the direction of the columns. In Figure 66, the column direction is the Y direction and the row direction is the X direction. Furthermore, the multiple slits SL of wiring M2 are located in positions that overlap with the multiple slits SL of wiring M1 in plan view. In addition, the multiple plugs PG, multiple vias V1 and multiple vias V2 are each located between the columns of the multiple slits SL.

[0162] According to the inventors' studies, when multiple slits SL are not provided in the wiring M2 and M1 beneath the source pads PADs, it was found that when an external connection member BW is formed on the source pads PADs, cracks are likely to occur in the interlayer insulating film IL3 due to stress from the external connection member BW. Furthermore, it was found that cracks are likely to occur not only in the interlayer insulating film IL3, but also in the interlayer insulating films IL2 and IL1 below it.

[0163] As in Embodiment 1, by providing multiple slits SL in the wiring M2 and M1, the stress can more easily escape downward through the multiple slits SL. Therefore, the occurrence of cracks can be suppressed, and the reliability of the semiconductor device 100 can be improved.

[0164] Furthermore, as described above, in Embodiment 1, the hydrogen alloy treatment is performed at least one of the following: after forming the interlayer insulating film IL2 but before forming the via V1, or after forming the interlayer insulating film IL3 but before forming the via V2. This hydrogen alloy treatment terminates the dangling bonds near the top surface of the semiconductor substrate SUB, thereby improving the variation in the threshold voltage of MOSFET1Qn.

[0165] However, the inventors of this invention have found that hydrogen alloy treatment tends to be easily absorbed by the barrier metal films (titanium film and titanium nitride film) contained in wiring M1 and wiring M2. As in Embodiment 1, by providing multiple slits SL in wiring M1 and wiring M2, hydrogen can be easily passed downward through the multiple slits SL, and the hydrogen can reach near the upper surface of the semiconductor substrate SUB.

[0166] Figure 68 is a graph showing the results of an experiment conducted by the inventors of the present invention. In Figure 68, the vertical axis represents the normal probability distribution, and the horizontal axis represents the fluctuation amount (ΔVth) of the threshold voltage of MOSFET1Qn.

[0167] As shown in Figure 68, in the cases where hydrogen alloy treatment has not been performed (□, △), the slope of the graph is gentler, regardless of the presence or absence of slit SL. This means that there is a large variation in ΔVth among the multiple MOSFET1Qn within the wafer surface.

[0168] On the other hand, in the cases where hydrogen alloy treatment is performed and slit SL is provided (〇), the slope of the graph is steeper, indicating that the variation in ΔVth has improved.

[0169] Figure 69 is a plan view corresponding to each pad PAD shown in Figure 1. Figure 70 is a cross-sectional view along the DD line in Figure 69. Note that plug PG and via V2 are not actually shown in Figure 70, but they are shown with dashed lines to make the hierarchical relationships of each component easier to understand.

[0170] As shown in Figures 69 and 70, in a plan view, at a position overlapping with the pad PAD, the wiring M2 is provided with multiple slits SL that pass through it, and the wiring M1 is provided with multiple slits SL that pass through it. Note that the pad PAD, which is part of the wiring M3, does not have such slits SL.

[0171] Furthermore, in a plan view, the semiconductor substrate SUB does not have MOSFETs 2Qn, 2Qp, 3Qn, 3Qp, or resistor RS in the position where it overlaps with the pad PAD. MOSFETs 2Qn, 2Qp, 3Qn, 3Qp, and resistor RS are electrically connected to the pad PAD via other wirings M1 to M3.

[0172] In a plan view, an element isolation section (LOC) is provided on the semiconductor substrate (SUB) at the position where it overlaps with the pad (PAD). A conductive film (PL) is provided on this element isolation section (LOC). The conductive film (PL) is connected to the wiring (M1) via a plug (PG). The conductive film (PL) is a film of the same layer as the conductive film (CF2) or conductive film (CF3), and is formed using the same process as those films.

[0173] Furthermore, within the semiconductor substrate SUB located beneath the conductive film PL (below the element isolation section LOC), p-type well regions HPW0 and PW0 are formed so as to surround the conductive film PL and the element isolation section LOC in a plan view. Well region PW0 is formed within well region HPW0. Well regions HPW0 and PW0 are not electrically connected to each MOSFET and wiring M1~M3, etc., and are electrically floating. Note that well region HPW0 is formed in the same process as well region HPW, and well region PW0 is formed in the same process as well regions PW1~PW3.

[0174] Even beneath the pad, in wiring M1 and wiring M2, the multiple slits SL form a rectangular shape in plan view, and are arranged in a matrix such that the longer side of these slits aligns with the column direction. Furthermore, the multiple slits SL of wiring M2 are positioned to overlap with the multiple slits SL of wiring M1 in plan view. In addition, the multiple plugs PG, multiple vias V1, and multiple vias V2 are each provided between the rows of multiple slits SL.

[0175] The presence of multiple slits SL in wiring M2 and M1 allows stress from the external connection member BW to escape downward through the multiple slits SL when the external connection member BW is formed on the pad PAD. Therefore, crack formation can be suppressed even under the pad PAD, thereby improving the reliability of the semiconductor device 100.

[0176] (Embodiment 2) The semiconductor device 100 and its manufacturing method in Embodiment 2 will be described below with reference to Figures 71 to 76. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0177] In Embodiment 1, a silicon nitride film SN1 was provided between the semiconductor substrate SUB and the interlayer insulating film IL1 in regions 1A to 4A. In Embodiment 2, the silicon nitride film SN1 in regions 2A to 4A is retained, but the silicon nitride film SN1 in region 1A is removed.

[0178] Figure 71 shows the manufacturing process after the formation of the holes CH1 in Figure 46. As shown in Figure 71, in Embodiment 2, the interlayer insulating film IL1 is recessed by isotropic etching. For this isotropic etching, an aqueous solution containing hydrofluoric acid is used, for example. As a result, the opening width of the holes CH1 located on the upper surface of the semiconductor substrate SUB becomes wider than the opening width of the holes CH1 in the semiconductor substrate SUB. The amount of recession of the interlayer insulating film IL1 due to the isotropic etching is, for example, 20 nm or more and 40 nm or less.

[0179] By widening the opening width of hole CH1, the aspect ratio is improved when forming the plug PG shown in Figure 52. This makes it easier to properly embed the plug PG inside hole CH1. Furthermore, by receding the interlayer insulating film IL1, the upper surface of the source region NS is exposed. Consequently, the plug PG not only contacts the side surface of the source region NS inside hole CH1, but also contacts the upper surface of the source region NS. This reduces the contact resistance between the plug PG and the source region NS.

[0180] Figure 72 shows the manufacturing process of a semiconductor device in Study Example 4. Note that Study Example 4 is not prior art, but rather new findings obtained through the inventors of the present invention.

[0181] First, to obtain the pore CH1 shown in Figure 71, the silicon nitride film SN1 in region 1A must be removed. However, as in Study Example 4, if a silicon oxide film is formed between the semiconductor substrate SUB and the silicon nitride film SN1, isotropic etching will cause not only the interlayer insulating film IL1 but also the silicon oxide film to recede. Such a silicon oxide film can be, for example, a through-film used when forming the source region NS in ion implantation as shown in Figure 36. Here, the silicon oxide film used in ion implantation as shown in Figure 36 is shown as the through-film TH2.

[0182] By receding both the interlayer insulating film IL1 and the through-film TH2, the upper surface of the source region NS is exposed. However, since the silicon nitride film SN1 remains in an overhang shape, when forming the barrier metal film of the plug PG, areas where it is difficult to deposit the barrier metal film occur inside the hole CH1. For example, it is difficult to uniformly deposit the barrier metal film in the space between the overhang-shaped silicon nitride film SN1 and the upper surface of the semiconductor substrate SUB. Consequently, areas where the barrier metal film is broken are likely to occur inside the hole CH1, and such areas become a cause of defects. Considering these problems, when widening the opening width of the hole CH1, it is preferable to remove the silicon nitride film SN1 in region 1A.

[0183] Figures 73 to 76 show the manufacturing process that takes place between the manufacturing process in Figure 36 and the manufacturing process in Figure 38, and illustrate the process of selectively removing the silicon nitride film SN1 in region 1A. Regions 3A and 4A are described in much the same way as region 2A, so their illustrations are omitted. Furthermore, in the state shown in Figure 73, the through-film TH2 may or may not be present. Here, we illustrate the case where the through-film TH2 has been removed.

[0184] As shown in Figure 73, after forming the silicon nitride film SN1 in Figure 36, an insulating film IF7 made of silicon oxide is formed on the silicon nitride film SN1, for example by CVD. The thickness of the insulating film IF7 is, for example, 10 nm or more and 30 nm or less.

[0185] As shown in Figure 74, first, a resist pattern RP5 is formed on the insulating film IF7 so as to open up region 1A and cover regions 2A to 4A. Next, the insulating film IF7 in region 1A is removed by anisotropic etching using the resist pattern RP5 as a mask. Then, the resist pattern RP5 is removed by ashing.

[0186] As shown in Figure 75, the silicon nitride film SN1 in region 1A is removed by performing isotropic etching using an aqueous solution containing phosphoric acid, with the insulating film IF7 in regions 2A to 4A as a mask. Subsequently, the insulating film IF7 may be removed by performing isotropic etching using an aqueous solution containing hydrofluoric acid, or the insulating film IF7 may be left in regions 2A to 4A. If the insulating film IF7 is left, it constitutes part of the interlayer insulating film IL1, similar to the insulating film IF5.

[0187] From the manufacturing process shown in Figure 75 onward, the same manufacturing process as in Embodiment 1 is carried out. Figure 76 shows the sequential formation of the insulating film IF5, the silicon nitride film SN2, and the insulating film IF6, which consists of the silicon oxide film, as explained in Figure 38.

[0188] Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of Symbols]

[0189] 100 Semiconductor Devices 10. Expanded Area 1A area (output circuit area) 2A, 3A, 4A area (control circuit area) 1Qn, 2Qn, 3Qn n-type MOSFETs 2Qp, 3Qp p-type MOSFETs BW External connection components CF1~CF3 Conductive film CP1~CP3 cap film CH1~CH3 holes DE drain electrode GE1~GE3 TT GI1~GI3 Gate Insulator GW gate wiring HM1, HM2 Hard Mask HPW, HPW0 well region IF1~IF7 Insulate Circuit IL1~IL3 Interlayer Insulation Film LOC element isolation section M1~M3 Wiring N1, N2 impurity region ND drain area NS source area NV drift region NW1~NW3 Well Area OP0~OP2 opening P1, P2 impurity region PAD PADs Source Pad PB Body Area PC, PC1-PC3 Column Area PG Plug PL conductive film PR High-concentration diffusion area PVF protective film PW0~PW3 well area RP1~RP5 Resist Pattern RS Resistor SE source electrode SL Slit SN1, SN2 silicon nitride films SUB Semiconductor Substrate SW Sidewall Spacer TH1, TH2 through-film TR Trench V1, V2 Via

Claims

1. A method for manufacturing a semiconductor device having a first region where a first MOSFET is formed and a second region where a second MOSFET is formed, A step of preparing a first-type conductive semiconductor substrate having an upper surface, A step of forming a first well region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate of the second region, A step of forming a first hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate, A step of forming a trench in the semiconductor substrate exposed from the first hard mask in the first region, After the step of forming the trench, the step of forming a first gate insulating film inside the trench, The process involves forming a first conductive film on the first gate insulating film and on the first hard mask, after the step of forming the first gate insulating film. After the step of forming the first conductive film, the first conductive film on the first hard mask is removed by performing an anisotropic etching treatment on the first conductive film, and a first gate electrode is formed inside the trench so as to fill the inside of the trench via the first gate insulating film. After the step of forming the first gate electrode, the step of forming a cap film made of an insulating film on the upper surface of the first gate electrode, After the step of forming the cap film, the first hard mask is removed, The process involves removing the first hard mask, followed by forming a second gate insulating film on the first well region, A step of forming a second conductive film on the second gate insulating film and the cap film, A step of forming a second gate electrode on the second gate insulating film by patterning the second conductive film by performing an anisotropic etching process, Equipped with, The first MOSFET includes the first gate insulating film and the first gate electrode. A method for manufacturing a semiconductor device, comprising the second MOSFET, the second gate insulating film, and the second gate electrode.

2. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the cap film is formed by oxidizing a part of the first gate electrode by thermal oxidation treatment.

3. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein, after the step of forming the cap film, the position of the upper surface of the cap film is higher than the position of the upper surface of the semiconductor substrate.

4. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the thickness of the cap film is greater than the thickness of the first gate insulating film.

5. In the method for manufacturing a semiconductor device according to claim 1, After the step of forming the first well region, the first heat treatment is performed on the first well region. Equipped with, A method for manufacturing a semiconductor device, wherein the step of forming the trench is performed after the step of performing the first heat treatment.

6. In the method for manufacturing a semiconductor device according to claim 5, A method for manufacturing a semiconductor device, wherein the first heat treatment is performed while a silicon nitride film is not formed on the upper surface of the semiconductor substrate.

7. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the first gate insulating film is formed while the first hard mask remains.

8. In the method for manufacturing a semiconductor device according to claim 1, The first hard mask consists of a silicon nitride film, A method for manufacturing a semiconductor device, wherein the first hard mask is removed by isotropic etching using an aqueous solution containing phosphoric acid.

9. In the method for manufacturing a semiconductor device according to claim 1, The first MOSFET includes a drift region, The semiconductor substrate is a semiconductor manufacturing method comprising the drift region.

10. In the method for manufacturing a semiconductor device according to claim 9, A step of forming the second conductivity type body region in the semiconductor substrate of the first region such that it is shallower than the depth of the trench, The steps include forming a first source region of the first conductivity type within the body region, Furthermore, A method for manufacturing a semiconductor device, comprising the first MOSFET including the first gate insulating film, the first gate electrode, the body region, the drift region, and the first source region.

11. In the method for manufacturing a semiconductor device according to claim 1, The steps include forming a second well region of the second conductivity type within the first well region, The process involves forming a third well region of the first conductivity type within the first well region, The steps include forming a second source region of the first conductivity type in the second well region, The process involves forming a second drain region of the first conductivity type within the third well region, Furthermore, The second gate insulating film is formed on the second well region and the third well region, A method for manufacturing a semiconductor device, comprising the second MOSFET including the second gate insulating film, the second gate electrode, the second source region, and the second drain region.

12. In the method for manufacturing a semiconductor device according to claim 1, The steps include forming a second well region of the second conductivity type within the first well region, The process involves forming a second source region of the first conductivity type and a second drain region of the first conductivity type in the second well region, Furthermore, The second gate insulating film is formed on the second well region, A method for manufacturing a semiconductor device, comprising the second MOSFET including the second gate insulating film, the second gate electrode, the second source region, and the second drain region.

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