Semiconductor equipment

Abstract

The present invention provides a semiconductor device that improves ohmic contact between the source electrode and the channel layer, thereby reducing contact resistance, and also improves alignment between the gate electrode layer and the gate semiconductor layer. [Solution] The device comprises a channel layer, a barrier layer disposed on the channel layer, a gate electrode layer disposed on the barrier layer and extending in a first direction horizontal to the upper surface of the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode layer, and source and drain electrodes connected to the channel layer and disposed horizontal to the upper surface of the barrier layer and separated from the gate electrode layer in a second direction different from the first direction, further comprising a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, wherein in cross-sections cut in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the gate electrode layer in the second direction is smaller than the length of the lower surface of the gate electrode layer in the second direction from which it contacts the upper surface of the gate semiconductor layer.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can improve ohmic contact between the source electrode and the channel layer, thereby reducing contact resistance, while also improving alignment between the gate electrode layer and the gate semiconductor layer. [Background technology]

[0002] In modern society, semiconductor devices are closely related to our daily lives. In particular, the importance of power semiconductor equipment used in a variety of fields, such as transportation (electric vehicles, railways, electric trams, etc.), renewable energy systems (solar power, wind power, etc.), and mobile devices, is steadily increasing. Power semiconductor devices are semiconductor devices used to handle high voltages and high currents, and perform functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices possess the ability and durability to handle high power, can handle large amounts of current, and can withstand high voltages. For example, power semiconductor devices handle voltages ranging from several hundred to several thousand volts and currents ranging from tens to several thousand amperes. Power semiconductor devices can minimize power loss and improve the efficiency of electrical energy. Furthermore, power semiconductor devices can be operated stably even in environments with high temperatures.

[0003] Such power semiconductor devices can be classified by material, for example, SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon wafers (Si wafers) to manufacture power semiconductor devices, the disadvantages of silicon, such as its unstable properties at high temperatures, can be compensated for. SiC power semiconductor devices are resistant to high temperatures while having low power loss, making them suitable for electric vehicles, renewable energy systems, and other applications. GaN power semiconductor devices require high costs, but they are efficient in terms of speed and may be suitable for applications such as fast charging of mobile devices. Further development and improvement of these power semiconductor devices are ongoing challenges. [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention has been made in view of the problems in the above-mentioned conventional semiconductor devices, and the object of the present invention is to provide a semiconductor device that can improve the ohmic contact between the source electrode and the channel layer, thereby reducing contact resistance, while also improving the alignment between the gate electrode layer and the gate semiconductor layer. [Means for solving the problem]

[0005] To achieve the above objective, the semiconductor device according to the present invention comprises a channel layer, a barrier layer disposed on the channel layer, a gate electrode layer disposed on the barrier layer and extending in a first direction horizontal to the upper surface of the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode layer, and a source electrode and a drain electrode connected to the channel layer and disposed horizontal to the upper surface of the barrier layer and spaced apart from the gate electrode layer in a second direction different from the first direction, further comprising a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, characterized in that, in a cross section cut in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the gate electrode layer in the second direction is smaller than the length of the lower surface of the gate electrode layer in the second direction in contact with the upper surface of the gate semiconductor layer.

[0006] Furthermore, a semiconductor device according to the present invention made to achieve the above objectives includes a channel layer, a barrier layer disposed on the channel layer, a gate electrode layer disposed on the barrier layer and extending in a first direction horizontal to the upper surface of the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode layer, and a source electrode and a drain electrode connected to the channel layer and disposed horizontal to the upper surface of the barrier layer and spaced apart from the gate electrode layer in a second direction different from the first direction, and further having a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, wherein the source electrode has a first portion located on the first barrier layer doping region and a second portion protruding from the first portion toward the first barrier layer doping region and located within the first barrier layer doping region, and in a cross-section cut in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the second portion in the second direction is greater than the length of the lower surface of the second portion in the second direction.

[0007] Furthermore, the semiconductor device according to the present invention, made to achieve the above objective, comprises a channel layer, a barrier layer disposed on the channel layer, a gate electrode layer disposed on the barrier layer and extending in a first direction horizontal to the upper surface of the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode layer, and a source electrode and a drain electrode connected to the channel layer and disposed horizontal to the upper surface of the barrier layer and separated from the gate electrode layer in a second direction different from the first direction, and further comprising a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, and the source The electrode has a first portion located on the first barrier layer doping region and a second portion projecting from the first portion toward the first barrier layer doping region and located within the first barrier layer doping region, and in a cross-section cut in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the second portion in the second direction is greater than the length of the lower surface of the second portion in the second direction, and the length of the upper surface of the gate electrode layer in the second direction is less than the length in the second direction at which the lower surface of the gate electrode layer contacts the upper surface of the gate semiconductor layer.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a gate semiconductor material layer on the barrier layer; forming a first barrier layer doping region by ion doping a portion of the barrier layer; forming a gate electrode material layer on the gate semiconductor material layer; etching the gate electrode material layer to form a gate electrode layer; etching the gate semiconductor material layer to form a gate semiconductor layer; and forming a source electrode that is connected to the first barrier layer doping region and separated from the gate electrode layer.

[0009] When a portion of the barrier layer is ion-doped to form a first barrier layer doped region, the gate semiconductor material layer is also ion-doped to form a first gate semiconductor material layer doped region, and the channel layer is also ion-doped to form a first channel layer doped region. The first step in forming the first barrier layer doping region involves forming a first photoresist pattern on the gate semiconductor material layer, ion doping a portion of the barrier layer using the first photoresist pattern via ion implantation (IIP), and annealing at 1100°C to 2000°C. After forming the first barrier layer doping region, the first gate semiconductor material layer doping region is etched and removed using the first photoresist pattern to expose the first barrier layer doping region. A portion of the surface of the first barrier layer doping region is etched to form a first recess on the surface of the first barrier layer doping region. The first barrier layer doping region is formed by creating a first photoresist pattern on the gate semiconductor material layer, etching a portion of the gate semiconductor material layer using the first photoresist pattern to expose a portion of the barrier layer, etching a portion of the surface of the barrier layer to form a first recess on the surface of the barrier layer, ion doping a portion of the barrier layer using the first photoresist pattern via ion implantation (IIP), and annealing at 1100°C to 2000°C. The steps for forming the first barrier layer doping region involve forming a first hard mask material layer on the gate semiconductor material layer, forming a first photoresist pattern on the first hard mask material layer, etching the first hard mask material layer using the first photoresist pattern to form a first hard mask layer, etching a portion of the gate semiconductor material layer using the first hard mask layer to expose a portion of the barrier layer, etching a portion of the surface of the barrier layer to form a first recess on the surface of the barrier layer, ion doping a portion of the barrier layer using the first hard mask layer via ion implantation (IIP), and annealing at 1100°C to 2000°C.

[0010] The step of forming the source electrode involves forming a barrier layer, a gate semiconductor layer, a gate electrode layer, and a first protective layer covering the first barrier doping region. A portion of the first protective layer is etched to expose the first barrier doping region, and the source electrode is formed on top of the first barrier doping region. The step of forming the source electrode involves forming a barrier layer, a gate semiconductor layer, a gate electrode layer, and a first protective layer covering the first barrier doping region. A portion of the first protective layer is etched to expose the first barrier doping region and the first channel layer doping region. A portion of the surface of the first channel layer doping region is etched to form a second recess on the surface of the first channel layer doping region, and the source electrode is formed on the first channel doping region. When forming a first barrier layer doping region by ion doping a portion of the barrier layer, a second barrier layer doping region is further formed by ion doping another portion of the barrier layer, a second channel layer doping region is further formed by ion doping another portion of the channel layer, and when forming the source electrode, a drain electrode is further formed so as to be connected to the second barrier layer doping region and separated from the gate electrode layer and the source electrode. The step of forming the gate electrode layer involves forming a second hard mask material layer on the gate electrode material layer, forming a second photoresist pattern on the second hard mask material layer, and etching the second hard mask material layer and the gate electrode material layer using the second photoresist pattern to form the second hard mask layer and the gate electrode layer. The step of forming the gate semiconductor layer involves removing the second photoresist pattern and using the second hard mask layer to etch the gate semiconductor material layer to form the gate semiconductor layer. [Effects of the Invention]

[0011] According to the semiconductor device of the present invention, the first and second barrier layer doping regions and the first and second channel layer doping regions disposed in the barrier layer improve the ohmic contact between the source electrode and the drain electrode and the channel layer, reducing the contact resistance, and also improving the alignment between the gate electrode layer and the gate semiconductor layer.

Brief Description of the Drawings

[0012] [Figure 1] It is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view taken along the line A-A' of FIG. 1. [Figure 3] It is an enlarged cross-sectional view of the P portion in FIG. 2. [Figure 4] It is an enlarged cross-sectional view of the Q portion in FIG. 2. [Figure 5] It is a cross-sectional view according to another embodiment of the present invention, which is an enlarged cross-sectional view of the P portion in FIG. 2. [Figure 6] It is a cross-sectional view according to another embodiment of the present invention, which is an enlarged cross-sectional view of the P portion in FIG. 2. [Figure 7] It is a cross-sectional view according to another embodiment of the present invention, which is an enlarged cross-sectional view of the P portion in FIG. 2. [Figure 8] It is a cross-sectional view according to another embodiment of the present invention, which is an enlarged cross-sectional view of the P portion in FIG. 2. [Figure 9] It is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' of FIG. 1. [Figure 10] It is an enlarged cross-sectional view of the Q portion in FIG. 9. [Figure 11] It is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' of FIG. 1. [Figure 12] It is an enlarged cross-sectional view of the Q portion in FIG. 11. [Figure 13] It is a cross-sectional view according to another embodiment of the present invention, which is an enlarged cross-sectional view of the Q portion in FIG. 11. [Figure 14]This is a cross-sectional view according to another embodiment of the present invention, taken along the line A-A' in Figure 1. [Figure 15] This is an enlarged cross-sectional view of portion Q in Figure 14. [Figure 16] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 14. [Figure 17] This is a cross-sectional view according to another embodiment of the present invention, taken along the line A-A' in Figure 1. [Figure 18] This is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 19] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 20] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 21] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 22] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 23] This is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. [Figure 24] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 30] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 31] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 32] This is a cross-sectional view illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 33] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 34] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 35] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 36] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 37] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 38] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 39] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 40] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Modes for carrying out the invention]

[0013] Next, specific examples of embodiments for implementing the semiconductor device according to the present invention will be described with reference to the drawings.

[0014] The present invention can be realized in a variety of different forms and is not limited to the embodiments described herein. To clearly explain the present invention, unnecessary explanatory parts have been omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrary for the sake of explanation, and the present invention is not necessarily limited to what is shown in the drawings. In the drawings, the thickness is shown enlarged to clearly represent various layers and regions. Furthermore, in the drawings, the thickness of some layers and areas is exaggerated for the sake of explanation. Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only the case where it is "directly on top of" another part, but also the case where there is yet another part in between. Conversely, when one part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on top of" a reference point means being located above or below the reference point, and does not necessarily mean being located "on top of" the opposite direction of gravity.

[0015] Furthermore, when a specification states that a certain part "includes" a certain component, unless otherwise stated, this means that it may include other components rather than excluding them. Furthermore, throughout the specification, "on a plane" refers to the view of the subject from above, and "on a cross-section" refers to the view of a cross-section obtained by cutting the subject perpendicularly, viewed from the side. Furthermore, throughout the specification, the two directions parallel to and intersecting the upper surface of the substrate are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as the third direction D3. For example, the first direction D1 and the second direction D2 are orthogonal to each other.

[0016] Figure 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; Figure 2 is a cross-sectional view taken along the line A-A' in Figure 1; Figure 3 is an enlarged cross-sectional view of portion P in Figure 2; and Figure 4 is an enlarged cross-sectional view of portion Q in Figure 2. For clear understanding and simplified illustration, Figure 1 primarily shows the channel layer 132, gate electrode layer 155, source electrode 173, field dispersion layer 177, and drain electrode 175.

[0017] Referring to Figures 1 to 4, the semiconductor device includes a channel layer 132, a barrier layer 136 placed on the channel layer 132, a gate electrode layer 155 placed on the barrier layer 136, a gate semiconductor layer 152 placed between the barrier layer 136 and the gate electrode layer 155, and source electrodes 173 and drain electrodes 175 placed on both sides of the gate electrode layer 155 and connected to the channel layer 132. The channel layer 132 is a layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 is arranged inside the channel layer 132.

[0018] The two-dimensional electron gas 134 is a charge transport model used in solid-state physics, representing a group of electrons that can move freely in two dimensions (e.g., in the D1-D2 plane) but are rigidly constrained within those two dimensions and cannot move in other dimensions (e.g., in the D3 direction). In other words, the two-dimensional electron gas 134 exists in three-dimensional space in a form similar to two-dimensional paper. Such two-dimensional electron gases 134 mainly appear in semiconductor heterogeneous junction structures, and in semiconductor devices according to embodiments of the present invention, they can be generated at the interface between the channel layer 132 and the barrier layer 136. For example, a two-dimensional electron gas 134 may be generated in the channel layer 132 in the portion closest to the barrier layer 136.

[0019] The channel layer 132 may contain nitrides comprising Group III-V materials, such as Al, Ga, In, B, or combinations thereof. The channel layer 132 may consist of one or multiple layers. As an example, channel layer 132 is Al x In y Ga 1-x-yN includes (0≦x≦1, 0≦y≦1, x+y≦1), and for example, the channel layer 132 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The channel layer 132 is a doped layer with impurities, or it may be an undoped layer. The thickness of channel layer 132 is approximately several hundred nanometers or less. The channel layer 132 is placed on the substrate 110, and a seed layer 115 or a buffer layer 120 is placed between the substrate 110 and the channel layer 132.

[0020] The substrate 110, seed layer 115, or buffer layer 120 are necessary layers for forming the channel layer 132, and may be omitted in some cases. For example, when using a GaN substrate as the channel layer 132, at least one of the substrate 110, seed layer 115, or buffer layer 120 can be omitted. Considering that GaN substrates are relatively expensive, a Si substrate 110 is used to grow a GaN-containing channel layer 132. In this case, the difference in lattice structures between Si and GaN can make it difficult to grow the channel layer 132 directly on top of the substrate 110. As a result, the seed layer 115 and buffer layer 120 are grown first on the substrate 110, and then the channel layer 132 is grown on top of the buffer layer 120. Furthermore, at least one of the substrate 110, seed layer 115, or buffer layer 120 may be removed in the final structure of the semiconductor device after being used in the manufacturing process.

[0021] The first channel layer doping region 1321 is located within the channel layer 132. The first channel layer doping region 1321 is located above the channel layer 132. In other words, the level of the upper surface (US_1321) of the first channel layer doping region 1321 in the third direction D3 is the same as the level of the upper surface (US_132) of the channel layer 132 in the third direction D3, and the upper surface (US_1321) of the first channel layer doping region 1321 and the upper surface (US_132) of the channel layer 132 are coplanar. Similarly, the second channel layer doping region 1322 is located within the channel layer 132. The second channel layer doping region 1322 is located above the channel layer 132. In other words, the level of the upper surface of the second channel layer doping region 1322 in the third direction D3 is the same as the level of the upper surface of the channel layer 132 in the third direction D3, and the upper surface of the second channel layer doping region 1322 and the upper surface of the channel layer 132 are coplanar.

[0022] The first channel layer doping region 1321 extends from the upper surface (US_132) of the channel layer 132 toward the lower surface of the channel layer 132. That is, the first channel layer doping region 1321 extends downward in the third direction D3 from the upper surface (US_132) of the channel layer 132. However, the lower surface of the first channel layer doping region 1321 extends downward in the third direction D3, but does not penetrate the channel layer 132, and the lower surface of the first channel layer doping region 1321 is located within the channel layer 132. In other words, the level of the lower surface of the first channel layer doping region 1321 in the third direction D3 is higher than the level of the lower surface of the channel layer 132 in the third direction D3. Similarly, the second channel layer doping region 1322 extends from the upper surface of the channel layer 132 toward the lower surface of the channel layer 132. In other words, the second channel layer doping region 1322 extends downward in the third direction D3 from the upper surface of the channel layer 132. However, the lower surface of the second channel layer doping region 1322 extends downward in the third direction D3, but does not penetrate the channel layer 132, and the lower surface of the second channel layer doping region 1322 is located within the channel layer 132. In other words, the level of the lower surface of the second channel layer doping region 1322 in the third direction D3 is higher than the level of the lower surface of the channel layer 132 in the third direction D3.

[0023] Here, the level of the upper surface (US_1321) of the first channel layer doping region 1321 in the third direction D3 is, for example, the shortest distance from the upper surface of the substrate 110 to the upper surface (US_1321) of the first channel layer doping region 1321 in the third direction D3. Similarly, the level of the lower surface of the first channel layer doping region 1321 toward the third direction D3, the level of the upper surface of the second channel layer doping region 1322 toward the third direction D3, the level of the lower surface of the second channel layer doping region 1322 toward the third direction D3, the level of the upper surface (US_132) of the channel layer 132 toward the third direction D3, and the level of the lower surface of the channel layer 132 toward the third direction D3 are the shortest distances from the upper surface of the substrate 110 toward the third direction D3.

[0024] The first channel layer doping region 1321 is located beneath the source electrode 173. In other words, at least a portion of the first channel layer doping region 1321 is superimposed on the source electrode 173 in the third direction D3. On the other hand, the first channel layer doping region 1321 does not overlap with the gate electrode layer 155 and the drain electrode 175 in the third direction D3. The second channel layer doping region 1322 is located below the drain electrode 175. In other words, at least a portion of the second channel layer doping region 1322 is superimposed on the drain electrode 175 and the third direction D3. On the other hand, the second channel layer doping region 1322 does not overlap with the gate electrode layer 155 and the source electrode 173 in the third direction D3. In other words, the first channel layer doping region 1321 and the second channel layer doping region 1322 are separated from each other in the second direction D2, and the gate electrode layer 155 and the gate semiconductor layer 152 are positioned between the first channel layer doping region 1321 and the second channel layer doping region 1322. The gate electrode layer 155 and the gate semiconductor layer 152 are separated from the first channel layer doping region 1321 and the second channel layer doping region 1322 in the second direction D2.

[0025] The source electrode 173 is electrically connected to the first channel layer doping region 1321 on one side of the gate electrode layer 155 in the second direction D2. For example, the source electrode 173 is electrically connected to the first channel layer doping region 1321 through the first barrier layer doping region 1361, which will be described later. The first channel layer doping region 1321 is in ohmic contact with the source electrode 173. The doping region 1321 in the first channel layer reduces the contact resistance between the source electrode 173 and the channel layer 132. The drain electrode 175 is electrically connected to the second channel layer doping region 1322 on the other side of the gate electrode layer 155 in the second direction D2. For example, the drain electrode 175 is electrically connected to the second channel layer doping region 1322 through the second barrier layer doping region 1362, which will be described later. The second channel layer doping region 1322 can make ohmic contact with the drain electrode 175. The second channel layer doping region 1322 reduces the contact resistance between the drain electrode 175 and the channel layer 132.

[0026] The first channel layer doping region 1321 and the second channel layer doping region 1322 are extended in a plane (e.g., Figure 1) along the first direction D1. That is, the first channel layer doping region 1321 and the second channel layer doping region 1322 have a rod shape that extends long along the first direction D1 on a plane. The first channel layer doping region 1321 and the second channel layer doping region 1322 are extended in directions parallel to each other. The first channel layer doping region 1321 and the second channel layer doping region 1322 are extended in a direction parallel to the gate electrode layer 155. The first channel layer doping region 1321 and the second channel layer doping region 1322 can be formed in at least a portion of the channel layer 132 by an ion implantation method, such as an ion implantation (IIP) method.

[0027] The first channel layer doping region 1321 and the second channel layer doping region 1322 contain the same material as the channel layer 132. For example, the first channel layer doping region 1321 and the second channel layer doping region 1322 may contain group III-V materials, such as nitrides containing Al, Ga, In, B, or combinations thereof. As an example, the first channel layer doping region 1321 and the second channel layer doping region 1322 are each doped with n-type doping. For example, the first channel layer doping region 1321 and the second channel layer doping region 1322 are Al x In y Ga 1-x-y N includes (0≦x≦1, 0≦y≦1, x+y≦1) and is doped with either silicon (Si) or germanium (Ge). However, this is not limited to the above; the substances, doping types, etc., of the first channel layer doping region 1321 and the second channel layer doping region 1322 can be changed in various ways without limitation.

[0028] The substrate 110 contains a semiconductor material. For example, the substrate 110 may include sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may also be an SOI (Silicon on Insulator) substrate. However, the material of the substrate 110 is not limited thereto, and all commonly used substrates can be applied. In some cases, the substrate 110 may contain an insulating substance. For example, after various layers including the channel layer 132 are first formed on a semiconductor substrate, the semiconductor substrate can be removed and replaced with an insulating substrate.

[0029] The seed layer 115 is disposed on the substrate 110. The seed layer 115 is disposed directly above the substrate 110. However, it is not limited thereto, and a predetermined other layer may be further disposed between the substrate 110 and the seed layer 115. [[ID=1'sub]]The seed layer 115 is a layer that serves as a seed for growing the buffer layer 120 and is composed of a crystal lattice structure that becomes the seed of the buffer layer 120. For example, the seed layer 115 contains AlN, but is not limited thereto. The buffer layer 120 is disposed on the seed layer 115. The buffer layer 120 is disposed directly above the seed layer 115. However, it is not limited thereto, and a predetermined other layer may be further disposed between the seed layer 115 and the buffer layer 120. <000,0289>

[0030] The buffer layer 120 is disposed between the seed layer 115 and the channel layer 132. The buffer layer 120 may contain a nitride containing a group III-V substance, such as Al, Ga, In, B, or a combination thereof. The buffer layer 120 is Al x In y Ga 1-x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1), and for example, the buffer layer 120 may contain AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The buffer layer 120 may be composed of a single layer or multiple layers. Note: In your original text, there seems to be a formatting issue in line 15 where it says "シード層115は、バッファー層120を成長させるためのシード役割を果たす層であって、バッファー層120のシードになる結晶格子構造物からなる。". I've tried to make the translation as accurate as possible while maintaining the structure. If you have any specific corrections or clarifications regarding the source text, please let me know.For example, the buffer layer 120 includes a superlattice layer and a high-resistivity layer. The superlattice layer is designed to alleviate the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 132, thereby reducing the tensile stress and compressive stress generated between the substrate 110 and the channel layer 132. The high-resistance layer prevents leakage current from flowing through the channel layer 132, thereby preventing degradation of the semiconductor device according to the embodiment of the present invention. For this reason, the high-resistance layer is made of a material with low conductivity so that the substrate 110 and the channel layer 132 are electrically insulated.

[0031] The barrier layer 136 is placed on top of the channel layer 132. The barrier layer 136 is positioned directly above the channel layer 132. However, the system is not limited to this, and other predetermined layers may be further arranged between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 that overlaps with the barrier layer 136 becomes the drift region (DTR). The drift region DTR is located between the source electrode 173 and the drain electrode 175. When a potential difference is generated between the source electrode 173 and the drain electrode 175, carriers move in the drift region DTR. The semiconductor device is turned on or off depending on whether a voltage is applied to the gate electrode layer 155 and the magnitude of the voltage applied to the gate electrode layer 155. When a voltage above the threshold voltage is applied to the gate electrode layer 155, and the semiconductor device is in the ON state, a channel is generated in the depletion region DPR. This causes the carrier to move in the drift region (DTR). If a voltage lower than the threshold voltage is applied to the gate electrode layer 155, or if no voltage is applied, the channel path is blocked in the depletion region DPR, and carrier movement does not occur.

[0032] The barrier layer 136 may contain a group III-V material, such as a nitride containing Al, Ga, In, B, or a combination thereof. Barrier layer 136 is Al x In y Ga 1-x-y N includes (0≦x≦1, 0≦y≦1, x+y≦1), and for example, the barrier layer 136 may include GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or a combination thereof. The energy band gap of the barrier layer 136 can be adjusted by the composition ratio of Al or In. The barrier layer 136 is doped with a predetermined impurity. At this time, the impurities doped into the barrier layer 136 are p-type dopants that can provide holes. For example, the impurity doped into the barrier layer 136 is magnesium (Mg). By increasing or decreasing the impurity doping concentration of the barrier layer 136, the threshold voltage, on-resistance, and other properties of the semiconductor device can be adjusted.

[0033] The barrier layer 136 contains a semiconductor material having different properties from the channel layer 132. The barrier layer 136 may differ from the channel layer 132 in at least one of the following: polarization characteristics, energy band gap, and lattice constant. For example, the barrier layer 136 contains a material having a different energy band gap than the channel layer 132. At this time, the barrier layer 136 has a higher energy band gap and a higher electrical polarizability than the channel layer 132. Such a barrier layer 136 induces a two-dimensional electron gas 134 in the channel layer 132, which has a relatively low electrical polarizability. For these reasons, the barrier layer 136 is also called a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 is formed within a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 has very high electron mobility.

[0034] The first barrier layer doping region 1361 is located within the barrier layer 136. The first barrier layer doping region 1361 is located on top of the barrier layer 136. In other words, the level of the upper surface (US_1361) of the first barrier layer doping region 1361 in the third direction D3 is the same as the level of the upper surface (US_136) of the barrier layer 136 in the third direction D3, and the upper surface (US_1361) of the first barrier layer doping region 1361 and the upper surface (US_136) of the barrier layer 136 are coplanar. Similarly, the second barrier layer doping region 1362 is located within the barrier layer 136. The second barrier layer doping region 1362 is located on top of the barrier layer 136. In other words, the level of the upper surface of the second barrier layer doping region 1362 in the third direction D3 is the same as the level of the upper surface of the barrier layer 136 in the third direction D3, and the upper surface of the second barrier layer doping region 1362 and the upper surface of the barrier layer 136 are coplanar.

[0035] The first barrier layer doping region 1361 extends from the upper surface of the barrier layer 136 toward the lower surface of the barrier layer 136. In other words, the first barrier layer doping region 1361 extends downward in the third direction D3 from the upper surface of the barrier layer 136. However, the lower surface of the first barrier layer doping region 1361 extends downward in the third direction D3, but does not penetrate the barrier layer 136, and the lower surface of the first barrier layer doping region 1361 is located within the barrier layer 136. In other words, the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3 is higher than the level of the lower surface of the barrier layer 136 in the third direction D3.

[0036] Similarly, the second barrier layer doping region 1362 extends from the upper surface of the barrier layer 136 toward the lower surface of the barrier layer 136. In other words, the second barrier layer doping region 1362 extends downward in the third direction D3 from the upper surface of the barrier layer 136. However, the lower surface of the second barrier layer doping region 1362 extends downward in the third direction D3, but does not penetrate the barrier layer 136, and the lower surface of the second barrier layer doping region 1362 is located within the barrier layer 136. In other words, the level of the lower surface of the second barrier layer doping region 1362 in the third direction D3 is higher than the level of the lower surface of the barrier layer 136 in the third direction D3.

[0037] Here, the level of the upper surface (US_1361) of the first barrier layer doping region 1361 in the third direction D3 is, for example, the shortest distance from the upper surface of the substrate 110 to the upper surface (US_1361) of the first barrier layer doping region 1361 in the third direction D3. Similarly, the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3, the level of the upper surface of the second barrier layer doping region 1362 in the third direction D3, the level of the lower surface of the second barrier layer doping region 1362 in the third direction D3, the level of the upper surface (US_136) of the barrier layer 136 in the third direction D3, and the level of the lower surface of the barrier layer 136 in the third direction D3 are the shortest distances from the upper surface of the substrate 110 to the third direction D3.

[0038] The first barrier layer doping region 1361 is located beneath the source electrode 173. In other words, at least a portion of the first barrier layer doping region 1361 overlaps the source electrode 173 in the third direction D3. On the other hand, the first barrier layer doping region 1361 does not overlap with the gate electrode layer 155 and the drain electrode 175 in the third direction D3. The second barrier layer doping region 1362 is located below the drain electrode 175. In other words, at least a portion of the second barrier layer doping region 1362 overlaps with the drain electrode 175 in the third direction D3. On the other hand, the second barrier layer doping region 1362 does not overlap with the gate electrode layer 155 and the source electrode 173 in the third direction D3. The first barrier layer doping region 1361 and the second barrier layer doping region 1362 are separated from each other in the second direction D2, and the gate electrode layer 155 and the gate semiconductor layer 152 are positioned between the first barrier layer doping region 1361 and the second barrier layer doping region 1362.

[0039] The gate electrode layer 155 and the gate semiconductor layer 152 are separated in the second direction D2 from the first barrier layer doping region 1361 and the second barrier layer doping region 1362. The source electrode 173 is electrically connected to the first barrier layer doping region 1361 on one side of the gate electrode layer 155 in the second direction D2. The first barrier layer doping region 1361 is in ohmic contact with the source electrode 173. The first barrier layer doping region 1361 reduces the contact resistance between the source electrode 173 and the channel layer 132. The drain electrode 175 is electrically connected to the second barrier layer doping region 1362 on the other side of the gate electrode layer 155 in the second direction D2. The second barrier layer doping region 1362 is in ohmic contact with the drain electrode 175. The second barrier layer doping region 1362 reduces the contact resistance between the drain electrode 175 and the channel layer 132.

[0040] The first barrier layer doping region 1361 and the second barrier layer doping region 1362 extend in a plane (for example, Figure 1) along the first direction D1. That is, the first barrier layer doping region 1361 and the second barrier layer doping region 1362 have a rod shape that extends long along the first direction D1 on a plane. The first barrier layer doping region 1361 and the second barrier layer doping region 1362 are extended in directions parallel to each other. The first barrier layer doping region 1361 and the second barrier layer doping region 1362 extend in a direction parallel to the gate electrode layer 155. The first barrier layer doping region 1361 and the second barrier layer doping region 1362 are formed in at least a portion of the barrier layer 136 by an ion implantation method, such as an ion implantation (IIP) method.

[0041] The first barrier layer doping region 1361 and the second barrier layer doping region 1362 contain the same material as the barrier layer 136. For example, the first barrier layer doping region 1361 and the second barrier layer doping region 1362 may contain group III-V materials, such as nitrides containing Al, Ga, In, B, or combinations thereof. As an example, the first barrier layer doping region 1361 and the second barrier layer doping region 1362 are each doped with n-type. For example, the first barrier layer doping region 1361 and the second barrier layer doping region 1362 are Al x In y Ga 1-x-y N includes (0≦x≦1, 0≦y≦1, x+y≦1) and is doped with either silicon (Si) or germanium (Ge). However, this is not the only way to do so; the substances and doping types in the first barrier layer doping region 1361 and the second barrier layer doping region 1362 can be varied and are not limited to these.

[0042] As an example, a semiconductor device according to an embodiment of the present invention is manufactured in the following order, as described later in Figures 24 to 32: first, a first barrier layer doping region 1361 is formed, then a gate electrode layer 155 and a gate semiconductor layer 152 are formed, and finally, a source electrode 173 connected to the first barrier layer doping region 1361 is formed. In other words, by forming the first barrier layer doping region 1361, which requires a high-temperature process, first, the ohmic contact between the source electrode 173 and the channel layer 132 is improved, reducing contact resistance. At the same time, the gate electrode layer 155 and the gate semiconductor layer 152 can be formed before the source electrode 173, improving the alignment between the gate electrode layer 155 and the gate semiconductor layer 152. Accordingly, the semiconductor device according to the embodiment of the present invention further includes a first barrier layer doping region 1361 and a first channel layer doping region 1321 disposed within the barrier layer 136. The first barrier layer doping region 1361 and the first channel layer doping region 1321 can improve ohmic contact between the source electrode 173 and the channel layer 132. Similarly, a semiconductor device according to an embodiment of the present invention further includes a second barrier layer doping region 1362 and a second channel layer doping region 1322 disposed within the barrier layer 136, the second barrier layer doping region 1362 and the second channel layer doping region 1322 can improve ohmic contact between the drain electrode 175 and the channel layer 132.

[0043] The gate electrode layer 155 is positioned on top of the barrier layer 136. The gate electrode layer 155 overlaps a portion of the barrier layer 136 in the third direction D3. The gate electrode layer 155 superimposes a portion of the drift region DTR of the channel layer 132 and the third direction D3. The gate electrode layer 155 is positioned between the source electrode 173 and the drain electrode 175 in the second direction D2. The gate electrode layer 155 is separated from the source electrode 173 and the drain electrode 175 in the second direction D2. The gate electrode layer 155 extends in a plane along the first direction D1. That is, the gate electrode layer 155 has a bar shape that extends along the first direction D1 on a plane.

[0044] The gate electrode layer 155 contains a conductive material. For example, the gate electrode layer 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitrogen oxide. For example, the gate electrode layer 155 is made of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride (TaCN nitride (TaCN), tungsten nitride (WN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC-TiN), titanium carbide nitride (TaAlC-TiN), titanium carbide nitride (TaAlC-TiN), titanium carbide nitride (TaAlC- This may include, but is not limited to, stainless steel (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The gate electrode layer 155 may consist of a single layer or multiple layers.

[0045] The gate semiconductor layer 152 is positioned between the barrier layer 136 and the gate electrode layer 155. Specifically, a gate semiconductor layer 152 is placed on top of the barrier layer 136, and a gate electrode layer 155 is placed on top of the gate semiconductor layer 152. The gate electrode layer 155 is in Schottky contact with the gate semiconductor layer 152. However, this is not the only option; in some cases, the gate electrode layer 155 may be in ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 is superimposed on the gate electrode layer 155 in the third direction D3. The upper surface (US_152) of the gate semiconductor layer 152 is entirely covered by the gate electrode layer 155. The gate semiconductor layer 152 is positioned between the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 is separated from the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 is positioned closer to the source electrode 173 than to the drain electrode 175. In other words, the separation distance between the gate semiconductor layer 152 and the source electrode 173 is smaller than the separation distance between the gate semiconductor layer 152 and the drain electrode 175.

[0046] The gate semiconductor layer 152 may contain a nitride comprising a group III-V material, such as Al, Ga, In, B, or a combination thereof. The gate semiconductor layer 152 is Al x In y Ga 1-x-y N includes (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1). For example, the gate semiconductor layer 152 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The gate semiconductor layer 152 contains a material having a different energy band gap than the barrier layer 136. For example, the gate semiconductor layer 152 contains GaN, and the barrier layer 136 contains AlGaN. The gate semiconductor layer 152 is doped with a predetermined impurity. At this time, the impurity doped into the gate semiconductor layer 152 is a p-type dopant that provides holes. For example, the gate semiconductor layer 152 contains GaN doped with p-type impurities. In other words, the gate semiconductor layer 152 consists of a p-GaN layer. However, it is not limited to this, and the gate semiconductor layer 152 may also be a p-AlGaN layer. The impurity doped into the gate semiconductor layer 152 may be magnesium (Mg). The gate semiconductor layer 152 may consist of a single layer or multiple layers.

[0047] The gate semiconductor layer 152 forms a depletion region (DPR) within the channel layer 132. The depletion region (DPR) is located within the drift region (DTR) and has a narrower width than the drift region (DTR). By placing a gate semiconductor layer 152 having a different energy band gap than the barrier layer 136 on top of the barrier layer 136, the energy band levels of the portion of the barrier layer 136 that overlaps with the gate semiconductor layer 152 are increased. As a result, a depletion region (DPR) is formed in the region of the channel layer 132 that is superimposed on the gate semiconductor layer 152. The depletion region DPR is a region within the channel pathway of the channel layer 132 where the two-dimensional electron gas 134 is not formed, or where the electron concentration is lower than that of the remaining region. In other words, the depletion region DPR refers to the region within the drift region DTR where the flow of the two-dimensional electron gas 134 is interrupted. When a depletion region (DPR) occurs, no current flows between the source electrode 173 and the drain electrode 175, and the channel path is blocked. As a result, the semiconductor device according to the embodiment of the present invention has normally-off characteristics. In other words, the semiconductor device according to the embodiment of the present invention is a normally-off semiconductor device (High Electron Mobility Transistor: HEMT).

[0048] In the normal state, when no voltage is applied to the gate electrode layer 155, a depletion region DPR exists, and the semiconductor device is in the off state. Although not shown in the diagram, if a voltage above the threshold voltage is applied to the gate electrode layer 155, the depletion region DPR disappears, and the two-dimensional electron gas 134 remains connected within the drift region DTR without being interrupted. In other words, a two-dimensional electron gas 134 is formed throughout the entire channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device enters the ON state. In summary, the semiconductor device according to the embodiment of the present invention includes semiconductor layers with different electrical polarization characteristics, and the semiconductor layer having a relatively large polarizability can induce a two-dimensional electron gas 134 in other semiconductor layers joined to it. Such a two-dimensional electron gas 134 is used as a channel between the source electrode 173 and the drain electrode 175, and the flow of such a two-dimensional electron gas 134 can be controlled by a bias voltage applied to the gate electrode layer 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is interrupted, and no current flows between the source electrode 173 and the drain electrode 175. With the gate on, as the flow of the two-dimensional electron gas 134 connects, a current flows between the source electrode 173 and the drain electrode 175.

[0049] The above describes the case where the semiconductor device according to the embodiment of the present invention is a normally-off high electron mobility transistor, but the invention is not limited to this. For example, the semiconductor device according to the embodiment of the present invention may be a normally-on high electron mobility transistor. In the case of a normally-on high electron mobility transistor, the gate semiconductor layer 152 can be omitted, thereby positioning the gate electrode layer 155 directly above the barrier layer 136. In other words, the gate electrode layer 155 is in contact with the barrier layer 136. However, the invention is not limited to this, and a gate dielectric layer may be interposed between the gate electrode layer 155 and the barrier layer 136. In this structure, when no voltage is applied to the gate electrode layer 155, the two-dimensional electron gas 134 is used as a channel, and a current flows between the source electrode 173 and the drain electrode 175. Furthermore, when a negative voltage is applied to the gate electrode layer 155, a depletion region (DPR) occurs below the gate electrode layer 155, where the flow of the two-dimensional electron gas 134 is interrupted.

[0050] The buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 described earlier are sequentially stacked on the substrate 110. In a semiconductor device, at least one of the buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 can be omitted. Such a buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 are made of the same semiconductor material, and the material composition ratio of each layer may differ depending on the role of each layer and the performance required of the semiconductor device.

[0051] Unlike what will be described later in Figures 24 to 32, the semiconductor device can be manufactured by forming a gate semiconductor layer 152, covering the gate semiconductor layer 152 with a first protective layer 140, and then etching the first protective layer 140 to form a source electrode 173 and a gate electrode layer 155. However, in this case, alignment of the gate semiconductor layer 152 and the gate electrode layer 155 is difficult. Therefore, the semiconductor device according to the embodiment of the present invention is manufactured by first forming the gate electrode layer 155 and the gate semiconductor layer 152, and then forming the source electrode 173 connected to the first barrier layer doping region 1361. In this case, the gate electrode layer 155 is formed first, the gate semiconductor layer 152 is formed using the gate electrode layer 155, and then the source electrode 173 is formed. Therefore, the gate semiconductor layer 152 and the gate electrode layer 155 are self-aligned. Alignment between the gate electrode layer 155 and the gate semiconductor layer 152 is easy and excellent.

[0052] However, if the gate electrode layer 155 is formed before the source electrode 173, there is a disadvantage in that a high-temperature process to improve ohmic contact between the source electrode 173 and the channel layer 132 is not possible. Therefore, as will be described later in Figures 24 to 32, the semiconductor device according to the embodiment of the present invention is manufactured by first forming a first barrier layer doping region 1361, then forming a gate electrode layer 155 and a gate semiconductor layer 152, and finally forming a source electrode 173 connected to the first barrier layer doping region 1361. In other words, by forming the first barrier layer doping region 1361, which requires a high-temperature process, first, the ohmic contact between the source electrode 173 and the channel layer 132 is improved, reducing contact resistance, while the gate electrode layer 155 and the gate semiconductor layer 152 are formed before the source electrode 173, improving the alignment between the gate electrode layer 155 and the gate semiconductor layer 152. Thus, the semiconductor device according to the embodiment of the present invention further includes a first barrier layer doping region 1361 and a first channel layer doping region 1321 located within the barrier layer 136. The first barrier layer doping region 1361 and the first channel layer doping region 1321 can improve ohmic contact between the source electrode 173 and the channel layer 132. Similarly, a semiconductor device according to an embodiment of the present invention further includes a second barrier layer doping region 1362 and a second channel layer doping region 1322 disposed within the barrier layer 136, the second barrier layer doping region 1362 and the second channel layer doping region 1322 can improve ohmic contact between the drain electrode 175 and the channel layer 132.

[0053] Furthermore, in the semiconductor device according to an embodiment of the present invention, as described later in Figures 28 and 29, a gate electrode layer 155 is formed by etching a second photoresist pattern (PR2 in Figure 27) with a first etching gas, the second photoresist pattern PR2 is removed, and a gate semiconductor layer 152 is formed by etching a second hard mask layer (156 in Figure 29) with a second etching gas different from the first etching gas. Specifically, by forming the gate electrode layer 155 using the second photoresist pattern PR2 and the gate semiconductor layer 152 using the second hard mask layer 156, the gate electrode layer 155 can be etched with the first etching gas and the gate semiconductor layer 152 can be etched with the second etching gas, increasing the degree of freedom in selecting the etching materials for the gate electrode layer 155 and the gate semiconductor layer 152. Through this, the lateral slope of the gate electrode layer 155 and the gate semiconductor layer 152 can be controlled in various ways.

[0054] For example, on a cross-section cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the angle (θ_155) between the lower surface (BS_155) and the side surface (SW_155) of the gate electrode layer 155 and the angle (θ_152) between the lower surface (BS_152) and the side surface (SW_152) of the gate semiconductor layer 152 are different from each other. For example, the angle (θ_155) between the lower surface (BS_155) and the side surface (SW_155) of the gate electrode layer 155 is even larger than the angle (θ_152) between the lower surface (BS_152) and the side surface (SW_152) of the gate semiconductor layer 152. Here, the gate electrode layer 155 has an upper surface (US_155) and a lower surface (BS_155) that face each other in the third direction D3 and extend in the second direction D2, respectively, on a cross section cut in the second direction D2 and third direction D3 perpendicular to the first direction D1 (for example, Figure 3), and both sides (SW_155) that connect the upper surface (US_155) and the lower surface (BS_155) and extend in the third direction D3. The upper surface (US_155) of the gate electrode layer 155 faces the second hard mask layer 156, and the lower surface (BS_155) of the gate electrode layer 155 faces the gate semiconductor layer 152. For example, the upper surface (US_155) of the gate electrode layer 155 is defined as the surface in contact with the second hard mask layer 156, the lower surface (BS_155) of the gate electrode layer 155 is defined as the surface in contact with the gate semiconductor layer 152, and the side surfaces (SW_155) of the gate electrode layer 155 are defined as surfaces that do not contact the second hard mask layer 156 or the gate semiconductor layer 152.

[0055] For example, the angle (θ_155) between the lower surface (BS_155) and the side surface (SW_155) of the gate electrode layer 155 can be 60° or more, for example, greater than 60°, 65° or more, 70° or more, 75° or more, 80° or more, or 85° or more, and 90° or less, for example, less than 90°, 85° or less, 80° or less, 75° or less, 70° or less, or 65° or less, and can be between 60° and 90°. Furthermore, the angle (θ_152) between the lower surface (BS_152) and the side surface (SW_152) of the gate semiconductor layer 152 can be 30° or more, for example, greater than 30°, 35° or more, 40° or more, 45° or more, 50° or more, 55° or more, 60° or more, greater than 60°, 65° or more, 70° or more, 75° or more, 80° or more, or 85° or more, and can be 89° or less, for example, less than 89°, 85° or less, 80° or less, 75° or less, 70° or less, 65° or less, 60° or less, less than 60°, 55° or less, 50° or less, 45° or less, 40° or less, or 35° or less, and can be between 30° and 89°.

[0056] As a result, on a cross-section cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the length of the upper surface (US_155) of the gate electrode layer 155 in the second direction D2 (W_US_155) is even smaller than the length of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 (W_BS_155). Here, the length (W_BS_155) of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 is the length in the second direction D2 where the lower surface (BS_155) of the gate electrode layer 155 is in contact with the upper surface (US_152) of the gate semiconductor layer 152, and excludes the length in the second direction D2 where the lower surface (BS_155) of the gate electrode layer 155 is not in contact with the upper surface (US_152) of the gate semiconductor layer 152. Furthermore, the length of the upper surface (US_152) of the gate semiconductor layer 152 in the second direction D2 (W_US_152) is even smaller than the length of the lower surface (BS_152) of the gate semiconductor layer 152 in the second direction D2 (W_BS_152). Furthermore, the difference in length in the second direction D2 between the lower surface (BS_155) and upper surface (US_155) of the gate electrode layer 155 (=(W_BS_155)-(W_US_155)) is even smaller than the difference in length in the second direction D2 between the lower surface (BS_152) and upper surface (US_152) of the gate semiconductor layer 152 (=(W_BS_152)-(W_US_152)). In this case, the contact area between the gate electrode layer 155 and the gate semiconductor layer 152 can be increased.

[0057] As mentioned above, by-products generated when etching the gate electrode layer 155 with the first etching gas can affect the etching of the gate semiconductor layer 152 with the second etching gas, potentially causing defects. To solve these problems, after etching the gate electrode layer 155 with the first etching gas, by-products generated when etching the gate electrode layer 155 with the first etching gas are removed through a process such as ashing or stripping before etching the gate semiconductor layer 152 with the second etching gas. This solves the problem of defects caused by by-products resulting from etching the gate electrode layer 155 and the gate semiconductor layer 152 with different etching materials.

[0058] The second photoresist pattern PR2 is also removed during the by-product removal process, such as ashing or stripping. In this process, the second hard mask layer 156 is not removed. The second hard mask layer 156 is then used as a mask in the process of forming the gate semiconductor layer 152 with a second etching gas. The second hard mask layer 156 has a shape in which the corners formed by the top surface (US_156) and the side surface (SW_156) are rounded, as part of the second hard mask layer 156 is etched according to the etching conditions during the etching of the gate semiconductor layer 152. Therefore, the semiconductor device according to an embodiment of the present invention further includes a second hard mask layer 156 disposed on top of the gate electrode layer 155. However, the second hard mask layer 156 may also be removed depending on the etching conditions during etching of the gate semiconductor layer 152.

[0059] If the second hard mask layer 156 contains the same material as the first protective layer 140 described later, the boundary between the second hard mask layer 156 and the first protective layer 140 may not be defined. On a cross-section cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the second hard mask layer 156 has an upper surface (US_156) and a lower surface (BS_156) that face each other in the third direction D3 and extend in the second direction D2, respectively, and side surfaces (SW_156) on both sides that connect the upper surface (US_156) and the lower surface (BS_156) and extend in the third direction D3. The upper surface (US_156) of the second hard mask layer 156 extends from the midpoint of the second direction D2 of the second hard mask layer 156 to both ends of the second direction D2. The upper surface (US_156) of the second hard mask layer 156 has a different height in the second direction D2. For example, the height of the upper surface (US_156) of the second hard mask layer 156 at both ends of the second direction D2 may be within ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2, and the points where the height exceeds ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2 correspond to the side surface (SW_156) of the second hard mask layer 156.

[0060] The lower surface (BS_156) of the second hard mask layer 156 extends from the midpoint of the second direction D2 to both ends of the second direction D2. The lower surface (BS_156) of the second hard mask layer 156 has different heights in the second direction D2. For example, the height of the lower surface (BS_156) of the second hard mask layer 156 at both ends of the second direction D2 may be within ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2, and the points where the height exceeds ±30%, ±20%, ±10%, ±5%, or ±1% of the height at the midpoint of the second direction D2 correspond to the side surface (SW_156) of the second hard mask layer 156. On cross-sections cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the corners formed by the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 have a rounded shape. In other words, the corners formed by the top surface (US_156) and side surface (SW_156) of the second hard mask layer 156 are not angular, but rather have a rounded shape that is beveled, and for example, they have curvature. As a result, the angle (θ_156U) between the top surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 decreases as it moves further away from the top surface (US_156) of the second hard mask layer 156 in the third direction D3. Here, the angle (θ_156U) between the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 due to the third direction D3 is the interior angle between the tangent line at a point on the side surface (SW_156) and the upper surface (US_156).

[0061] Furthermore, the ratio of the length of the upper surface (US_156) of the second hard mask layer 156 in the second direction D2 (W_US_156) to the length of the lower surface (BS_156) of the second hard mask layer 156 in the second direction D2 (W_BS_156) can be 9:10 or greater, for example, 9:10.5 or greater, 9:11 or greater, or 9:11.5 or greater, and can be 9:12 or less, for example, 9:11.5 or less, 9:11 or less, or 9:10.5 or less, and can be between 9:10 and 9:12. The length (W_US_156) of the top surface (US_156) of the second hard mask layer 156 in the second direction D2 is the length measured over the substantially flat top surface (US_156) in the second direction D2, excluding the rounded shape of the corners. Here, being flat means being parallel to the second direction D2.

[0062] For example, on a cross-section cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the angle (θ_155) between the lower surface (BS_155) and the side surface (SW_155) of the gate electrode layer 155 and the angle (θ_156U) between the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 are different from each other. For example, the angle (θ_156U) between the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 is even larger than the angle (θ_155) between the lower surface (BS_155) and the side surface (SW_155) of the gate electrode layer 155. For example, the angle (θ_156U) between the top surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 can be 90° or greater, for example, greater than 90°, 95° or greater, 100° or greater, 105° or greater, 110° or greater, or 115° or greater, and 120° or less, for example, less than 120°, 115° or less, 110° or less, 105° or less, 100° or less, or 95° or less, and can be between 90° and 120°. As an example, the second hard mask layer 156 may include silicon oxide, silicon nitride, silicon nitride, or a combination thereof.

[0063] A semiconductor device according to an embodiment of the present invention further includes first to third protective layers (140, 150, 160) disposed on a barrier layer 136, a gate electrode layer 155, and a second hard mask layer 156. As an example, a semiconductor device includes a first protective layer 140, a second protective layer 150 disposed on the first protective layer 140, and a third protective layer 160 disposed on the second protective layer 150. The first protective layer 140 covers the upper surface (US_156) of the barrier layer 136, the gate electrode layer 155, and the second hard mask layer 156, and covers the side surface (SW_155) of the gate electrode layer 155, the side surface (SW_152) of the gate semiconductor layer 152, and the side surface (SW_156) of the second hard mask layer 156. The lower surface of the first protective layer 140 is in contact with the barrier layer 136, the gate electrode layer 155, the gate semiconductor layer 152, and the second hard mask layer 156. The upper surface of the first protective layer 140 is in contact with the second protective layer 150. The second protective layer 150 and the third protective layer 160 are separated from the barrier layer 136, gate electrode layer 155, gate semiconductor layer 152, and second hard mask layer 156 by the first protective layer 140. Therefore, the second protective layer 150 and the third protective layer 160 do not come into contact with the barrier layer 136, the gate electrode layer 155, the gate semiconductor layer 152, and the second hard mask layer 156.

[0064] The barrier layer 136 or gate electrode layer 155, etc., is protected by the first to third protective layers (140, 150, 160) and separated from other components. The first to third protective layers (140, 150, 160) contain insulating material. For example, the first to third protective layers (140, 150, 160) contain oxides such as SiO2 and Al2O3. As another example, the first to third protective layers (140, 150, 160) may contain nitrides such as SiN or oxynitrides such as SiON. The first to third protective layers (140, 150, 160) may contain the same substance or different substances. If the first to third protective layers (140, 150, 160) are made of the same material, the boundaries between the first to third protective layers (140, 150, 160) may not be visible. The first to third protective layers (140, 150, and 160) may each consist of a single layer or multiple layers.

[0065] As an example, the first protective layer 140 is placed on top of the barrier layer 136, the first barrier layer doping region 1361, and the second barrier layer doping region 1362. The lower surface of the first protective layer 140 is in contact with the upper surface of the barrier layer 136, the upper surface of the first barrier layer doping region 1361, and the upper surface of the second barrier layer doping region 1362. Furthermore, the first protective layer 140 is placed on top of the gate electrode layer 155 and the gate semiconductor layer 152. The lower surface of the first protective layer 140 is in contact with the upper surface and side surface of the gate electrode layer 155 and the side surface of the gate semiconductor layer 152. When the second hard mask layer 156 is located above the gate electrode layer 155, the lower surface of the first protective layer 140 is in contact with the upper surface and side surface of the second hard mask layer 156, the side surface of the gate electrode layer 155, and the side surface of the gate semiconductor layer 152.

[0066] As described above, in the embodiment of the present invention, the semiconductor device is manufactured by first forming the gate electrode layer 155 and the gate semiconductor layer 152, then forming a first protective layer 140 that covers the barrier layer 136, the gate semiconductor layer 152, the gate electrode layer 155, the first barrier layer doping region 1361, and the second barrier layer doping region 1362, etching a part of the first protective layer 140 to expose the first barrier layer doping region 1361 and the second barrier layer doping region 1362, forming a source electrode 173 on the first barrier layer doping region 1361, and forming a drain electrode 175 on the second barrier layer doping region 1362, thereby ensuring that the first protective layer 140 covers the entire gate electrode layer 155. In this case, the alignment between the gate electrode layer 155 and the gate semiconductor layer 152 can be improved.

[0067] On the other hand, when a gate semiconductor layer 152 is formed, the gate semiconductor layer 152 is covered with a first protective layer 140, and then the first protective layer 140 is etched to form a source electrode 173 and a gate electrode layer 155, the upper part of the gate electrode layer 155 is placed on top of the first protective layer 140. Furthermore, the gate electrode layer 155 and the gate semiconductor layer 152 are connected only by vias that penetrate the first protective layer 140. In other words, on a cross-section cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 3), the length of the upper surface (US_155) of the gate electrode layer 155 toward the second direction D2 (W_US_155) is greater than the length of the lower surface (BS_155) of the gate electrode layer 155 toward the second direction D2 (W_BS_155). In this case, alignment between the gate electrode layer 155 and the gate semiconductor layer 152 is difficult, and the contact area between the gate electrode layer 155 and the gate semiconductor layer 152 is small.

[0068] The source electrode 173 and the drain electrode 175 are placed on top of the channel layer 132. The source electrode 173 and the drain electrode 175 are separated from each other in the second direction D2, and the second hard mask layer 156, the gate electrode layer 155, and the gate semiconductor layer 152 are arranged between the source electrode 173 and the drain electrode 175. The second hard mask layer 156, the gate electrode layer 155, and the gate semiconductor layer 152 are separated from the source electrode 173 and the drain electrode 175 in the second direction D2. The source electrode 173 is electrically connected to the channel layer 132 on one side of the gate electrode layer 155 in the second direction D2. The source electrode 173 is electrically connected to the channel layer 132 through the first barrier layer doping region 1361 and the first channel layer doping region 1321. The first barrier layer doping region 1361 and the first channel layer doping region 1321 are in ohmic contact with the source electrode 173. The doping region 1361 in the first barrier layer and the doping region 1321 in the first channel layer reduce the contact resistance between the source electrode 173 and the channel layer 132.

[0069] The drain electrode 175 is electrically connected to the second channel layer doping region 1322 on the other side of the gate electrode layer 155 in the second direction D2. The drain electrode 175 is electrically connected to the channel layer 132 through the second barrier layer doping region 1362 and the second channel layer doping region 1322. The second barrier layer doping region 1362 and the second channel layer doping region 1322 are in ohmic contact with the drain electrode 175. The contact resistance between the drain electrode 175 and the channel layer 132 is reduced by the doping region 1362 of the second barrier layer and the doping region 1322 of the second channel layer.

[0070] The source electrode 173 and the drain electrode 175 are positioned outside or above the drift region DTR of the channel layer 132. The interface between the source electrode 173 and the channel layer 132 is one side edge of the drift region DTR. Similarly, the interface between the drain electrode 175 and the channel layer 132 is the other edge of the drift region DTR. As an example, the source electrode 173 penetrates the first protective layer 140 and is positioned on the first barrier layer doping region 1361 and the first channel layer doping region 1321, while the drain electrode 175 penetrates the first protective layer 140 and is positioned on the second barrier layer doping region 1362 and the second channel layer doping region 1322. At this time, the first barrier layer doping region 1361 and the first channel layer doping region 1321 are not recessed, and the source electrode 173 is positioned on the upper surface of the first barrier layer doping region 1361. The lower surface of the source electrode 173 is in contact with the upper surface of the first barrier layer doping region 1361. Similarly, the second barrier layer doping region 1362 and the second channel layer doping region 1322 are not recessed, and the drain electrode 175 is positioned on the upper surface of the second barrier layer doping region 1362. The lower surface of the drain electrode 175 is in contact with the upper surface of the second barrier layer doping region 1362.

[0071] The length of the source electrode 173 in the second direction D2 (W_173) is less than or equal to the length of the first barrier layer doping region 1361 in the second direction D2 (W_1361). Furthermore, the length of the source electrode 173 in the second direction D2 (W_173) is less than or equal to the length of the first channel layer doping region 1321 in the second direction D2 (W_1321). As an example, the length of the source electrode 173 in the second direction D2 (W_173) is smaller than the length of the first barrier layer doping region 1361 in the second direction D2 (W_1361) or the length of the first channel layer doping region 1321 in the second direction D2 (W_1321) by more than 0 μm and less than or equal to 0.8 μm. Similarly, the length of the drain electrode 175 in the second direction D2 is less than or equal to the length of the second barrier layer doping region 1362 in the second direction D2. Furthermore, the length of the drain electrode 175 in the second direction D2 is less than or equal to the length of the first channel layer doping region 1321 in the second direction D2. As an example, the length of the drain electrode 175 in the second direction D2 is even smaller than the length of the second barrier layer doping region 1362 in the second direction D2 by more than 0 μm and less than or equal to 0.8 μm.

[0072] In this case, the source electrode 173 and drain electrode 175 are not located on one side of the drift region DTR of the channel layer 132 in the second direction D2, but are positioned on the third direction D3 of the drift region DTR. For example, the drift region DTR extends from the channel layer 132 to the first channel layer doping region 1321 and the second channel layer doping region 1322, thereby positioning the source electrode 173 and the drain electrode 175 above the drift region DTR. As described above, the first barrier layer doping region 1361, the first channel layer doping region 1321, the second barrier layer doping region 1362, and the second channel layer doping region 1322 are doped at high concentrations. At this time, the carriers that have passed through the two-dimensional electron gas 134 are transferred to the source electrode 173 and the drain electrode 175 by passing through the first barrier layer doping region 1361, the first channel layer doping region 1321, the second barrier layer doping region 1362, and the second channel layer doping region 1322, which are doped to a high concentration. The source electrode 173 and the drain electrode 175 do not come into direct horizontal contact with the two-dimensional electron gas 134. The horizontal direction refers to the direction parallel to the upper surface of the channel layer 132 or the barrier layer 136.

[0073] The source electrode 173 and the drain electrode 175 extend in a plane along the first direction D1. That is, the source electrode 173 and the drain electrode 175 have a rod shape that extends long along the first direction D1 on a plane. The source electrode 173 and the drain electrode 175 extend in directions parallel to each other. The source electrode 173 and the drain electrode 175 extend in a direction parallel to the gate electrode layer 155. The source electrode 173 and the drain electrode 175 contain a conductive material. For example, the source electrode 173 and the drain electrode 175 may include metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal nitrogen oxides.

[0074] For example, the source electrode 173 and drain electrode 175 are made of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbide nitride (TaCN This may include, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 and the drain electrode 175 may consist of a single layer or multiple layers.

[0075] The source electrode 173 includes a lower source electrode 173a, an intermediate source electrode 173b, and an upper source electrode 173c. The intermediate source electrode 173b is positioned on top of the lower source electrode 173a. The upper source electrode 173c is positioned above the intermediate source electrode 173b. The lower source electrode 173a is in direct contact with the first barrier layer doping region 1361 or the first channel layer doping region 1321 and is electrically connected to the channel layer 132. The intermediate source electrode 173b and the upper source electrode 173c do not directly contact the channel layer 132, but are electrically connected to the channel layer 132 through the lower source electrode 173a. The drain electrode 175 includes a lower drain electrode 175a, an intermediate drain electrode 175b, and an upper drain electrode 175c. The intermediate drain electrode 175b is positioned above the lower drain electrode 175a. The upper drain electrode 175c is positioned above the intermediate drain electrode 175b. The lower drain electrode 175a is in direct contact with the second barrier layer doping region 1362 or the second channel layer doping region 1322, and is electrically connected to the channel layer 132. The intermediate drain electrode 175b and the upper drain electrode 175c do not directly contact the channel layer 132, but are electrically connected to the channel layer 132 through the lower drain electrode 175a.

[0076] The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a are positioned on the first protective layer 140. The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a are positioned between the first protective layer 140 and the second protective layer 150. The lower source electrode 173a and the lower drain electrode 175a are positioned on both sides of the gate electrode layer 155, spaced apart from each other, with trenches penetrating the first protective layer 140 and the barrier layer 136, and recessing the upper surface of the channel layer 132. The lower source electrode 173a and the lower drain electrode 175a are positioned in trenches located on both sides of the gate electrode layer 155, respectively. The lower source electrode 173a and the lower drain electrode 175a are formed to fill the trench. Within the trench, the lower source electrode 173a is in contact with the first barrier layer doping region 1361 or the first channel layer doping region 1321. Furthermore, within the trench, the lower drain electrode 175a is in contact with the second barrier layer doping region 1362 or the second channel layer doping region 1322.

[0077] The first channel layer doping region 1321 or the second channel layer doping region 1322 forms the bottom surface and side walls of the trench, and the first barrier layer doping region 1361 or the second barrier layer doping region 1362 forms the side walls of the trench. Therefore, the lower source electrode 173a and the lower drain electrode 175a are in contact with the upper surface and side surface of the first channel layer doping region 1321 or the second channel layer doping region 1322. Furthermore, the lower source electrode 173a and the lower drain electrode 175a are in contact with the side surface of the first barrier layer doping region 1361 or the second barrier layer doping region 1362. The upper surfaces of the lower source electrode 173a and the lower drain electrode 175a protrude from the upper surface of the first protective layer 140. Furthermore, at least one of the lower source electrode 173a and the lower drain electrode 175a covers at least a portion of the upper surface of the first protective layer 140. A second protective layer 150 is placed on the lower source electrode 173a and the lower drain electrode 175a. At least a portion of the lower source electrode 173a and the lower drain electrode 175a is covered by the second protective layer 150.

[0078] A semiconductor device according to an embodiment of the present invention further includes a first field dispersion layer 177a disposed on a first protective layer 140. The first field dispersion layer 177a is positioned between the source electrode 173 and the drain electrode 175. The gate electrode layer 155 is covered by the first field dispersion layer 177a. The first field dispersion layer 177a is electrically connected to the source electrode 173. For example, the first field dispersion layer 177a is connected to the lower source electrode 173a. The first field dispersion layer 177a contains the same material as the lower source electrode 173a and is located in the same layer as the lower source electrode 173a. The first field dispersion layer 177a is formed simultaneously with the lower source electrode 173a in the same process. The boundary between the first field dispersion layer 177a and the lower source electrode 173a is not clearly defined, and the first field dispersion layer 177a can be formed integrally with the lower source electrode 173a. However, the system is not limited to this, and the first field dispersion layer 177a may be a separate component separated from the lower source electrode 173a. Furthermore, the first field dispersion layer 177a may be located in a different layer from the lower source electrode 173a, or it may be formed by a different process. Depending on the circumstances, the first field dispersion layer 177a is electrically connected to the gate electrode layer 155. For example, an opening is formed in the first protective layer 140 that overlaps with the gate electrode layer 155, and the first field dispersion layer 177a is connected to the gate electrode layer 155 through the opening. At this time, the first field dispersion layer 177a is not connected to the source electrode 173.

[0079] A semiconductor device according to an embodiment of the present invention further includes a second field dispersion layer 177b disposed on a second protective layer 150. The second field dispersion layer 177b, together with the first field dispersion layer 177a, constitutes a field dispersion layer. The second field dispersion layer 177b is positioned between the source electrode 173 and the drain electrode 175. The second field dispersion layer 177b is superimposed on the gate electrode layer 155 in the third direction D3. The second field dispersion layer 177b is superimposed on the first field dispersion layer 177a in the third direction D3. The gate electrode layer 155 and the first field dispersion layer 177a are covered by the second field dispersion layer 177b. The second field dispersion layer 177b is wider than the first field dispersion layer 177a. The second field dispersion layer 177b completely covers the first field dispersion layer 177a. However, this is not the only option; the width, positional relationship, etc., of the first field dispersion layer 177a and the second field dispersion layer 177b can be varied in many ways.

[0080] The second field dispersion layer 177b is electrically connected to the source electrode 173. For example, the second field dispersion layer 177b is connected to the intermediate source electrode 173b. The second field dispersion layer 177b contains the same material as the intermediate source electrode 173b and is located in the same layer as the intermediate source electrode 173b. The second field dispersion layer 177b is formed simultaneously with the intermediate source electrode 173b using the same process. The boundary between the second field dispersion layer 177b and the intermediate source electrode 173b is not clearly defined, and the second field dispersion layer 177b is formed integrally with the intermediate source electrode 173b. However, the system is not limited to this, and the second field dispersion layer 177b may be a separate component separated from the intermediate source electrode 173b. Furthermore, the second field dispersion layer 177b may be located in a different layer from the intermediate source electrode 173b, or it may be formed by a different process.

[0081] A semiconductor device according to an embodiment of the present invention further includes a third field dispersion layer 177c disposed on a third protective layer 160. The third field dispersion layer 177c, together with the first field dispersion layer 177a and the second field dispersion layer 177b, constitutes a field dispersion layer. The third field dispersion layer 177c is positioned between the source electrode 173 and the drain electrode 175. The third field dispersion layer 177c is superimposed on the gate electrode layer 155 in the third direction D3. The third field dispersion layer 177c is superimposed on the first field dispersion layer 177a and the second field dispersion layer 177b in the third direction D3. The gate electrode layer 155, the first field dispersion layer 177a, and the second field dispersion layer 177b are covered by the third field dispersion layer 177c. The third field dispersion layer 177c has a greater width than the second field dispersion layer 177b. The third field dispersion layer 177c completely covers the second field dispersion layer 177b. However, this is not the only option; the widths and positional relationships of the first field dispersion layer 177a, the second field dispersion layer 177b, and the third field dispersion layer 177c can be varied in many ways.

[0082] The third field dispersion layer 177c is electrically connected to the source electrode 173. For example, the third field dispersion layer 177c is connected to the upper source electrode 173c. The third field dispersion layer 177c contains the same material as the upper source electrode 173c and is located in the same layer as the upper source electrode 173c. The third field dispersion layer 177c is formed simultaneously with the upper source electrode 173c in the same process. The boundary between the third field dispersion layer 177c and the upper source electrode 173c is not clearly defined, and the third field dispersion layer 177c is formed integrally with the upper source electrode 173c. However, this is not limited to the above, and the third field dispersion layer 177c may be a separate component separated from the upper source electrode 173c. Furthermore, the third field dispersion layer 177c may be located in a different layer from the upper source electrode 173c, or may be formed by a different process.

[0083] In one embodiment, at least one of the first field dispersion layer 177a, the second field dispersion layer 177b, or the third field dispersion layer 177c can be omitted. For example, the semiconductor device may include a first field dispersion layer 177a but may not include a second field dispersion layer 177b or a third field dispersion layer 177c. Alternatively, the semiconductor device may include a second field dispersion layer 177b but may not include a first field dispersion layer 177a or a third field dispersion layer 177c. Alternatively, the semiconductor device may include a third field dispersion layer 177c but may not include a first field dispersion layer 177a or a second field dispersion layer 177b. Alternatively, the semiconductor device may not include the first field dispersion layer 177a, the second field dispersion layer 177b, and the third field dispersion layer 177c.

[0084] Figure 5 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion P in Figure 2. Since the embodiment shown in Figure 5 has the same parts as the embodiment shown in Figure 3, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment. Referring to Figure 5, the length (W_BS_156) of the lower surface (BS_156) in the second direction D2 of the second hard mask layer 156 decreases depending on the etching conditions during etching of the gate semiconductor layer 152. As a result, on cross-sections cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 5), the length of the lower surface (BS_156) of the second hard mask layer 156 in the second direction D2 (W_BS_156) is even smaller than the length of the upper surface of the gate electrode layer 155 in the second direction D2 (W_US_155).

[0085] Figure 6 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion P in Figure 2. Since the embodiment shown in Figure 6 has the same parts as the embodiment shown in Figure 3, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment. Referring to Figure 6, the length of the upper surface (US_155) in the second direction D2 (W_US_155) and the length of the lower surface (BS_155) in the second direction D2 (W_BS_155) of the gate electrode layer 155 are reduced depending on the etching conditions when etching the gate semiconductor layer 152.

[0086] On cross-sections cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 6), the length of the upper surface (US_155) of the gate electrode layer 155 in the second direction D2 (W_US_155) and the length of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 (W_BS_155) are smaller than the length of the lower surface (BS_156) of the second hard mask layer 156 in the second direction D2 (W_BS_156) and the length of the upper surface (US_152) of the gate semiconductor layer 152 in the second direction D2 (W_US_152). Furthermore, the length of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 (W_BS_155) is smaller than the length of the upper surface (US_155) of the gate electrode layer 155 in the second direction D2 (W_US_155). As a result, the gate electrode layer 155 has an inverted trapezoidal shape on a cross-section cut in the second direction D2 and the third direction D3, which are perpendicular to the first direction D1 (for example, Figure 6).

[0087] As described above, the second hard mask layer 156 is partially etched during the etching of the gate semiconductor layer 152, and as a result, the second hard mask layer 156 has a rounded shape not only at the corners formed by the upper surface (US_156) and the side surface (SW_156), but also at the corners formed by the lower surface (BS_156) and the side surface (SW_156). On cross-sections cut in the second and third directions D2 and D3 perpendicular to the first direction D1 (for example, Figure 6), the corners formed by the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 have a rounded shape. In other words, the corner formed by the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 is not angular, but rather has a rounded shape that is beveled, and for example, has curvature.

[0088] The angle (θ_156B) between the bottom surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 decreases as it moves further away from the bottom surface (BS_156) of the second hard mask layer 156 in the third direction D3. Here, the angle (θ_156B) between the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 due to the third direction D3 is the interior angle between the tangent line at one point on the side surface (SW_156) and the lower surface (BS_156). For example, the angle (θ_156B) between the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 can be 90° or greater, for example, greater than 90°, 95° or greater, 100° or greater, 105° or greater, 110° or greater, or 115° or greater, and 120° or less, for example, less than 120°, 115° or less, 110° or less, 105° or less, 100° or less, or 95° or less, and can be between 90° and 120°.

[0089] The rounded shape of the corner formed by the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 is less pronounced than the rounded shape of the corner formed by the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156, while the rounded shape of the corner formed by the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156 is more pronounced than the rounded shape of the corner formed by the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156. In other words, the curvature of the corner formed by the upper surface (US_156) and the side surface (SW_156) of the second hard mask layer 156 is smaller than the curvature of the corner formed by the lower surface (BS_156) and the side surface (SW_156) of the second hard mask layer 156.

[0090] Figure 7 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion P in Figure 2. Since the embodiment shown in Figure 7 has the same parts as the embodiment shown in Figure 6, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0091] Figure 6 shows that, depending on the etching conditions during the etching of the gate semiconductor layer 152, the length of the lower surface (BS_155) in the second direction D2 (W_BS_155) becomes even smaller than the length of the upper surface (US_155) in the second direction D2 (W_US_155), and that the gate electrode layer 155 has an inverted trapezoidal shape on a cross section cut in the second direction D2 and third direction D3 perpendicular to the first direction D1 (for example, Figure 6). In this case, at the midpoint in the third direction D3 between the upper surface (US_155) and lower surface (BS_155) of the gate electrode layer 155, the length in the second direction D2 (W_M_155) is smaller than the length in the second direction D2 of the upper surface (US_155) of the gate electrode layer 155 (W_US_155), and larger than the length in the second direction D2 of the lower surface (BS_155) (W_BS_155).

[0092] Referring to Figure 7, when etching the gate electrode layer 155, the sides (SW_155) on both sides of the gate electrode layer 155 have a concave shape toward the gate electrode layer 155, depending on the etching conditions during etching of the gate semiconductor layer 152. Therefore, at the midpoint in the third direction D3 between the upper surface (US_155) and lower surface (BS_155) of the gate electrode layer 155, the length in the second direction D2 (W_M_155) is smaller than the length in the second direction D2 of the upper surface (US_155) of the gate electrode layer 155 (W_US_155) and the length in the second direction D2 of the lower surface (BS_155) (W_BS_155). As an example, the length of the gate electrode layer 155 in the second direction D2 decreases roughly from the upper surface (US_155) of the gate electrode layer 155 to the midpoint of the third direction D3, reaching a minimum value near the midpoint of the third direction D3, and then roughly increases from the midpoint of the third direction D3 to the lower surface (BS_155).

[0093] Figure 8 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion P in Figure 2. Since the embodiment shown in Figure 8 has the same parts as the embodiment shown in Figure 7, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0094] In Figure 7, at the midpoint of the third direction D3 between the upper surface (US_155) and lower surface (BS_155) of the gate electrode layer 155, the length in the second direction D2 (W_M_155) is smaller than the length in the second direction D2 of the upper surface (US_155) of the gate electrode layer 155 (W_US_155) and the length in the second direction D2 of the lower surface (BS_155) (W_BS_155), and the lengths in the second direction D2 of the upper surface (US_155) of the gate electrode layer 155 (W_US_155) and the length in the second direction D2 of the lower surface (BS_155) (W_BS_155) are roughly similar.

[0095] Referring to Figure 8, at the midpoint in the third direction D3 between the upper surface (US_155) and lower surface (BS_155) of the gate electrode layer 155, the length in the second direction D2 (W_M_155) is smaller than the length in the second direction D2 of the upper surface (US_155) of the gate electrode layer 155 (W_US_155) and the length in the second direction D2 of the lower surface (BS_155) (W_BS_155). The length of the upper surface (US_155) of the gate electrode layer 155 in the second direction D2 (W_US_155) is smaller than the length of the lower surface (BS_155) in the second direction D2 (W_BS_155). Figure 8 shows that the length of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 (W_BS_155) is greater than the length of the upper surface (US_156) of the second hard mask layer 156 in the second direction D2 (W_US_156) and the length of the lower surface (BS_156) in the second direction D2 (W_BS_156), but this is illustrative. As another example, the length of the lower surface (BS_155) of the gate electrode layer 155 in the second direction D2 (W_BS_155) is smaller than the length of the upper surface (US_156) of the second hard mask layer 156 in the second direction D2 (W_US_156) and the length of the lower surface (BS_156) in the second direction D2 (W_BS_156).

[0096] Figure 9 is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' in Figure 1. Figure 10 is an enlarged cross-sectional view of portion Q in Figure 9. Since the embodiments shown in Figures 9 and 10 are identical in parts to those shown in Figures 2 and 4, a detailed explanation of them will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0097] Referring to Figures 9 and 10, the length of the source electrode 173 in the second direction D2 (W_173) is greater than or equal to the length of the first barrier layer doping region 1361 in the second direction D2 (W_1361). Furthermore, the length of the source electrode 173 in the second direction D2 (W_173) is greater than or equal to the length of the first channel layer doping region 1321 in the second direction D2 (W_1321). For example, the length of the source electrode 173 in the second direction D2 (W_173) is greater than the length of the first barrier layer doping region 1361 in the second direction D2 (W_1361) or the length of the first channel layer doping region 1321 in the second direction D2 (W_1321) by more than 0 μm and less than or equal to 0.2 μm. Similarly, the length of the drain electrode 175 in the second direction D2 is greater than or equal to the length of the second barrier layer doping region 1362 in the second direction D2. Furthermore, the length of the drain electrode 175 in the second direction D2 is greater than or equal to the length of the second channel layer doping region 1322 in the second direction D2. For example, the length of the drain electrode 175 in the second direction D2 is greater than the length of the second barrier layer doping region 1362 in the second direction D2 by more than 0 μm and less than or equal to 0.2 μm, compared to the length of the second channel layer doping region 1322 in the second direction D2.

[0098] Figure 11 is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' in Figure 1. Figure 12 is an enlarged cross-sectional view of portion Q in Figure 11. Since the embodiments shown in Figures 11 and 12 correspond to the same parts as the embodiments shown in Figures 2 and 4, a detailed explanation of them will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0099] Referring to Figures 11 and 12, the source electrode 173 has a first portion 1731 and a second portion 1732. The first portion 1731 is positioned on top of the first barrier layer doping region 1361. The lower surface (BS_1731) of the first portion 1731 is in contact with the upper surface (US_1361) of the first barrier layer doping region 1361. Part 2, 1732, is placed below Part 1, 1731. The lower surface (BS_1731) of the first part 1731 is in contact with the upper surface (US_1732) of the second part 1732. The second part 1732 is located within the first barrier layer doping region 1361. For example, the second portion 1732 protrudes from the first portion 1731 toward the first barrier layer doping region 1361 and is positioned within the first barrier layer doping region 1361. One side of the second portion 1732 in the second direction D2 (SW_1732) is in contact with one side of the first barrier layer doping region 1361 in the second direction D2.

[0100] As will be described later in Figure 34, when the first gate semiconductor material layer (152_L in Figure 34) is etched to expose the barrier layer 136, a portion of the surface of the barrier layer 136 is etched, forming a first recess (R1 in Figure 34) on the surface of the barrier layer 136, so that one side surface (SW_1732) of the second portion 1732 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first barrier layer doping region 1361 can be increased, thereby mitigating electric field concentration. For example, the length of the upper surface (US_1732) of the second part 1732 in the second direction D2 (W_US_1732) is greater than the length of the lower surface (BS_1732) of the second part 1732 in the second direction D2 (W_BS_1732). The angle (θ_1732) between the second direction D2 side surface (SW_1732) of the second part 1732 and the upper surface (US_1361) of the first barrier layer doping region 1361 can be 90° or greater, for example, greater than 90°, 95° or greater, 100° or greater, 105° or greater, 110° or greater, or 115° or greater, and can be 120° or less, for example, less than 120°, 115° or less, 110° or less, 105° or less, 100° or less, or 95° or less, and can be between 90° and 120°.

[0101] Furthermore, the length of the upper surface (US_1732) of the second part 1732 in the second direction D2 (W_US_1732) is smaller than the length of the lower surface (BS_1731) of the first part 1731 in the second direction D2 (W_BS_1731). In other words, a portion of the lower surface (BS_1731) of the first portion 1731 is in contact with the upper surface (US_1732) of the second portion 1732, while the other portion of the lower surface (BS_1731) of the first portion 1731 that is not in contact with the upper surface (US_1732) of the second portion 1732 is in contact with the upper surface (US_1361) of the first barrier layer doping region 1361. For example, the second portion 1732 extends downward in the third direction D3 but does not penetrate the first barrier layer doping region 1361. The lower surface (BS_1732) of the second portion 1732 does not come into contact with the upper surface (US_1321) of the first channel layer doping region 1321. A portion of the first barrier layer doping region 1361 is positioned between the second portion 1732 and the first channel layer doping region 1321.

[0102] In other words, the level of the lower surface of the second portion 1732 (BS_1732) in the third direction D3 is higher than the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3, and higher than the level of the upper surface of the first channel layer doping region 1321 (US_1321) in the third direction. The level of the lower surface (BS_1732) of the second section 1732 in the third direction D3 is lower than the level of the upper surface (US_1361) of the first barrier layer doping region 1361 in the third direction D3. The level of the lower surface (BS_1732) of the second section 1732 in the third direction D3 is located within the first barrier layer doping region 1361.

[0103] Similarly, the drain electrode 175 has a first portion and a second portion. The first portion of the drain electrode 175 is positioned on the second barrier layer doping region 1362. Part 2 is placed below Part 1. The second portion is located within the second barrier layer doping region 1362. For example, the second portion protrudes from the first portion toward the second barrier layer doping region 1362 and is positioned within the second barrier layer doping region 1362. One side of the second part in the second direction D2 has an inclination. For example, the length of the upper surface of the second part in the second direction D2 is greater than the length of the lower surface of the second part in the second direction D2. Furthermore, the length of the upper surface of the second part in the second direction D2 is smaller than the length of the lower surface of the first part in the second direction D2. Furthermore, the second portion extends downward in the third direction D3, but does not penetrate the second barrier layer doping region 1362. The descriptions of the other parts of the drain electrode 175, specifically the first and second parts, are the same as those of the first part 1731 and second part 1732 of the source electrode 173, so repetitive descriptions are omitted.

[0104] Figure 13 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 11. Since the embodiment shown in Figure 13 has the same parts as the embodiment shown in Figure 12, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0105] Referring to Figure 13, the second portion 1732 of the source electrode 173 extends downward in the third direction D3 and penetrates the first barrier layer doping region 1361. The second section 1732 is connected to the first channel layer doping region 1321. The lower surface (BS_1732) of the second portion 1732 is in contact with the upper surface (US_1321) of the first channel layer doping region 1321. In other words, the level of the lower surface of the second section 1732 (BS_1732) in the third direction D3 is the same as the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3, and the same as the level of the upper surface of the first channel layer doping region 1321 (US_1321) in the third direction. Similarly, the second portion of the drain electrode 175 extends downward in the third direction D3 and penetrates the second barrier layer doping region 1362. The second part is connected to the second channel layer doping region 1322.

[0106] Figure 14 is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' in Figure 1, and Figure 15 is an enlarged cross-sectional view of portion Q in Figure 14. Since the embodiments shown in Figures 14 and 15 correspond to the same parts as the embodiments shown in Figures 11 and 13, a detailed explanation of these will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0107] Referring to Figures 14 and 15, the source electrode 173 further has a third portion 1733. Part 3, 1733, is placed below Part 2, 1732. The lower surface (BS_1732) of the second part 1732 is in contact with the upper surface (US_1733) of the third part 1733. The third portion 1733 is located within the first channel layer doping region 1321. For example, the third portion 1733 protrudes from the second portion 1732 toward the first channel layer doping region 1321 and is positioned within the first channel layer doping region 1321. One side of the third portion 1733 in the second direction D2 (SW_1733) is in contact with one side of the first channel layer doping region 1321 in the second direction D2.

[0108] As will be described later in Figure 40, when the first protective layer 140 is formed and a part of the first protective layer 140 is etched to expose the first channel layer doping region 1321, a part of the surface of the first channel layer doping region 1321 is etched, and a second recess (R2 in Figure 40) is formed on the surface of the first channel layer doping region 1321, so that one side surface (SW_1733) of the third portion 1733 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first channel layer doping region 1321 can be increased, thereby mitigating electric field concentration.

[0109] For example, the length of the upper surface (US_1733) of the third part 1733 in the second direction D2 (W_US_1733) is the same as the length of the lower surface (BS_1733) of the third part 1733 in the second direction D2 (W_BS_1732). The angle (θ_1733) between the second direction D2 side surface (SW_1733) of the third part 1733 and the upper surface (US_1321) of the first channel layer doping region 1321 can be 90° or greater, for example, greater than 90°, greater than 95°, greater than 100°, greater than 105°, greater than 110°, or greater than 115°, and 120° or less, for example, less than 120°, less than or equal to 115°, less than or equal to 110°, less than or equal to 105°, less than or equal to 100°, or less than or equal to 95°, and can be between 90° and 120°. In one embodiment, the length of the upper surface (US_1733) of the third portion 1733 in the second direction D2 (W_US_1733) is smaller than the length of the lower surface (BS_1732) of the second portion 1732 in the second direction D2 (W_BS_1732). In other words, a portion of the lower surface (BS_1732) of the second portion 1732 is in contact with the upper surface (US_1733) of the third portion 1733, while the other portion of the lower surface (BS_1732) of the second portion 1732 that is not in contact with the upper surface (US_1733) of the third portion 1733 is in contact with the upper surface (US_1321) of the first channel layer doping region 1321.

[0110] The second portion 1732 of the source electrode 173 extends downward in the third direction D3 and penetrates the first barrier layer doping region 1361. The second section 1732 is connected to the first channel layer doping region 1321. The lower surface (BS_1732) of the second portion 1732 is in contact with the upper surface (US_1321) of the first channel layer doping region 1321. In other words, the level of the lower surface of the second section 1732 (BS_1732) in the third direction D3 is the same as the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3, and the same as the level of the upper surface of the first channel layer doping region 1321 (US_1321) in the third direction.

[0111] The third portion 1733 of the source electrode 173 extends downward in the third direction D3, but does not penetrate the first channel layer doping region 1321. The third portion 1733 does not contact the lower surface of the first channel layer doping region 1321, and a portion of the first channel layer doping region 1321 is positioned between the third portion 1733 and the lower surface of the first channel layer doping region 1321. In other words, the level of the lower surface of the third section 1733 (BS_1733) in the third direction D3 is lower than the level of the lower surface of the first barrier layer doping region 1361 in the third direction D3, and lower than the level of the upper surface of the first channel layer doping region 1321 (US_1321) in the third direction D3. Also, the level of the lower surface (BS_1733) of the third portion 1733 in the third direction D3 is higher than the level of the lower surface of the first channel layer doping region 1321 in the third direction D3, and the third direction D3 of the lower surface (BS_1733) of the third portion 1733 is disposed within the first channel layer doping region 1321.

[0112] Similarly, the drain electrode 175 further has a third portion. The third portion of the drain electrode 175 is disposed under the second portion. The third portion is disposed within the second channel layer doping region 1322. For example, the third portion protrudes from the second portion toward the second channel layer doping region 1322 and is disposed within the second channel layer doping region 1322. One side surface of the third portion in the second direction D2 has an inclination. The length of the upper surface of the third portion in the second direction D2 is smaller than the length of the lower surface of the third portion in the second direction D2. The third portion extends under the third direction D3 but does not penetrate the second channel layer doping region 1322. The description of the third portion of the other drain electrode 175 is the same as the description of the third portion 1733 of the source electrode 173, so repetitive descriptions are omitted.

[0113] FIG. 16 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of the Q portion of FIG. 14. Since the embodiment shown in FIG. 16 corresponds to the same portion as the embodiment shown in FIG. 15, the description thereof is omitted, and the differences will be mainly described. Also, the same reference numerals are used for the same components as in the previous embodiment.

[0114] Referring to FIG. 16, the length (W_US_1732) of the upper surface (US_1732) of the second portion 1732 in the second direction D2 is smaller than the length (W_BS_1731) of the lower surface (BS_1731) of the first portion 1731 in the second direction D2. In other words, a portion of the lower surface (BS_1731) of the first portion 1731 is in contact with the upper surface (US_1732) of the second portion 1732, while the other portion of the lower surface (BS_1731) of the first portion 1731 that is not in contact with the upper surface (US_1732) of the second portion 1732 is in contact with the upper surface (US_1361) of the first barrier layer doping region 1361. The length of the upper surface (US_1732) of the second part 1732 in the second direction D2 (W_US_1732) is greater than the length of the lower surface (BS_1732) of the second part 1732 in the second direction D2 (W_BS_1732). Furthermore, the length of the upper surface (US_1733) of the third part 1733 in the second direction D2 (W_US_1733) is the same as the length of the lower surface (BS_1732) of the second part 1732 in the second direction D2 (W_BS_1732).

[0115] In one embodiment, the length of the upper surface (US_1733) of the third portion 1733 in the second direction D2 (W_US_1733) is smaller than the length of the lower surface (BS_1732) of the second portion 1732 in the second direction D2 (W_BS_1732). In other words, a portion of the lower surface (BS_1732) of the second portion 1732 is in contact with the upper surface (US_1733) of the third portion 1733, while the other portion of the lower surface (BS_1732) of the second portion 1732 that is not in contact with the upper surface (US_1733) of the third portion 1733 is in contact with the upper surface (US_1321) of the first channel layer doping region 1321. The length of the upper surface (US_1733) of the third part 1733 in the second direction D2 (W_US_1733) is greater than the length of the lower surface (BS_1733) of the third part 1733 in the second direction D2 (W_BS_1733). The angle (θ_1732) between one side surface in the second direction D2 of the second part 1732 (SW_1732) and the upper surface (US_1361) of the first barrier layer doping region 1361 is the same as the angle (θ_1733) between one side surface in the second direction D2 of the third part 1733 (SW_1733) and the upper surface (US_1321) of the first channel layer doping region 1321.

[0116] In one embodiment, the angle (θ_1732) between one side surface (SW_1732) of the second portion 1732 in the second direction D2 and the upper surface (US_1361) of the first barrier layer doping region 1361 is different from the angle (θ_1733) between one side surface (SW_1733) of the third portion 1733 in the second direction D2 and the upper surface (US_1321) of the first channel layer doping region 1321. For example, the angle (θ_1732) between one side surface (SW_1732) of the second part 1732 in the second direction D2 and the upper surface (US_1361) of the first barrier layer doping region 1361 is greater than or less than the angle (θ_1733) between one side surface (SW_1733) of the third part 1733 in the second direction D2 and the upper surface (US_1321) of the first channel layer doping region 1321. Similarly, the length of the upper surface of the second portion of the drain electrode 175 in the second direction D2 is smaller than the length of the lower surface of the first portion in the second direction D2. The length of the upper surface of the third part in the second direction D2 is less than the length of the lower surface of the second part in the second direction D2. The angle between one side surface in the second direction D2 of the second part and the upper surface of the second barrier layer doping region 1362 is the same as or different from the angle between one side surface in the second direction D2 of the third part and the upper surface of the second channel layer doping region 1322. The description of the other parts of the drain electrode 175 (1731, 1732, 1733) is the same as the description of the parts of the source electrode 173 (1731, 1732, 1733), so a repetitive explanation will be omitted.

[0117] Figure 17 is a cross-sectional view according to another embodiment of the present invention, which is a cross-sectional view taken along the line A-A' in Figure 1, and Figure 18 is an enlarged cross-sectional view of portion Q in Figure 17. Since the embodiments shown in Figures 17 and 18 have the same parts as the embodiments shown in Figures 14 and 15, a detailed explanation of them will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0118] Referring to Figures 17 and 18, the second portion 1732 of the source electrode 173 further comprises the (2-1) portion 17321 and the (2-2) portion 17322. Part (2-1) 17321 is placed below Part 1 1731. Part (2-2) 17322 is placed below Part (2-1) 17321. The (2-2) portion 17322 is located between the (2-1) portion 17321 and the first channel layer doping region 1321. Alternatively, part (2-2) 17322 is placed between part (2-1) 17321 and part 3 1733. Part (2-1) 17321 and Part (2-2) 17322 are located within the first barrier layer doping region 1361.

[0119] For example, the length (W_US_17321) of the upper surface (US_17321) of part (2-1) 17321 in the second direction D2 is greater than or equal to the length (W_BS_17321) of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2. The length (W_BS_17321) of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 is greater than or equal to the length (W_US_17322) of the upper surface (US_17322) of part (2-2) 17322 in the second direction D2. The length (W_US_17322) of the upper surface (US_17322) of part (2-2) 17322 in the second direction D2 is greater than or equal to the length (W_BS_17322) of the lower surface (BS_17322) of part (2-2) 17322 in the second direction D2. The length of the upper surface (US_17321) of part (2-1) 17321 in the second direction D2 (W_US_17321) is greater than the length of the lower surface (BS_17322) of part (2-2) 17322 in the second direction D2 (W_BS_17322).

[0120] As an example, in Figure 18, the length of the upper surface (US_17321) of the (2-1) part 17321 in the second direction D2 (W_US_17321) is greater than the length of the lower surface (BS_17321) of the (2-1) part 17321 in the second direction D2 (W_BS_17321), and the length of the lower surface (BS_17321) of the (2-1) part 17321 in the second direction D2 (W_BS_17321) is The figure shows the case where the length of the upper surface (US_17322) of part (2-2) 17322 in the second direction D2 (W_US_17322) is the same as the length of the upper surface (US_17322) of part (2-2) 17322 in the second direction D2 (W_US_17322), and the length of the lower surface (BS_17322) of part (2-2) 17322 in the second direction D2 (W_BS_17322). Similarly, the second part of the drain electrode 175 also has a (2-1) part and a (2-2) part. The description of the other second parts of the drain electrode 175 is the same as the description of the second part 1732 of the source electrode 173, so a repetitive explanation will be omitted.

[0121] Figure 19 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 18. Since the embodiment shown in Figure 19 has the same parts as the embodiment shown in Figure 18, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0122] Referring to Figure 19, the length of the upper surface (US_17321) of the (2-1) part 17321 in the second direction D2 (W_US_17321) is the same as the length of the lower surface (BS_17321) of the (2-1) part 17321 in the second direction D2 (W_BS_17321), and the length of the lower surface (BS_17321) of the (2-1) part 17321 in the second direction D2 (W_BS_17321) is This shows the case where the length of the upper surface (US_17322) of the (2-2) part 17322 in the second direction D2 (W_US_17322) is the same, and the length of the upper surface (US_17322) of the (2-2) part 17322 in the second direction D2 (W_US_17322) is greater than the length of the lower surface (BS_17322) of the (2-2) part 17322 in the second direction D2 (W_BS_17322). The explanation of the second part of the drain electrode 175 is the same as the explanation of the second part 1732 of the source electrode 173, so a repetitive explanation will be omitted.

[0123] Figure 20 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. Since the embodiment shown in Figure 20 has the same parts as the embodiment shown in Figure 18, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0124] Referring to Figure 20, the third portion 1733 of the source electrode 173 further comprises the (3-1) portion 17331 and the (3-2) portion 17332. Part (3-1) 17331 is placed below Part 2 1732. Part (3-2) 17332 is placed below Part (3-1) 17331. The (3-2) portion 17332 is located between the (3-1) portion 17331 and the first channel layer doping region 1321. Parts (3-1) 17331 and (3-2) 17332 are located within the first channel layer doping region 1321. As an example, the length (W_US_17331) in the second direction D2 of the upper surface (US_17331) of the (3-1) part 17331 is greater than or equal to the length (W_BS_17331) in the second direction D2 of the lower surface (BS_17331) of the (3-1) part 17331. The length (W_BS_17331) in the second direction D2 of the lower surface (BS_17331) of the (3-1) part 17331 is greater than or equal to the length (W_US_17332) in the second direction D2 of the upper surface (US_17332) of the (3-2) part 17332. The length (W_US_17332) in the second direction D2 of the upper surface (US_17332) of the (3-2) part 17332 is greater than or equal to the length (W_BS_17322) in the second direction D2 of the lower surface (BS_17332) of the (3-2) part 17332. The length (W_US_17331) in the second direction D2 of the upper surface (US_17331) of the (3-1) part 17331 is greater than the length (W_BS_17332) in the second direction D2 of the lower surface (BS_17332) of the (3-2) part 17332.

[0125] Also, referring to FIG. 20, the length (W_US_17331) in the second direction D2 of the upper surface (US_17331) of the (3-1) part 17331 is greater than the length (W_BS_17331) in the second direction D2 of the lower surface (BS_17331) of the (3-1) part 17331, the length (W_BS_17331) in the second direction D2 of the lower surface (BS_17331) of the (3-1) part 17331 is the same as the length (W_US_17332) in the second direction D2 of the upper surface (US_17332) of the (3-2) part 17332, and the length (W_US_17332) in the second direction D2 of the upper surface (US_17332) of the (3-2) part 17332 is the same as the length (W_BS_17332) in the second direction D2 of the lower surface (BS_17332) of the (3-2) part 17332 are shown. Similarly, the third part of the drain electrode 175 also further has the (3-1) part and the (3-2) part. The description of the other third parts of the drain electrode 175 is the same as the description of the third part 1733 of the source electrode 173, so a repetitive explanation will be omitted.

[0126] Figure 21 is a cross-sectional view according to another embodiment of the present invention, and is an enlarged cross-sectional view of portion Q in Figure 17. Since the embodiment shown in Figure 21 has the same parts as the embodiment shown in Figure 20, a detailed explanation of it will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0127] Referring to Figure 21, the length of the upper surface (US_17331) of part (3-1) 17331 in the second direction D2 (W_US_17331) is the same as the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331), and the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331) is This shows the case where the length of the upper surface (US_17332) of the (3-2) part 17332 in the second direction D2 (W_US_17332) is the same as the length of the upper surface (US_17332) of the (3-2) part 17332 in the second direction D2 (W_US_17332) is greater than the length of the lower surface (BS_17332) of the (3-2) part 17332 in the second direction D2 (W_BS_17332). The explanation of the third part of the drain electrode 175 is the same as the explanation of the third part 1733 of the source electrode 173, so a repetitive explanation will be omitted.

[0128] Figures 22 and 23 are cross-sectional views according to another embodiment of the present invention, and are enlarged cross-sectional views of portion Q in Figure 17. Since the embodiments shown in Figures 22 and 23 are equivalent to those shown in Figure 18, a detailed explanation of them will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0129] Referring to Figures 22 and 23, the second portion 1732 of the source electrode 173 further comprises the (2-1) portion 17321 and the (2-2) portion 17322, and the third portion 1733 of the source electrode 173 further comprises the (3-1) portion 17331 and the (3-2) portion 17332. In Figure 22, the length of the upper surface (US_17321) of part (2-1) 17321 in the second direction D2 (W_US_17321) is greater than the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321), and the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321) is greater than the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321). 2-2) The length of the upper surface (US_17322) of part 17322 in the second direction D2 (W_US_17322) is the same as the length of the upper surface (US_17322) of part (2-2) of part 17322 in the second direction D2 (W_US_17322) is the same as the length of the lower surface (BS_17322) of part (2-2) of part 17322 in the second direction D2 (W_BS_17322).

[0130] Furthermore, the length of the upper surface (US_17331) of part (3-1) 17331 in the second direction D2 (W_US_17331) is the same as the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331), and the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331) is the same as the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331). -2) The length of the upper surface (US_17332) of part 17332 in the second direction D2 (W_US_17332) is the same, and the length of the upper surface (US_17332) of part 17332 in the second direction D2 (W_US_17332) is greater than the length of the lower surface (BS_17332) of part 17332 in the second direction D2 (W_BS_17332). In Figure 23, the length of the upper surface (US_17321) of part (2-1) 17321 in the second direction D2 (W_US_17321) is greater than the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321), and the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321) is greater than the length of the lower surface (BS_17321) of part (2-1) 17321 in the second direction D2 (W_BS_17321). 2-2) The length of the upper surface (US_17322) of part 17322 in the second direction D2 (W_US_17322) is the same as the length of the upper surface (US_17322) of part (2-2) of part 17322 in the second direction D2 (W_US_17322) is the same as the length of the lower surface (BS_17322) of part (2-2) of part 17322 in the second direction D2 (W_BS_17322).

[0131] Furthermore, the length of the upper surface (US_17331) of part (3-1) 17331 in the second direction D2 (W_US_17331) is greater than the length of the lower surface (BS_17331) of part (3-1) 17331 in the second direction D2 (W_BS_17331), and the length of the lower surface (BS_17331) of part (3- 1) 17331 in the second direction D2 (W_BS_17331) is greater than the length of the lower surface (BS_17331) of part (3- 2) The length of the upper surface (US_17332) of part 17332 in the second direction D2 (W_US_17332) is the same as the length of the upper surface (US_17332) of part (3-2) of part 17332 in the second direction D2 (W_US_17332) is the same as the length of the lower surface (BS_17332) of part (3-2) of part 17332 in the second direction D2 (W_BS_17332). The description of the second and third parts of the drain electrode 175 is the same as the description of the second part 1732 and the third part 1733 of the source electrode 173, so a repetitive explanation will be omitted.

[0132] Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 24 to 32. At the same time, refer to Figures 1 to 4, which were explained earlier. Figures 24 to 32 are cross-sectional process views illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention.

[0133] Referring to Figure 24, a seed layer 115, a buffer layer 120, a channel layer 132, and a barrier layer 136 are sequentially formed on the substrate 110. Furthermore, a gate semiconductor material layer (152_L) is formed on top of the barrier layer 136. As an example, the seed layer 115, buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor material layer (152_L) are formed sequentially using an epitaxial growth method. A seed layer 115 is first formed on the substrate 110, and then a buffer layer 120 is formed on top of the seed layer 115. The buffer layer 120 includes a superlattice layer and a high-resistivity layer. A channel layer 132 is formed on the buffer layer 120, a barrier layer 136 is formed on the channel layer 132, and a gate semiconductor material layer (152_L) is formed on the barrier layer 136.

[0134] For example, the equipment used to grow the seed layer 115, buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor material layer (152_L) may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE). The seed layer 115, buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor material layer (152_L) are made of semiconductor material from the same substrate. However, the material composition ratio of each layer may differ, taking into consideration the role of each layer and the performance required of the semiconductor device.

[0135] As an example, the substrate 110 contains Si, the seed layer 115 contains AlN, and the superlattice layer of the buffer layer 120 has a structure in which layers made of AlGaN and layers made of GaN are repeatedly stacked. The high-resistance layer of the buffer layer 120 contains GaN, the channel layer 132 contains GaN, and the barrier layer 136 contains AlGaN. The channel layer 132 and the barrier layer 136 may or may not be doped with impurities. The gate semiconductor material layer (152_L) contains GaN and is doped with impurities. The gate semiconductor material layer (152_L) is doped with p-type impurities, such as magnesium (Mg). Due to the difference in lattice structures between Si and GaN, it can be difficult to grow a channel layer 132 made of GaN directly on a substrate 110 made of Si. Therefore, by forming a seed layer 115 or a buffer layer 120 on the substrate 110 first, and then forming the channel layer 132, the lattice structure of the channel layer 132 can be stably formed.

[0136] Next, a first photoresist pattern PR1 is formed on the gate semiconductor material layer (152_L). First, a photoresist composition is coated onto the gate semiconductor material layer (152_L) to form a photoresist film. As an example, a photoresist film is formed by applying a photoresist composition onto a gate semiconductor material layer (152_L) using methods such as spin coating, spray coating, dip coating, or knife-edge coating, or by applying it using printing methods such as inkjet printing or screen printing, and then drying the applied photoresist composition. A first photoresist pattern PR1 is formed by selectively exposing a photoresist film and dissolving and removing the unexposed or exposed areas of the photoresist film using a developer. As an example, the region exposed by the first photoresist pattern PR1 is the region where the source electrode 173 and drain electrode 175 will be formed later.

[0137] Referring to Figure 25, a portion of the gate semiconductor material layer (152_L) exposed by the first photoresist pattern PR1 is ion-doped. As an example, ion doping uses the ion implantation (IIP) method. By adjusting the power of the ion implant, you can control the depth to which ions are doped. Ions are doped into the gate semiconductor material layer (152L), the barrier layer 136, and the channel layer 132, with the most ions being doped into the barrier layer 136, for example. In this case, since ion doping is performed on the surface of the gate semiconductor material layer (152_L), the power of the ion implant can be, for example, 30 eV to 80 eV. In the region where the source electrode 173 is formed, a first gate semiconductor material layer doping region 1521 is formed in the gate semiconductor material layer (152_L), a first barrier layer doping region 1361 is formed in the barrier layer 136, and a first channel layer doping region 1321 is formed in the channel layer 132. Furthermore, in the region where the drain electrode 175 is formed, a second gate semiconductor material layer doping region 1522 is formed in the gate semiconductor material layer (152_L), a second barrier layer doping region 1362 is formed in the barrier layer 136, and a second channel layer doping region 1322 is formed in the channel layer 132.

[0138] After ion doping, the first photoresist pattern PR1 is removed, and the ion-doped first barrier layer doping region 1361, first channel layer doping region 1321, second barrier layer doping region 1362, and second channel layer doping region 1322 are annealed at high temperature. For example, the annealing temperature can be 1100°C or higher, for example, 1200°C or higher, 1300°C or higher, 1400°C or higher, 1500°C or higher, 1600°C or higher, 1700°C or higher, 1800°C or higher, or 1900°C or higher, and 2000°C or lower, for example, 1900°C or lower, 1800°C or lower, 1700°C or lower, 1600°C or lower, 1500°C or lower, 1400°C or lower, 1300°C or lower, or 1200°C or lower, for example, 1100°C to 2000°C.

[0139] In one embodiment, after forming the first barrier layer doping region 1361, the first gate semiconductor material layer doping region 1521 and the second gate semiconductor material layer doping region 1522 are etched and removed using the first photoresist pattern PR1, exposing the first barrier layer doping region 1361 and the second barrier layer doping region 1362. At this time, a portion of the surface of the first barrier layer doping region 1361 and the second barrier layer doping region 1362 is etched, and a first recess (R1 in Figure 35), which will be described later in Figure 35, is formed on the surface of the first barrier layer doping region 1361 and the second barrier layer doping region 1362. As a result, one side (SW_1732) of the second portion 1732 of the source electrode 173 in the second direction D2 has a slope. Furthermore, one side of the second portion of the drain electrode 175 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first barrier layer doping region 1361 is increased, and the contact area between the drain electrode 175 and the second barrier layer doping region 1362 is increased to mitigate electric field concentration.

[0140] Referring to Figure 26, a gate electrode material layer (155_L) is formed on top of the gate semiconductor material layer (152_L). In other words, the gate semiconductor material layer (152_L) is located between the barrier layer 136 and the gate electrode material layer (155_L). As an example, the gate electrode material layer (155_L) is formed using a vapor deposition process. For example, the gate electrode material layer (155_L) can be formed using, but is not limited to, electron beam evaporation (E-beam evaporation), sputtering, physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD).

[0141] A first hard mask material layer (156_L) is formed on top of the gate electrode material layer (155_L). For example, the first hard mask material layer (156_L) is a spin-on hardmask layer (SOH). The spin-on hard mask material layer is formed on the gate electrode material layer (155_L) through a spin coating process. The first hard mask material layer (156_L) may include silicon oxide, silicon nitride, silicon nitride, or a combination thereof.

[0142] Next, a second photoresist pattern PR2 is formed on the first hard mask material layer (156_L). First, a photoresist composition is coated onto the first hard mask material layer (156_L) to form a photoresist film. As an example, a photoresist film is formed by applying a photoresist composition onto a first hard mask material layer (156_L) using methods such as spin coating, spray coating, dip coating, or knife-edge coating, or by applying it using printing methods such as inkjet printing or screen printing, and then drying the applied photoresist composition. Next, the photoresist film is selectively exposed. A second photoresist pattern PR2 is formed by dissolving and removing the photoresist film corresponding to the unexposed or exposed areas using a developing solution.

[0143] Referring to Figures 27 and 28, the second photoresist pattern PR2 is used to etch the first hard mask material layer (156_L) and the gate electrode material layer (155_L) to form the second hard mask layer 156 and the gate electrode layer 155. As an example, the etching of the first hard mask material layer (156_L) and the gate electrode material layer (155_L) is performed by dry etching using the first etching gas. The first etching gas includes a fluoride gas, which may include, for example, CHF3, CF4, or a mixture thereof. At this time, etching of the first hard mask material layer (156_L) and the gate electrode material layer (155_L) is performed sequentially. Alternatively, the first hard mask material layer (156_L) is etched first, and then the gate electrode material layer (155_L) is etched. In this case as well, etching of the first hard mask material layer (156_L) and the gate electrode material layer (155_L) is performed using the same first etching gas. In this way, by forming the gate electrode layer 155 using the second photoresist pattern PR2 and forming the gate semiconductor layer 152 using the second hard mask layer 156 as described later, the gate electrode layer 155 can be etched with the first etching gas and the gate semiconductor layer 152 can be etched with the second etching gas, increasing the degree of freedom in selecting the etching material for the gate electrode layer 155 and the gate semiconductor layer 152.

[0144] Referring to Figure 29, the gate semiconductor material layer (152_L) is etched using the second hard mask layer 156 to form the gate semiconductor layer 152. As an example, the gate semiconductor material layer (152_L) is patterned using the second hard mask layer 156. Therefore, the gate semiconductor layer 152 has a pattern similar to that of the gate electrode layer 155. In other words, the gate semiconductor layer 152 and the gate electrode layer 155 are self-aligned, which facilitates and improves the alignment between the gate electrode layer 155 and the gate semiconductor layer 152. Because the loss of the second hard mask layer 156 is less than that of the second photoresist pattern PR2, the pattern of the gate semiconductor layer 152 is precise.

[0145] In one embodiment, at this time, a portion of the surface of the first barrier layer doping region 1361 and the second barrier layer doping region 1362 is etched, and a first recess (R1 in Figure 35), which will be described later in Figure 35, is formed on the surface of the first barrier layer doping region 1361 and the second barrier layer doping region 1362. As a result, one side (SW_1732) of the second portion 1732 of the source electrode 173 in the second direction D2 has a slope. Furthermore, one side of the second portion of the drain electrode 175 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first barrier layer doping region 1361 is increased, and the contact area between the drain electrode 175 and the second barrier layer doping region 1362 is increased to mitigate electric field concentration.

[0146] As an example, the gate semiconductor material layer (152_L) is etched using dry etching with a second etching gas. Unlike the first etching gas, the second etching gas contains chloride gas, which may include, for example, Cl2, BCl3, or a mixture thereof. In the process of etching the gate semiconductor material layer (152_L), selective etching process conditions are required to have a difference in etching rate between the gate semiconductor material layer (152_L) and the barrier layer 136 in order to minimize damage to the barrier layer 136. For example, the barrier layer 136 made of AlGaN is hardly etched, while the gate semiconductor material layer (152_L) made of p-GaN is frequently etched. At this time, oxygen (O2) is added to the etching gas to use a surface oxidation etching method. As a result, if the barrier layer 136 has a predetermined thickness without being damaged, the channel layer 132 has a high current density. At this time, when the gate semiconductor layer 152 is etched, the second hard mask layer 156 is partially etched depending on the etching conditions, and the second hard mask layer 156 has a shape in which the corners formed by the top surface (US_156) and the side surface (SW_156) are rounded.

[0147] In one embodiment, before etching the gate electrode layer 155 and the gate semiconductor layer 156, or after etching both the gate electrode layer 155 and the gate semiconductor layer 156, a treatment process is performed to remove by-products and reduce damage to the barrier layer 136 by dry etching. For example, by-product removal is carried out through an ashing or stripping process. The ashing and stripping processes are performed sequentially. For example, first, an ashing process is performed to remove impurities through an oxygen (O2) plasma treatment process or an ozone (O3) treatment process, followed by a stripping process. In addition to the ashing or stripping process, dry and wet treatment processes are performed separately. For example, the treatment process may include, for instance, a dry cleaning process using N2O plasma, N2 plasma, NH3 plasma, or O2 plasma, or a wet cleaning process using diluted HF (DHF), BOE, or ammonia water (NH4OH). In this process, the second photoresist pattern PR2 is removed, and the second hard mask layer 156 that remained on the gate electrode layer 155 is removed.

[0148] Referring to Figure 30, the first protective layer 140 is formed on the barrier layer 136, the first barrier layer doping region 1361, the second barrier layer doping region 1362, the gate semiconductor layer 152, and the gate electrode layer 155. The first protective layer 140 is formed using a vapor deposition process. The first protective layer 140 contains an insulating material. For example, the first protective layer 140 may contain a substance such as SiO2, SiN, SiON, or Al2O3. The first protective layer 140 is shown as a single layer in the diagram, but it may consist of multiple layers depending on the circumstances. At this time, different materials are sequentially deposited to form the first protective layer 140. Alternatively, by using the same material and applying different deposition conditions, a first protective layer 140 consisting of multiple layers with mutually different properties is formed.

[0149] In particular, the portion of the first protective layer 140 adjacent to the barrier layer 136 is made of an insulating material of much higher quality than the other portions. This is to prevent electrons forming channels in the channel layer 132 located below the barrier layer 136 from being trapped. The portion of the first protective layer 140 that is in contact with the barrier layer 136 is made of SiO2. Thus, after first forming the gate electrode layer 155 and the gate semiconductor layer 152, the first protective layer 140 is formed to cover the barrier layer 136, the first barrier layer doping region 1361, the second barrier layer doping region 1362, the gate semiconductor layer 152, and the gate electrode layer 155, thereby ensuring that the first protective layer 140 completely covers the gate electrode layer 155. In this case, the alignment between the gate electrode layer 155 and the gate semiconductor layer 152 is improved.

[0150] Referring to Figures 31 and 32, the first protective layer 140 is patterned to form a trench, and the lower source electrode 173a and the lower drain electrode 175a are formed within the trench. As an example, trenches are formed in the region where the first barrier layer doping region 1361 and the first channel layer doping region 1321 are formed, and in the region where the second barrier layer doping region 1362 and the second channel layer doping region 1322 are formed. In one embodiment, during the process of forming the trench, not only the first protective layer 140 but also a portion of the first barrier layer doping region 1361 and the second barrier layer doping region 1362 are patterned together. Furthermore, the entirety of the first barrier layer doping region 1361 and the second barrier layer doping region 1362, and a portion of the first channel layer doping region 1321 and the second channel layer doping region 1322 are patterned together.

[0151] For example, when a portion of the first protective layer 140 is etched to expose the first channel layer doping region 1321 and the second channel layer doping region 1322, a portion of the surface of the first channel layer doping region 1321 and the second channel layer doping region 1322 is etched, and a second recess (R2 in Figure 40), which will be described later in Figure 40, is formed on the surface of the first channel layer doping region 1321 and the second channel layer doping region 1322. As a result, one side (SW_1733) of the third portion 1733 of the source electrode 173 in the second direction D2 has a slope. Furthermore, one side of the third portion of the drain electrode 175 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first channel layer doping region 1321 is increased, and the contact area between the drain electrode 175 and the second channel layer doping region 1322 is increased to alleviate electric field concentration. Furthermore, the first field dispersion layer 177a is formed in the process of forming the lower source electrode 173a and the lower drain electrode 175a.

[0152] Referring again to Figures 1 to 4, a second protective layer 150 is formed on the first protective layer 140, the lower source electrode 173a, the lower drain electrode 175a, and the first field dispersion layer 177a. A trench is formed by patterning the second protective layer 150, and an intermediate source electrode 173b and an intermediate drain electrode 175b are formed in the trench, along with the second field dispersion layer 177b. Furthermore, a third protective layer 160 is formed on the second protective layer 150, the intermediate source electrode 173b, the intermediate drain electrode 175b, and the second field dispersion layer 177b. A trench is formed by patterning the third protective layer 160, and the upper source electrode 173c and upper drain electrode 175c are formed in the trench, along with the third field dispersion layer 177c.

[0153] Figures 33 to 40 are cross-sectional process views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. Since the embodiments shown in Figures 33 to 40 correspond to the same parts as the embodiments shown in Figures 24 to 32, a detailed explanation of these will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previous embodiment.

[0154] Referring to Figure 33, a seed layer 115, a buffer layer 120, a channel layer 132, and a barrier layer 136 are sequentially formed on the substrate 110. Furthermore, a gate semiconductor material layer (152_L) is formed on the barrier layer 136, and a first hard mask layer HM1 is formed on the gate electrode material layer (155_L). The first hard mask layer HM1 is formed by first forming a hard mask material layer on the gate electrode material layer (155_L), then forming a first photoresist pattern PR1 on the hard mask material layer, and finally etching the hard mask material layer using the first photoresist pattern PR1. As an example, a hard mask material layer is a spin-on hardmask layer (SOH). The spin-on hard mask material layer is formed on the gate electrode material layer (155_L) through a spin coating process. The hard mask material layer may include silicon oxide, silicon nitride, silicon nitride, or a combination thereof. As an example, the first photoresist pattern PR1 and the region exposed by the first photoresist pattern PR1 are regions where the source electrode 173 and drain electrode 175 will be formed later.

[0155] Referring to Figure 34, a portion of the gate semiconductor material layer (152_L) is etched and removed using the first photoresist pattern PR1 or the first hard mask layer HM1, exposing the barrier layer 136. At this time, a portion of the surface of the barrier layer 136 is etched, and a first recess R1 is formed on the surface of the barrier layer 136. As a result, one side (SW_1732) of the second portion 1732 of the source electrode 173 in the second direction D2 has a slope. Furthermore, one side of the second portion of the drain electrode 175 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first barrier layer doping region 1361 is increased, and the contact area between the drain electrode 175 and the second barrier layer doping region 1362 is increased to mitigate electric field concentration.

[0156] Referring to Figure 35, a portion of the barrier layer 136 exposed by the first photoresist pattern PR1 or the first hard mask layer HM1 is ion-doped. As an example, ion doping uses the ion implantation (IIP) method. By adjusting the power of the ion implant, you can control the depth to which ions are doped. Ions are doped into the barrier layer 136 and the channel layer 132, with the barrier layer 136 being doped with the most abundant ions. In this case, since ion doping is performed directly on the surface of the barrier layer 136, the power of the ion implant can be, for example, 10 eV to 30 eV. In the region where the source electrode 173 is formed, a first barrier layer doping region 1361 is formed in the barrier layer 136, and a first channel layer doping region 1321 is formed in the channel layer 132. Furthermore, in the region where the drain electrode 175 is formed, a second barrier layer doping region 1362 is formed in the barrier layer 136, and a second channel layer doping region 1322 is formed in the channel layer 132.

[0157] Referring to Figure 36, after ion doping, the first photoresist pattern PR1 and the first hard mask layer HM1 are removed, and the ion-doped first barrier layer doping region 1361, first channel layer doping region 1321, second barrier layer doping region 1362, and second channel layer doping region 1322 are annealed at high temperature. For example, the annealing temperature can be 1100°C or higher, for example, 1200°C or higher, 1300°C or higher, 1400°C or higher, 1500°C or higher, 1600°C or higher, 1700°C or higher, 1800°C or higher, or 1900°C or higher, and 2000°C or lower, for example, 1900°C or lower, 1800°C or lower, 1700°C or lower, 1600°C or lower, 1500°C or lower, 1400°C or lower, 1300°C or lower, or 1200°C or lower.

[0158] Referring to Figure 37, a gate electrode material layer (155_L) is formed on top of the gate semiconductor material layer (152_L). Furthermore, a second hard mask material layer (156_L) is formed on top of the gate electrode material layer (155_L). Next, a second photoresist pattern PR2 is formed on the second hard mask material layer (156_L).

[0159] Referring to Figure 38, the second hard mask material layer (156_L) and the gate electrode material layer (155_L) are etched using the second photoresist pattern PR2 to form the second hard mask layer 156 and the gate electrode layer 155. The gate semiconductor layer 152 is formed by etching the gate semiconductor material layer (152_L) using the second hard mask layer 156. In one embodiment, before etching the gate electrode layer 155 and the gate semiconductor layer 156, or after etching both the gate electrode layer 155 and the gate semiconductor layer 156, a treatment process is performed to remove by-products and reduce damage to the barrier layer 136 by dry etching. In this process, the second photoresist pattern PR2 is removed along with the second hard mask layer 156 that remained on the gate electrode layer 155.

[0160] Referring to Figure 39, the first protective layer 140 is formed on the barrier layer 136, the first barrier layer doping region 1361, the second barrier layer doping region 1362, the gate semiconductor layer 152, and the gate electrode layer 155.

[0161] Referring to Figure 40, the first protective layer 140 is patterned to form a trench. As an example, trenches are formed in the region where the first barrier layer doping region 1361 and the first channel layer doping region 1321 are formed, and in the region where the second barrier layer doping region 1362 and the second channel layer doping region 1322 are formed. In one embodiment, during the process of forming the trench, not only the first protective layer 140 but also a portion of the first barrier layer doping region 1361 and the second barrier layer doping region 1362 are patterned together. Furthermore, the entirety of the first barrier layer doping region 1361 and the second barrier layer doping region 1362, and a portion of the first channel layer doping region 1321 and the second channel layer doping region 1322 are patterned together.

[0162] For example, when a portion of the first protective layer 140 is etched to expose the first channel layer doping region 1321 and the second channel layer doping region 1322, a portion of the surface of the first channel layer doping region 1321 and the second channel layer doping region 1322 is etched, and a second recess R2 is formed on the surface of the first channel layer doping region 1321 and the second channel layer doping region 1322. As a result, one side (SW_1733) of the third portion 1733 of the source electrode 173 in the second direction D2 has a slope. Furthermore, one side of the third portion of the drain electrode 175 in the second direction D2 has a slope. In this case, the contact area between the source electrode 173 and the first channel layer doping region 1321 is increased, and the contact area between the drain electrode 175 and the second channel layer doping region 1322 is increased to alleviate electric field concentration.

[0163] Referring again to Figures 1 to 4, the lower source electrode 173a and the lower drain electrode 175a are formed in the trench. In the process of forming the lower source electrode 173a and the lower drain electrode 175a, the first field dispersion layer 177a is formed together. Next, a second protective layer 150 is formed on the first protective layer 140, the lower source electrode 173a, the lower drain electrode 175a, and the first field dispersion layer 177a. A trench is formed by patterning the second protective layer 150, and an intermediate source electrode 173b and an intermediate drain electrode 175b are formed in the trench, along with the second field dispersion layer 177b. Furthermore, a third protective layer 160 is formed on the second protective layer 150, the intermediate source electrode 173b, the intermediate drain electrode 175b, and the second field dispersion layer 177b. A trench is formed by patterning the third protective layer 160, and the upper source electrode 173c and upper drain electrode 175c are formed in the trench, along with the third field dispersion layer 177c.

[0164] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0165] 110 circuit boards 115 Seed Layer 120 buffer layers 132 channel layer 134 Two-dimensional electron gas 136 Barrier layer 140, 150, 160 (1st to 3rd) protective layer 152 Gate Semiconductor Layer 155 Gate Stop 156 Second hard mask layer 173 Source electrode 173a Lower source electrode 173b Intermediate source electrode 173c Upper source electrode 175 Drain electrode 175a Lower drain electrode 175b Intermediate drain electrode 175c Upper drain electrode 177 Field Dispersion Layer 177a First field dispersion layer 177b Second field dispersion layer 177c Third field dispersion layer 1321, 1322 (1st and 2nd channel layer doping regions) 1361, 1362 (1st and 2nd) Barrier layer doping regions 1731, 1732, 1733 First to third parts of the source electrode 1751, 1752, 1753 First to third parts of the drain electrode

Claims

1. A semiconductor device, Channel layer and A barrier layer is placed on the channel layer, A gate electrode layer is disposed on the barrier layer and extends in a first direction horizontal to the upper surface of the barrier layer, A gate semiconductor layer is disposed between the barrier layer and the gate electrode layer, It has a source electrode and a drain electrode connected to the channel layer, which are arranged horizontally to the upper surface of the barrier layer and spaced apart from the gate electrode layer in a second direction different from the first direction, The barrier layer further comprises a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, A semiconductor device characterized in that, in a cross-section obtained by cutting in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the gate electrode layer in the second direction is smaller than the length of the lower surface of the gate electrode layer in the second direction that contacts the upper surface of the gate semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a first channel layer doping region disposed within the channel layer and located below the source electrode.

3. The length of the source electrode in the second direction is greater than or equal to the length of the first barrier layer doping region in the second direction. The semiconductor device according to claim 2, characterized in that the length of the source electrode in the second direction is greater than or equal to the length of the first channel layer doping region in the second direction.

4. The length of the source electrode in the second direction is less than or equal to the length of the first barrier layer doping region in the second direction. The semiconductor device according to claim 2, characterized in that the length of the source electrode in the second direction is less than or equal to the length of the first channel layer doping region in the second direction.

5. The source electrode is A first portion located on the first barrier layer doping region, The invention includes a second portion that protrudes from the first portion toward the first barrier layer doping region and is located within the first barrier layer doping region, The semiconductor device according to claim 2, characterized in that one side surface of the second portion in the second direction has an inclination.

6. The second portion extends downward in the third direction, does not penetrate the first barrier layer doping region, and does not contact the upper surface of the first channel layer doping region. The semiconductor device according to claim 5, characterized in that a portion of the first barrier layer doping region is located between the second portion and the first channel layer doping region.

7. The semiconductor device according to claim 5, characterized in that the second portion of the source electrode extends downward in the third direction, penetrates the first barrier layer doping region, and is connected to the first channel layer doping region.

8. The source electrode further includes a third portion that protrudes from the second portion toward the first channel layer doping region and is located within the first channel layer doping region. The semiconductor device according to claim 5, characterized in that one side surface of the third portion in the second direction has an inclination.

9. The second portion of the source electrode extends downward in the third direction, penetrates the first barrier layer doping region, and connects to the first channel layer doping region. The third portion of the source electrode extends downward in the third direction, does not penetrate the first channel layer doping region, and does not contact the lower surface of the first channel layer doping region. The semiconductor device according to claim 8, characterized in that a portion of the first channel layer doping region is located between the third portion and the lower surface of the first channel layer doping region.

10. The length of the lower surface of the first portion of the source electrode in the second direction is greater than or equal to the length of the upper surface of the second portion of the source electrode in the second direction. The length of the upper surface of the second portion in the second direction is greater than the length of the lower surface of the second portion in the second direction. The length of the lower surface of the second portion in the second direction is greater than or equal to the length of the upper surface of the third portion of the source electrode in the second direction. The semiconductor device according to claim 8, characterized in that the length of the upper surface of the third portion in the second direction is greater than the length of the lower surface of the third portion in the second direction.

11. The semiconductor device according to claim 8, characterized in that the angle between one side surface in the second direction of the second portion of the source electrode and the upper surface of the first barrier layer doping region is different from the angle between one side surface in the second direction of the third portion of the source electrode and the upper surface of the first channel layer doping region.

12. The second portion of the source electrode includes a (2-1) portion located below the first portion in the third direction, and a (2-2) portion located below the (2-1) portion in the third direction and between the third portion and the (2-1) portion. The length of the upper surface of the (2-1) portion in the second direction is greater than or equal to the length of the lower surface of the (2-1) portion in the second direction. The length of the lower surface of the (2-1) portion in the second direction is greater than or equal to the length of the upper surface of the (2-2) portion in the second direction. The length of the upper surface of the (2-2) portion in the second direction is greater than or equal to the length of the lower surface of the (2-2) portion in the second direction. The semiconductor device according to claim 8, characterized in that the length of the upper surface of the (2-1) portion in the second direction is greater than the length of the lower surface of the (2-2) portion in the second direction.

13. The third portion of the source electrode includes a (3-1) portion located below the second portion in the third direction, and a (3-2) portion located below the (3-1) portion in the third direction. The length of the lower surface of the second portion of the source electrode in the second direction is greater than or equal to the length of the upper surface of the (3-1) portion in the second direction. The length of the upper surface of the (3-1) portion in the second direction is greater than or equal to the length of the lower surface of the (3-1) portion in the second direction. The length of the upper surface of the (3-2) portion in the second direction is greater than or equal to the length of the lower surface of the (3-2) portion in the second direction. The semiconductor device according to claim 8, characterized in that the length of the upper surface of the (3-1) portion in the second direction is greater than the length of the lower surface of the (3-2) portion in the second direction.

14. The aforementioned semiconductor device is A second barrier layer doping region is disposed within the barrier layer and connected to the drain electrode, The semiconductor device according to claim 2, further comprising a second channel layer doping region disposed within the channel layer and located below the drain electrode.

15. The drain electrode is A first portion located on the first barrier layer doping region, A second portion that protrudes from the first portion toward the second barrier layer doping region and is located within the second barrier layer doping region, The semiconductor device according to claim 14, further comprising: a third portion that protrudes from the second portion toward the second channel layer doping region and is located within the second channel layer doping region.

16. The semiconductor device further comprises a first protective layer disposed on the barrier layer and the first barrier layer doping region, The first protective layer covers the entire gate electrode layer. The semiconductor device according to claim 1, characterized in that the source electrode penetrates the first protective layer and is connected to the doping region of the first barrier layer.

17. The semiconductor device according to claim 1, characterized in that the angle between the lower surface of the gate electrode layer and one side surface in the second direction is even greater than the angle between the lower surface of the gate semiconductor layer and one side surface in the second direction.

18. The semiconductor device further comprises a hard mask layer disposed on the gate electrode layer, The semiconductor device according to claim 1, characterized in that the corner formed by the upper surface of the hard mask layer and the second side surface has a rounded shape.

19. Channel layer and A barrier layer is placed on the channel layer, A gate electrode layer is disposed on the barrier layer and extends in a first direction horizontal to the upper surface of the barrier layer, A gate semiconductor layer is disposed between the barrier layer and the gate electrode layer, It has a source electrode and a drain electrode connected to the channel layer, which are arranged horizontally to the upper surface of the barrier layer and spaced apart from the gate electrode layer in a second direction different from the first direction, The barrier layer further comprises a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, The source electrode has a first portion located on the first barrier layer doping region, and a second portion that protrudes from the first portion toward the first barrier layer doping region and is located within the first barrier layer doping region. A semiconductor device characterized in that, in a cross-section obtained by cutting in a second direction perpendicular to the first direction and a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the second portion in the second direction is greater than the length of the lower surface of the second portion in the second direction.

20. Channel layer and A barrier layer is placed on the channel layer, A gate electrode layer is disposed on the barrier layer and extends in a first direction horizontal to the upper surface of the barrier layer, A gate semiconductor layer is disposed between the barrier layer and the gate electrode layer, It has a source electrode and a drain electrode connected to the channel layer, which are arranged horizontally to the upper surface of the barrier layer and spaced apart from the gate electrode layer in a second direction different from the first direction, The barrier layer further comprises a first barrier layer doping region disposed within the barrier layer and connected to the source electrode, The source electrode has a first portion located on the first barrier layer doping region, and a second portion that protrudes from the first portion toward the first barrier layer doping region and is located within the first barrier layer doping region. A semiconductor device characterized in that, in a cross-section obtained by cutting in a second direction perpendicular to the first direction and in a third direction perpendicular to the upper surface of the barrier layer, the length of the upper surface of the second portion in the second direction is greater than the length of the lower surface of the second portion in the second direction, and the length of the upper surface of the gate electrode layer in the second direction is less than the length in the second direction at which the lower surface of the gate electrode layer contacts the upper surface of the gate semiconductor layer.

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