Semiconductor equipment

Abstract

We provide a novel semiconductor device. [Solution] A semiconductor device comprising a first layer, a second layer on the first layer, and a third layer on the second layer, wherein the first layer comprises a functional circuit including a first transistor, the second layer comprises a plurality of pixel circuits including a second transistor, and the third layer comprises a plurality of light-emitting elements, one of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements, the functional circuit has a function to control the operation of the pixel circuit, and the pixel circuit has a function to control the luminescence brightness of the light-emitting element.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] In recent years, there has been a growing demand for higher resolution display devices. Examples of devices requiring high-resolution displays include those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), and these are currently undergoing extensive development. Display devices used in these applications require both high resolution and miniaturization.

[0004] VR, AR, SR, and MR are collectively referred to as xR. Examples of display devices for xR include light-emitting devices equipped with light-emitting elements such as organic EL (Electro-Luminescence) elements or light-emitting diodes (LEDs), as well as liquid crystal display devices.

[0005] For example, the basic structure of an organic EL element consists of a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be obtained from the light-emitting organic compound. Because a display device using such an organic EL element does not require a backlight, which is necessary for liquid crystal displays and the like, it is possible to realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1. [Prior art documents]

Patent Document

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] For display devices for XR, miniaturization, low power consumption, and multifunctionality are required.

[0008] One aspect of the present invention is to provide a miniaturized display device as one of the problems. One aspect of the present invention is to provide a display device with high color reproducibility as one of the problems. One aspect of the present invention is to provide a high-definition display device as one of the problems. One aspect of the present invention is to provide a display device with high emission luminance as one of the problems. One aspect of the present invention is to provide a highly reliable display device as one of the problems. One aspect of the present invention is to provide a novel display device as one of the problems.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] Furthermore, in (1), an OS transistor may be used as the second transistor.

[0013] (2) Another aspect of the present invention is a semiconductor device comprising a first layer, a second layer on the first layer, and a first member on the second layer, wherein the first layer comprises a functional circuit, the second layer comprises a display unit including a plurality of pixels and a plurality of storage units, each of the plurality of pixels comprises a pixel circuit and a light-emitting element on the pixel circuit, the plurality of storage units are arranged along at least a portion of the outer periphery of the display unit, and the display unit and the plurality of storage units are covered by the first member. In (2), it is preferable that the storage units are arranged in a sealed region. In (2), the third layer may be light-transmitting.

[0014] (3) One aspect of the present invention is a semiconductor device comprising a first layer, a second layer on the first layer, and a third layer on the second layer, wherein the first layer comprises a storage unit including a plurality of memory cells, the second layer comprises a functional circuit, and the third layer comprises a display unit including a plurality of pixels, the functional circuit comprises a storage unit driving circuit and a display unit driving circuit, and each of the plurality of pixels comprises a pixel circuit and a light-emitting element on the pixel circuit.

[0015] Furthermore, in (3), the memory cell comprises a first transistor, the functional circuit comprises a second transistor, and the pixel circuit comprises a third transistor. For example, the composition of the first semiconductor layer contained in the first transistor and the composition of the second semiconductor layer contained in the second transistor may differ from the composition of the third semiconductor layer contained in the third transistor.

[0016] The above-mentioned memory unit may include DRAM. The above-mentioned light-emitting element may be an organic EL element. The light-emitting element may have a tandem structure. The diagonal size of the area including the multiple pixel circuits and the multiple light-emitting elements is preferably 0.5 inches or more and 2.0 inches or less. In other words, the diagonal size of the display unit is preferably 0.5 inches or more and 2.0 inches or less.

[0017] The above functional circuit may include at least one of the following: a CPU, a GPU, a super-resolution circuit, a sensor circuit, a communication circuit, or an input / output circuit. The above first component may be light-transmitting. [Effects of the Invention]

[0018] According to one aspect of the present invention, a miniaturized display device can be provided. Alternatively, a display device with high color reproducibility can be provided. Alternatively, a high-definition display device can be provided. Alternatively, a display device with high luminous brightness can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0020] [Figure 1] Figure 1A is a perspective view illustrating an example of a semiconductor device configuration. Figure 1B is a block diagram of the semiconductor device. [Figure 2] Figure 2 is a perspective view illustrating an example of a semiconductor device configuration. [Figure 3] Figure 3 is a block diagram illustrating an example of the display drive circuit configuration. [Figure 4] Figures 4A and 4B1 to 4B6 illustrate examples of the display unit configuration. [Figure 5] Figures 5A and 5B illustrate an example of the configuration of a semiconductor device. [Figure 6] Figures 6A and 6B illustrate an example of a semiconductor device configuration. [Figure 7] Figure 7 is a perspective view illustrating an example of a semiconductor device configuration. [Figure 8] Figures 8A and 8B are perspective views illustrating an example of a semiconductor device configuration. [Figure 9] Figures 9A and 9B are perspective views illustrating an example of a semiconductor device configuration. [Figure 10] Figures 10A and 10B are perspective views illustrating an example of a semiconductor device configuration. [Figure 11] Figures 11A and 11B are perspective views illustrating an example of a semiconductor device configuration. [Figure 12] Figures 12A and 12B are perspective views illustrating an example of a semiconductor device configuration. [Figure 13] Figures 13A and 13B are perspective views illustrating an example of a semiconductor device configuration. [Figure 14] Figures 14A and 14B are perspective views illustrating an example configuration of a semiconductor device. [Figure 15] Figures 15A and 15B illustrate an example of the configuration of a semiconductor device. [Figure 16] Figures 16A and 16B illustrate an example of a semiconductor device configuration. [Figure 17] Figures 17A to 17C illustrate examples of the operation of a semiconductor device. [Figure 18] Figure 18 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 19] Figure 19 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 20] Figure 20 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 21] Figure 21 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 22] Figure 22 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 23] Figure 23 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 24] Figure 24 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 25] Figure 25 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 26] Figure 26 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 27] Figure 27 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 28] Figure 28 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 29] Figures 29A to 29D illustrate examples of the configuration of light-emitting elements. [Figure 30] Figures 30A to 30D show examples of display device configurations. [Figure 31] Figures 31A to 31D show examples of the configuration of a display device. [Figure 32] Figure 32A is a top view showing an example of a transistor configuration. Figures 32B and 32C are cross-sectional views showing an example of a transistor configuration. [Figure 33] Figure 33A illustrates the classification of crystal structures. Figure 33B illustrates the XRD spectrum of the CAAC-IGZO film. Figure 33C illustrates the micro-electron diffraction pattern of the CAAC-IGZO film. [Figure 34] Figures 34A to 34E illustrate an example of an electronic device. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0022] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices and may contain semiconductor devices.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0024] One example of a case where X and Y are electrically connected is that one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. Note that a switch has an on state and an off state. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0025] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, such as operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0026] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0027] Furthermore, for example, it can be expressed as, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both the wire and the electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0029] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification, "capacitive element" includes not only a circuit element comprising a pair of electrodes and a dielectric material contained between the electrodes, but also parasitic capacitance occurring between wirings, the gate capacitance occurring between one of the sources or drains of a transistor and the gate, etc. Also, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." In addition, the term "a pair of electrodes" in "capacitance" can be replaced with terms such as "a pair of conductors," "a pair of conductive regions," and "a pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0030] In this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain can be used interchangeably. In addition, when describing the connection relationships of a transistor, this specification uses the notation "one of the source or drain" (or the first electrode or first terminal) and "the other of the source or drain" (or the second electrode or second terminal). Depending on the structure of the transistor, it may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0031] Furthermore, in this specification, the term "node" can be replaced with terminals, wiring, electrodes, conductive layers, conductors, impurity regions, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node".

[0032] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0033] Furthermore, in this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0034] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require electrode B to be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0035] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0036] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0037] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0038] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. "Approximately parallel" or "roughly parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. "Perpendicular" means that two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° or more and 120° or less.

[0039] The embodiments described herein will be explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be interpreted as being limited to the contents of the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in order to make the drawings easier to understand, some components may be omitted in perspective views or top views, etc.

[0040] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the size or aspect ratio. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0041] In the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatch patterns are the same, and reference numerals may not be assigned.

[0042] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "A", "b", "_1", "[n]", or "[m,n]" may be added to the symbol.

[0043] (Embodiment 1) A semiconductor device according to one aspect of the present invention will be described. The semiconductor device according to one aspect of the present invention can function as a display device.

[0044] <Example configuration of semiconductor device 100A> Figures 1A and 2 are perspective views of a semiconductor device 100A according to one aspect of the present invention. Figure 1B is a block diagram illustrating the configuration of the semiconductor device 100A. The semiconductor device 100A comprises a layer 20 on layer 10, a layer 30 on layer 20, and a sealing substrate 40 on layer 30. Layer 30 includes a plurality of pixel circuits 51, and a layer 60 is provided between the sealing substrate 40 and the plurality of pixel circuits 51. In Figure 2, layers 10, 20, 30, 60, and the sealing substrate 40 are shown separated to make the configuration of the semiconductor device 100A easier to understand.

[0045] Layer 10 includes a memory unit 11. The memory unit 11 also includes a plurality of memory cells 12. The memory cells 12 function as memory elements. Various types of memory devices can be used as the memory unit 11. For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FeRAM), Antiferroelectric Memory, etc. may be used.

[0046] Furthermore, flash memory may be used as the memory unit 11. Alternatively, NOSRAM (Nonvolaite Oxide Semiconductor Random Access Memory) or DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) may be used as the memory unit 11. NOSRAM and DOSRAM are types of memory devices that use transistors having oxide semiconductors in the channel formation region (hereinafter also referred to as "OS transistors").

[0047] The memory unit 11 may include multiple types of storage devices. For example, it may include both non-volatile and volatile storage devices. The memory unit 11 has the function of storing various programs used by the semiconductor device 100A, as well as data necessary for the operation of the semiconductor device 100A.

[0048] Layer 20 comprises a functional circuit 90 and a terminal section 29. The functional circuit 90 includes a CPU 21 (Central Processing Unit), a GPU 22 (Graphics Processing Unit), a display drive circuit 23, a memory drive circuit 24, a super-resolution circuit 25, a sensor circuit 26, a communication circuit 27, and an input / output circuit 28.

[0049] The functional circuit 90 does not have to have all of these configurations, and may have other configurations. For example, it may include a potential generation circuit that generates multiple different potentials, and / or a power management circuit that controls the supply and stop of power for each circuit in the semiconductor device 100A. The supply and stop of power may be performed for each circuit that makes up the CPU 21. For example, power consumption can be reduced by stopping the power supply to a circuit that is determined not to be used for a while and restarting the power supply when necessary. The data required when restarting the power supply can be stored in a memory circuit in the CPU 21 or in the memory unit 11 before the circuit is stopped. By storing the data required when the circuit is restored, a high-speed restoration of a stopped circuit can be achieved. The operation of a circuit may also be stopped by stopping the supply of a clock signal.

[0050] Furthermore, the functional circuit 90 may include a DSP (Digital Signal Processor) and / or an FPGA (Field Programmable Gate Array), etc.

[0051] The CPU 21 has the function of controlling the operation of the GPU 22 and the circuits provided in layer 20 according to the program stored in the memory unit 11. The GPU 22 has the function of performing calculation processing to form image data. In addition, the GPU 22 can perform many matrix operations (multiply-accumulate operations) in parallel, so it can perform calculation processing using neural networks, for example, at high speed. The GPU 22 has the function of correcting image data using correction data stored in the memory unit 11, for example. For example, the GPU 22 has the function of generating image data with corrected brightness, hue, and / or contrast.

[0052] The display drive circuit 23 is electrically connected to the multiple pixel circuits 51 provided in layer 30 and has the function of supplying image data to the multiple pixel circuits 51. Various circuits such as shift registers, level shifters, inverters, latches, analog switches, or logic circuits can be used in the display drive circuit 23.

[0053] Furthermore, layer 60 is provided superimposed on layer 30. Layer 60 is equipped with multiple light-emitting elements 61. One light-emitting element 61 and one pixel circuit 51 are electrically connected and function as one pixel. The luminescence brightness of the light-emitting elements 61 is controlled by the pixel circuit 51. The display unit 31 is composed of multiple pixels. In other words, it can be said that the display unit 31 is equipped with multiple pixels. Layer 60 may also be included in layer 30. In this case, it can be said that the display unit 31 is included in layer 30. The pixel circuit 51 and the light-emitting elements 61 will be explained later.

[0054] The super-resolution circuit 25 has the function of determining the potential of any pixel on the display unit 31 by sum-of-products calculation of the potentials and weights of the surrounding pixels. The super-resolution circuit 25 also has the function of upconverting image data with a lower resolution than that of the display unit 31. Furthermore, the super-resolution circuit 25 also has the function of downconverting image data with a higher resolution than that of the display unit 31.

[0055] While image data upconversion or downconversion can also be performed by the GPU22, the inclusion of the super-resolution circuit 25 reduces the load on the GPU22. For example, the GPU22 can process up to 2K resolution (or 4K resolution), and the super-resolution circuit 25 can upconvert to 4K resolution (or 8K resolution), thereby reducing the load on the GPU22. This also increases the processing speed of the semiconductor device 100A.

[0056] The memory drive circuit 24 is electrically connected to the memory unit 11 provided in layer 10 and has the function of writing data to the memory unit 11 and the function of reading data from the memory unit 11.

[0057] The sensor circuit 26 has the function of acquiring one or more pieces of information from a person's sight, hearing, touch, taste, and smell. More specifically, the sensor circuit 26 has the function of detecting or measuring at least one of the following: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared radiation. The sensor circuit 26 may also have other functions.

[0058] The communication circuit 27 has the function of communicating wirelessly or via a wired connection. In particular, having the function of communicating wirelessly is preferable because it can eliminate the number of components such as cables for connection.

[0059] If the communication circuit 27 has the function of communicating wirelessly, the communication circuit 27 can communicate via an antenna. Furthermore, as a communication protocol or communication technology, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark) can be used.

[0060] The communication circuit 27 allows the semiconductor device 100A to connect with other devices and perform information input and output via computer networks such as the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area Network), and GAN (Global Area Network), which are the foundation of the World Wide Web (WWW).

[0061] The input / output circuit 28 has the function of distributing signals supplied to the semiconductor device 100A via the terminal section 29 to each circuit such as the CPU 21 and / or GPU 22. The input / output circuit 28 also has the function of distributing signals supplied to the semiconductor device 100A via the communication circuit 27 to each circuit such as the CPU 21 and / or GPU 22.

[0062] Furthermore, the input / output circuit 28 has the function of outputting signals to the outside via the terminal section 29. Additionally, the input / output circuit 28 has the function of outputting signals to the outside via the communication circuit 27.

[0063] Since FPCs (Flexible Printed Circuits) and the like are electrically connected to the terminal portion 29, the layer 30 and the sealing substrate 40 are not formed in the area overlapping with the terminal portion 29.

[0064] Figure 3 is a block diagram illustrating an example configuration of the display drive circuit 23. The display drive circuit 23 includes a control circuit 71, a timing controller 72, a serial-to-parallel conversion circuit 73, a latch circuit 74, a DAC 75, an amplification circuit 76, a first drive circuit 232, and a second drive circuit 233. Note that the display drive circuit 23 does not have to include all of these components, and may include other components as well.

[0065] The control circuit 71 is electrically connected to the timing controller 72, the serial-to-parallel conversion circuit 73, the latch circuit 74, the DAC 75, the amplification circuit 76, the first drive circuit 232, and the second drive circuit 233, and has the function of controlling the operation of the display unit drive circuit 23. For example, it controls the adjustment of the output characteristics of the DAC 75 and the stopping of the amplification circuit 76 when the display image is not being updated. Furthermore, when the display unit 31 is divided into multiple sub-screens and driven, the control circuit 71 has the function of controlling the above operations for each sub-screen. In addition, the control circuit 71 may have the function of controlling the setting conditions of weights used by the GPU 22 and the super-resolution circuit 25 for each sub-screen.

[0066] The timing controller 72 has a function to control the timing of display image updates according to the frame frequency. When the display unit 31 is divided into multiple sub-screens and driven, the timing controller 72 has a function to control the timing of display image updates for each sub-screen.

[0067] The serial-to-parallel conversion circuit 73 has the function of distributing the digital image signal input in a serial transmission method to each signal line (for example, wiring 237 described later). The distributed digital image signals are temporarily held in the latch circuit 74 and then converted into analog image signals by the DAC 75. The analog image signals are amplified by the amplification circuit 76 and supplied to the signal lines.

[0068] Figure 4A is a block diagram illustrating the connection relationship between the display drive circuit 23 and the display unit 31.

[0069] The display unit drive circuit 23 includes a first drive circuit 232 and a second drive circuit 233. The circuit included in the first drive circuit 232 functions, for example, as a scan line drive circuit. The circuit included in the second drive circuit 233 functions, for example, as a signal line drive circuit. Note that some circuit may be provided at a position facing the first drive circuit 232 across the display unit 31. Similarly, some circuit may be provided at a position facing the second drive circuit 233 across the display unit 31.

[0070] The display unit drive circuit 23 is sometimes referred to as the "peripheral drive circuit." Various circuits such as shift registers, level shifters, inverters, latches, analog switches, and logic circuits can be used in the peripheral drive circuit. Transistors and capacitive elements can also be used in the peripheral drive circuit.

[0071] Furthermore, the display unit 31 has m (m is an integer of 1 or more) wires 236, each arranged substantially parallel to the other and whose potential is controlled by a circuit included in the first drive circuit 232, and n (n is an integer of 1 or more) wires 237, each arranged substantially parallel to the other and whose potential is controlled by a circuit included in the second drive circuit 233. The wires 236 are electrically connected to the first drive circuit 232. The wires 237 are electrically connected to the second drive circuit 233.

[0072] The display unit 31 has a plurality of pixels 230 arranged in a matrix. For example, a pixel 230 that controls red light, a pixel 230 that controls green light, and a pixel 230 that controls blue light can be combined into a single pixel 240, and full-color display can be achieved by controlling the amount of light emitted (luminescence) of each pixel 230. Thus, each of these three pixels 230 functions as a sub-pixel. That is, each of the three sub-pixels controls the amount of light emitted, etc., of red light, green light, or blue light (see Figure 4B1). Note that the color of light controlled by each of the three sub-pixels is not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), and yellow (Y) (see Figure 4B2). Also, the areas of each of the three sub-pixels do not have to be the same. If the luminous efficiency and reliability differ depending on the emitted color, the area of ​​the sub-pixels may be changed for each emitted color (see Figure 4B3). The configuration of the subpixel arrangement shown in Figure 4B3 may also be referred to as the "S-stripe arrangement."

[0073] Alternatively, the four subpixels may be combined and function as a single pixel. For example, a subpixel controlling white light may be added to the three subpixels that control red, green, and blue light respectively (see Figure 4B4). Adding a subpixel to control white light can increase the brightness of the display area. Alternatively, a subpixel controlling yellow light may be added to the three subpixels that control red, green, and blue light respectively (see Figure 4B5). Alternatively, a subpixel controlling white light may be added to the three subpixels that control cyan, magenta, and yellow light respectively (see Figure 4B6).

[0074] By increasing the number of subpixels that function as a single pixel, and by appropriately combining subpixels that control light such as red, green, blue, cyan, magenta, and yellow, the reproduction of midtones can be improved. Therefore, color reproduction can be enhanced.

[0075] Furthermore, a display device according to one aspect of the present invention can reproduce a variety of color gamuts. For example, it can reproduce color gamuts such as the PAL (Phase Alternating Line) and NTSC (National Television System Committee) standards used in television broadcasting, the sRGB (standard RGB) and Adobe RGB standards widely used in display devices for electronic devices such as personal computers, digital cameras, and printers, the ITU-R BT.709 (International Telecommunication Union Radiocommunication Sector Broadcasting Service (Television) 709) standard used in HDTV (High Definition Television), the DCI-P3 (Digital Cinema Initiatives P3) standard used in digital cinema projection, and the ITU-R BT.2020 (REC.2020 (Recommendation 2020)) standard used in UHDTV (Ultra High Definition Television).

[0076] Furthermore, by arranging 240 pixels in a 1920 x 1080 matrix, a display unit 31 capable of full-color display at a resolution known as Full HD (also called "2K resolution," "2K1K," or "2K"). Also, for example, by arranging 240 pixels in a 3840 x 2160 matrix, a display unit 31 capable of full-color display at a resolution known as Ultra HD (also called "4K resolution," "4K2K," or "4K"). Furthermore, by arranging 240 pixels in a 7680 x 4320 matrix, a display unit 31 capable of full-color display at a resolution known as Super Hi-Vision (also called "8K resolution," "8K4K," or "8K"). By increasing the number of pixels, it is also possible to realize a display unit 31 capable of full-color display at resolutions of 16K and even 32K.

[0077] Furthermore, the pixel density (resolution) of the display unit 31 is preferably 1000 ppi or more and 10000 ppi or less. For example, it may be 2000 ppi or more and 6000 ppi or less, or 3000 ppi or more and 5000 ppi or less.

[0078] There are no particular limitations on the aspect ratio of the display unit 31. The display unit 31 of the semiconductor device 100A can support various aspect ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0079] When the semiconductor device 100A is used as a display device for xR, the diagonal size of the display unit 31 can be 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display unit 31 may be 1.5 inches or close to 1.5 inches. By setting the diagonal size of the display unit 31 to 2.0 inches or less, preferably close to 1.5 inches, it becomes possible to process it in a single exposure process of the exposure apparatus (typically a scanner apparatus), thereby improving the productivity of the manufacturing process.

[0080] Figure 5 shows an example of the circuit configuration of pixel 230. Pixel 230 comprises a pixel circuit 51 and a light-emitting element 61. Figure 5A shows the connections of each element in pixel 230. Figure 5B schematically shows the vertical relationship between layer 20, which comprises the display unit drive circuit 23, layer 30, which comprises the pixel circuit 51, and layer 60, which comprises the light-emitting element 61.

[0081] The pixel circuit 51 shown as an example in Figures 5A and 5B comprises transistors 52A, 52B, 52C, and a capacitor 53. Transistors 52A, 52B, and 52C can be composed of OS transistors. Each OS transistor of transistors 52A, 52B, and 52C preferably has a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0082] Transistor 52B comprises a gate electrode electrically connected to transistor 52A, a first terminal electrically connected to the light-emitting element 61, and a second terminal electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to the light-emitting element 61.

[0083] Transistor 52A includes a first terminal electrically connected to the gate electrode of transistor 52B and a second terminal electrically connected to wiring SL which functions as a source line, and has the function of controlling a conduction state or a non-conduction state based on the potential of wiring GL1 which functions as a gate line.

[0084] Transistor 52C has a first terminal electrically connected to wiring V0 and a second terminal electrically connected to the light-emitting element 61, and has the function of controlling a conduction state or a non-conduction state based on the potential of wiring GL2 which functions as a gate line. Wiring V0 is wiring for supplying a reference potential and wiring for outputting the current flowing through the pixel circuit 51 to the display unit drive circuit 23.

[0085] Capacitor 53 comprises a conductive film electrically connected to the gate electrode of transistor 52B and a conductive film electrically connected to the second terminal of transistor 52C.

[0086] The light-emitting element 61 comprises a first electrode electrically connected to the first terminal of the transistor 52B and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61.

[0087] This allows the intensity of light emitted by the light-emitting element 61 to be controlled according to the image signal applied to the gate electrode of transistor 52B. In addition, variations in the gate-source potential of transistor 52B can be suppressed by the reference potential of the wiring V0 provided via transistor 52C.

[0088] Furthermore, the wiring V0 can output a current value that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 may be converted to a voltage by a source follower circuit or the like.

[0089] As the light-emitting element 61, a self-emissive display element such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode, also called an "organic EL element" or "OEL") can be used. Alternatively, a self-emissive light-emitting element such as a micro-LED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser may be used as the light-emitting element 61.

[0090] In the configuration example shown in Figure 5B, the wiring electrically connecting the pixel circuit 51 and the display unit drive circuit 23 can be shortened, thereby reducing the wiring resistance. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, enabling the display unit 31 to be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 51, thus increasing the pixel density of the display unit 31. Additionally, increasing the pixel density of the display unit 31 improves the resolution of the image displayed on the display unit 31. For example, the pixel density of the display unit 31 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the semiconductor device 100A can be used, for example, in a display device for xR applications such as AR or VR. A semiconductor device 100A according to one aspect of the present invention can be suitably applied to electronic devices such as HMDs, where the distance between the display unit and the user is close.

[0091] Figure 6A shows a modified version of the circuit configuration of pixel 230 shown in Figure 5A. The circuit configuration shown in Figure 6A has the same configuration as the circuit configuration shown in Figure 5A, but without transistor 52C, wiring GL2, and wiring V0.

[0092] Alternatively, as shown in Figure 6B, a transistor with a back gate may be used for transistor 52A, and the back gate and gate may be electrically connected. Alternatively, as shown in Figure 6B, the back gate and either the source or drain of the transistor may be electrically connected.

[0093] As described above, one embodiment of the present invention, the semiconductor device 100A, has a configuration in which a display unit 31, a functional circuit 90, and a storage unit 11 are stacked. By stacking the display unit 31, the functional circuit 90, and the storage unit 11, the semiconductor device 100A can be miniaturized. Furthermore, by providing the display unit drive circuit 23 on top of the display unit 31, the width of the bezel around the display unit 31 can be made extremely narrow, thereby increasing the area of ​​the display unit 31. As a result, the resolution of the display unit 31 can be increased. As a result, the display quality of the semiconductor device 100A can be improved.

[0094] Furthermore, if the resolution of the display unit 31 is constant, the area occupied per pixel can be increased. Therefore, the luminescence brightness of the display unit 31 can be increased. Also, the aperture ratio of the pixels can be increased. For example, the aperture ratio of the pixels can be set to 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. In addition, by increasing the area occupied per pixel, the current density supplied to the pixels can be reduced. Therefore, the load on the pixels is reduced, and the reliability of the semiconductor device 100A can be increased.

[0095] Furthermore, by stacking the display unit 31, the functional circuit 90, and the memory unit 11, the wiring connecting them electrically can be shortened. As a result, wiring resistance and parasitic capacitance are reduced, and the operating speed of the semiconductor device 100A can be increased. In addition, the power consumption of the semiconductor device 100A is reduced.

[0096] For example, when performing matrix operations on GPU22, the memory unit 11 is used to temporarily store the large amount of data used in the calculation and the calculation result data. The closer GPU22 and memory unit 11 are, the lower the latency and the faster the calculation processing becomes.

[0097] In particular, the configuration in which a layer 20 containing a functional circuit 90 is sandwiched between a layer 30 containing a display unit 31 and a layer 10 containing a storage unit 11 is preferable because it allows for shorter wiring for both the connection between the display unit 31 and the display unit drive circuit 23, and the connection between the storage unit 11 and the storage unit drive circuit 24.

[0098] Although not shown in the figures, in semiconductor device 100A, it is preferable that layer 10 is in contact with a material with high thermal conductivity (for example, a metallic material such as copper or aluminum).

[0099] <Variation> Next, we will describe a modified version of semiconductor device 100A. To reduce repetition in the explanation, we will mainly describe the differences from semiconductor device 100A. For explanations not listed below, please refer to the explanation for semiconductor device 100A.

[0100] <Example 1> Figure 7 shows a semiconductor device 100B, which is a modified example of semiconductor device 100A. Figure 7 is a perspective view of semiconductor device 100B according to one embodiment of the present invention. In Figure 7, layers 10, 20, 30, 60, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100B easier to understand.

[0101] The semiconductor device 100B differs from the semiconductor device 100A in the stacking order of layers 10 and 20. Specifically, the semiconductor device 100B comprises layer 10 on layer 20, layer 30 on layer 10, and a sealing substrate 40 on layer 30. In addition, instead of a terminal portion 29 on layer 20, a terminal portion 19 is provided on layer 10. Although not shown in the figures, it is preferable that layer 20 in the semiconductor device 100B is in contact with a heat sink. A heat sink is a device that has the function of releasing the heat generated in the semiconductor device 100B to the outside of the semiconductor device 100B.

[0102] A semiconductor device according to one aspect of the present invention can change the stacking order of each layer depending on the purpose or application.

[0103] <Modification 2> Figure 8 shows a semiconductor device 100C, which is a modified example of semiconductor device 100A. Figures 8A and 8B are perspective views of semiconductor device 100C according to one embodiment of the present invention. In Figure 8B, layers 10, 20, and 30 are shown separated to make the configuration of semiconductor device 100C easier to understand.

[0104] The semiconductor device 100C does not have a terminal portion 29 on layer 20, and instead has a terminal portion 39 on layer 30.

[0105] <Variation 3> Figure 9 shows a semiconductor device 100D, which is a modified example of semiconductor device 100A. Figures 9A and 9B are perspective views of semiconductor device 100D according to one embodiment of the present invention. In Figure 9B, layers 20, 30, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100D easier to understand.

[0106] The semiconductor device 100D does not have layer 10, and instead of layer 10, it has a plurality of memory chips 32 that function as storage units 11 around the display unit 31 on layer 30. The plurality of memory chips 32 are arranged along the outer circumference of the display unit 31. The semiconductor device 100D has memory chips 32 on three sides of the display unit 31, and on the remaining side, a plurality of wires 38 are used to electrically connect layer 30 and layer 20. The wires 38 can be formed by the wire bonding method.

[0107] Various memory devices such as DRAM, SRAM, or flash memory can be used as the memory chip 32. The memory chip 32 can also be mounted on layer 30 using various materials and methods such as anisotropic conductive adhesive, ball bonding, or wire bonding. Alternatively, it may be mounted on layer 30 by Cu-Cu bonding (a method of ensuring electrical connection by exposing Cu pads at the bonding interface and bringing the two pads into contact) or by bonding using TSV (Through Silicon Via) and bumps.

[0108] Furthermore, it is preferable to position the memory chip 32 in a location that overlaps with the sealing material 712 (also called the "sealing material"; the sealing material 712 will be described later) that adheres the layer 30 and the sealing substrate 40. The area where the layer 30, the sealing material 712, and the sealing substrate 40 overlap is also called the "sealing region." By placing the memory chip 32 in the sealing region, the memory chip 32 can be efficiently positioned.

[0109] When the memory chip 32 is installed on top of the sealing material, the display unit 31 and the memory chip 32 are covered by the sealing substrate 40. By covering the memory chip 32 with the sealing substrate 40, it is possible to prevent external impurities from diffusing into the memory chip 32.

[0110] <Modification 4> Figure 10 shows a semiconductor device 100E, which is a modified example of semiconductor device 100D. Figures 10A and 10B are perspective views of semiconductor device 100E according to one embodiment of the present invention. In Figure 10B, layers 20, 30, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100E easier to understand. Note that layer 60 is omitted from the description.

[0111] The semiconductor device 100E has memory chips 32 on one of the two opposing sides of the four sides adjacent to the display unit 31, and wires 38 that electrically connect layers 30 and 20 on the other two sides.

[0112] By increasing the number of wires 38 that electrically connect layer 30 and layer 20, the signal transmission speed between layer 30 and layer 20 can be increased.

[0113] <Modification 5> Figure 11 shows a semiconductor device 100F, which is a modified example of semiconductor device 100D. Figures 11A and 11B are perspective views of semiconductor device 100F according to one embodiment of the present invention. In Figure 11B, layers 20, 30, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100F easier to understand. Note that layer 60 is omitted from the description.

[0114] The encapsulation substrate 40 of the semiconductor device 100F is provided with a plurality of notches 42. The notches 42 are located in positions that overlap with the memory chip 32.

[0115] In semiconductor device 100F, the sealing substrate 40 and layer 30 are bonded together so that the memory chip 32 fits within the notch 42. Semiconductor device 100E can be made thinner than semiconductor device 100D.

[0116] <Variation 6> Figure 12 shows a semiconductor device 100G, which is a modified example of semiconductor device 100D. Figures 12A and 12B are perspective views of semiconductor device 100G according to one embodiment of the present invention. In Figure 12B, layers 20, 30, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100G easier to understand. Note that layer 60 is omitted from the description.

[0117] The semiconductor device 100G differs from the semiconductor device 100D in that the encapsulating substrate 40 is superimposed on the display unit 31, but not on the memory chip 32.

[0118] By stacking the encapsulating substrate 40 with the display unit 31 instead of the memory chip 32, the thickness of the semiconductor device 100G can be reduced. Furthermore, because the encapsulating substrate 40 is smaller, the semiconductor device 100G can be made lighter.

[0119] <Example 7> Figure 13 shows semiconductor device 100H, which is a modified example of semiconductor device 100C. Figures 13A and 13B are perspective views of semiconductor device 100H. Semiconductor device 100H differs from semiconductor device 100C in that it does not have layer 10. In Figure 13B, layers 20, 30, and the sealing substrate 40 are shown separated to make the configuration of semiconductor device 100H easier to understand.

[0120] Furthermore, semiconductor device 100H differs from semiconductor device 100C in that it has a memory unit 11 in layer 20. By omitting layer 10, the thickness of semiconductor device 100H can be reduced. Also, by omitting layer 10, semiconductor device 100H can be made lighter.

[0121] <Differentiation Example 8> Figure 14 shows a modified semiconductor device 100I, which is a modified version of semiconductor device 100H. Figures 14A and 14B are perspective views of semiconductor device 100I. Semiconductor device 100I differs from semiconductor device 100H in that it does not have layer 20. In Figure 14B, layer 30 and the sealing substrate 40 are shown separately to make the configuration of semiconductor device 100I easier to understand.

[0122] Furthermore, the semiconductor device 100I includes a display drive circuit 23 and a pixel circuit 51 in layer 30. Depending on the purpose and / or application, necessary functional circuits may be formed in layer 30. Also, depending on the purpose and / or application, by omitting unnecessary functional circuits, it is possible to reduce the power consumption and manufacturing cost of the semiconductor device. In addition, the thickness of the semiconductor device can be reduced, making it lighter.

[0123] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0124] (Embodiment 2) In this embodiment, an example of a configuration in which the display unit 31 provided in layer 30 is divided into a plurality of sub-screens 35 will be described.

[0125] Figure 15A shows an example configuration when the display unit 31 is divided into 32 sub-screens 35. Figure 15A shows the sub-screens 35 arranged in a 4x8 matrix. By dividing the display unit 31 into multiple sub-screens 35, the operation of sub-screens 35 in areas where the display image does not need to be updated can be stopped. In other words, only the sub-screens 35 in areas where the display image needs to be rewritten can be operated. Therefore, the power consumption of the semiconductor device can be reduced.

[0126] Furthermore, since the pixel circuit 51 is composed of OS transistors with extremely low off-current, the data written to the pixels can be retained for a long period of time. Therefore, the display frame frequency can be set arbitrarily (made variable). In addition, the display unit 31 can be driven for each sub-screen 35. Therefore, the frame frequency can also be set for each sub-screen 35.

[0127] Furthermore, in the case where the display unit 31 is divided into multiple sub-screens 35, a first drive circuit 232 and a second drive circuit 233 corresponding to each sub-screen 35 are provided in layer 20. Figure 15B shows an example in which the first drive circuit 232 and the second drive circuit 233 are provided in the area overlapping with the sub-screen 35. In Figure 15B, the position corresponding to the outer edge of the sub-screen 35 is indicated by a dashed line. Also, Figure 15B shows an example in which the first drive circuit 232 and the second drive circuit 233 provided for each sub-screen 35 are arranged to intersect at or near the center of their respective sub-screens 35, but the present invention is not limited to this.

[0128] Furthermore, when a layer 10 containing a memory unit 11 is provided between layer 20 and layer 30, the memory cell 12 is not placed in the region of layer 10 that overlaps with the first drive circuit 232 and the second drive circuit 233. In this way, the first drive circuit 232 and the second drive circuit 233 and the sub-screen 35 can be electrically connected over a short distance by penetrating through layer 10.

[0129] Figure 16A shows an example of the configuration of layer 10. In Figure 16A, the position corresponding to the outer edge of the sub-screen 35 is indicated by a dashed line. In Figure 16A, an example is shown in which multiple memory cells 12 are divided into four memory cell groups 15 in the region overlapping with the sub-screen 35. Furthermore, the region between adjacent memory cell groups 15 overlaps with the first drive circuit 232 and the second drive circuit 233 provided in layer 20, and no memory cells 12 are provided in this region.

[0130] Figure 16B is a perspective view illustrating the regions of layers 10, 20, and 30 that overlap with one sub-screen 35. By not providing a memory cell 12 in the region overlapping with the first drive circuit 232 and the second drive circuit 233 of layer 20, the conductor 55 that electrically connects the first drive circuit 232 and the second drive circuit 233 to the sub-screen 35 can be extended in the stacking direction of layers 10, 20, and 30. Therefore, the first drive circuit 232 and the second drive circuit 233 and the sub-screen 35 can be connected over an extremely short distance, resulting in low wiring resistance and parasitic capacitance, and enabling high-speed operation. In addition, the degradation of the video signal is reduced, improving the display quality of the semiconductor device. Furthermore, the power consumption of the semiconductor device can be reduced. The conductor 55 is composed of conductors and TSVs provided within each layer.

[0131] Furthermore, the semiconductor device according to one aspect of the present invention can perform parallel processing of data communication between the GPU 22 and the memory unit 11 using a large number of wires. Therefore, the semiconductor device according to one aspect of the present invention can operate at high speed. In addition, the semiconductor device according to one aspect of the present invention does not require the image data processed by the GPU 22 and stored in the memory unit 11 to be compressed according to communication standards such as HDMI®, MIPI®, or DisplayPort. Therefore, the semiconductor device according to one aspect of the present invention can operate at high speed and reduce power consumption.

[0132] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0133] (Embodiment 3) A semiconductor device according to one aspect of the present invention may have a display correction system. The display correction system controls the current I flowing through the light-emitting element 61. EL By correcting these issues, display defects caused by faulty pixels such as bright spots or dark spots can be reduced.

[0134] The circuit diagram shown in Figure 17A is a partial illustration of the pixel circuit 51 shown in Figure 5A. Current I flowing through the light-emitting element 61 ELIn the case of defective pixels that cause bright spots, the number of such pixels is extremely high compared to pixels with normal display. Also, current I EL In the case of defective pixels that cause dark spots, their number is extremely low compared to pixels that display normally.

[0135] CPU21 monitors the current I flowing through transistor 52C. MONI The data is acquired periodically. The monitor current I MONI The current is converted into digital data that can be handled by the CPU 21, and calculations are performed using this digital data on the CPU 21 or GPU 22. The calculations on the CPU 21 or GPU 22 estimate the defective pixels and perform corrections to make the display defects caused by the defective pixels less noticeable. For example, if pixel 230D shown in Figure 17B is a defective pixel, the current I flowing to the adjacent pixel 230N is EL Correct it.

[0136] This correction can be estimated, for example, by performing calculations based on artificial neural networks such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs).

[0137] The correction described above causes the current I flowing to the adjacent pixel 230N to... EL Current I EL_C By correcting the image, the defective pixels 230D and 230N are combined and displayed as pixel 230C (see Figure 17C). Displaying the image as pixel 230C makes display defects caused by defective pixels, such as bright spots or dark spots, less noticeable, bringing the display closer to normal.

[0138] Furthermore, in one aspect of the present invention, the semiconductor device can store data in the storage unit 11 during the calculation process described above. The semiconductor device according to one aspect of the present invention is particularly effective because, since the display unit 31, the functional circuit 90, and the storage unit 11 are located in close proximity, high-speed processing can be achieved when performing calculations involving a massive amount of computation, such as calculations based on artificial neural networks.

[0139] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0140] (Embodiment 4) This embodiment describes an example of a cross-sectional configuration of a semiconductor device according to one aspect of the present invention.

[0141] Semiconductor device 100A Figure 18 is a cross-sectional view showing an example of the configuration of semiconductor device 100A, and shows a part of the semiconductor device 100A. As mentioned above, semiconductor device 100A is composed of layer 10, layer 20, layer 30, layer 60, and a sealing substrate 40.

[0142] [Layer 10] Layer 10 has a substrate 701, on which a transistor 431 is provided. Transistor 431 is, for example, a transistor provided in memory cell 12.

[0143] For example, a single-crystal semiconductor substrate such as a single-crystal silicon substrate can be used as the substrate 701. Alternatively, a semiconductor substrate other than a single-crystal semiconductor substrate may be used as the substrate 701.

[0144] The transistor 431 includes a conductor 443 that functions as a gate electrode, an insulator 445 that functions as a gate insulator, and a portion of the substrate 701. The portion of the substrate 701 functions as a region containing the channel formation region of the transistor 431 (semiconductor region 447), a source region (either low-resistance region 449a or low-resistance region 449b), and a drain region (the other of low-resistance region 449a or low-resistance region 449b). The transistor 431 may be a p-channel transistor or an n-channel transistor.

[0145] When a single-crystal silicon substrate is used as the substrate 701, the transistor 431 is a transistor that contains silicon in the channel formation region (also called a "Si transistor").

[0146] Transistor 431 is electrically isolated from other transistors by the element isolation layer 403. Figure 18 shows the case where transistor 431 and other transistors are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed using the LOCOS (LOCal Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method, etc.

[0147] Here, the transistor 431 has a convex semiconductor region 447. Furthermore, the sides and top surface of the semiconductor region 447 are covered by a conductor 443 via an insulator 445. Note that Figure 18 does not show how the conductor 443 covers the sides of the semiconductor region 447. The conductor 443 can be made of a material that adjusts the work function.

[0148] A transistor with a convex semiconductor region, such as transistor 431, can be called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. Furthermore, while Figure 18 shows a configuration where a portion of the substrate 701 is processed to form the convex portion, a semiconductor with a convex shape may also be formed by processing an SOI substrate.

[0149] Note that the configuration of transistor 431 shown in Figure 18 is just one example, and the system is not limited to this configuration. An appropriate configuration may be used depending on the circuit configuration or the way the circuit operates. For example, transistor 431 may be a planar transistor.

[0150] On the substrate 701, in addition to the element isolation layer 403 and the transistor 431, insulators 405, 407, 409, and 411 are provided. Conductors 451 are embedded in insulators 405, 407, 409, and 411. Here, the height of the upper surface of the conductor 451 and the height of the upper surface of the insulator 411 can be made to be approximately the same.

[0151] Insulators 421 and 422 are provided on the conductor 451 and on the insulator 411, respectively. The conductor 453 is embedded in insulators 421 and 422. Here, the height of the upper surface of the conductor 453 and the height of the upper surface of the insulator 422 can be made to be approximately the same.

[0152] An insulator 423 is provided on the conductor 453 and on the insulator 422. The conductor 455 is embedded in the insulator 423. Here, the height of the upper surface of the conductor 455 and the height of the upper surface of the insulator 423 can be made to be approximately the same.

[0153] Furthermore, if necessary, insulators and conductors may be laminated to form a multilayer wiring structure for layer 10.

[0154] [Layer 20] Layer 20 has a substrate 702, on which transistors 441 and 442 are provided. Transistor 441 is, for example, a transistor provided in the display unit drive circuit 23. Transistor 442 is, for example, a transistor provided in the memory unit drive circuit 24.

[0155] As substrate 702, a single-crystal semiconductor substrate such as a single-crystal silicon substrate can be used, similar to substrate 701. Alternatively, a semiconductor substrate other than a single-crystal semiconductor substrate may be used for substrate 702. Layer 20 can have the same configuration as layer 10. Therefore, a detailed explanation of layer 20 is omitted.

[0156] In Figure 18, transistor 442 on layer 20 and transistor 431 on layer 10 are electrically connected via conductor 456. Conductor 456 functions as a TSV (Total Slip Differential). Note that layer 10 and layer 20 may also be electrically connected via bumps or the like.

[0157] Layer 20 comprises a conductor 760. The conductor 760 is the conductor provided by the terminal portion 29. Figure 18 shows an example in which the conductor 760 is electrically connected to the FPC 716 (Flexible Printed Circuit) via an anisotropic conductor 780. Various signals are supplied to the semiconductor device 100A via the FPC 716.

[0158] Furthermore, the conductor 760 is electrically connected to the conductor 347 of layer 20 via conductors 353, 355, and 357. Figure 18 shows three conductors, conductors 353, 355, and 357, as conductors that electrically connect the conductor 760 and the conductor 347, but the present invention is not limited to these. There may be one, two, or four or more conductors that electrically connect the conductor 760 and the conductor 347. By providing multiple conductors that electrically connect the conductor 760 and the conductor 347, contact resistance can be reduced.

[0159] [Layer 30] Layer 30 is provided on top of layer 20. Layer 30 includes an insulator 214, and a transistor 750 is provided on the insulator 214. Transistor 750 is, for example, a transistor provided in the pixel circuit 51. An OS transistor can preferably be used as transistor 750. OS transistors have the characteristic of having an extremely small off-current. Therefore, the retention time of image data, etc. can be extended, and the frequency of refresh operations can be reduced. Therefore, the power consumption of the semiconductor device 100A can be reduced.

[0160] Conductors 301 (conductors 301a and 301b) are embedded in insulators 254, 280, 274, and 281. Conductor 301a is electrically connected to either the source or drain of transistor 750, and conductor 301b is electrically connected to the other source or drain of transistor 750. Here, the height of the upper surfaces of conductors 301a and 301b can be made to be approximately the same as the height of the upper surface of insulator 281.

[0161] Conductors 311, 313, 331, capacitor 790, 333, and 335 are embedded in the insulator 361. Conductors 311 and 313 are electrically connected to the transistor 750 and function as wiring. Conductors 333 and 335 are electrically connected to the capacitor 790. Here, the height of the upper surfaces of conductors 331, 333, and 335 can be made to be approximately the same as the height of the upper surface of the insulator 361.

[0162] Conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the upper surface of conductor 351 and the height of the upper surface of insulator 363 can be made to be approximately the same.

[0163] Insulators 405, 407, 409, 411, 421, 422, 423, 214, 280, 274, 281, 361, and 363 may function as interlayer films and as planarizing films that cover the uneven shapes beneath them. For example, the upper surface of insulator 363 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0164] As shown in Figure 18, the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. In other words, the capacitor 790 has a laminated structure in which an insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Although Figure 18 shows an example in which the capacitor 790 is provided on an insulator 281, the capacitor 790 may be provided on an insulator different from the insulator 281.

[0165] Figure 18 shows an example in which conductors 301a and 301b are formed in the same layer. It also shows an example in which conductors 311, 313, and the lower electrode 321 are formed in the same layer. Furthermore, it shows an example in which conductors 331, 333, and 335 are formed in the same layer. It also shows an example in which conductors 341 and 343 are formed in the same layer. In addition, it shows an example in which conductors 353, 355, and 357 are formed in the same layer. By forming multiple conductors in the same layer, the manufacturing process of the semiconductor device 100A can be simplified, thereby reducing the manufacturing cost of the semiconductor device 100A. Note that these may be formed in different layers and may be made of different types of materials.

[0166] [Layer 60] Layer 60 is provided on top of layer 30. Layer 60 includes a light-emitting element 61. The light-emitting element 61 has a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0167] Materials that can be used in organic compounds include fluorescent materials or phosphorescent materials. Materials that can be used in quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials.

[0168] The conductor 772 is electrically connected to the other side of the source or drain of the transistor 750 via conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed on the insulator 363 and functions as a pixel electrode.

[0169] The conductor 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. Examples of transparent materials include oxide materials containing indium and zinc, oxide materials containing indium, gallium, and zinc (also known as "IGZO"), oxide materials containing indium and tin (also known as "ITO"), or oxide materials containing indium, tin, and silicon (also known as "ITSO"). As a reflective material, examples include materials containing aluminum, silver, etc.

[0170] For example, if the light emitted by the light-emitting element 61 is emitted from the conductor 788 side, it is preferable that the conductor 772 contains a reflective material. The conductor 772 may have a single-layer structure or a multi-layer laminated structure. For example, when the conductor 772 is used as an anode, it may have a three-layer structure with silver sandwiched between two layers of ITO.

[0171] Furthermore, if silicon nitride is present on the surface to be formed with the conductor 772 in contact, the conductor 772 may have a three-layer structure in which aluminum, titanium oxide, and ITO (or ITSO) are stacked in that order from the surface to be formed. Alternatively, if silicon nitride is present on the surface to be formed with the conductor 772 in contact, the conductor 772 may have a two-layer structure in which aluminum and IGZO are stacked in that order from the surface to be formed.

[0172] Note that conductors 301, 331, 351, 353, 355, 357, 453, 456, and 760 may have the same configuration as conductor 245 described in other embodiments. For example, conductor 351, which is electrically connected to the light-emitting element 61, may be a conductor containing tungsten and titanium nitride. More specifically, the side wall of the insulator 363 and tungsten may be adjacent via titanium nitride.

[0173] Although not shown in Figure 18, the semiconductor device 100A can be equipped with optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members.

[0174] The semiconductor device 100A shown in Figure 18 can be configured as a top-emission light-emitting element 61 that emits light towards the conductor 788, using a reflective material for the conductor 772 and a translucent material for the conductor 788. Alternatively, the light-emitting element 61 may be configured as a bottom-emission element that emits light towards the conductor 772, or as a dual-emission element that emits light towards both the conductor 772 and the conductor 788. Furthermore, a structure 778 is provided.

[0175] [Sealing substrate 40] The sealing substrate 40 is provided above the layer 30, covering the display section 31 and the layer 60. The sealing substrate 40 is bonded to the layer 30 by a sealing material 712 (also called "sealing material"). If the light-emitting element 61 is a light-emitting element with a top emission structure or a dual emission structure, a light-transmitting material is used for the sealing substrate 40.

[0176] By providing the sealing substrate 40, it is possible to prevent impurities from entering the layer 60, thereby improving the reliability of the semiconductor device 100A.

[0177] A light-shielding layer 738 is provided on the layer 60 side. The light-shielding layer 738 has the function of blocking light emitted from adjacent areas. In addition, the light-shielding layer 738 has the function of preventing ambient light from reaching the transistor 750, etc.

[0178] Furthermore, the light-shielding layer 738 is covered with an insulator 734. The insulator 734 may be provided as needed. In this embodiment, a solid encapsulation structure is shown in which a packing layer 732 is provided between the light-emitting element 61 and the insulator 734, but a hollow encapsulation structure without a packing layer 732 may also be used. If the semiconductor device 100A is a hollow encapsulation structure, an inert gas containing a Group 18 element (noble gas) and / or nitrogen may be sealed in the area corresponding to the packing layer 732. If the light emitted by the light-emitting element 61 is emitted towards the encapsulation substrate 40, it is preferable to use a light-transmitting material as the packing layer 732.

[0179] Furthermore, the transistor in the semiconductor device according to one aspect of the present invention can include transistors containing various semiconductors. For example, a transistor containing a single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor in the channel-forming region can be used. In addition, the semiconductor is not limited to a single element whose main component is a single element, but can also be a compound semiconductor (e.g., SiGe, GaAs, etc.) or an oxide semiconductor.

[0180] Furthermore, transistors of various structures can be used as transistors in a semiconductor device according to one aspect of the present invention. For example, various transistor configurations can be used, such as planar type, fin type, tri-gate type, top-gate type, bottom-gate type, and double-gate type (where the gates are located above and below the channel). In addition, MOS type transistors, junction type transistors, bipolar transistors, etc., can be used as transistors according to one aspect of the present invention.

[0181] <Example 1> A modified example of the semiconductor device 100A shown in FIG. 18 is shown in FIG. 19. The semiconductor device 100A shown in FIG. 19 is different from the semiconductor device 100A shown in FIG. 18 in that a coloring layer 736 is provided. The coloring layer 736 is provided so as to have a region overlapping with the light-emitting element 61. By providing the coloring layer 736, the color purity of the light extracted from the light-emitting element 61 can be enhanced. Thereby, a high-quality image can be displayed on the semiconductor device 100A. Further, since, for example, all the light-emitting elements 61 of the semiconductor device 100A can be light-emitting elements that emit white light, the EL layer 786 does not have to be formed by painting, and the semiconductor device 100A can be made high-definition.

[0182] The light-emitting element 61 can have a microcavity structure. Thereby, light of a predetermined color (for example, RGB) can be extracted without providing a coloring layer, and the semiconductor device 100A can perform color display. By adopting a configuration without a coloring layer, absorption of light by the coloring layer can be suppressed. Thereby, the semiconductor device 100A can display a high-brightness image, and also the power consumption of the semiconductor device 100A can be reduced. Even when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, formed by painting, a configuration without a coloring layer can be adopted. The luminance of the semiconductor device 100A can be, for example, 500 cd / m 2 to 20000 cd / m 2 below, preferably 1000 cd / m 2 to 20000 cd / m 2 [[ID= (12]]below, more preferably 5000 cd / m 2 to 20000 cd / m 2 below.

[0183] 《Semiconductor device 100C》 A cross-sectional configuration example of a semiconductor device 100C, which is a modified example of the semiconductor device 100A, is shown in FIG. 20. In the cross-sectional configuration example of the semiconductor device 100C shown in FIG. 20, instead of the conductor 347, a conductor 348 is provided on the insulator 361 included in the layer 30.

[0184] Conductor 348 is electrically connected to conductor 760 via conductors 353, 355, and 357. Conductor 348 functions similarly to conductor 347.

[0185] <Example 1> Figure 21 shows an example of a cross-sectional configuration in which layer 30 is superimposed on layer 10 via layer 20. Figure 21 is a modified example of semiconductor device 100C. In Figure 21, layer 20 is superimposed on layer 10 such that the transistors on layer 20 and the transistors on layer 10 face each other. Therefore, layer 30 is provided on the substrate 702 side of layer 20.

[0186] The conductor in layer 10 and the conductor in layer 20 can be electrically connected, for example, by a Cu-Cu bond. In Figure 21, for example, the conductor 455 in layer 10 and the conductor 465 in layer 20 are electrically connected by a Cu-Cu bond. In this case, the conductors 455 and 465 are formed from conductors containing Cu (copper). Furthermore, it is preferable that the insulator 423 into which the conductor 455 is embedded and the insulator 424 into which the conductor 465 is embedded are both insulators containing the same element. For example, the insulators 423 and 424 may each be silicon oxide or silicon oxynitride. By making the insulators 423 and 424 insulators containing the same element, the bonding strength between layer 10 and layer 20 is increased. Furthermore, it is preferable to improve the flatness of both surfaces by performing CMP treatment on both bonding surfaces before bonding layer 10 and layer 20.

[0187] Note that the joint positions of conductor 455 and conductor 465 may or may not perfectly coincide, depending on the alignment accuracy during bonding. Figure 21 illustrates the case where they do not perfectly coincide.

[0188] Furthermore, in Figure 21, the conductor of layer 20 and the conductor of layer 30 may be electrically connected via a TSV. For example, both the conductors 461 and 462 of layer 20 are TSVs that penetrate the substrate 702.

[0189] <Modification 2> Figure 22 shows a modified example of the semiconductor device 100C. In the example cross-sectional configuration shown in Figure 22, an example is shown in which the transistor provided in layer 30 is a Si transistor. In Figure 22, layer 30 includes a substrate 703, and a transistor 750 is provided on the substrate 703. The substrate 703 is, for example, a single-crystal silicon substrate. Therefore, the transistor 750 shown in Figure 22 contains single-crystal silicon in the semiconductor layer where the channel is formed. Note that the same substrate as substrates 701 and 702 can be used as substrate 703. In the semiconductor device 100C shown in Figure 22, layer 30 includes an insulator 361, an insulator 363, a conductor 348, and a capacitor 790, in addition to the same configuration as layer 20.

[0190] In semiconductor devices 100A, 100B, and 100D to 100G, transistors other than OS transistors (for example, Si transistors) may be used for the transistors in layer 30. Various transistors can be used for the transistors in layers 10, 20, and 30 depending on the purpose or application.

[0191] <Variation 3> Furthermore, as shown in Figure 23, a bump 454 and an adhesive layer 457 may be provided between layer 10 and layer 20. Layer 10 and layer 20 are fixed by the adhesive layer 457 and electrically connected by the bump 454. In Figure 23, conductor 456 and conductor 455 are electrically connected via the bump 454. Similarly, a bump 458 and an adhesive layer 459 may be provided between layer 20 and layer 30. Layer 20 and layer 30 are fixed by the adhesive layer 459 and electrically connected by the bump 458. Note that the number of bumps 454 electrically connecting layer 10 and layer 20 is not limited to one, but may be multiple. The number of bumps 458 electrically connecting layer 20 and layer 30 is not limited to one, but may be multiple.

[0192] Semiconductor device 100H Figure 24 shows an example of the cross-sectional configuration of semiconductor device 100H, which is a modified version of semiconductor device 100C. Figure 24 corresponds to the cross-sectional configuration of semiconductor device 100C shown in Figure 20, with layer 10 removed. Since semiconductor device 100H does not have layer 10, it is not necessary to provide elements such as conductor 456 to electrically connect layer 10 and layer 20.

[0193] <Example 1> Figure 25 shows a modified example of the semiconductor device 100H. In the cross-sectional configuration example shown in Figure 25, the transistors in layer 30 are made of Si transistors. In Figure 25, layer 30 can have the same configuration as the layer 30 shown in Figure 22.

[0194] <Modification 2> Furthermore, in the configuration shown in Figure 25, a bump 458 and an adhesive layer 459 may be provided between layer 20 and layer 30, as shown in Figure 26. Layer 20 and layer 30 are fixed by the adhesive layer 459 and electrically connected by the bump 458. Note that, as with the configuration example shown in Figure 23, the number of bumps 458 electrically connecting layer 20 and layer 30 is not limited to one, but may be multiple.

[0195] <Variation 3> Furthermore, if the transistors in layer 30 are composed of Si transistors, layer 30 may be placed on top of layer 20 so that the transistors in layer 30 and the transistors in layer 20 face each other (see Figure 27). In the layer 30 shown in Figure 27, insulators 361 and 363 are provided on the substrate 703. Conductors 348 are provided on insulator 361. Conductors 341 and 351 are embedded in insulator 363.

[0196] The conductor in layer 20 and the conductor in layer 30 can be electrically connected, for example, by a Cu-Cu bond. In Figure 27, for example, the conductor 465 in layer 20 and the conductor 475 in layer 30 are electrically connected by a Cu-Cu bond. In this case, the conductors 465 and 475 are formed from conductors containing Cu (copper). Furthermore, it is preferable that the insulator 424 into which the conductor 465 is embedded and the insulator 425 into which the conductor 475 is embedded are both insulators containing the same element. For example, the insulators 424 and 425 may each be silicon oxide or silicon oxynitride. By making the insulators 424 and 425 insulators containing the same element, the bonding strength between layer 20 and layer 30 is increased. Furthermore, it is preferable to improve the flatness of both surfaces by performing CMP treatment on both bonding surfaces before bonding layer 20 and layer 30.

[0197] Note that the joint positions of conductor 465 and conductor 475 may or may not perfectly coincide, depending on the alignment accuracy during bonding. Figure 27 illustrates the case where they do not perfectly coincide.

[0198] Furthermore, in Figure 27, a TSV may be provided in layer 30. Both conductors 471 and 472 shown in Figure 27 are TSVs that penetrate the substrate 703. In Figure 27, conductor 471 is electrically connected to conductor 341. Conductor 472 is electrically connected to conductor 348.

[0199] Semiconductor device 100I Figure 28 shows an example of the cross-sectional configuration of semiconductor device 100I. The semiconductor device 100I shown in Figure 28 is a modified version of the semiconductor device 100H shown in Figure 25. Therefore, Figure 28 shows an example of the cross-sectional configuration when the transistors in layer 30 are composed of Si transistors.

[0200] As described in the above embodiment, the semiconductor device 100I includes a display drive circuit 23 and a pixel circuit 51 in layer 30. Transistor 750 in Figure 28 is, for example, a transistor included in the pixel circuit 51. Also, transistor 751 in Figure 28 is, for example, a transistor included in the display drive circuit 23.

[0201] Depending on the purpose and / or application, necessary functional circuits may be formed in layer 30. Furthermore, by omitting unnecessary functional circuits, depending on the purpose and / or application, the power consumption and manufacturing costs of the semiconductor device can be reduced. Additionally, the thickness of the semiconductor device can be reduced, thus enabling weight reduction.

[0202] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0203] (Embodiment 5) In this embodiment, the light-emitting element 61 (also referred to as the "light-emitting device") will be described.

[0204] <Example of light-emitting element configuration> As shown in Figure 29A, the light-emitting element 61 has an EL layer 786 between a pair of electrodes (conductor 772, conductor 788). The EL layer 786 can be composed of multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430. Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). Light-emitting layer 4411 may include, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0205] A configuration having a layer 4420, an emissive layer 4411, and a layer 4430 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 29A is referred to as a single structure.

[0206] Furthermore, Figure 29B shows a modified example of the EL layer 786 of the light-emitting element 61 shown in Figure 29A. Specifically, the light-emitting element 61 shown in Figure 29B has a layer 4430-1 on a conductor 772, a layer 4430-2 on layer 4430-1, a light-emitting layer 4411 on layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on layer 4420-1, and a conductor 788 on layer 4420-2. For example, when the conductor 772 is the anode and the conductor 788 is the cathode, layer 4430-1 functions as a hole injection layer, layer 4430-2 functions as a hole transport layer, layer 4420-1 functions as an electron transport layer, and layer 4420-2 functions as an electron injection layer. Alternatively, when conductor 772 is used as the cathode and conductor 788 as the anode, layer 4430-1 functions as an electron injection layer, layer 4430-2 functions as an electron transport layer, layer 4420-1 functions as a hole transport layer, and layer 4420-2 functions as a hole injection layer. This layer structure allows for efficient injection of carriers into the light-emitting layer 4411 and improves the efficiency of carrier recombination within the light-emitting layer 4411.

[0207] As shown in Figure 29C, a configuration in which multiple light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also an example of a single structure.

[0208] Furthermore, as shown in Figure 29D, a configuration in which multiple light-emitting units (EL layers 786a, EL layers 786b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure or stacked structure in this specification. It should be noted that a tandem structure enables the realization of a light-emitting element capable of high-brightness emission.

[0209] Furthermore, if the light-emitting element 61 is in the tandem structure shown in Figure 29D, the light-emitting colors of the EL layer 786a and EL layer 786b may be the same. For example, the light-emitting colors of both the EL layer 786a and EL layer 786b may be green. Note that if the display unit 31 includes three sub-pixels R, G, and B, and each sub-pixel has a light-emitting element, the light-emitting elements of each sub-pixel may be in a tandem structure. Specifically, the EL layer 786a and EL layer 786b of the R sub-pixel each have a material capable of emitting red light, the EL layer 786a and EL layer 786b of the G sub-pixel each have a material capable of emitting green light, and the EL layer 786a and EL layer 786b of the B sub-pixel each have a material capable of emitting blue light. In other words, the materials of the light-emitting layer 4411 and the light-emitting layer 4412 may be the same. By making the light-emitting color of EL layer 786a and EL layer 786b the same, the current density per unit of luminous intensity can be reduced. Therefore, the reliability of the light-emitting element 61 can be improved.

[0210] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, or white, depending on the material that makes up the EL layer 786. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the light-emitting element.

[0211] The light-emitting layer may contain two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). A light-emitting element that emits white light (also called a "white light-emitting device") preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, one should select light-emitting materials such that the light emitted by each of the two or more materials is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a light-emitting element that emits white light as a whole can be obtained. The same applies to light-emitting elements having three or more light-emitting layers.

[0212] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable that the layer contains two or more light-emitting materials, and the light emitted by each light-emitting material contains spectral components of two or more colors from R, G, and B.

[0213] <Method for forming the light-emitting element 61> The following describes the method for forming the light-emitting element 61.

[0214] Figure 30A shows a schematic top view of the light-emitting element 61. The light-emitting element 61 has multiple red light-emitting elements 61R, multiple green light-emitting elements 61G, and multiple blue light-emitting elements 61B. In Figure 30A, the labels R, G, and B are added within the light-emitting area of ​​each light-emitting element for easy distinction. The configuration of the light-emitting element 61 shown in Figure 30A may also be called an SBS (Side By Side) structure. Furthermore, although the configuration shown in Figure 30A is an example with three colors, red (R), green (G), and blue (B), it is not limited to this. For example, a configuration with four or more colors may also be used.

[0215] The light-emitting elements 61R, 61G, and 61B are each arranged in a matrix. Figure 30A shows a so-called stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this; other arrangement methods such as delta arrangement and zigzag arrangement may be applied, and pentile arrangement can also be used.

[0216] It is preferable to use organic EL devices such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) as the light-emitting elements 61R, 61G, and 61B. Examples of light-emitting materials for the EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials.

[0217] Figure 30B is a schematic cross-sectional view corresponding to the dashed line A1-A2 in Figure 30A. Figure 30B shows cross-sections of the light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulating layer 251 and have a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode. The insulating layer 251 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulating layer 251. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as silicon oxide film, silicon oxide nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum oxide nitride film, and hafnium oxide film.

[0218] The light-emitting element 61R has an EL layer 786R between a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode. The EL layer 786R has a luminescent organic compound that emits light with intensity in at least the red wavelength range. The EL layer 786G of the light-emitting element 61G has a luminescent organic compound that emits light with intensity in at least the green wavelength range. The EL layer 786B of the light-emitting element 61B has a luminescent organic compound that emits light with intensity in at least the blue wavelength range.

[0219] Each of the EL layers 786R, 786G, and 786B may have, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0220] A conductor 772, which functions as a pixel electrode, is provided for each light-emitting element. A conductor 788, which functions as a common electrode, is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 772 that functions as a pixel electrode or the conductor 788 that functions as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 772 that functions as a pixel electrode transparent and the conductor 788 that functions as a common electrode reflective, a bottom-emission type display device can be made. Conversely, by making the conductor 772 that functions as a pixel electrode reflective and the conductor 788 that functions as a common electrode transparent, a top-emission type display device can be made. Furthermore, by making both the conductor 772 that functions as a pixel electrode and the conductor 788 that functions as a common electrode transparent, a dual-emission type display device can also be made.

[0221] An insulating layer 272 is provided to cover the ends of the conductive material 772, which functions as a pixel electrode. The ends of the insulating layer 272 are preferably tapered. The insulating layer 272 can be made of the same material as that used for the insulating layer 251.

[0222] Each of the EL layers 786R, 786G, and 786B has a region that contacts the upper surface of the conductor 772, which functions as a pixel electrode, and a region that contacts the surface of the insulating layer 272. The edges of the EL layers 786R, 786G, and 786B are located on the insulating layer 272.

[0223] As shown in Figure 30B, a gap is provided between the two EL layers between light-emitting elements of different colors. It is preferable that the EL layers 786R, 786G, and 786B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent EL layers, which can cause unintended light emission (also known as crosstalk). Therefore, contrast can be enhanced, and a display device with high display quality can be realized.

[0224] EL layer 786R, EL layer 786G, and EL layer 786B can be differentiated by methods such as vacuum deposition using a shadow mask like a metal mask. Alternatively, they can be differentiated by photolithography. By using photolithography, it is possible to realize a display device with high resolution that is difficult to achieve when using a metal mask.

[0225] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. In addition, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0226] Furthermore, a protective layer 271 is provided on the conductive material 788, which functions as a common electrode, covering the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0227] The protective layer 271 can be, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide film, silicon oxide nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum oxide nitride film, and hafnium oxide film. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) may be used as the protective layer 271. The protective layer 271 may be formed using ALD, CVD, and sputtering methods. Although the example shows a configuration including an inorganic insulating film as the protective layer 271, it is not limited to this. For example, the protective layer 271 may be a multilayer structure of an inorganic insulating film and an organic insulating film.

[0228] In this specification, "nitride oxide" refers to a compound with a higher nitrogen content than oxygen content. Similarly, "oxiditride" refers to a compound with a higher oxygen content than nitrogen content. The content of each element can be measured, for example, using Rutherford backscattering spectrometry (RBS).

[0229] When indium gallium zinc oxide is used as the protective layer 271, it can be processed using either a wet etching method or a dry etching method. For example, when IGZO is used as the protective layer 271, chemicals such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also called a mixed aluminum etchant)) can be used. The mixed aluminum etchant can be formulated in a volume ratio of approximately phosphoric acid:acetic acid:nitric acid:water = 53.3:6.7:3.3:36.7.

[0230] Figure 30C shows a different example from the one described above. Specifically, Figure 30C has a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 786W that emits white light between a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode.

[0231] The EL layer 786W can be configured, for example, by stacking two or more light-emitting layers selected so that their respective light-emitting colors are complementary. Alternatively, a stacked EL layer with a charge-generating layer sandwiched between the light-emitting layers may be used.

[0232] Figure 30C shows three light-emitting elements 61W arranged side by side. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. As a result, the display device can display a color image.

[0233] Here, the EL layer 786W and the conductor 788, which functions as a common electrode, are separated between two adjacent light-emitting elements 61W. This prevents current from flowing through the EL layer 786W between two adjacent light-emitting elements 61W, thus preventing unintended light emission. In particular, when a stacked EL layer with a charge generation layer between two light-emitting layers is used as the EL layer 786W, the effect of crosstalk becomes more pronounced as the resolution increases, i.e., the distance between adjacent pixels decreases, resulting in a decrease in contrast. Therefore, this configuration makes it possible to realize a display device that combines high resolution and high contrast.

[0234] The separation of the EL layer 786W and the conductor 788, which functions as a common electrode, is preferably performed by photolithography. This allows for a narrower spacing between light-emitting elements, enabling the realization of a display device with a higher aperture ratio compared to cases where a shadow mask such as a metal mask is used.

[0235] In the case of a bottom-emission type light-emitting element, a colored layer can be provided between the conductive element 772, which functions as a pixel electrode, and the insulating layer 251.

[0236] Figure 30D shows a different example from the one described above. Specifically, Figure 30D shows a configuration in which the insulating layer 272 is not provided between the light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B. This configuration allows for a display device with a high aperture ratio. In addition, the protective layer 271 covers the sides of the EL layer 786R, EL layer 786G, and EL layer 786B. This configuration suppresses impurities (typically water, etc.) that could enter from the sides of the EL layer 786R, EL layer 786G, and EL layer 786B. Furthermore, in the configuration shown in Figure 30D, the top surface shapes of the conductor 772, EL layer 786R, and conductor 788 are roughly the same. Such a structure can be formed all at once using a resist mask or the like after the conductor 772, EL layer 786R, and conductor 788 have been formed. This process, which involves using the conductor 788 as a mask to process the EL layer 786R and the conductor 788, can also be called self-aligned patterning. Although the EL layer 786R has been described here, the same configuration can be used for the EL layer 786G and the EL layer 786B.

[0237] Furthermore, in Figure 30D, a protective layer 273 is provided on top of the protective layer 271. For example, by forming the protective layer 271 using an apparatus capable of forming a highly covering film (typically an ALD apparatus, etc.) and forming the protective layer 273 using an apparatus capable of forming a film with lower covering properties than the protective layer 271 (typically a sputtering apparatus, etc.), a region 275 can be provided between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 786R and the EL layer 786G, and between the EL layer 786G and the EL layer 786B.

[0238] The region 275 has any one or more selected from, for example, air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). Also, the region 275 may contain, for example, a gas used when forming the protective layer 273. For example, when forming the protective layer 273 by sputtering, the region 275 may contain any one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. Alternatively, when forming the protective layer 273 by sputtering, the film of the protective layer 273 may also contain the gas used during sputtering. In this case, when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like, an element such as argon may be detected.

[0239] Also, when the refractive index of the region 275 is lower than the refractive index of the protective layer 271, light emitted from the EL layer 786R, the EL layer 786G, or the EL layer 786B is reflected at the interface between the protective layer 271 and the region 275. As a result, it may be possible to suppress the light emitted from the EL layer 786R, the EL layer 786G, or the EL layer 786B from entering an adjacent pixel. Thereby, since the mixing of different emission colors from adjacent pixels can be suppressed, the display quality of the display device can be improved.

[0240] In the case of the configuration shown in FIG. 30D, the region between the light-emitting element 61R and the light-emitting element 61G, or the region between the light-emitting element 61G and the light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be 1 μm or less, preferably 500 nm or less, more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, it has a region where the distance between the side surface of the EL layer 786R and the side surface of the EL layer 786G, or the distance between the side surface of the EL layer 786G and the side surface of the EL layer 786B is 1 μm or less, preferably has a region of 0.5 μm (500 nm) or less, and more preferably has a region of 100 nm or less.

[0241] Also, for example, when the region 275 has a gas, it is possible to suppress color mixing or crosstalk of light from each light-emitting element while separating the elements from each other.

[0242] Also, the region 275 may be filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc. Further, a photoresist may be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

[0243] Also, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with the light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce the power consumption compared to the white light-emitting device. When it is desired to keep the power consumption low, it is suitable to use the light-emitting device having an SBS structure. On the other hand, the white light-emitting device is suitable because the manufacturing process is simpler than that of the light-emitting device having an SBS structure, so the manufacturing cost can be reduced or the manufacturing yield can be increased.

[0244] Figure 31A shows a different example from the one described above. Specifically, the configuration shown in Figure 31A differs from the configuration shown in Figure 30D in the configuration of the insulating layer 251. When the light-emitting elements 61R, 61G, and 61B are processed, a portion of the upper surface of the insulating layer 251 is scraped away, creating a recess. A protective layer 271 is formed in this recess. In other words, in a cross-sectional view, the lower surface of the protective layer 271 is located below the lower surface of the conductor 772. Having this region effectively suppresses impurities (typically water, etc.) that could enter the light-emitting elements 61R, 61G, and 61B from below. The recess can be formed when impurities (also called residues) that may adhere to the sides of each light-emitting element during processing are removed by wet etching or the like. After removing the above-mentioned residues, covering the sides of each light-emitting element with the protective layer 271 makes it possible to create a highly reliable display device.

[0245] Figure 31B shows a different example from the above. Specifically, the configuration shown in Figure 31B includes an insulating layer 276 and a microlens array 277 in addition to the configuration shown in Figure 31A. The insulating layer 276 functions as an adhesive layer. When the refractive index of the insulating layer 276 is lower than that of the microlens array 277, the microlens array 277 can concentrate the light emitted from the light-emitting elements 61R, 61G, and 61B. This can improve the light extraction efficiency of the display device. This is particularly preferable when the user views the display surface of the display device from the front, as it allows for the viewing of a bright image. Various types of curing adhesives can be used as the insulating layer 276, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0246] Figure 31C shows a different example from the one described above. Specifically, the configuration shown in Figure 31C has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in Figure 31A. In addition, there is an insulating layer 276 above the three light-emitting elements 61W, and above the insulating layer 276 there are colored layers 264R, 264G, and 264B. Specifically, a colored layer 264R that transmits red light is provided in a position overlapping with the left light-emitting element 61W, a colored layer 264G that transmits green light is provided in a position overlapping with the central light-emitting element 61W, and a colored layer 264B that transmits blue light is provided in a position overlapping with the right light-emitting element 61W. As a result, the semiconductor device can display a color image. The configuration shown in Figure 31C is also a modified version of the configuration shown in Figure 30C.

[0247] Figure 31D shows a different example from the one described above. Specifically, in the configuration shown in Figure 31D, the protective layer 271 is provided adjacent to the sides of the conductor 772 and the EL layer 786. The conductor 788 is provided as a continuous layer common to each light-emitting element. In addition, in the configuration shown in Figure 31D, it is preferable that region 275 is filled with a filler material.

[0248] The color purity of the emitted light can be improved by adding a microcavity structure to the light-emitting element 61. To add a microcavity structure to the light-emitting element 61, the product of the distance d between the conductor 772 and the conductor 788 and the refractive index n of the EL layer 786 (optical distance) should be configured such that it is m times half the wavelength λ (where m is an integer greater than or equal to 1). The distance d can be calculated using Equation 1.

[0249] d = m × λ / (2 × n) ... Equation 1.

[0250] According to Equation 1, the distance d of the light-emitting element 61 in the microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 786. Therefore, the EL layer 786G may be made thicker than the EL layer 786B, and the EL layer 786R may be made thicker than the EL layer 786G.

[0251] More precisely, distance d is the distance from the reflective region of the conductor 772, which functions as a reflective electrode, to the reflective region of the conductor 788, which functions as a semi-transparent / semi-reflective electrode. For example, if the conductor 772 is a laminate of silver and a transparent conductive film called ITO, and the ITO is on the EL layer 786 side, the distance d corresponding to the emission color can be set by adjusting the thickness of the ITO. That is, even if the thicknesses of EL layers 786R, 786G, and 786B are the same, a distance d suitable for the emission color can be obtained by changing the thickness of the ITO.

[0252] However, it can be difficult to precisely determine the location of the reflective regions in conductors 772 and 788. In this case, it is assumed that the effect of the microcavity can be sufficiently obtained by assuming that any location in conductors 772 and 788 is a reflective region.

[0253] The light-emitting element 61 is composed of a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like. Detailed configuration examples of the light-emitting element 61 will be described in other embodiments. In order to improve the light extraction efficiency in the microcavity structure, it is preferable to make the optical distance from the conductor 772, which functions as a reflective electrode, to the light-emitting layer an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer constituting the light-emitting element 61.

[0254] Furthermore, when light is emitted from the conductor 788 side, it is preferable that the reflectance of the conductor 788 is greater than its transmittance. Preferably, the light transmittance of the conductor 788 should be 2% to 50%, more preferably 2% to 30%, and even more preferably 2% to 10%. By reducing the transmittance (increasing the reflectance) of the conductor 788, the effect of the microcavity can be enhanced.

[0255] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0256] (Embodiment 6) This embodiment describes a transistor that can be used in a semiconductor device according to one aspect of the present invention.

[0257] <Example of transistor configuration> Figures 32A, 32B, and 32C are a top view and a cross-sectional view of a transistor 200 and its surroundings, which can be used in a semiconductor device according to one aspect of the present invention. The transistor 200 can be applied to a semiconductor device according to one aspect of the present invention. For example, it can be used as a transistor provided in layer 30.

[0258] Figure 32A is a top view of transistor 200. Figures 32B and 32C are cross-sectional views of transistor 200. Here, Figure 32B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 32A, and is also a cross-sectional view of transistor 200 in the channel length direction. Similarly, Figure 32C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 32A, and is also a cross-sectional view of transistor 200 in the channel width direction. Note that in the top view of Figure 32A, some elements have been omitted for clarity.

[0259] As shown in Figure 32, the transistor 200 includes a metal oxide 231a disposed on a substrate (not shown), a metal oxide 231b disposed on the metal oxide 231a, conductors 242a and 242b disposed on the metal oxide 231b at a distance from each other, an insulator 280 disposed on the conductors 242a and 242b with an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed between the metal oxide 231b, conductors 242a, conductors 242b, and insulator 280 and conductor 260, and a metal oxide 231c disposed between the metal oxide 231b, conductors 242a, conductors 242b, and insulator 280 and insulator 250. Here, as shown in Figures 32B and 32C, it is preferable that the upper surface of the conductor 260 substantially coincides with the upper surfaces of the insulator 250, insulator 254, metal oxide 231c, and insulator 280. In the following, metal oxide 231a, metal oxide 231b, and metal oxide 231c may be collectively referred to as metal oxide 231. Also, conductors 242a and conductor 242b may be collectively referred to as conductor 242.

[0260] In the transistor 200 shown in FIG. 32, the side surfaces of the conductor 242a and the conductor 242b on the side of the conductor 260 have a substantially vertical shape. Note that the transistor 200 shown in FIG. 32 is not limited to this, and the angle formed by the side surface and the bottom surface of the conductor 242a and the conductor 242b may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Further, the opposing side surfaces of the conductor 242a and the conductor 242b may have a plurality of surfaces.

[0261] As shown in FIG. 32, it is preferable that the insulator 254 is disposed between the insulator 224, the metal oxide 231a, the metal oxide 231b, the conductor 242a, the conductor 242b, the metal oxide 231c, and the insulator 280. Here, as shown in FIGS. 32B and 32C, the insulator 254 preferably contacts the side surface of the metal oxide 231c, the upper surface and the side surface of the conductor 242a, the upper surface and the side surface of the conductor 242b, the side surfaces of the metal oxide 231a and the metal oxide 231b, and the upper surface of the insulator 224.

[0262] Note that in the transistor 200, a configuration in which three layers of the metal oxide 231a, the metal oxide 231b, and the metal oxide 231c are stacked in a region where a channel is formed (hereinafter, also referred to as a channel formation region) and in the vicinity thereof is shown, but the present invention is not limited to this. For example, a two-layer structure of the metal oxide 231b and the metal oxide 231c or a stacked structure of four or more layers may be provided. Further, in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Further, each of the metal oxide 231a, the metal oxide 231b, and the metal oxide 231c may have a stacked structure of two or more layers.

[0263] For example, when the metal oxide 231c has a stacked structure including a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide preferably has the same composition as the metal oxide 231b, and the second metal oxide preferably has the same composition as the metal oxide 231a.

[0264] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode or drain electrode, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. In other words, in the transistor 200, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing a positional margin, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to make the display device high-resolution. It also makes it possible to make the display device narrow-bezel.

[0265] As shown in Figure 32, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0266] The transistor 200 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on top of the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on top of the insulator 216 and the conductor 205, and an insulator 224 disposed on top of the insulator 222. It is preferable that a metal oxide 231a is disposed on top of the insulator 224.

[0267] It is preferable that an insulator 274 and an insulator 281, which function as interlayer films, are placed on top of the transistor 200. Here, it is preferable that the insulator 274 is placed in contact with the upper surfaces of the conductor 260, insulator 250, insulator 254, metal oxide 231c, and insulator 280.

[0268] It is preferable that insulators 222, 254, and 274 have a function to suppress the diffusion of at least one of the hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0269] Here, insulator 224, metal oxide 231, and insulator 250 are separated from insulators 280 and 281 by insulators 254 and 274. Therefore, it is possible to suppress the incorporation of impurities such as hydrogen and excess oxygen contained in insulators 280 and 281 into insulators 224, metal oxide 231, and insulator 250.

[0270] It is preferable that a conductor 245 (conductor 245a and conductor 245b) is provided that is electrically connected to the transistor 200 and functions as a plug. In addition, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 245 that functions as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulator 254, insulator 280, insulator 274, and insulator 281. Alternatively, a first conductor of the conductor 245 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 245 may be provided further inside. Here, the height of the upper surface of the conductor 245 and the height of the upper surface of the insulator 281 can be made to be approximately the same. Although the transistor 200 shows a configuration in which the first conductor and the second conductor of the conductor 245 are stacked, the present invention is not limited to this. For example, the conductor 245 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned to distinguish it according to the order of formation.

[0271] In transistor 200, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 231 (metal oxide 231a, metal oxide 231b, and metal oxide 231c) that includes the channel formation region. For example, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that forms the channel formation region of metal oxide 231.

[0272] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition, it is preferable that it contains element M. As element M, one or more of the following can be used: aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that element M contains either gallium (Ga) or tin (Sn), or both.

[0273] Furthermore, as shown in Figure 32B, the thickness of the metal oxide 231b in the region that does not overlap with the conductor 242 may be thinner than the thickness of the metal oxide 231b in the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 231b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is deposited on the upper surface of the metal oxide 231b, a region with low resistance may be formed near the interface with the conductive film. In this way, by removing the region with low resistance located between the conductors 242a and 242b on the upper surface of the metal oxide 231b, it is possible to prevent the formation of a channel in that region.

[0274] According to one aspect of the present invention, a display device with a small size transistor and high resolution can be provided. Alternatively, a display device with a large on-current transistor and high brightness can be provided. Alternatively, a display device with a fast-operating transistor can be provided. Alternatively, a display device with a stable electrical characteristic transistor can be provided and highly reliable can be provided. Alternatively, a display device with a small off-current transistor can be provided and low power consumption can be provided.

[0275] A detailed configuration of the transistor 200, which can be used in a display device according to one aspect of the present invention, will be described.

[0276] The conductor 205 is arranged to have an overlapping region with the metal oxide 231 and the conductor 260. Furthermore, it is preferable that the conductor 205 is embedded in the insulator 216.

[0277] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 216. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of the insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of the insulator 216. In other words, conductor 205b is enclosed by conductors 205a and 205c.

[0278] It is preferable that the conductors 205a and 205c use conductive materials that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0279] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to suppress the diffusion of impurities such as hydrogen contained in conductor 205b into the metal oxide 231 via the insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress the oxidation of conductor 205b and the resulting decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for conductor 205a. For example, titanium nitride can be used for conductor 205a.

[0280] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0281] Here, the conductor 260 may function as the first gate (also called the top gate) electrode. Also, the conductor 205 may function as the second gate (also called the bottom gate) electrode. In that case, by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, the V of transistor 200 can be controlled. th This can be controlled. In particular, by applying a negative potential to the conductor 205, the V of transistor 200 can be controlled. th By making the voltage greater than 0V, it becomes possible to reduce the off-current. Therefore, applying a negative potential to the conductor 205 reduces the drain current when the potential applied to the conductor 260 is 0V compared to not applying a negative potential.

[0282] The conductor 205 should be larger than the channel-forming region in the metal oxide 231. In particular, as shown in Figure 32C, it is preferable that the conductor 205 extends to the region outside the end that intersects with the channel width direction of the metal oxide 231. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 231, with an insulator in between.

[0283] With the above configuration, the channel-forming region of the metal oxide 231 can be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode.

[0284] As shown in Figure 32C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205.

[0285] The insulator 214 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 200 from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 214 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable).

[0286] For example, it is preferable to use aluminum oxide or silicon nitride as the insulator 214. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side beyond the insulator 214. Alternatively, it suppresses the diffusion of oxygen contained in the insulator 224, etc., toward the substrate side beyond the insulator 214.

[0287] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as insulators 216, 280, and 281.

[0288] Insulators 222 and 224 function as gate insulators.

[0289] Here, it is preferable that the insulator 224 in contact with the metal oxide 231 desorbs oxygen upon heating. In this specification, the oxygen that is desorbed upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be silicon oxide or silicon oxynitride, etc., as appropriate. By providing an oxygen-containing insulator in contact with the metal oxide 231, the oxygen deficiency in the metal oxide 231 can be reduced, and the reliability of the transistor 200 can be improved.

[0290] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as the insulator 224. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0291] As shown in Figure 32C, the thickness of the insulator 224 in the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 231b may be thinner than the thickness of the other regions. In the insulator 224, it is preferable that the thickness of the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 231b is such that the above-mentioned oxygen can diffuse sufficiently.

[0292] It is preferable that insulator 222 functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 200 from the substrate side, similar to insulator 214, etc. For example, it is preferable that insulator 222 has lower hydrogen permeability than insulator 224. By surrounding insulator 224, metal oxide 231, and insulator 250, etc., with insulator 222, insulator 254, and insulator 274, it is possible to suppress the ingress of impurities such as water or hydrogen into the transistor 200 from the outside.

[0293] Furthermore, it is preferable that the insulator 222 has a function to suppress the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (i.e., it is difficult for the above-mentioned oxygen to permeate it). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 has a function to suppress the diffusion of oxygen and impurities, thereby reducing the diffusion of oxygen contained in the metal oxide 231 to the substrate side. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the metal oxide 231.

[0294] The insulator 222 may be an insulator containing an oxide of either or both aluminum and hafnium, which are insulating materials. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 231 and the incorporation of impurities such as hydrogen from the periphery of the transistor 200 into the metal oxide 231.

[0295] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the above insulators.

[0296] The insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0297] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0298] The metal oxide 231 comprises metal oxide 231a, metal oxide 231b on metal oxide 231a, and metal oxide 231c on metal oxide 231b. By having metal oxide 231a below metal oxide 231b, the diffusion of impurities from structures formed below metal oxide 231a to metal oxide 231b can be suppressed. Furthermore, by having metal oxide 231c on metal oxide 231b, the diffusion of impurities from structures formed above metal oxide 231c to metal oxide 231b can be suppressed.

[0299] Furthermore, it is preferable that the metal oxide 231 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 231 contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 231a to the total number of atoms of all elements constituting metal oxide 231a is higher than the ratio of the number of atoms of element M contained in metal oxide 231b to the total number of atoms of all elements constituting metal oxide 231b. It is also preferable that the atomic ratio of element M contained in metal oxide 231a to In is higher than the atomic ratio of element M contained in metal oxide 231b to In. Here, metal oxide 231c can be any metal oxide that can be used in metal oxide 231a or metal oxide 231b.

[0300] It is preferable that the energy at the lower end of the conduction band of metal oxide 231a and metal oxide 231c is higher than the energy at the lower end of the conduction band of metal oxide 231b. In other words, it is preferable that the electron affinity of metal oxide 231a and metal oxide 231c is smaller than the electron affinity of metal oxide 231b. In this case, it is preferable that metal oxide 231c is a metal oxide that can be used for metal oxide 231a. Specifically, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 231c to the total number of atoms of all elements constituting metal oxide 231c is higher than the ratio of the number of atoms of element M contained in metal oxide 231b to the total number of atoms of all elements constituting metal oxide 231b. It is also preferable that the atomic ratio of element M contained in metal oxide 231c to In is higher than the atomic ratio of element M contained in metal oxide 231b to In.

[0301] Here, at the junctions of metal oxide 231a, metal oxide 231b, and metal oxide 231c, the energy levels at the lower end of the conduction band change smoothly. In other words, the energy levels at the lower end of the conduction band at the junctions of metal oxide 231a, metal oxide 231b, and metal oxide 231c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between metal oxide 231a and metal oxide 231b, and at the interface between metal oxide 231b and metal oxide 231c.

[0302] Specifically, by having metal oxides 231a and 231b, and metal oxides 231b and 231c, share a common element other than oxygen (which serves as the main component), a mixed layer with a low defect level density can be formed. For example, if metal oxide 231b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., may be used as metal oxides 231a and 231c. Furthermore, metal oxide 231c may be in a layered structure. For example, a layered structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a layered structure of In-Ga-Zn oxide and an oxide that does not contain In may be used as metal oxide 231c.

[0303] Specifically, for metal oxide 231a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For metal oxide 231b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. For metal oxide 231c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures for metal oxide 231c include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0304] In this case, the main carrier pathway is through metal oxide 231b. By configuring metal oxide 231a and metal oxide 231c as described above, the defect level density at the interface between metal oxide 231a and metal oxide 231b, and at the interface between metal oxide 231b and metal oxide 231c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain high on-current and high frequency characteristics. Furthermore, if metal oxide 231c is in a multilayer structure, in addition to the effect of reducing the defect level density at the interface between metal oxide 231b and metal oxide 231c as described above, it is expected that the diffusion of constituent elements of metal oxide 231c towards the insulator 250 will be suppressed. More specifically, by making metal oxide 231c in a multilayer structure and positioning an oxide that does not contain In on top of the multilayer structure, it is possible to suppress In that could diffuse towards the insulator 250. Since the insulator 250 functions as a gate insulator, if In diffuses, it will result in poor transistor characteristics. Therefore, by using a layered structure for the metal oxide 231c, it becomes possible to provide a highly reliable display device.

[0305] A conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode and a drain electrode is provided on the metal oxide 231b. It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as the conductor 242, or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0306] By providing the conductor 242 in contact with the metal oxide 231, the oxygen concentration in the vicinity of the conductor 242 in the metal oxide 231 may be reduced. Furthermore, a metal compound layer containing the metal in the conductor 242 and components of the metal oxide 231 may be formed in the vicinity of the conductor 242 in the metal oxide 231. In such cases, the carrier concentration increases in the region of the metal oxide 231 near the conductor 242, resulting in a low-resistance region.

[0307] Here, the region between the conductor 242a and the conductor 242b is formed by superimposing it on the opening of the insulator 280. This allows the conductor 260 to be positioned self-aligned between the conductor 242a and the conductor 242b.

[0308] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the metal oxide 231c. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable.

[0309] Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0310] A metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. This suppresses the oxidation of the conductor 260 by oxygen from the insulator 250.

[0311] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0312] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or oxides containing aluminum and hafnium (hafnium aluminate).

[0313] Although the conductor 260 is shown as a two-layer structure in Figure 32, it may also be a single-layer structure or a laminated structure of three or more layers.

[0314] It is preferable to use a conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0315] The conductor 260a has the function of suppressing oxygen diffusion, thereby preventing the conductor 260b from oxidizing due to oxygen contained in the insulator 250 and reducing its conductivity. It is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide as a conductive material that has the function of suppressing oxygen diffusion.

[0316] The conductor 260b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0317] As shown in Figures 32A and 32C, in the region of the metal oxide 231b that does not overlap with the conductor 242, in other words, in the channel-forming region of the metal oxide 231, the side surface of the metal oxide 231 is covered by the conductor 260. This makes it easier to apply the electric field of the conductor 260, which functions as the first gate electrode, to the side surface of the metal oxide 231. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0318] The insulator 254, like the insulator 214, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 200 from the insulator 280 side. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Furthermore, as shown in Figures 32B and 32C, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 231c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 231a and metal oxide 231b, and the top surface of the insulator 224. With this configuration, it is possible to suppress the ingress of hydrogen contained in the insulator 280 into the metal oxide 231 from the top or side surfaces of the conductor 242a, conductor 242b, metal oxide 231a, metal oxide 231b, and the insulator 224.

[0319] Furthermore, it is preferable that the insulator 254 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (i.e., it is difficult for the above-mentioned oxygen to permeate through it). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0320] The insulator 254 is preferably deposited using a sputtering method. By depositing the insulator 254 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulator 224 that is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 231 via the insulator 224. Here, the insulator 254 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 231 to the insulator 280. In addition, the insulator 222 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 231 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 231. This reduces oxygen deficiency in the metal oxide 231 and suppresses the normally-on state of the transistor.

[0321] As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as a film. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator containing an oxide of one or both of aluminum and hafnium.

[0322] The insulator 224, insulator 250, and metal oxide 231 are covered by the hydrogen barrier insulator 254, so the insulator 280 is separated from the insulator 224, metal oxide 231, and insulator 250 by the insulator 254. This prevents impurities such as hydrogen from entering the transistor 200 from the outside, thus providing the transistor 200 with good electrical characteristics and reliability.

[0323] The insulator 280 is provided on the insulator 224, the metal oxide 231, and the conductor 242 via the insulator 254. For example, the insulator 280 is preferably silicon oxide, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0324] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Furthermore, the upper surface of the insulator 280 may be flattened.

[0325] The insulator 274 preferably functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen into the insulator 280 from above, similar to the insulator 214. For example, the insulator 274 can be an insulator that can be used for the insulator 214, insulator 254, etc.

[0326] It is preferable to provide an insulator 281, which functions as an interlayer film, on top of the insulator 274. It is preferable that the insulator 281, like the insulator 224, has a reduced concentration of impurities such as water or hydrogen in the film.

[0327] Conductors 245a and 245b are placed in the openings formed in insulators 281, 274, 280, and 254. Conductors 245a and 245b are provided facing each other with conductor 260 in between. The height of the upper surfaces of conductors 245a and 245b may be on the same plane as the upper surface of insulator 281.

[0328] Furthermore, an insulator 241a is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 245a is formed in contact with its side surface. Conductor 242a is located in at least a portion of the bottom of the opening, and conductor 245a is in contact with conductor 242a. Similarly, an insulator 241b is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 245b is formed in contact with its side surface. Conductor 242b is located in at least a portion of the bottom of the opening, and conductor 245b is in contact with conductor 242b.

[0329] It is preferable that the conductors 245a and 245b be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 245a and 245b may be arranged in a laminated structure.

[0330] When the conductor 245 has a laminated structure, it is preferable to use a conductor that has the function of suppressing the diffusion of impurities such as water or hydrogen, as described above, for the conductors that come into contact with the metal oxide 231a, metal oxide 231b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminate. By using such a conductive material, it is possible to suppress the absorption of oxygen added to the insulator 280 by the conductors 245a and 245b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulator 281 into the metal oxide 231 through the conductors 245a and 245b.

[0331] For insulators 241a and 241b, for example, insulators that can be used for insulator 254 may be used. Since insulators 241a and 241b are provided in contact with insulator 254, it is possible to suppress the mixing of impurities such as water or hydrogen from insulator 280, etc., into the metal oxide 231 through conductors 245a and 245b. In addition, it is possible to suppress the absorption of oxygen contained in insulator 280 into conductors 245a and 245b.

[0332] Although not shown in the figures, conductors that function as wiring may be placed in contact with the upper surfaces of conductor 245a and conductor 245b. The conductors that function as wiring are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductors may be formed to be embedded in openings provided in the insulator.

[0333] <Materials used in transistors> This section describes the constituent materials that can be used in transistors.

[0334] [substrate] As the substrate for forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include silicon, germanium, and other semiconductor substrates, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on a substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0335] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0336] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0337] Examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxiditrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxiditrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0338] Examples of insulators with low dielectric constant include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resins.

[0339] Transistors using oxide semiconductors can have their electrical characteristics stabilized by surrounding them with an insulator (insulator 214, insulator 222, insulator 254, and insulator 274, etc.) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxide nitride, or silicon nitride can be used.

[0340] The insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is released by heating. For example, by having a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 231, the oxygen deficiency of the metal oxide 231 can be compensated for.

[0341] [conductor] It is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., as a conductor, or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0342] Multiple conductors formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0343] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0344] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0345] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0346] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0347] (Embodiment 7) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0348] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 33A. Figure 33A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0349] As shown in Figure 33A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0350] The structure within the thick frame shown in Figure 33A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from "Crystal" or the energetically unstable "Amorphous."

[0351] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 33B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 33B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 33B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 33B is 500 nm.

[0352] As shown in Figure 33B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 33B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0353] The crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed using nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 33C. Figure 33C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 33C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, in nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0354] As shown in Figure 33C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0355] [Structure of oxide semiconductors] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 33A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, etc.

[0356] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0357] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0358] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0359] In In-M-Zn oxide (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. The In layer may also contain element M. The In layer may also contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0360] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0361] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0362] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal atoms.

[0363] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0364] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and / or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0365] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0366] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0367] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0368] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0369] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0370] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0371] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0372] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0373] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0374] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0375] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0376] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0377] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0378] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0379] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, which may result in a low trap level density.

[0380] Charges trapped in the trap levels of oxide semiconductors can take a long time to disappear and sometimes behave like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high density of trap levels may exhibit unstable electrical properties.

[0381] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0382] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0383] In oxide semiconductors, the presence of silicon and / or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and the concentrations of silicon and carbon near the interface with the oxide semiconductor (concentrations obtained by SIMS) are 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0384] When alkali metals or alkaline earth metals are present in oxide semiconductors, they can form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0385] In oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. This can result in unstable electrical properties of the transistor. Therefore, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻¹⁰. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm3 Do the following:

[0386] Hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these vacancies, electrons, which act as carriers, can be generated. Furthermore, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0387] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0388] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0389] (Embodiment 8) This embodiment describes electronic equipment to which a semiconductor device according to one aspect of the present invention can be applied.

[0390] A semiconductor device according to one aspect of the present invention can be applied to the display unit of an electronic device. Therefore, it is possible to realize an electronic device with high display quality, or an extremely high-definition electronic device, or a highly reliable electronic device.

[0391] Electronic devices using a semiconductor device according to one aspect of the present invention include televisions, display devices such as monitors, lighting devices, desktop or notebook personal computers, word processors, and DVDs (Digital Versatile). Examples include image playback devices that play still images or videos stored on recording media such as discs, portable CD players, radios, tape recorders, headphone stereos, stereos, desk clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet devices, portable game consoles, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book readers, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and energy storage devices for power leveling and smart grids can also be included in the category of electronic equipment. In addition, mobile devices propelled by engines using fuel or electric motors using electricity from energy storage devices may also be included in the category of electronic equipment. Examples of such mobile devices include electric vehicles (EVs), hybrid electric vehicles (HEVs) that combine internal combustion engines and electric motors, plug-in hybrid electric vehicles (PHEVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.

[0392] An electronic device according to one aspect of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0393] Examples of secondary batteries include lithium-ion batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air batteries, nickel-zinc batteries, and silver-zinc batteries.

[0394] An electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, the display unit can display images and information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0395] An electronic device according to one aspect of the present invention may have sensors (including those with functions to measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0396] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0397] Furthermore, electronic devices having multiple display units may have functions such as displaying image information primarily on one part of the display unit and text information primarily on another part, or displaying a three-dimensional image by displaying images that take parallax into account on multiple display units. Furthermore, electronic devices having an image receiving unit may have functions such as capturing still images or moving images, automatically or manually correcting captured images, saving captured images to a recording medium (external or built into the electronic device), and displaying captured images on a display unit. It should be noted that the functions of an electronic device according to one aspect of the present invention are not limited to these, and it may have a variety of functions.

[0398] A semiconductor device according to one aspect of the present invention can display high-definition images. Therefore, it can be suitably used in portable electronic devices, wearable electronic devices, and e-book readers. For example, it can be suitably used in xR devices such as VR devices or AR devices.

[0399] Figure 34A shows the external appearance of the head-mounted display 810. The head-mounted display 810 includes a mounting part 811, lenses 812, a main body 813, a display unit 814, a cable 815, etc. A battery 816 is also built into the mounting part 811. A semiconductor device according to one embodiment of the present invention can be applied to the display unit 814.

[0400] Cable 815 supplies power from battery 816 to main unit 813. Main unit 813 is equipped with a wireless receiver and can display received image data and other video information on display unit 814. In addition, a camera provided on main unit 813 captures the movement of the user's eyeballs and / or eyelids, and by calculating the user's gaze based on that information, the user's gaze can be used as an input means.

[0401] Furthermore, the attachment portion 811 may be provided with multiple electrodes in positions that come into contact with the user. The main body 813 may have a function to recognize the user's gaze by detecting the current flowing through the electrodes in accordance with the user's eye movements. It may also have a function to monitor the user's pulse by detecting the current flowing through the electrodes. The attachment portion 811 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function to display the user's biometric information on the display unit 814. It may also detect the user's head movements and change the image displayed on the display unit 814 in accordance with those movements.

[0402] Figure 34B shows the external appearance of the head-mounted display 820. The head-mounted display 820 is a goggle-type information processing device.

[0403] The head-mounted display 820 has a housing 821, operation buttons 823, a band-shaped fixing device 824, and two display units 822. Having two display units 822 allows the user to view one display unit per eye. This enables the display of high-resolution images, even when performing 3D displays using parallax. A battery 825 is also provided on the fixing device 824. While the battery 825 could be located on the housing 821, locating it on the fixing device 824 is preferable because it allows the center of gravity of the head-mounted display 820 to be shifted backward, improving the user's comfort. In addition to the battery 825, other components such as drive circuits for operating the display units 822 may also be provided on the fixing device 824 to adjust the center of gravity of the head-mounted display 820.

[0404] The operation button 823 has functions such as a power button. The device may also have other buttons besides the operation button 823.

[0405] A semiconductor device according to one aspect of the present invention can be applied to the display unit 822. Because the semiconductor device according to one aspect of the present invention has extremely high resolution, pixels are difficult for the user to see, and a more realistic image can be displayed.

[0406] Figure 34C shows the external appearance of the camera 830 equipped with the viewfinder 840.

[0407] The camera 830 includes a housing 831, a display unit 832, operation buttons 833, a shutter button 834, and the like. The camera 830 also has a detachable lens 836 attached to it.

[0408] Here, the camera 830 is configured so that the lens 836 can be removed from the housing 831 and replaced, but the lens 836 and the housing could also be integrated.

[0409] The camera 830 can take an image by pressing the shutter button 834. Additionally, the display unit 832 functions as a touch panel, and images can also be taken by touching the display unit 832.

[0410] The camera body 831 has a mount with electrodes, and in addition to the viewfinder 840, a strobe device and the like can be connected to it.

[0411] The viewfinder 840 includes a housing 841, a display unit 842, buttons 843, etc.

[0412] The housing 841 has a mount that engages with the mount of the camera 830, allowing the viewfinder 840 to be attached to the camera 830. The mount also has electrodes, which allow images and other data received from the camera 830 to be displayed on the display unit 842.

[0413] Button 843 functions as a power button. Button 843 can be used to switch the display on and off of the display unit 842.

[0414] A semiconductor device according to one aspect of the present invention can be applied to the display unit 832 of the camera 830 and the display unit 842 of the viewfinder 840.

[0415] In Figure 34C, the camera 830 and the viewfinder 840 are shown as separate electronic devices and are configured to be detachable. However, the viewfinder, which includes a semiconductor device according to one aspect of the present invention, may be built into the housing 831 of the camera 830.

[0416] The information terminal 850 shown in Figure 34D includes a housing 851, a display unit 852, a microphone 857, a speaker unit 854, a camera 853, and an operation switch 855. A semiconductor device according to one aspect of the present invention can be applied to the display unit 852. The display unit 852 also functions as a touch panel. Furthermore, the information terminal 850 includes an antenna, battery, etc. inside the housing 851. The information terminal 850 can be used, for example, as a smartphone, mobile phone, tablet information terminal, tablet personal computer, e-book reader, etc.

[0417] Figure 34E shows an example of a wristwatch-type information terminal. The information terminal 860 includes a housing 861, a display unit 862, a band 863, a buckle 864, an operation switch 865, input / output terminals 866, etc. The information terminal 860 also has an antenna and battery inside the housing 861. The information terminal 860 can run various applications such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games.

[0418] Furthermore, the display unit 862 is equipped with a touch sensor and can be operated by touching the screen with a finger or stylus. For example, an application can be launched by touching the icon 867 displayed on the display unit 862. The operation switch 865 can have various functions, including setting the time, turning the power on and off, turning wireless communication on and off, activating and deactivating silent mode, and activating and deactivating power saving mode. For example, the functions of the operation switch 865 can also be configured by the operating system built into the information terminal 860.

[0419] Furthermore, the information terminal 860 is capable of performing standardized short-range wireless communication. For example, it can communicate with a wireless communication-enabled headset to make hands-free calls. The information terminal 860 is also equipped with an input / output terminal 866, which can be used to send and receive data with other information terminals. It can also be charged via the input / output terminal 866. Note that charging may be performed by wireless power supply without using the input / output terminal 866.

[0420] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. [Explanation of Symbols]

[0421] 10: Layer, 11: Memory unit, 12: Memory cell, 15: Memory cell group, 19: Terminal unit, 20: Layer, 21: CPU, 22: GPU, 23: Display unit driver circuit, 24: Memory unit driver circuit, 25: Super-resolution circuit, 26: Sensor circuit, 27: Communication circuit, 28: Input / output circuit, 29: Terminal unit, 30: Layer, 31: Display unit, 32: Memory chip, 35: Sub-screen, 38: Wire, 39: Terminal unit, 40: Encapsulated substrate, 42: Notch, 51: Pixel circuit, 53: Capacitor, 55: Conductor, 60: Layer, 61: Light-emitting element, 71: Control circuit, 72: Timing controller, 73: Serial-to-parallel conversion circuit, 74: Latch circuit, 75: DAC, 76: Amplifier circuit, 90: Functional circuit

Claims

[Claim 1] The first layer and, The second layer on the first layer, The sealing substrate on the second layer, The first layer has a circuit, The circuit is electrically connected to the second layer, The second layer comprises a display unit and a storage unit including a memory chip. The memory chip is arranged along at least a portion of the outer periphery of the display unit, The display unit and the storage unit are covered by a sealing substrate. Semiconductor equipment.

Images