Semiconductor device and method for manufacturing the same

Abstract

The goal is to reduce on-resistance while suppressing the increase in size of semiconductor devices in the plane direction of the semiconductor substrate. [Solution] The process involves forming a gate electrode 22 on a gate insulating film 21, forming an interlayer insulating film 30 to cover the gate electrode 22, and forming a contact hole 33 in the interlayer insulating film 30 to expose the impurity region 14 and the contact region 15. The formation of the contact hole 33 involves performing a first etching using the insulating films 21 and 32, which are placed on one surface 10a of the semiconductor substrate 10 and cover at least the contact region 15, as etching stopper films, and then performing a second etching that causes less damage to the semiconductor substrate 10 than the first etching to remove the insulating film used as an etching stopper film.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device composed of gallium nitride (hereinafter also simply referred to as GaN) and a method for manufacturing the same.

Background Art

[0002] Conventionally, semiconductor devices composed of GaN have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a semiconductor substrate composed of GaN and having one surface is provided. On the semiconductor substrate, a p-type body layer is formed in the surface layer portion on one surface side, and an n-type source region and a contact region having a higher impurity concentration than the body layer are formed in the surface layer portion of the body layer. Further, a gate electrode is formed on one surface of the semiconductor substrate via a gate insulating film, and an interlayer insulating film is formed so as to cover the gate electrode. A contact hole for exposing the source region and the contact region is formed in the interlayer insulating film. Then, a source electrode electrically connected to the source region and the contact region through the contact hole is disposed on one surface of the semiconductor substrate.

[0003] When manufacturing such a semiconductor device, after forming a gate insulating film and an interlayer insulating film, a contact hole for exposing the source region and the contact region is formed by dry etching or the like. At this time, it has been reported that the p-type layer of the semiconductor substrate composed of GaN is easily n-type converted by damage. Therefore, in this method for manufacturing a semiconductor device, a body electrode made of metal is disposed on the contact region before forming the interlayer insulating film, and when forming a contact hole in the interlayer insulating film, the body electrode is used as an etching stopper film. And the source electrode is disposed in the contact hole so as to be connected to the body electrode.

[0004] The interlayer insulating film is composed of an oxide film, and the body electrode is composed of nickel, palladium, or the like. When the body electrode is made of nickel, palladium, or the like, it is a material with low adhesion to the oxide film that constitutes the interlayer insulating film. Therefore, in this semiconductor device manufacturing method, in order to suppress the peeling of the body electrode when forming the contact hole, the contact hole is formed such that the outer edge of the body electrode is covered with the interlayer insulating film. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2022-50236 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Incidentally, in the semiconductor device described above, it is desirable to separate the gate electrode and the source electrode by a predetermined distance in order to suppress leakage current flow between the gate electrode and the source electrode. However, in the semiconductor device described above, the outer edge of the body electrode is covered with an interlayer insulating film, so the distance between the gate electrode and the source electrode becomes longer than the distance between the gate electrode and the body electrode. Furthermore, since the body electrode and the source electrode are electrically connected, in order to suppress leakage current between the gate electrode and the source electrode, the distance between the gate electrode and the body electrode must be greater than the predetermined distance, which further increases the distance between the gate electrode and the source electrode. Consequently, the semiconductor device described above tends to be enlarged in the plane direction of the semiconductor substrate, and the on-resistance may increase due to the excessive distance between the gate electrode and the source electrode.

[0007] The present disclosure aims to provide a semiconductor device and a method for manufacturing the same that can reduce on-resistance while suppressing an increase in size in the planar direction of the semiconductor substrate. [Means for solving the problem]

[0008] According to one aspect of this disclosure, a method for manufacturing a semiconductor device involves preparing a semiconductor substrate (10) comprising GaN, having one surface (10a), and having a drift layer (12) of a first conductivity type; forming a body layer (13) of a second conductivity type on the surface of the one surface of the semiconductor substrate, forming an impurity region (14) of a first conductivity type and a contact region (15) of a second conductivity type having a higher impurity concentration than the body layer on the surface of the body layer; forming a gate insulating film (21) at a position including the surface of the portion of the body layer between the drift layer and the body layer; forming a gate electrode (22) on the gate insulating film; and forming an interlayer covering the gate electrode. The process involves forming an insulating film (30), forming contact holes (33) in the interlayer insulating film to expose the impurity region and the contact region, and forming electrodes (41) that are electrically connected to the impurity region and the contact region through the contact holes. Forming the contact holes involves performing a first etching using insulating films (21, 32) arranged on one surface of the semiconductor substrate and covering at least the contact region as an etching stopper film, and performing a second etching that causes less damage to the semiconductor substrate than the first etching to remove the insulating film used as the etching stopper film.

[0009] According to this method, an insulating film is used as an etching stopper film, eliminating the need for body electrodes with a larger planar shape than the contact holes. This makes it easier to shorten the distance between the electrode placed in the contact hole and the gate electrode. Consequently, it is possible to suppress the increase in size of the semiconductor device in the planar direction of the semiconductor substrate, thereby reducing on-resistance.

[0010] According to another aspect of this disclosure, the semiconductor device comprises an impurity layer (11) of a first conductivity type or a second conductivity type, a drift layer (12) of a first conductivity type disposed on the impurity layer, a body layer (13) of a second conductivity type formed on the surface of the drift layer, an impurity region (14) of a first conductivity type formed on the surface of the body layer, and a contact region (15) of a second conductivity type having a higher impurity concentration than the body layer, a gate insulating film (21) disposed on the surface of the body layer between the drift layer and the impurity region, a gate electrode (22) disposed on the gate insulating film, an interlayer insulating film (30) covering the gate electrode, a first electrode (41) electrically connected to the body layer and the impurity region through a contact hole formed in the interlayer insulating film, and a second electrode (42) electrically connected to the impurity layer, wherein the interlayer insulating film has a portion that contacts at least one of the impurity region and the contact region, the contact portion is made of a different material from the gate insulating film, and the portion of the impurity region and the contact region that contacts the interlayer insulating film is made of a material that generates compressive stress.

[0011] According to this method, by using an insulating film as an etching stopper film, a body electrode with a larger planar shape than the contact hole becomes unnecessary. Therefore, the distance between the electrode placed in the contact hole and the gate electrode can be easily shortened. Consequently, the semiconductor device can be prevented from becoming larger in the planar direction of the semiconductor substrate, and on-resistance can be reduced. Furthermore, the interlayer insulating film is composed of a material that generates compressive stress in the impurity region and the portion of the contact region that is in contact with the interlayer insulating film. Therefore, on-resistance can also be reduced by the polarization effect caused by the compressive stress.

[0012] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of the semiconductor device in the first embodiment. [Figure 2] It is a plan view of the semiconductor device shown in FIG. 1. [Figure 3] It is a figure showing a model for which the investigation regarding the leakage current was performed. [Figure 4] It is a figure showing the relationship between the gate voltage and the leakage current. [Figure 5] It is a figure showing the relationship between the depth and the silicon concentration. [Figure 6A] It is a sectional view showing the manufacturing process of the semiconductor device shown in FIG. 1. [Figure 6B] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6A. [Figure 6C] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6B. [Figure 6D] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6C. [Figure 6E] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6D. [Figure 6F] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6E. [Figure 6G] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6F. [Figure 6H] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6G. [Figure 6I] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 6H. [Figure 7] It is a sectional view of the semiconductor device in the second embodiment. [Figure 8A] It is a sectional view showing the manufacturing process of the semiconductor device shown in FIG. 7. [Figure 8B] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 8A. [Figure 8C] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 8B. [Figure 8D] It is a sectional view showing the manufacturing process of the semiconductor device following FIG. 8C. [Figure 8E] It is a sectional view showing the manufacturing process of the semiconductor device following FIG.​This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8E. [Figure 8G] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8F. [Figure 8H] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8G. [Figure 8I] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8H. [Figure 8J] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8I. [Figure 9] This is a cross-sectional view showing the manufacturing process of a semiconductor device in the third embodiment. [Figure 10A] Figure 9 is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 10B] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 10A. [Figure 10C] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 10B. [Figure 10D] Figure 10C is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 10E] Figure 10D is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 10F] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 10E. [Figure 10G] Figure 10F is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 11A] This is a plan view of a semiconductor device in another embodiment. [Figure 11B] This is a plan view of a semiconductor device in another embodiment. [Figure 12A] This is a cross-sectional view of a semiconductor device in another embodiment. [Figure 12B] This is a cross-sectional view of a semiconductor device in another embodiment. [Figure 12C] This is a cross-sectional view of a semiconductor device in another embodiment. [Figure 12D] This is a cross-sectional view of a semiconductor device in another embodiment. [Figure 12E]This is a cross-sectional view of a semiconductor device in another embodiment. [Figure 12F] This is a cross-sectional view of a semiconductor device in another embodiment. [Modes for carrying out the invention]

[0014] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First Embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, a semiconductor device in which a planar gate type MOSFET is formed will be described. Note that MOSFET is an abbreviation for metal oxide semiconductor field effect transistor.

[0016] First, the configuration of the semiconductor device manufactured by the semiconductor device manufacturing method of this embodiment will be described with reference to Figures 1 and 2. Figure 2 is a plan view in which the gate electrode 22, first interlayer insulating film 31, source electrode 41, etc., which will be described later, are omitted, and hatching has been applied to the second interlayer insulating film 32, which will be described later, for ease of understanding. Also, Figure 1 is a cross-sectional view along line II in Figure 2.

[0017] Semiconductor devices are n + The substrate 11 is made of n-type GaN. In this embodiment, the drain layer is made of the substrate 11, and the substrate 11 corresponds to the impurity layer. A drift layer 12 is formed on the substrate 11, which is made of n-type GaN and has a lower n-type impurity concentration than the substrate 11. A p-type body layer 13 is selectively formed on the surface of the drift layer 12. This body layer 13 is a layer that constitutes the channel of the MOSFET. + The source region 14, which is of a type and has a higher impurity concentration than the drift layer 12, and p +A contact region 15 is formed, which has a higher impurity concentration than the body layer 13. In this embodiment, the contact region 15 is formed to penetrate the source region 14 and reach the body layer 13.

[0018] The drift layer 12 is formed by epitaxially growing a GaN layer on the substrate 11. The body layer 13, source region 14, and contact region 15 are formed by ion implantation of impurities into the drift layer 12. In this embodiment, the source region 14 corresponds to the impurity region.

[0019] In this embodiment, the semiconductor substrate 10 is composed of a substrate 11, a drift layer 12, a body layer 13, a source region 14, a contact region 15, etc. In other words, the semiconductor substrate 10 is composed of GaN. Hereinafter, the side of the semiconductor substrate 10 that is on the substrate 11 side will be referred to as the other side 10b of the semiconductor substrate 10, and the side of the semiconductor substrate 10 that is on the source region 14 side will be referred to as the first side 10a. The first side 10a of the semiconductor substrate 10 in this embodiment is composed of a source region 14, a contact region 15, and a drift layer 12.

[0020] A gate insulating film 21 is formed on one surface 10a of the semiconductor substrate 10, including the surface portion between the drift layer 12 and the source region 14 of the body layer 13. A gate electrode 22 is formed on the gate insulating film 21. The gate insulating film 21 is made of, for example, an oxide film.

[0021] Furthermore, an interlayer insulating film 30 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate insulating film 21 and the gate electrode 22. Contact holes 33 are formed in the interlayer insulating film 30 and the gate insulating film 21 to expose the source region 14 and the contact region 15.

[0022] A source electrode 41 is positioned on the interlayer insulating film 30, within a contact hole 33, and electrically connected to the source region 14 and the contact region 15. The source electrode 41 in this embodiment is configured to have a body electrode 41b positioned on the portion of one surface 10a of the semiconductor substrate 10 that is exposed from the contact hole 33, for ohmic contact with the semiconductor substrate 10, and a main electrode 41a positioned on the interlayer insulating film 30 or within the contact hole 33 and connected to the body electrode 41b. The body electrode 41b is made of, for example, nickel or palladium, and the main electrode 41a is made of, for example, aluminum or aluminum silicon. In Figure 1, the body electrode 41b is shown positioned on the contact region 15, but the body electrode 41b may also be positioned on the source region 14, or it may be positioned over the entire portion of one surface 10a of the semiconductor substrate 10 that is exposed from the contact hole 33. However, the outer edge portion of the body electrode 41b in the planar direction is not covered by the interlayer insulating film 30.

[0023] A drain electrode 42, which is electrically connected to the substrate 11, is formed on the other side 10b of the semiconductor substrate 10.

[0024] The above describes the basic configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. In this embodiment, the source electrode 41 corresponds to the first electrode, and the drain electrode 42 corresponds to the second electrode.

[0025] Next, the configuration of the interlayer insulating film 30 in the semiconductor device of this embodiment will be described. The interlayer insulating film 30 of this embodiment is composed of a first interlayer insulating film 31 that covers the gate electrode 22 and a second interlayer insulating film 32 that contacts at least one of the source region 14 and the contact region 15. The gate insulating film 21 has its end in the planar direction of the semiconductor substrate 10 positioned on the second interlayer insulating film 32. In this embodiment, the wall surface of the contact hole 33 is composed of the gate insulating film 21, the first interlayer insulating film 31 and the second interlayer insulating film 32. In other words, the contact hole 33 of this embodiment is composed of a contact hole 21a formed in the gate insulating film 21, a first contact hole 31a formed in the first interlayer insulating film 31 and a second contact hole 32a formed in the second interlayer insulating film 32, all of which are in communication with each other.

[0026] Here, the configuration of the second interlayer insulating film 32 in this embodiment will be described. The second interlayer insulating film 32 is made of a material in which at least one constituent element is different from that of the first interlayer insulating film 31 and the gate insulating film 21. That is, the second interlayer insulating film 32 is made of a material different from that of the first interlayer insulating film 31 and the gate insulating film 21.

[0027] Furthermore, the second interlayer insulating film 32 is positioned to be in contact with at least one of the source region 14 and the contact region 15, as described above. In this embodiment, the second interlayer insulating film 32 is positioned to be in contact with the source region 14. The second interlayer insulating film 32 is made of a material capable of generating compressive stress in the portion of the semiconductor substrate 10 that is in contact with the second interlayer insulating film 32 by generating tensile stress.

[0028] For example, in this embodiment, the gate insulating film 21 and the first interlayer insulating film 31 are composed of a silicon oxide (i.e., SiO2) film or the like. The second interlayer insulating film 32 is composed of an aluminum nitride (i.e., AlN) film, a silicon nitride (i.e., SiN) film, an amorphous silicon film or the like.

[0029] Furthermore, when the second interlayer insulating film 32 is composed of an aluminum nitride-based film, a silicon nitride-based film, and an amorphous silicon-based film as described above, the second interlayer insulating film 32 is made of a material with a higher resistivity than the source electrode 41 and the contact region 15.

[0030] Then, the inventors investigated the leakage current of the gate electrode 22 using a model in which an n-type GaN layer 52 is placed on the other-sided electrode 51, an aluminum nitride-based insulating film 53 is placed on the GaN layer 52, and a gate electrode 22 is placed on this insulating film 53, as shown in Figure 3, and obtained the results shown in Figure 4.

[0031] In Figure 4, the aluminum nitride-based insulating film 53 is 150 μm thick, and as shown in Figure 5, the insulating film 53 contains impurities such as silicon. Specifically, as shown in Figure 5, the insulating film 53 contains silicon with a content of 5 × 10⁻¹⁶. 19 cm -3 It is included to some extent.

[0032] As shown in Figure 4, increasing the gate voltage Vg applied to the gate electrode 22 increases the leakage current Ig, but it is confirmed that the aluminum nitride-based insulating film 53 can sufficiently satisfy the currently required leakage current. In other words, it is confirmed that even if the aluminum nitride-based insulating film 53 contains impurities such as silicon, it can still exhibit sufficient insulating properties. That is, the aluminum nitride-based insulating film can provide sufficient insulating properties even when used as a through-film during ion implantation or as a cap film during heat treatment. Although not specifically shown here, the inventors have obtained similar results for silicon nitride-based and amorphous silicon-based insulating films.

[0033] Next, the operation of the semiconductor device of this embodiment will be described.

[0034] In the semiconductor device, when the device is in the off state before a gate voltage is applied to the gate electrode 22, no inversion layer is formed in the body layer 13. Therefore, even if a positive voltage is applied to the drain electrode 42, electrons do not flow from the source region 14 into the body layer 13, resulting in an off state where no current flows between the source electrode 41 and the drain electrode 42.

[0035] When a predetermined gate voltage is applied to the gate electrode 22 of the semiconductor device, a channel (i.e., an inversion layer) is formed on the surface of the body layer 13 that is in contact with the gate insulating film 21. The semiconductor device then turns on when electrons injected from the source electrode 41 flow from the source region 14 through the channel formed in the body layer 13 to the drift layer 12, and then from the drift layer 12 to the drain electrode 42.

[0036] In this embodiment, the semiconductor device is arranged such that the second interlayer insulating film 32 is in contact with the source region 14. Furthermore, the second interlayer insulating film 32 is made of a material that generates compressive stress in the semiconductor substrate 10 (i.e., the source region 14) in contact with the second interlayer insulating film 32. As a result, electrons are induced in the source region 14 by the polarization effect caused by compression. Therefore, the on-resistance can be reduced.

[0037] Furthermore, in the semiconductor device of this embodiment, as described above, the on-resistance can be reduced by the polarization effect. Therefore, even if the impurity concentration in the source region 14 is low, the on-resistance can be made equivalent to that of a semiconductor device without a polarization effect. In the semiconductor device of this embodiment, the source region 14 and the body layer 13 are formed by ion implantation, as will be described later. When the on-resistance of the semiconductor device of this embodiment is to be equivalent to that of a semiconductor device without a polarization effect, the impurity concentration in the source region 14 can be lowered, and consequently, the depth of the body layer 13 can be made shallower. Therefore, by making the depth of the body layer 13 shallower, if the portion of the drift layer 12 on one side 10a of the semiconductor substrate 10 that is located between the body layers 13 is made into the JFET portion, the depth of the JFET portion can be made shallower, and the JFET resistance can be reduced.

[0038] Next, the manufacturing method of the semiconductor device described above will be explained with reference to Figures 6A to 6I. Note that in Figures 6A to 6I, the other side 10b of the semiconductor substrate 10 is omitted.

[0039] First, as shown in Figure 6A, a semiconductor substrate 10 is prepared in which a drift layer 12, a body layer 13, a source region 14, and a contact region 15 are formed, and a second interlayer insulating film 32 is placed on one surface 10a of the semiconductor substrate 10.

[0040] Such a semiconductor substrate 10 can be prepared, for example, as follows. First, an n-type semiconductor substrate 10 is prepared. Next, impurities are ion-implanted with a mask appropriately placed, and then a heat treatment is performed to activate the impurities. In this case, by placing the second interlayer insulating film 32 before the heat treatment, the second interlayer insulating film 32 can be used as a cap film, and damage to one surface 10a of the semiconductor substrate 10 during the heat treatment can be suppressed. Alternatively, by placing the second interlayer insulating film 32 between the mask and one surface 10a of the semiconductor substrate 10 before ion-implanting the impurities, the second interlayer insulating film 32 can be used as a through film, and damage to one surface 10a of the semiconductor substrate 10 during ion-implantation of impurities can be suppressed. In this case, the second interlayer insulating film 32 may contain impurities when ion implantation or heat treatment is performed, but sufficient insulation can be ensured, for example, by making the second interlayer insulating film 32 an aluminum nitride-based insulating film. The second interlayer insulating film 32 may also be placed after the heat treatment has been performed.

[0041] Next, as shown in Figure 6B, the resist 100 is placed on the second interlayer insulating film 32 and the resist 100 is patterned. Then, etching is performed using the resist 100 as a mask, and the second interlayer insulating film 32 is patterned so that it remains in the area where the contact hole 33 will be formed in the process shown in Figure 6G, which will be described later. The second interlayer insulating film 32 is patterned so that its planar shape is larger than that of the contact hole 33. In other words, the second interlayer insulating film 32 is patterned so that at least the contact region 15 is covered. After that, the resist 100 is removed by ashing or the like.

[0042] Next, as shown in Figure 6C, the gate insulating film 21 is placed over the second interlayer insulating film 32 by CVD or the like. Then, if necessary, heat treatment is performed to densify the gate insulating film 21 and improve the film quality. At this time, in this embodiment, since the body electrode 41b has not yet been placed, the metal atoms of the body electrode 41b do not diffuse into the gate insulating film 21 or the semiconductor substrate 10, thus suppressing a decrease in reliability.

[0043] Next, as shown in Figure 6D, the gate electrode 22 is placed on the gate insulating film 21 by CVD or the like. Subsequently, as shown in Figure 6E, the resist 110 is placed on the gate electrode 22 and the resist 110 is patterned. Then, etching or the like is performed using the patterned resist 110 as a mask to pattern the gate electrode 22. Specifically, the gate electrode 22 is patterned so as to include the portion of the body layer 13 between the drift layer 12 and the source region 14 and the portion facing it. After that, the resist 110 is removed by ashing or the like.

[0044] Next, as shown in Figure 6F, the first interlayer insulating film 31 is placed over the gate electrode 22 by CVD or the like. Then, if necessary, heat treatment is performed to densify the film and improve its quality, and the surface of the first interlayer insulating film 31 opposite to the semiconductor substrate 10 is planarized.

[0045] Next, as shown in Figure 6G, a resist 120 is placed on the first interlayer insulating film 31 and the resist 120 is patterned. Then, by performing dry etching or the like using the patterned resist 120 as a mask, a first contact hole 31a is formed in the first interlayer insulating film 31 and a contact hole 21a is formed in the gate insulating film 21. In this embodiment, a second interlayer insulating film 32 is placed in the area where the contact hole 33 is formed, and the second interlayer insulating film 32 is made of a different material from the first interlayer insulating film 31 and the gate insulating film 21. Therefore, the second interlayer insulating film 32 acts as an etching stopper film, suppressing damage to the p-type contact region 15 and preventing it from changing to an n-type. In this embodiment, dry etching corresponds to the first etching.

[0046] Next, as shown in Figure 6H, a contact hole 33 is formed by forming a second contact hole 32a that communicates with the first contact hole 31a in the second interlayer insulating film 32 exposed from the contact hole 21a of the first contact hole 31a and the gate insulating film 21. When forming the second contact hole 32a, a method is used that is less likely to damage the semiconductor substrate 10 than when forming the first contact hole 31a. In other words, when forming the second contact hole 32a, a method is used that does not damage the p-type contact region 15 and turn it into an n-type region. For example, in this embodiment, when forming the second contact hole 32a, a method that is less likely to damage the semiconductor substrate 10, such as wet etching, is employed. In this embodiment, wet etching corresponds to the second etching.

[0047] Subsequently, as shown in Figure 6I, a predetermined semiconductor manufacturing process is carried out to form a source electrode 41, including a body electrode 41b and a main electrode 41a, on one side 10a of the semiconductor substrate 10. Although not shown, a drain electrode 42 is also formed on the other side 10b of the semiconductor substrate 10. This completes the manufacturing of the semiconductor device shown in Figure 1.

[0048] According to the embodiment described above, the second interlayer insulating film 32 is used as an etching stopper film, eliminating the need for a body electrode with a planar shape larger than the contact hole 33. Therefore, the distance between the source electrode 41 and the gate electrode 22, which are placed in the contact hole 33, can be easily shortened. Consequently, the semiconductor device can be prevented from becoming larger in the planar direction of the semiconductor substrate 10, and the on-resistance can be reduced.

[0049] (1) In this embodiment, the interlayer insulating film 30 is configured to have a first interlayer insulating film 31 and a second interlayer insulating film 32, and the second interlayer insulating film 32 is positioned to contact either the source region 14 or the contact region 15 of the semiconductor substrate 10 after the contact hole 33 is formed. Therefore, the on-resistance can be further reduced by the polarization effect. In addition, since the second interlayer insulating film 32 is used as an etching stopper film, there is no need to use another etching stopper film, and the increase in manufacturing steps can be suppressed.

[0050] (2) In this embodiment, the second interlayer insulating film 32 is formed before the gate insulating film 21 is formed. Therefore, the second interlayer insulating film 32 can be used as a through-film when ion implantation is performed or as a cap film when activation treatment is performed. Thus, the manufacturing process can be simplified compared to cases where the through-film and cap film are prepared separately.

[0051] (3) In this embodiment, the resistance of the second interlayer insulating film 32 in the portion that contacts the source region 14 and the contact region 15 is higher than the resistance of the source electrode 41 and the source region 14. Therefore, the insulating properties of the second interlayer insulating film 32 can be ensured.

[0052] (4) In this embodiment, the second interlayer insulating film 32 is composed of at least one of aluminum nitride-based, silicon nitride-based, and amorphous silicon. Therefore, even if the second interlayer insulating film 32 is used as a through-film when ion implantation is performed or as a cap film when activation treatment is performed, the insulating properties of the second interlayer insulating film 32 can be sufficiently ensured.

[0053] (Second Embodiment) A second embodiment will now be described. This embodiment modifies the manufacturing method of the semiconductor device compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0054] First, the structure of the semiconductor device of this embodiment will be described with reference to Figure 7. In the semiconductor device of this embodiment, the gate insulating film 21 is located on the opposite side of the contact hole 33, with the second interlayer insulating film 32 in between, and is not located on the second interlayer insulating film 32. The first interlayer insulating film 31 is located on the second interlayer insulating film 32. Therefore, the contact hole 33 of this embodiment is configured by the communication between the first contact hole 31a formed in the first interlayer insulating film 31 and the second contact hole 32a formed in the second interlayer insulating film 32.

[0055] Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 8A to 8J. Note that in Figures 8A to 8J, the other side 10b of the semiconductor substrate 10 is omitted.

[0056] First, as shown in Figure 8A, a semiconductor substrate 10 is prepared in which a drift layer 12, a body layer 13, a source region 14, and a contact region 15 are formed, and a gate insulating film 21 is formed on one surface 10a of the semiconductor substrate 10. Then, if necessary, heat treatment is performed to densify the gate insulating film 21 and improve the film quality.

[0057] Next, as shown in Figure 8B, a resist 130 is placed on the gate insulating film 21 and the resist 130 is patterned. Then, etching or the like is performed using the resist 130 as a mask to pattern the gate insulating film 21. After that, the resist 130 is removed by ashing or the like. Subsequently, as shown in Figure 8C, a second interlayer insulating film 32 is placed on one side 10a of the semiconductor substrate 10 so as to cover the gate insulating film 21, using a CVD method or the like. In this embodiment, the thickness of the second interlayer insulating film 32 is made thicker than the thickness of the gate insulating film 21.

[0058] Next, as shown in Figure 8D, the resist 140 is placed on the second interlayer insulating film 32 and the resist 140 is patterned. Then, etching or the like is performed using the patterned resist 140 as a mask, and the second interlayer insulating film 32 is patterned so that it remains in the area where the contact holes 33 will be formed in the process shown in Figure 8H, which will be described later. The second interlayer insulating film 32 is patterned so that its planar shape is larger than that of the contact holes 33. In this embodiment, the second interlayer insulating film 32 is patterned so that the gate insulating film 21 and the second interlayer insulating film 32 are arranged side by side in the planar direction of the semiconductor substrate 10 and in contact with each other. After that, the resist 140 is removed by ashing or the like.

[0059] Next, as shown in Figure 8E, the gate electrode 22 is placed on the gate insulating film 21 and the second interlayer insulating film 32 by CVD or the like. Then, as shown in Figure 8F, the resist 150 is placed on the gate electrode 22 and the resist 150 is patterned. Then, the patterned resist 150 is used as a mask to perform etching or the like to pattern the gate electrode 22. After that, the resist 150 is removed by ashing or the like.

[0060] Next, as shown in Figure 8G, the first interlayer insulating film 31 is placed over the gate electrode 22 by CVD or the like. Then, if necessary, heat treatment is performed to densify the film and improve its quality, and the surface of the first interlayer insulating film 31 opposite to the semiconductor substrate 10 is planarized.

[0061] Then, as shown in Figure 8H, a resist 120 is placed on the first interlayer insulating film 31 and the resist 120 is patterned. Then, by performing dry etching or the like using the patterned resist 120 as a mask, a first contact hole 31a is formed in the first interlayer insulating film 31. In this embodiment, a second interlayer insulating film 32 is placed in the area where the contact hole 33 (i.e., the first contact hole 31a) is formed, and the second interlayer insulating film 32 is made of a different material from the first interlayer insulating film 31. Therefore, the second interlayer insulating film 32 acts as an etching stopper film, and damage is applied to the p-type contact region 15, preventing it from changing to an n-type.

[0062] Next, as shown in Figure 8I, a contact hole 33 is formed by forming a second contact hole 32a communicating with the first contact hole 31a in the second interlayer insulating film 32 exposed from the bottom surface of the first contact hole 31a. When forming the second contact hole 32a, it is preferable to employ a method that minimizes damage to the semiconductor substrate 10, such as wet etching, so as not to damage the p-type contact region 15 and prevent it from becoming an n-type region.

[0063] Subsequently, as shown in Figure 8J, the same process as in Figure 6I is performed to form the source electrode 41, which includes the body electrode 41b and the main electrode 41a, and the drain electrode 42, thereby manufacturing the semiconductor device shown in Figure 7.

[0064] According to the embodiment described above, since the second interlayer insulating film 32 is used as an etching stopper film, the same effects as in the first embodiment can be obtained.

[0065] (1) In this embodiment, the gate insulating film 21 is formed before the second interlayer insulating film 32 is formed. Therefore, the gate insulating film 21 can be heat-treated while the second interlayer insulating film 32 is not in place, and contamination of the gate insulating film 21 by impurities contained in the second interlayer insulating film 32 can be suppressed.

[0066] (Third embodiment) A third embodiment will now be described. This embodiment modifies the manufacturing method of the semiconductor device compared to the first embodiment. Other aspects are the same as in the first embodiment, so further explanation will be omitted here.

[0067] First, the structure of the semiconductor device of this embodiment will be described with reference to Figure 9. In this embodiment, the interlayer insulating film 30 is composed of a second interlayer insulating film 32, and the first interlayer insulating film 31 is not present. That is, the second interlayer insulating film 32 of this embodiment is formed to cover the gate electrode 22 while in contact with the source region 14. The contact hole 33 is composed of a second contact hole 32a formed in the second interlayer insulating film 32.

[0068] The above describes the configuration of the semiconductor device in this embodiment. Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 10A to 10G.

[0069] First, as shown in Figure 10A, a semiconductor substrate 10 is prepared in which a drift layer 12, a body layer 13, a source region 14, and a contact region 15 are formed, and a gate insulating film 21 is formed on one surface 10a of the semiconductor substrate 10, similar to the second embodiment described above. Then, a gate electrode 22 is formed on the gate insulating film 21.

[0070] Next, as shown in Figure 10B, the resist 160 is placed on the gate electrode 22 and the resist 160 is patterned. Then, etching or the like is performed using the resist 160 as a mask to pattern the gate electrode 22. After that, the resist 160 is removed by ashing or the like.

[0071] Next, as shown in Figure 10C, the resist 170 is placed on the gate insulating film 21 and the gate electrode 22, and the resist 170 is patterned. Then, etching is performed using the resist 170 as a mask, and the gate insulating film 21 is patterned so that it remains in the area where the contact hole 33 will be formed in the process shown in Figure 10E, which will be described later. The gate insulating film 21 is patterned so that at least the portion covering the contact area 15 remains. After that, the resist 170 is removed by ashing or the like. In this embodiment, the gate insulating film 21 formed between the gate electrode 22 and one surface 10a of the semiconductor substrate 10 and the gate insulating film 21 in the portion where the contact hole 33 will be formed are patterned so that they are separated.

[0072] Then, as shown in Figure 10D, the interlayer insulating film 30 is arranged to cover the gate insulating film 21 and the gate electrode 22 by CVD or the like. The interlayer insulating film 30 in this embodiment corresponds to the second interlayer insulating film 32 in the first embodiment and is made of the same material as the second interlayer insulating film 32 in the first embodiment.

[0073] Subsequently, as shown in Figure 10E, the resist 120 is placed on the interlayer insulating film 30 and the resist 120 is patterned. Then, contact holes 33 are formed in the interlayer insulating film 30 by performing dry etching or the like using the patterned resist 120 as a mask. In this embodiment, a gate insulating film 21 is placed in the area where the contact holes 33 are formed, and the gate insulating film 21 is made of a different material from the interlayer insulating film 30. Therefore, the gate insulating film 21 acts as an etching stopper film, and damage to the contact region 15 can be suppressed.

[0074] Next, as shown in Figure 10F, the gate insulating film 21 exposed from the contact hole 33 is removed. When removing the gate insulating film 21, it is preferable to use a method that minimizes damage to the semiconductor substrate 10, such as wet etching, so as to prevent damage from being applied to the p-type contact region 15 and causing it to become an n-type region.

[0075] Subsequently, as shown in Figure 10G, the same process as in Figure 6I is performed to form the source electrode 41, which includes the body electrode 41b and the main electrode 41a, and the drain electrode 42, thereby manufacturing the semiconductor device shown in Figure 9.

[0076] According to the embodiment described above, since the gate insulating film 21 as an insulating film is used as an etching stopper film, the same effects as in the first embodiment can be obtained.

[0077] (1) In this embodiment, since the first interlayer insulating film 31 is not used, the manufacturing process can be simplified.

[0078] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0079] For example, in each of the above embodiments, a method for manufacturing a semiconductor device in which an n-channel type MOSFET is formed, in which the first conductivity type is n-type and the second conductivity type is p-type, was described. However, each of the above embodiments can also be applied to a method for manufacturing a semiconductor device in which a p-channel type MOSFET is formed, in which the conductivity types of each component are reversed compared to the n-channel type. Furthermore, each of the above embodiments can also be applied to a method for manufacturing a semiconductor device in which an IGBT with a similar structure is formed, in addition to a MOSFET. Note that when a semiconductor device in which an IGBT is formed is used, the n in each of the above embodiments is used. + The substrate 11 of type p + Except for changing the substrate 11 to a different type, the embodiments are the same as described above. In addition, although planar gate type semiconductor devices were described in the above embodiments, trench gate type semiconductor devices may also be used.

[0080] Furthermore, in each of the above embodiments, the detailed placement of the second interlayer insulating film 32 can be changed as appropriate, as long as it is positioned in contact with at least one of the source region 14 and the contact region 15. For example, as shown in Figure 11A, the second interlayer insulating film 32 may be positioned to be in contact with both the source region 14 and the contact region 15. Alternatively, as shown in Figure 11B, the second interlayer insulating film 32 may be positioned to be in contact only with the contact region 15. When the second interlayer insulating film 32 is in contact with the contact region 15, compressive stress is generated in the contact region 15, and holes are reduced by the induction of electrons. As a result, depletion of the pn junction interface between the source region 14 and the contact region 15 is suppressed, and the on-resistance can be reduced by increasing the region through which current flows.

[0081] Furthermore, in the first and second embodiments described above, the second interlayer insulating film 32 and the detailed shape of the area around the second interlayer insulating film 32 can be modified as appropriate. For example, as shown in Figure 12A, the second interlayer insulating film 32 may have the same thickness as the gate insulating film 21, and the first interlayer insulating film 31 may be placed on the second interlayer insulating film 32. As shown in Figure 12B, the second interlayer insulating film 32 may be positioned to cover the outer edge portion of the gate insulating film 21 in the planar direction, and the outer edge portion of the gate electrode 22 in the planar direction may be separated from the second interlayer insulating film 32. As shown in Figure 12C, in the configuration of Figure 12B, the gate electrode 22 may be positioned to cover the end of the second interlayer insulating film 32 opposite to the contact hole 33 side. However, even with such a configuration, the gate electrode 22 does not reach the contact hole 33 and is covered by the first interlayer insulating film 31. As shown in Figure 12D, in the configuration of Figure 12B, the gate electrode 22 may be positioned such that its outer edge in the planar direction is in contact with the second interlayer insulating film 32. As shown in Figure 12E, the second interlayer insulating film 32 may have a thickness equal to the sum of the thicknesses of the gate insulating film 21 and the gate electrode 22, and may be formed so that the outer edge in the planar direction of the gate electrode 22 reaches the second interlayer insulating film 32. As shown in Figure 12F, the second interlayer insulating film 32 may have a thickness equal to the sum of the thicknesses of the gate insulating film 21, the gate electrode 22, and the first interlayer insulating film 31, and the wall surface of the contact hole 33 may be composed solely of the second interlayer insulating film 32.

[0082] Furthermore, in each of the above embodiments, the second etching may be dry etching, provided that it causes less damage to the semiconductor substrate 10 than the first etching.

[0083] Furthermore, in each of the above embodiments, the source electrode 41 may not have a body electrode 41b and may consist only of the main electrode 41a. [Explanation of Symbols]

[0084] 10 Semiconductor substrates 10a one side 12 Drift Layers 13 Body Layers 14. Source area (impurity area) 15 Contact Area 21 Gate insulating film 22 Grid cells 30 Interlayer insulating film 33 Contact Holes

Claims

1. A method for manufacturing a semiconductor device, A semiconductor substrate (10) is prepared which is composed of gallium nitride, has one surface (10a), and has a first conductivity type drift layer (12), A second conductivity type body layer (13) is formed on the surface layer of one side of the semiconductor substrate, and a first conductivity type impurity region (14) and a second conductivity type contact region (15) with a higher impurity concentration than the body layer are formed on the surface layer of the body layer. A gate insulating film (21) is formed at a position including the surface of the portion of the body layer between the drift layer and the body layer, Forming a gate electrode (22) on the gate insulating film, To form an interlayer insulating film (30) covering the gate electrode, A contact hole (33) is formed in the interlayer insulating film, exposing the impurity region and the contact region. The process involves forming an electrode (41) that is electrically connected to the impurity region and the contact region through the contact hole, A method for manufacturing a semiconductor device, comprising: forming the contact holes by performing a first etching using an insulating film (21, 32) arranged on one surface of the semiconductor substrate and covering at least the contact area as an etching stopper film; and performing a second etching that causes less damage to the semiconductor substrate than the first etching, thereby removing the insulating film used as the etching stopper film.

2. The formation of the interlayer insulating film involves forming a first interlayer insulating film (31) that covers the gate electrode, and forming a second interlayer insulating film (32) on one surface of the semiconductor substrate, which is made of a different material from the first interlayer insulating film and generates compressive stress in the contact portion of the semiconductor substrate by contacting it. The method for manufacturing a semiconductor device according to claim 1, wherein the formation of the contact holes is performed by: first etching to form a first contact hole (31a) in the first interlayer insulating film using the second interlayer insulating film as an etching stopper film; and second etching to expose the semiconductor substrate in the second interlayer insulating film in communication with the first contact hole, and to form a second contact hole (32a) such that a part of the second interlayer insulating film is in contact with at least one of the body layer and the impurity region.

3. Before forming the gate insulating film, the interlayer insulating film between the two layers is formed. A method for manufacturing a semiconductor device according to claim 2, wherein after forming the gate insulating film and forming the gate electrode, the first interlayer insulating film is formed.

4. Forming the body layer, the impurity region, and the contact region involves ion implantation of impurities and heat treatment after ion implantation of impurities. The method for manufacturing a semiconductor device according to claim 3, wherein the formation of the second interlayer insulating film is performed before the heat treatment.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the formation of the second interlayer insulating film is performed before ion implantation of the impurities.

6. The formation of the second interlayer insulating film is performed after the formation of the gate insulating film. The method for manufacturing a semiconductor device according to claim 2, wherein a heat treatment is performed after forming the gate insulating film and before forming the second interlayer insulating film.

7. By forming the gate insulating film, the gate insulating film is also placed in the portion that is exposed by forming the contact hole. The method for manufacturing a semiconductor device according to claim 1, wherein the formation of the contact hole is performed by first etching to form a contact hole (33) in the interlayer insulating film using the gate insulating film as an etching stopper film, and by second etching to remove the gate insulating film used as the etching stopper film and expose the semiconductor substrate.

8. A semiconductor device, An impurity layer (11) which is of the first conductivity type or the second conductivity type, A first conductive drift layer (12) is disposed on the impurity layer, A second conductive body layer (13) formed on the surface of the drift layer, A first conductivity type impurity region (14) formed on the surface of the body layer, and a second conductivity type contact region (15) having a higher impurity concentration than the body layer, A gate insulating film (21) is disposed on the surface between the drift layer and the impurity region of the body layer, A gate electrode (22) disposed on the gate insulating film, The interlayer insulating film (30) covering the gate electrode, A first electrode (41) is electrically connected to the body layer and the impurity region through a contact hole formed in the interlayer insulating film, The device comprises a second electrode (42) electrically connected to the impurity layer, The interlayer insulating film has a portion that contacts at least one of the impurity region and the contact region, the contact portion is made of a material different from the gate insulating film, and the interlayer insulating film has a portion of the impurity region and the contact region that contacts the interlayer insulating film, and is made of a material that generates compressive stress.

9. The semiconductor device according to claim 8, wherein the portion of the interlayer insulating film that contacts at least one of the impurity region and the contact region has a higher resistance than the first electrode and the impurity region.

10. The semiconductor device according to claim 8 or 9, wherein the interlayer insulating film comprises any of aluminum nitride, silicon nitride, or amorphous silicon.

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