Controller circuit and DC / DC converter using the same

Abstract

This invention provides a controller circuit that can suppress fluctuations in the output voltage when waking from sleep mode. [Solution] The controller circuits 10, 30, and 60 are for DC / DC converters 1, 2, and 4 that generate output voltages corresponding to the input voltage. These controller circuits 10, 30, and 60 include PWM comparators 108, 600, and 602 that compare a periodic ramp voltage with a comparison voltage, and voltage supply circuits 20, 40, and 70 that supply an initial voltage for the comparison voltage to the PWM comparators 108, 600, and 602. The initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage.

Description

Technical Field

[0001] The present disclosure relates to a controller circuit and a DC / DC converter using the same.

Background Art

[0002] Conventionally, a DC / DC converter that switches a transistor to generate an output voltage according to an input voltage is known (see, for example, Patent Document 1).

[0003] FIG. 13 is a circuit diagram of a DC / DC converter 9 according to the prior art described in Patent Document 1. The DC / DC converter 9 according to the prior art steps down an input voltage V 91 , OUT9 , 92 , 92 , , 92 , 92 , 91 to generate an output voltage V OUT9 As shown in FIG. 13, the DC / DC converter 9 according to the prior art includes an error amplifier 90, an oscillator 92, a PWM comparator 94 (PWM: Pulse Width Modulation), a NAND gate 96, an AND gate 98, switches SW91 to SW93, a high-side transistor MH9, a low-side transistor ML9, resistors R 91 ~R 93 and capacitors C 91 , C 92 .

[0004] The switch SW91 is provided between the output terminal of the error amplifier 90 and the non-inverting input terminal of the PWM comparator 94. One end of the resistor R 93 is connected to the non-inverting input terminal of the PWM comparator 94, and the other end of the resistor R 93 is connected to one end of the capacitor C 92 . The switch SW92 is provided between one end of the capacitor C 92 and the ground. The switch SW93 connects one end of the capacitor C 91 to one of the application end of the output voltage V OUT9 and one end of the capacitor C 92 . The other ends of the capacitors C 91 , C​​​

[0005] The conventional DC / DC converter 9 can enter a sleep mode under light load conditions in which the high-side transistor MH9 and low-side transistor ML9 are turned off and stopped, and the error amplifier 90 and PWM comparator 94 are in a sleep state. The transition to and release of sleep mode is controlled by the sleep signal S SLP9 It is controlled by [something].

[0006] When in sleep mode, sleep signal S SLP9 The voltage is low, and switch SW91 is off. Switch SW92 is on, and capacitor C 92 It is biased at 0V. Furthermore, switch SW93 is connected to capacitor C 91 One end is the output voltage V OUT9 Connect to the applied charge terminal, capacitor C 91 The output voltage V OUT9 It is biased by this.

[0007] When sleep mode is deactivated, sleep signal S SLP9 The signal level is high, switch SW91 is on, and switch SW92 is off. Also, switch SW93 is connected to capacitor C. 91 One end is connected to capacitor C 92 It connects to one end.

[0008] Error amplifier 90 outputs voltage V OUT9 resistor R 91 ,R 92 The feedback voltage V obtained by voltage division. FB9 and reference voltage V REF9 Comparison voltage V corresponding to the difference C9 The PWM comparator 94 generates the comparison voltage V. C9 and the periodic ramp voltage V generated by oscillator 92 RAMP9 By comparing it with the comparison signal S, CMP9 The NAND gate 96 generates the comparison signal S. CMP9 High-side gate signal S GH9 The AND gate 98 generates the comparison signal S CMP9Low-side gate signal S GL9 The high-side transistor MH9 generates the high-side gate signal S. GH9 The low-side transistor ML9 switches accordingly, and the low-side gate signal S GL9 By switching according to the output voltage V OUT9 This is generated.

[0009] When the DC / DC converter 9 enters sleep mode, the sleep signal S SLP9 The signal level changes from high to low, and the error amplifier 90 and PWM comparator 94 enter sleep mode. Furthermore, the high-side transistor MH9 and the low-side transistor MN9 are turned off and stopped.

[0010] Figure 14 is a timing chart illustrating the operation of a conventional DC / DC converter 9 when the sleep mode is released. 91 Prior to this, the DC / DC converter 9 is in sleep mode, and timing t 91 Sleep mode is deactivated.

[0011] When sleep mode is deactivated, switch SW92 turns off, and switch SW93 turns off capacitor C. 91 One end is connected to capacitor C 92 It is connected to one end. This results in the comparison voltage V of the non-inverting input terminal of the PWM comparator 94. C9 This is the voltage represented by the following equation. V C9 =k9×V OUT9 ={C 91 / (C 91 +C 92 )} × V OUT9 ...(1) Here, k9 = C 91 / (C 91 +C 92 )

[0012] The PWM comparator 94 uses the comparison voltage V expressed by equation (1).C9 With this as the initial voltage, the ramp voltage V RAMP9 The PWM comparator 94 compares the signal S accordingly. CMP9 Generates lamp voltage V RAMP9 The amplitude voltage is equal to the input voltage V IN9 It is proportional to k9 × V IN9 It is represented by the comparison signal S. CMP9 In response to the generation of [the specified value], the switching of the high-side transistor MH9 and the low-side transistor ML9 is resumed. At this time, by appropriately adjusting k9, the desired duty cycle (=V) is set when the sleep mode is released. OUT9 / V IN9 This can be achieved. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Japanese Patent Publication No. 2018-107931

[0014] [overview] However, the inventors have come to recognize the following problems. In the prior art DC / DC converter 9, the lamp voltage V RAMP9 The amplitude voltage is the input voltage V IN9 It is proportional to V. Therefore, the DC / DC converter 9 is V MIN9 <V IN9 <V MAX9 Input voltage range V IN9 When operating with input voltage V IN9 ga V MIN9 As it approaches this value, the amplitude voltage also decreases accordingly. MAX9 and V MIN9 The difference (=V) MAX9 -V MIN9 If the input voltage V is large, IN9 ga V MIN9 The amplitude voltage becomes even smaller as it approaches this value.

[0015] Lamp voltage V RAMP9 When the amplitude voltage decreases, the comparison voltage V C9Even if the initial voltage is slightly off, the initial value of the duty cycle will shift significantly, and the output voltage V OUT9 Overshoot and undershoot may occur in this case. Also, the voltage that can actually be used is the power supply voltage V dd91 Lower voltage V dd92 ( <V dd91 ) and there is a limit to the magnitude of the amplitude voltage that can be generated.

[0016] This disclosure has been made in view of these circumstances, and one of its exemplary purposes is to provide a controller circuit for a DC / DC converter that can suppress output voltage fluctuations when sleep mode is released.

[0017] A controller circuit in one aspect of the present disclosure is a controller circuit for a DC / DC converter that generates an output voltage corresponding to an input voltage. This controller circuit includes a PWM comparator that compares a periodic ramp voltage with a comparison voltage, and a voltage supply circuit that supplies an initial voltage of the comparison voltage to the PWM comparator. The initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage.

[0018] Furthermore, any combination of the above components, as well as any conversion of the expressions of this disclosure between methods, apparatus, systems, etc., are also valid as aspects of this disclosure. [Brief explanation of the drawing]

[0019] [Figure 1] Figure 1 is a block diagram of a DC / DC converter according to the first embodiment. [Figure 2] Figure 2 is a block diagram of the resistive voltage divider according to the same embodiment. [Figure 3] Figure 3 is a timing chart showing an example of the operation of the controller circuit according to the same embodiment. [Figure 4] Figure 4 is a timing chart showing an example of the operation of the resistive voltage divider according to the same embodiment. [Figure 5] Figure 5 is a block diagram of the DC / DC converter according to the second embodiment. [Figure 6] Figure 6 is a block diagram of the voltage supply circuit according to the third embodiment. [Figure 7] Figure 7 is a block diagram of the resistive voltage divider according to the same embodiment. [Figure 8] Figure 8 is a circuit diagram of the resistor circuit according to the same embodiment. [Figure 9] Figure 9 is a block diagram of the DC / DC converter according to the fourth embodiment. [Figure 10] Figure 10 is a block diagram of the resistive voltage divider according to the same embodiment. [Figure 11] Figure 11 is a timing chart showing an example of operation of the DC / DC converter in step-down mode according to the fourth embodiment. [Figure 12] Figure 12 is a timing chart showing an example of operation of the DC / DC converter in boost mode according to the same embodiment. [Figure 13] Figure 13 is a circuit diagram of a conventional DC / DC converter. [Figure 14] Figure 14 is a timing chart illustrating the operation of a conventional DC / DC converter when the sleep mode is released.

[0020] [Detailed explanation] (overview) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0021] A controller circuit according to one embodiment is a controller circuit for a DC / DC converter that generates an output voltage corresponding to an input voltage. This controller circuit includes a PWM comparator that compares a periodic ramp voltage with a comparison voltage, and a voltage supply circuit that supplies an initial voltage of the comparison voltage to the PWM comparator. The initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage.

[0022] In this configuration, the initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage. Therefore, the PWM comparator can generate a signal that achieves the desired duty cycle without changing the amplitude voltage of the ramp voltage. This eliminates the need to reduce the amplitude voltage of the ramp voltage, and suppresses the influence of fluctuations in the PWM comparator's comparison voltage on the duty cycle. As a result, fluctuations in the output voltage when waking from sleep mode can be suppressed.

[0023] In one embodiment, the voltage supply circuit may include an input voltage divider circuit that divides the input voltage to generate a comparison voltage and an adjusted voltage, an output voltage divider circuit that divides the output voltage to generate a bias voltage, a comparator that compares the amplitude voltage of the ramp voltage with the comparison voltage generated by the input voltage divider circuit, and a voltage divider adjustment circuit that adjusts the voltage division ratio in the input voltage divider circuit and the output voltage divider circuit, respectively. The voltage divider adjustment circuit may adjust the voltage division ratio in the input voltage divider circuit so that the adjusted voltage approaches the amplitude voltage based on the comparison result of the comparator, and adjust the voltage division ratio in the output voltage divider circuit so that the output voltage is divided by the voltage division ratio of the adjusted voltage to generate a bias voltage.

[0024] In one embodiment, the input voltage divider circuit may use the comparison voltage generated by the input voltage divider circuit as the first comparison voltage and further generate a second comparison voltage smaller than the first comparison voltage. The voltage supply circuit may further include a second comparator that compares the second comparison voltage with the amplitude voltage when the comparator is the first comparator. The voltage divider adjustment circuit may adjust the voltage division ratio in the input voltage divider circuit based on the first comparison result of the first comparator and the second comparison result of the second comparator so that the amplitude voltage is between the voltage of the first comparison voltage and the voltage division ratio of the second comparison voltage, and adjust the voltage division ratio in the output voltage divider circuit so that a bias voltage is generated by dividing the output voltage with a voltage division ratio between the voltage division ratio of the first comparison voltage and the voltage division ratio of the second comparison voltage after adjustment in the input voltage divider circuit.

[0025] In one embodiment, the input voltage divider circuit may include a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor connected in series. One end of the first voltage divider resistor, opposite to the second voltage divider resistor, may be connected to the input voltage application terminal. One end of the fourth voltage divider resistor, opposite to the third voltage divider resistor, may be connected to ground. The first comparison voltage may be the voltage between the first and second voltage divider resistors. The second comparison voltage may be the voltage between the third and fourth voltage divider resistors. The adjustment voltage may be the voltage between the second and third voltage divider resistors. At least one of the first and fourth voltage divider resistors may be a variable resistor. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit by adjusting the resistance values ​​of the first and fourth voltage divider resistors, and may adjust the voltage division ratio in the output voltage divider circuit so that the output voltage is divided by the voltage division ratio of the adjusted voltage to generate a bias voltage.

[0026] In one embodiment, the voltage divider adjustment circuit may sequentially change the voltage division ratio in the input voltage divider circuit based on the first and second comparison results. If the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage, the first and second comparison voltages may be increased while downcounting or upcounting. If the comparison result of the second comparator indicates that the second comparison voltage is greater than the amplitude voltage, the first and second comparison voltages may be decreased while counting in the opposite direction to when the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage. The voltage division ratio in the output voltage divider circuit may be adjusted based on the count result.

[0027] In one embodiment, the voltage divider adjustment circuit may terminate the adjustment of the voltage division ratio in the input voltage divider circuit when the comparison result of the first comparator indicates that the amplitude voltage is smaller than the first comparison voltage, and the comparison result of the second comparator indicates that the second comparison voltage is smaller than the amplitude voltage.

[0028] In one embodiment, the fourth voltage divider resistor may be a variable resistor. The voltage divider adjustment circuit may adjust the voltage division ratio in the input voltage divider circuit by switching the resistance value of the fourth voltage divider resistor.

[0029] In one embodiment, the voltage supply circuit may further include a capacitor provided between the output node of the output voltage divider circuit and the input terminal of the PWM comparator, and a switch connected in parallel with the capacitor.

[0030] In one embodiment, the voltage supply circuit may supply a bias voltage as the initial voltage via the switch when the switch is on.

[0031] In one embodiment, the voltage supply circuit may be configured such that when the PWM comparator is in sleep mode, the voltage at the output terminal of the output voltage divider circuit is ground voltage and the switch is on, and when the PWM comparator switches from sleep mode to wake-up mode, the switch is turned off and the bias voltage generated by adjusting the voltage division ratio in the output voltage divider circuit is supplied as the initial voltage via capacitive coupling of a capacitor.

[0032] In one embodiment, the voltage supply circuit may further include a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator.

[0033] In one embodiment, the voltage supply circuit may further include a capacitor provided between the output terminal of the buffer circuit and the resistor circuit, or between the resistor circuit and the input terminal of the PWM comparator, and a switch connected in parallel with the capacitor.

[0034] In one embodiment, the resistance circuit may be composed of a variable resistor.

[0035] In one embodiment, the voltage supply circuit may further include a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator. The resistor circuit may include a first resistor path consisting of a first resistor and a second resistor connected in series, and a second resistor path consisting of a third resistor and a fourth resistor connected in series. The first resistor path may be connected in parallel with the second resistor path. The ratio of the combined resistance of the first and second voltage divider resistors to the combined resistance of the third and fourth voltage divider resistors may be the same as the ratio of the combined resistance of the first and second resistors to the combined resistance of the third and fourth resistors.

[0036] In one embodiment, the DC / DC converter may be of the step-up / step-down type. The controller circuit may further include a second PWM comparator, with the first PWM comparator being a PWM comparator. The first PWM comparator may compare the first lamp voltage with a comparison voltage, using the lamp voltage as the first lamp voltage. The second PWM comparator may compare the second lamp voltage, obtained by inverting the first lamp voltage, with a comparison voltage common to both the first and second PWM comparators. The voltage supply circuit may supply initial voltages for the comparison voltages to the first and second PWM comparators, respectively.

[0037] In one embodiment, the voltage supply circuit may include an input voltage divider circuit that divides the input voltage to generate an input comparison voltage and a first adjustment voltage, an output voltage divider circuit that divides the output voltage to generate an output comparison voltage and a second adjustment voltage, a comparator, and a voltage divider adjustment circuit that adjusts the voltage division ratio in each of the input voltage divider circuit and the output voltage divider circuit. The comparator may compare the input comparison voltage or the output comparison voltage with a common amplitude voltage of the first ramp voltage and the second ramp voltage. The voltage divider adjustment circuit may, based on the comparison result of the comparator, adjust the voltage division ratio in the input voltage divider circuit so that the first adjusted voltage approaches the amplitude voltage when the input voltage is greater than the output voltage, and adjust the voltage division ratio in the output voltage divider circuit so that the second adjusted voltage is the voltage obtained by dividing the output voltage by the voltage division ratio of the adjusted first adjusted voltage. If the output voltage is greater than the input voltage, adjust the voltage division ratio in the input voltage divider circuit so that the second adjusted voltage approaches the amplitude voltage, and adjust the voltage division ratio in the input voltage divider circuit so that the first adjusted voltage is the voltage obtained by dividing the input voltage by the voltage division ratio of the adjusted second adjusted voltage.

[0038] In one embodiment, the voltage supply circuit may be configured to supply an initial voltage obtained by adding half the amplitude voltage to the difference voltage obtained by subtracting the adjusted second adjusted voltage from the adjusted first adjusted voltage when the output voltage is greater than the input voltage.

[0039] A DC / DC converter according to one embodiment may include the above-described controller circuit.

[0040] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0041] In this specification, "member A is connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0042] Similarly, "member C is positioned (placed) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0043] In this specification, the symbols attached to electrical signals such as voltage signals and current signals, or to circuit elements such as resistors, capacitors, and inductors, shall represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, and inductance) as needed.

[0044] Furthermore, in this specification, "integrated" includes cases where all components of a circuit are formed on a semiconductor substrate, or where the main components of a circuit are integrated, and some resistors, capacitors, etc., may be provided outside the semiconductor substrate for adjusting circuit constants.

[0045] (First Embodiment) Figure 1 is a block diagram of the DC / DC converter 1 according to the first embodiment. The DC / DC converter 1 according to the first embodiment is a step-down type, and the input voltage V IN1 The output voltage V obtained by stepping down the voltage OUT1 It generates [something]. The DC / DC converter 1 includes a controller circuit 10 and peripheral circuits 15.

[0046] The controller circuit 10 is a circuit for controlling the operation of the DC / DC converter 1. The controller circuit 10 according to this embodiment includes a voltage supply circuit 20, a first error amplifier 100, a clamp circuit 102, a current sense amplifier 104, a second error amplifier 106, a PWM comparator 108, a logic circuit 110, a level shifter 112, a buffer circuit 114, a NOT gate 116, a voltage source 120, a sleep comparator 122, a high-side transistor MH1, a low-side transistor ML1, resistors R1 to R3, a capacitor C1, a feedback pin FB, an input pin VIN, a switching pin SW, and a ground pin GND.

[0047] The controller circuit 10 may be integrated into a single semiconductor chip. However, some of the components of the controller circuit 10 may be externally mounted to the semiconductor chip; for example, the high-side transistor MH1 and the low-side transistor ML1 may be externally mounted to the semiconductor chip.

[0048] The peripheral circuit 15 includes an inductor L2 and a capacitor C2. One end of the inductor L2 is connected to the switching pin SW, and the other end of the inductor L2 is connected to one end of the capacitor C2. One end of the capacitor C2 is connected to the feedback pin FB, and the other end of the capacitor C2 is grounded. The output voltage V is connected to one end of the capacitor C2. OUT9 This occurs. The input voltage V is connected to the input pin VIN. IN1 When the current is applied, the ground pin GND is grounded.

[0049] The controller circuit 10 according to this embodiment is configured to be switchable between a sleep mode and a wake-up mode. The sleep mode is a mode in which at least the PWM comparator 108 is in a sleep state. More specifically, the first error amplifier 100, the second error amplifier 106, and the PWM comparator 108 are each in a sleep state, and the high-side transistor MH1 and the low-side transistor ML1 are each turned off and stopped. The wake-up mode is a mode in which at least the PWM comparator 108 is in an operating state. More specifically, the first error amplifier 100, the second error amplifier 106, and the PWM comparator 108 are each in an operating state, and the high-side transistor MH1 and the low-side transistor ML1 are each switching.

[0050] Resistors R1 and R2 are connected in series and divide the output voltage V OUT1 . One end of resistor R1 is connected to the feedback pin FB, and the other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to ground. The feedback voltage V OUT1 generated by dividing the output voltage V FB1 is input to the inverting input terminal of the first error amplifier 100 and the inverting input terminal of the sleep comparator 122. Note that the feedback voltage V FB1 is expressed by the following equation. V FB1 =V OUT1 ×R2 / (R1 + R2)

[0051] The first error amplifier 100 may be composed of a transconductance amplifier. The first error amplifier 100 generates a first error current I REF1 corresponding to the difference between the reference voltage V FB1 input to the non-inverting input terminal and the feedback voltage V ERR1 input to the inverting input terminal. The clamp circuit 102 clamps the voltage at the output terminal of the first error amplifier 100.

[0052] One end of resistor R3 is connected to the output terminal of the first error amplifier 100, and the other end of resistor R3 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to ground. First error current I ERR1 Error voltage V that occurs depending on the situation ERR1 This is input to the non-inverting input terminal of the second error amplifier 106. The current sense amplifier 104 receives the output current I flowing through the inductor L1. L1 Detects the sense voltage V SNS1 Generates a sense voltage V. SNS1 This is input to the inverting input terminal of the second error amplifier 106.

[0053] The second error amplifier 106 controls the error voltage V ERR1 and sense voltage V SNS1 The second error current I corresponds to the difference between the two. ERR2 It generates the second error current I ERR2 The corresponding comparative voltage V C1 This is generated. More specifically, the second error current I is generated from the capacitor C3 of the voltage supply circuit 20, which will be described later. ERR2 The second error current I is sunk or transferred to capacitor C3. ERR2 As a result of this source, the comparison voltage V C1 This is generated.

[0054] The PWM comparator 108 receives a periodic ramp voltage V from the inverting input terminal. RAMP1 and the comparison voltage V input to the non-inverting input terminal C1 By comparing it with the PWM signal S PWM1 This generates the lamp voltage V according to this embodiment. RAMP1 The amplitude voltage is equal to the input voltage V IN1 It has a fixed size that is not dependent on anything.

[0055] The logic circuit 110 receives the PWM signal S PWM1 High-side signal S H1 and low-side control signal S L1 The level shifter 112 generates the high-side control signal S. H1 Shift the level of the high-side gate signal S GH1The NOT gate generates the low-side gate signal S. L1 Invert the signal to obtain the low-side gate signal S GL1 Generates.

[0056] The high-side transistor MH1 and the low-side transistor MN1 are each composed of MOS (Metal Oxide Semiconductor) transistors, and in this embodiment, both are N-channel type. The drain of the high-side transistor MH1 is connected to the input pin VIN, and the source of the high-side transistor MH1 is connected to the switching pin SW. The drain of the low-side transistor ML1 is connected to the switching pin SW, and the source of the low-side transistor ML1 is connected to the ground pin GND. The operation of the high-side transistor MH1 is controlled by the high-side gate signal S input via the buffer circuit 114. GH1 Controlled by the low-side transistor ML1, the operation of the low-side gate signal S GL1 It is controlled by [something].

[0057] The sleep comparator 122 may consist of, for example, a hysteresis comparator and a window comparator. The sleep comparator 122 receives a feedback voltage V input to the inverting input terminal. FB1 And the reference voltage V is input to the non-inverting input terminal. REF2 (>V REF1 ) Compared with the sleep signal S SLP1 Generates a reference voltage V. REF2 The reference voltage V REF2 This is the voltage obtained by adding the voltage generated by the voltage source 120 to the signal. Sleep signal S SLP1 The feedback voltage V under light load conditions is FB1 When it floats, it becomes a low level.

[0058] Sleep signal S SLP1 This is input to the voltage supply circuit 20, the first error amplifier 100, the second error amplifier 106, the PWM comparator 108, and the logic circuit 110, respectively. Sleep signal S SLP1When the signal S is at a high level, the controller circuit 10 enters sleep mode, and the sleep signal S SLP1 When the signal level is low, the controller circuit 10 enters wake-up mode.

[0059] The voltage supply circuit 20 provides a comparison voltage V to the PWM comparator 108. C1 This is a circuit that supplies the initial voltage. Here, the initial voltage is the comparison voltage V when the controller circuit 10 switches from sleep mode to wake-up mode. C1 This is the voltage given as the initial value. The initial voltage is the input voltage V IN1 and output voltage V OUT1 The ratio (V OUT1 / V IN1 This is the voltage corresponding to the voltage.

[0060] The voltage supply circuit 20 according to this embodiment includes a resistive voltage divider 22, a NOT gate 24, a switch SW1, and a capacitor C3. Capacitor C3 is provided between the output terminal of the resistive voltage divider 22 (specifically, the output node of the second voltage divider circuit described later) and the non-inverting input terminal of the PWM comparator 108. Switch SW1 is provided in parallel with capacitor C3. NOT gate 24 receives the sleep signal S SLP1 Accordingly, it controls the on / off state of switch SW1. Specifically, NOT gate 24 controls the sleep signal S SLP1 When the signal is high, switch SW1 is turned off, and the sleep signal S SLP1 When the level is low, switch SW1 is turned on.

[0061] The resistive voltage divider 22 controls the power supply voltage V dd , input voltage V IN1 Output voltage V OUT1 and clock signal S CLK Depending on the bias voltage V C_BIAS1 This generates the bias voltage V. In this embodiment, the bias voltage V C_BIAS1 In sleep mode, the comparison voltage V is sent to the non-inverting input terminal of the PWM comparator 108 via switch SW1. C1 It is supplied as the initial voltage.

[0062] Figure 2 is a block diagram of the resistive voltage divider unit 22 according to this embodiment. As shown in Figure 2, the resistive voltage divider unit 22 includes a power supply voltage divider circuit 220, an input voltage divider circuit 222, an output voltage divider circuit 224, a first comparator 226, a second comparator 228, and a voltage divider adjustment circuit 230.

[0063] The power supply voltage divider circuit 220 controls the power supply voltage V dd The voltage is divided, and the lamp voltage V RAMP1 A target voltage V with the same amplitude as the voltage. DIVA Generates the target voltage V. DIVA This is input to the non-inverting input terminal of the first comparator 226 and the non-inverting input terminal of the second comparator 228. The power supply voltage divider circuit 220 according to this embodiment has two voltage divider resistors R A1 ,R A2 Includes voltage divider resistor R A1 One end is the power supply voltage V dd It is connected to the applied terminal and the voltage divider resistor R A1 The other end is a voltage divider resistor R A2 It is connected to one end of the voltage divider resistor R. A2 The other end is connected to ground. Voltage divider resistor R A1 and voltage divider resistor R A2 Between these two points, the target voltage V is expressed by the following equation. DIVA This will occur. V DIVA =R A2 / (R A1 +R A2 )

[0064] The input voltage divider circuit 222 controls the input voltage V IN1 The voltage is divided, and the first comparison voltage V CMPB1 , second comparison voltage V CMPB2 and adjustment voltage V DIVB1 Generates the second comparison voltage V. CMPB2 The first comparison voltage V CMPB1 This is a lower voltage than the first comparison voltage V. CMPB1 This is input to the inverting input terminal of the first comparator 226, and the second comparison voltage V CMPB2 This is input to the inverting input terminal of the second comparator 228.

[0065] The input voltage divider circuit 222 according to this embodiment has a first voltage divider resistor R connected in series. B1 , second voltage divider resistor R B2 , third voltage divider resistor R B3 and the fourth voltage divider resistor R B4 Includes the first voltage divider resistor R B1 and the fourth voltage divider resistor R B4 These are variable resistors. The first voltage divider resistor R B1 The resistance value is the resistance signal S R1 Adjusted by the fourth voltage divider resistor R B4 The resistance value is the resistance signal S R2 It is adjusted by [the specified method].

[0066] First voltage divider resistor R B1 The second voltage divider resistor R B2 On the opposite end, the input voltage V IN1 It is connected to the applied terminal and the first voltage divider resistor R B1 The other end is the second voltage divider resistor R B2 It is connected to one end of the second voltage divider resistor R. B2 The other end is the third voltage divider resistor R B3 It is connected to one end of the fourth voltage divider resistor R. B4 The third voltage divider resistor R B3 The other end is connected to ground, and the fourth voltage divider resistor R B4 The other end is the third voltage divider resistor R B3 It is connected to the other end.

[0067] Second voltage divider resistor R B2 and the third voltage divider resistor R B3 This provides hysteresis to the counting operation in the voltage divider adjustment circuit 230, which will be described later. Second voltage divider resistor R B2 and the third voltage divider resistor R B3 By providing the second voltage divider resistor R B2 and the third voltage divider resistor R B3 If there is no (i.e., the first voltage divider resistor R) B1 and the fourth voltage divider resistor R B4 Compared to the case where the two are short-circuited, this makes it possible to reliably converge the process of adjusting the voltage division ratio in the input voltage divider circuit 222.

[0068] First comparison voltage V CMPB1 The first voltage divider resistor R is expressed by the following equation. B1 and the second voltage divider resistor R B2 This is the voltage generated between [the two points]. V CMPB1 =V IN1 ×(R B2 +R B3 +R B4 ) / (R B1 +R B2 +R B3 +R B4 )

[0069] Second comparison voltage V CMPB2 The third voltage divider resistor R is represented by the following equation. B3 and the fourth voltage divider resistor R B4 This is the voltage generated between [the two points]. V CMPB2 =V IN1 ×R B4 / (R B1 +R B2 +R B3 +R B4 )

[0070] Adjustment voltage V DIVB1 The second voltage divider resistor R is represented by the following equation. B2 and the third voltage divider resistor R B3 This is the voltage generated between [the two points]. V DIVB1 =V IN1 ×(R B3 +R B4 ) / (R B1 +R B2 +R B3 +R B4 ) Therefore, the first comparison voltage V CMPB1 , second comparison voltage V CMPB2 and adjustment voltage V DIVB1 The relationship between magnitudes is V CMPB2 <V DIVB1 <V CMPB1 This is the result.

[0071] The first comparator 226 controls the first comparison voltage V CMPB1 and lamp voltage V RAMP1The amplitude voltage is compared with the first comparison voltage V. The first comparator 226 in this embodiment compares the first comparison voltage V CMPB1 and target voltage V DIVA The results are compared, and a down signal S is given according to the comparison result (first comparison result). DN1 Generates a down signal S. DN1 The target voltage V DIVA The first comparison voltage V CMPB1 When it is greater than this, it becomes a high level, and the target voltage V DIVA The first comparison voltage V CMPB1 When it is smaller than this, it becomes a low level.

[0072] The second comparator 228 controls the second comparison voltage V CMPB2 and lamp voltage V RAMP1 The amplitude voltage is compared with the second comparison voltage V. The second comparator 228 in this embodiment compares the second comparison voltage V CMPB2 and target voltage V DIVA This is compared with the second comparison result, and the up signal S is determined according to the comparison result (second comparison result). UP1 Generates an up signal S. UP1 This is the second comparison voltage V CMPB2 Target voltage V DIVA When it is greater than this, it becomes a high level, and the second comparison voltage V CMPB2 Target voltage V DIVA When it is smaller than this, it becomes a low level.

[0073] The output voltage divider circuit 224 outputs V OUT1 The voltage is divided, and the bias voltage V C_BIAS1 This generates the output voltage divider circuit 224 according to this embodiment, which has a fifth voltage divider resistor R connected in series. B5 , 6th voltage divider resistor R B6 , the 7th voltage divider resistor R B7 and the 8th voltage divider resistor R B8 Includes the fifth voltage divider resistor R B5 and the 8th voltage divider resistor R B8 These are all variable resistors. The fifth voltage divider resistor R B5 The resistance value is the resistance signal S R3 Adjusted by the 8th voltage divider resistor R B8 The resistance value is the resistance signal S R4 It is adjusted by the sixth voltage divider resistor R. In this embodiment, the sixth voltage divider resistor RB6 This is the second voltage divider resistor R B2 It has the same resistance value as the 7th voltage divider resistor R B7 This is the third voltage divider resistor R B3 It has the same resistance value as [another product].

[0074] The fifth voltage divider resistor R according to this embodiment B5 , 6th voltage divider resistor R B6 , the 7th voltage divider resistor R B7 and the 8th voltage divider resistor R B8 This is the first voltage dividing resistor R B1 , second voltage divider resistor R B2 , third voltage divider resistor R B3 and the fourth voltage divider resistor R B4 It is connected in the same way as above. However, the fifth voltage divider resistor R B5 The sixth voltage divider resistor R B6 On the opposite end, the output voltage V OUT1 It is connected to the applied terminal of the bias voltage V. C_BIAS1 The sixth voltage divider resistor R is represented by the following equation. B6 and the 7th voltage divider resistor R B7 This is the voltage generated between (output node 225). V C_BIAS1 =V OUT1 ×(R B7 +R B8 ) / (R B5 +R B6 +R B7 +R B8 )

[0075] The voltage divider adjustment circuit 230 adjusts the voltage division ratio in the input voltage divider circuit 222 and the output voltage divider circuit 224, respectively. The voltage divider adjustment circuit 230 according to this embodiment receives the clock signal S CLK , down signal S DN1 and up signal S UP1 Resistance signal S R1 ~S R4 Generates the first voltage divider resistor R B1 , 4th voltage divider resistor R B4 , fifth voltage divider resistor R B5 and the 8th voltage divider resistor R B8 Adjust the resistance value of each component.

[0076] The voltage divider adjustment circuit 230 according to this embodiment receives a down signal S DN1 and up signal S UP1 Based on this, the adjustment voltage V DIVB1 The voltage division ratio in the input voltage divider circuit 222 is adjusted so that the voltage approaches the amplitude voltage. Specifically, the voltage divider adjustment circuit 230 uses the first voltage divider resistor R B1 and the fourth voltage divider resistor R B4 By adjusting the resistance values ​​of each component, the voltage division ratio in the input voltage divider circuit 222 is adjusted.

[0077] The voltage divider adjustment circuit 230 according to this embodiment receives a down signal S DN1 and up signal S UP1 Based on this, the voltage division ratio in the input voltage division circuit 222 is sequentially changed. The voltage division adjustment circuit 230 according to this embodiment includes a counter (not shown) and a down signal S DN1 and up signal S UP1 Depending on the level, for example, the clock signal S CLK Each time it starts up, it counts down or up.

[0078] The voltage divider adjustment circuit 230 according to this embodiment receives a down signal S DN1 If the level is high (Target voltage V DIVA The first comparison voltage V CMPB1 The down signal S is greater than DN1 (If indicated by) Clock S CLK Each time the voltage rises, it counts down. In this case, the voltage divider adjustment circuit 230 controls the first comparison voltage V CMPB1 and second comparison voltage V CMPB2 To increase the value. For example, the voltage divider adjustment circuit 230 uses a resistance signal S that indicates the count value. R1 ,S R2 Outputs the first voltage divider resistor R B1 Reduce the fourth voltage divider resistor R B4 You can enlarge it.

[0079] Conversely, the up signal S UP1 When the voltage is high (second comparison voltage V CMPB2 Target voltage V DIVA Up signal S is greater thanUP1 (As indicated by) the voltage divider adjustment circuit 230 according to this embodiment, clock S CLK The count increases each time the voltage rises. In this case, the voltage divider adjustment circuit 230 controls the first comparison voltage V CMPB1 and second comparison voltage V CMPB2 To reduce the value. For example, the voltage divider adjustment circuit 230 uses a resistance signal S that indicates the count value. R1 ,S R2 Outputs the first voltage divider resistor R B1 Increase the fourth voltage divider resistor R B4 You can make it smaller.

[0080] In this embodiment, the voltage divider adjustment circuit 230 receives a down signal S DN1 If the signal is at a high level, it counts down and the up signal S UP1 An example of upcounting when the signal S is high will be explained, but it is not limited to this. For example, the voltage divider adjustment circuit 230 receives a down signal S DN1 When the signal is at a high level, it counts up, and the up signal S UP1 If the signal is at a high level, it may be down-counted. In this way, the voltage divider adjustment circuit 230 controls the up signal S UP1 If the signal is at a high level, the down signal S DN1 The opposite count is performed compared to when the level is high.

[0081] The voltage divider adjustment circuit 230 according to this embodiment has a target voltage V DIVA The first comparison voltage V CMPB1 The down signal S is smaller than DN1 This indicates the second comparison voltage V CMPB2 Target voltage V DIVA Smaller than the up signal S UP1 When this is indicated, the adjustment of the voltage division ratio in the input voltage division circuit 222 is terminated. Specifically, the voltage division adjustment circuit 230 receives the down signal S DN1 and up signal S UP1 When both become low levels, the adjustment of the voltage division ratio in the input voltage divider circuit 222 is terminated.

[0082] The voltage divider adjustment circuit 230 adjusts the voltage division ratio in the input voltage divider circuit 222, and at the same time adjusts the first comparison voltage V in the input voltage divider circuit 222. CMPB1 The voltage division ratio and the second comparison voltage V CMPB2 Output voltage V OUT1 Dividing the voltage to obtain a bias voltage V C_BIAS1 The voltage division ratio in the output voltage divider circuit 224 is adjusted so that the following is generated. Specifically, the voltage divider adjustment circuit 230 adjusts the fifth voltage divider resistor R so that the following equation holds true. B5 and the 8th voltage divider resistor R B8 Adjust the resistance value of each component. R B4 / (R B1 +R B2 +R B3 +R B4 )<(R B7 +R B8 ) / (R B5 +R B6 +R B7 +R B8 )<(R B2 +R B3 +R B4 ) / (R B1 +R B2 +R B3 +R B4 )

[0083] The voltage divider adjustment circuit 230 according to this embodiment adjusts the adjusted voltage V based on the first comparison result of the first comparator 226 and the second comparison result of the second comparator 228. DIVB1 Output voltage V OUT1 Dividing the voltage to obtain a bias voltage V C_BIAS1 The voltage division ratio in the output voltage divider circuit 224 is adjusted so that the following is generated. Specifically, the voltage divider adjustment circuit 230 adjusts the fifth voltage divider resistor R so that the following equation holds true. B5 and the 8th voltage divider resistor R B8 Adjust the resistance value of each component. (R B3 +R B4 ) / (R B1 +R B2 +R B3 +R B4 )=(R B7 +R B8 ) / (RB5 +R B6 +R B7 +R B8 )

[0084] More specifically, the voltage divider adjustment circuit 230 has a fifth voltage divider resistor R B5 The resistance value of the first voltage divider resistor R B1 Match the resistance value of the 8th voltage divider resistor R B8 The resistance value of the fourth voltage divider resistor R B4 The voltage division ratio in the output voltage divider circuit 224 is adjusted by matching the resistance value. The voltage division adjustment circuit 230 receives the above down signal S DN1 and up signal S UP1 The voltage division ratio in the output voltage divider circuit may be adjusted based on the count result corresponding to the value.

[0085] Ideally, at the end of adjusting the voltage division ratio in the input voltage divider circuit 222, the adjusted voltage V DIB1 Target voltage V DIVA In this case, the bias voltage V C_BIAS1 Target voltage V DIVA ×V OUT1 / V IN1 The voltage division ratio in the output voltage divider circuit 224 is adjusted accordingly. Therefore, ideally, the bias voltage V C_BIAS1 is, k A =R A2 / (R A1 +R A2 It can be expressed as follows: V C_BIAS1 =(k A ×V dd ×V OUT1 ) / V IN1

[0086] Figure 3 is a timing chart showing an example of the operation of the controller circuit 10 according to this embodiment. 11 Prior to this, the controller circuit 10 is in sleep mode, and the sleep signal S SLP1 It is at a low level. In sleep mode, switch SW1 is on, and the resistor voltage divider 22 is at the bias voltage V C_BIAS1 This generates an ideal bias voltage V.C_BIAS1 It is assumed that the following is generated. Bias voltage V C_BIAS1 The comparison voltage V is sent to the non-inverting input terminal of the PWM comparator 108 via switch SW1. C1 Initial value V INIT1 It is supplied as such.

[0087] timing t 11 In this case, sleep signal S SLP1 The voltage switches to a high level, and the controller circuit 10 enters wake-up mode. Accordingly, switch SW1 is turned off, and the first error amplifier 100, the second error amplifier 106, and the PWM comparator 108 are each released from sleep mode and begin operation. Also, the high-side transistor MH1 and the low-side transistor ML1 each have a comparison voltage V C1 and lamp voltage V RAMP1 PWM signal S corresponding to the comparison result PWM1 It will start switching accordingly.

[0088] Note that in Figure 3, the comparison voltage V C1 and lamp voltage V RAMP1 The bottom is 0V, but the bottom can be a voltage greater than 0V. However, the magnitude of the bottom is the comparison voltage V C1 and lamp voltage V RAMP1 It is the same as this.

[0089] The PWM comparator 108 has a bias voltage V C_BIAS1 Comparing voltage V C1 Initial voltage V INIT1 PWM signal S PWM1 Generates at timing t. 11 Hereafter, the second error current S generated by the second error amplifier 106 ERR2 The comparison voltage V C1 The PWM signal S is adjusted. PWM1 Duty (T ON1 / T1) is modulated. Note that in Figure 3, the comparison voltage V C1 Minor fluctuations in this area have been omitted.

[0090] Figure 4 is a timing chart showing an example of the operation of the resistive voltage divider 22 according to this embodiment. 21 In this configuration, the resistive voltage divider 22 is set to a bias voltage V C_BIAS1 The process for generating the result shall begin. Timing t 21 In this configuration, the voltage division ratio in the input voltage divider circuit 222 is initialized to a predetermined voltage division ratio. The initial value of the count value CNT is preferably about half of the counter's maximum output value. For example, in the case of a 5-bit counter that counts from 0 to 31, the initial value of the count value CNT is preferably 16, as shown in Figure 4.

[0091] The differential voltage ΔV shown in Figure 4 B1 The first comparison voltage V CMPB1 and the second comparison voltage V CMPB2 The difference is expressed by the following equation. ΔV B1 =V CMPB1 -V CMPB2 =V IN1 ×(R B2 +R B3 ) / (R B1 +R B2 +R B3 +R B4 )

[0092] At the initial voltage division ratio, the first comparison voltage V CMPB1 and second comparison voltage V CMPB2 These are, respectively, the target voltage V DIVA It is larger than this. Therefore, the down signal S DN1 This is a low-level, up-signal S UP1 This becomes high level. Accordingly, timing t 22 In this case, the counter counts up, and the count value CNT increases from 16 to 17. Also, the first comparison voltage V CMPB1 Step voltage ΔV STEP1 The voltage drops by this amount, and the second comparison voltage V CMPB2 Step voltage ΔV STEP2 The voltage division ratio in the input voltage divider circuit 222 is changed so that the voltage decreases by that amount.

[0093] When the voltage division ratio in the input voltage divider circuit 222 is changed, the step voltage ΔV STEP1 ,V CMPB2 The magnitude is the differential voltage ΔV B1 It is preferable that it be smaller than this. This makes it possible to more reliably converge the voltage division ratio in the input voltage divider circuit 222 to an appropriate size.

[0094] The following is about timing t 23 ,t 24 In this case, the down signal S DN1 and up signal S UP1 Accordingly, the count value CNT is changed, and the count value CNT increases from 17 to 18, and from 18 to 19. Also, timing t 23 ,t 24 At this point, the voltage division ratio in the input voltage divider circuit 222 is changed. In this example of operation, timing t 24 In this case, the down signal S DN1 and up signal S UP1 Both become low levels. Accordingly, the adjustment of the voltage division ratio in the input voltage divider circuit 222 is completed. Also, based on this retained count result, the voltage division ratio in the output voltage divider circuit 224 is adjusted, and the bias voltage V C_BIAS1 This is generated.

[0095] The configuration and operation examples of the DC / DC converter 1 and its controller circuit 10 according to this embodiment have been described above. The controller circuit 10 according to this embodiment controls the periodic ramp voltage V RAMP1 Comparison voltage V C1 A PWM comparator 108 compares the two, and the PWM comparator 108 receives a comparison voltage V C1 Initial voltage V INIT1 It has a voltage supply circuit 20 that supplies the initial voltage V. INIT1 The input voltage V IN1 and output voltage V OUT1 The voltage is proportional to the ratio of [the two values].

[0096] According to this configuration, the initial voltage V INIT1 This results in a voltage of a size appropriate to the duty cycle, unlike the conventional technology described above, which uses a ramp voltage VRAMP1 The amplitude voltage of the input voltage V IN1 It is not necessary to make it proportional to the input voltage V. IN1 Even if the lamp voltage V becomes low, RAMP1 The amplitude voltage remains unchanged, while the comparison voltage V C3 The impact of fluctuations on the duty cycle is suppressed. As a result, the output voltage V when sleep mode is released is reduced. OUT1 The disruption is suppressed.

[0097] (Second Embodiment) Figure 5 is a block diagram of the DC / DC converter 2 according to the second embodiment. The DC / DC converter 2 receives an input voltage V IN1 Step down the voltage to produce output voltage V OUT2 This generates a DC / DC converter 2 according to this embodiment, which includes a controller circuit 30 and peripheral circuits 15. The controller circuit 30 according to this embodiment differs from the controller circuit 10 according to the first embodiment mainly in that it has an error amplifier circuit 32 instead of a second error amplifier 106, and the configuration of the voltage supply circuit 40 differs from that of the voltage supply circuit 20 according to the first embodiment.

[0098] The error amplifier circuit 32 includes a second error amplifier 320, a third error amplifier 322, and a capacitor C4. The second error amplifier 320 and the third error amplifier 322 each receive the sleep signal S SLP1 When the sleep signal S is low, the system enters sleep mode. SLP1 The system operates when the level is low.

[0099] The second error amplifier 320 receives the sense voltage V at the inverting input terminal. SNS1 and the error voltage V input to the non-inverting input terminal ERR1 Third error current I corresponding to the difference ERR3 This generates the following. One end of capacitor C4 is connected to the output terminal of the second error amplifier 320, and the other end of capacitor C4 is connected to the bias voltage V BIAS1 It is connected to the applied terminal. Third error current I ERR3The sense voltage V is sunk to one end of capacitor C4, either as a source or from one end of capacitor C4. SNS1 and error voltage V ERR1 The difference is integrated, and an error voltage V is applied to one end of capacitor C4. ERR2 This is generated.

[0100] The third error amplifier 322 consists of a transconductance amplifier having two inverting input terminals and two non-inverting input terminals. The third error amplifier 322 receives a sense voltage V at the first inverting input terminal. SNS1 The following is input, and a bias voltage V is applied to the second inverting input terminal. BIAS1 When this is input, an error voltage V is input to the first non-inverting input terminal. ERR1 The following is input, and an error voltage V is input to the second non-inverting input terminal. ERR2 It is set up so that this can be input.

[0101] The third error amplifier 322 calculates the difference between the voltages input to the two inverting input terminals and the voltages input to the two non-inverting input terminals, i.e., (V ERR1 +V ERR2 )-(V SNS1 +V BIAS1 ) corresponds to the fourth error current I ERR4 It generates the fourth error current I. ERR4 The corresponding comparative voltage V C2 This is generated. More specifically, the fourth error current I is generated at resistor R4 of the voltage supply circuit 40, which will be described later. ERR4 The comparison voltage V is caused by the flow of this current. C2 This is generated.

[0102] The voltage supply circuit 40 according to the second embodiment includes a resistive voltage divider 22, a buffer circuit 42, and a resistor circuit 44.

[0103] The buffer circuit 42 receives the bias voltage V generated by the resistive voltage divider 22 (specifically, the output voltage divider circuit 224). C_BIAS2It is provided to buffer the voltage. The buffer circuit 42 according to this embodiment includes an operational amplifier 420 that constitutes a voltage follower. The inverting input terminal of the operational amplifier 420 is connected to the output terminal of the operational amplifier 420, and the non-inverting input terminal of the operational amplifier 420 is connected to the output terminal of the resistive voltage divider 22 (specifically, the output node 225 of the output voltage divider circuit 224).

[0104] The resistor circuit 44 is provided between the output terminal of the buffer circuit 42 and the non-inverting input terminal of the PWM comparator 108. In this embodiment, the resistor circuit 44 consists of one resistor R4. The resistor R4 is a variable resistor, one end of which is connected to the output terminal of the operational amplifier 420, and the other end of which is connected to the non-inverting input terminal of the PWM comparator 108.

[0105] When the controller circuit 30 is in sleep mode, the first error amplifier 100, the second error amplifier 320, the third error amplifier 322, and the PWM comparator 108 each enter a sleep state. At this time, capacitor C4 is short-circuited using a switch (not shown), and the output terminal of the second error amplifier 320 is discharged. Also, the bias voltage V generated by the resistive voltage divider 22 C_BIAS2 The bias voltage V is supplied to the non-inverting input terminal of the PWM comparator 108 via the buffer circuit 42 and resistor R4. C2 It is supplied as the initial voltage.

[0106] When the controller circuit 30 switches from sleep mode to wake-up mode, the sleep states of the first error amplifier 100, the second error amplifier 320, the third error amplifier 322, and the PWM comparator 108 are all released. At this time, the error voltage V ERR1 and sense voltage V SNS1 If there is no difference, then the bias voltage V C2 is V C_BIAS2 This is maintained. As a result, the high-side transistor MH1 and the low-side transistor ML1 are, respectively, controlled by the input voltage V IN1 and output voltage V OUT2 Switching is performed with the appropriate duty cycle.

[0107] The configuration of the DC / DC converter 2 and its controller circuit 30 according to the second embodiment has been described above.

[0108] In the first embodiment, the resistor voltage divider 22 acts as a phase compensation resistor from the perspective of the second error amplifier 106, and its combined resistance is an important parameter in terms of the characteristics of the DC / DC1 converter. However, since the combined resistance of the resistor voltage divider 22 fluctuates, it may sometimes be of an inappropriate magnitude.

[0109] In the voltage supply circuit 40 according to the second embodiment, a buffer circuit 42 is provided, and the current capability at the output terminal of the operational amplifier 420 is high, allowing any current to be sinked or sourced. The phase compensation resistor as seen from the third error amplifier 322 does not include a resistor voltage divider 22, and mainly consists of resistor R4. Therefore, by adjusting the resistance value of resistor R4 to an appropriate value, an appropriate phase compensation resistor can be realized regardless of the change in the combined resistance of the resistor voltage divider 22.

[0110] Furthermore, in the prior art described in Patent Document 1 above, the resistor R 93 Although the resistance value is fixed, the lamp voltage V RAMP9 The amplitude voltage is the input voltage V IN9 It is proportional to the input voltage V. IN9 As it increases, the comparison voltage V C9 Changes in duty cycles in response to changes in [the variable] are suppressed.

[0111] Compared to the conventional technology, the lamp voltage V according to the second embodiment RAMP1 The amplitude of the voltage is fixed. Therefore, the resistance value of resistor R4 is set to the input voltage V IN1 (or the voltage division ratio in the resistive voltage divider 22) is adjusted accordingly. Specifically, the input voltage V IN1 As the input voltage V increases, the resistance value of resistor R4 is decreased, and more specifically, the resistance value of resistor R4 is decreased as the input voltage V increases. IN1 By making it inversely proportional, it becomes possible to obtain a gain equivalent to that of the conventional technology described above.

[0112] (Third embodiment) Figure 6 is a block diagram of the voltage supply circuit 50 according to the third embodiment. The voltage supply circuit 50 according to the third embodiment may be provided in the controller circuit 10 instead of the voltage supply circuit 20 according to the first embodiment.

[0113] The voltage supply circuit 50 according to the third embodiment includes a resistive voltage divider 52, a buffer circuit 42, a resistor circuit 54, a NOT gate 56, a switch SW2, and a capacitor C5.

[0114] Capacitor C5 is placed between the output terminal of the buffer circuit 42 and the resistor circuit 54. Specifically, one end of capacitor C5 is connected to the output terminal of the operational amplifier 420, and the other end of capacitor C5 is connected to the resistor circuit 54. In wake-up mode, capacitor C5 is connected to the error voltage V ERR1 and sense voltage V SNS1 It works to integrate the difference between the two. Capacitor C5 may be placed between the resistor circuit 54 and the non-inverting input terminal of the PWM comparator 108.

[0115] Switch SW2 is connected in parallel with capacitor C5. The on / off state of switch SW2 is controlled by NOT gate 56. For example, sleep signal S SLP1 When the signal is high, switch SW2 turns off, and the sleep signal S SLP1 When the signal level is low, switch SW2 turns on.

[0116] The resistor circuit 54 is provided between the other end of the capacitor C5 and the non-inverting input terminal of the PWM comparator 108. The resistor circuit 54 according to this embodiment includes multiple resistors and is configured so that its combined resistance can be adjusted. The combined resistance of the resistor circuit 54 is determined by the resistance signal S from the resistor voltage divider 52. R5 It is adjusted by [this]. Also, in wake-up mode, the resistor circuit 54 receives a second error current I ERR2 The second error current I flows. ERR2 A comparison voltage is generated for the PWM comparator 108 accordingly.

[0117] Figure 7 is a block diagram of the resistive voltage divider 52 according to the third embodiment. The resistive voltage divider 52 according to this embodiment includes a power supply voltage divider circuit 220, an input voltage divider circuit 522, an output voltage divider circuit 524, a first comparator 526, a second comparator 528, and a voltage divider adjustment circuit 530.

[0118] The input voltage divider circuit 522 controls the input voltage V IN1 The voltage is divided, and the first comparison voltage V CMPB11 , second comparison voltage V CMPB12 and adjustment voltage V DIBV2 The input voltage divider circuit 522 has a first voltage divider resistor R B11 , second voltage divider resistor R B12 , third voltage divider resistor R B13 and the fourth voltage divider resistor R B14 Includes the first voltage divider resistor R B11 , second voltage divider resistor R B12 , third voltage divider resistor R B13 and the fourth voltage divider resistor R B14 This is the first voltage dividing resistor R according to the first embodiment. B1 , second voltage divider resistor R B2 , third voltage divider resistor R B3 and the fourth voltage divider resistor R B4 It is connected in the same way. In this embodiment, the first voltage divider resistor R B11 This is not a variable resistor, but a fourth voltage divider resistor R B14 Only this is a variable resistor. The fourth voltage divider resistor R B14 The resistance value is the resistance signal S R6 It is adjusted by [the specified method].

[0119] The output voltage divider circuit 524 outputs V OUT3 The voltage is divided, and the bias voltage V C_BIAS3 It generates the following. The output voltage divider circuit 524 has a fifth voltage divider resistor R B15 , 6th voltage divider resistor R B16 , the 7th voltage divider resistor R B17 and the 8th voltage divider resistor R B18 Includes the fifth voltage divider resistor R B15 , 6th voltage divider resistor R B16 , the 7th voltage divider resistor R B17 and the 8th voltage divider resistor R B18 This is the fifth voltage dividing resistor R according to the first embodiment.B5 , 6th voltage divider resistor R B6 , the 7th voltage divider resistor R B7 and the 8th voltage divider resistor R B8 It is connected in the same way. In this embodiment, the fifth voltage divider resistor R B15 This is not a variable resistor, but rather the 8th voltage divider resistor R B18 Only this is a variable resistor. The 8th voltage divider resistor R B18 The resistance value is the resistance signal S R7 It is adjusted by [the specified method].

[0120] The first comparator 526 controls the first comparison voltage V CMPB11 and target voltage V DIVA Compared with the down signal S DN2 The second comparator 528 generates the second comparison voltage V CMPB12 and target voltage V DIVA Compared with the up signal S UP2 Generates.

[0121] The voltage divider adjustment circuit 530 has a fourth voltage divider resistor R B14 By switching the resistance value of the 8th voltage divider resistor R, the voltage division ratio in the input voltage divider circuit 522 is adjusted, and the 8th voltage divider resistor R B18 The voltage division ratio in the output voltage divider circuit 524 is adjusted by switching the resistance value. The voltage division adjustment circuit 530 according to this embodiment receives a down signal S DN2 and up signal S UP2 Based on this, the voltage division ratios in the input voltage divider circuit 522 and the output voltage divider circuit 524 are adjusted. The method by which the voltage division adjustment circuit 530 adjusts the voltage division ratio is as follows: first voltage divider resistor R B11 and fifth voltage divider resistor R B15 Except for not adjusting the individual resistance values, this method is the same as the method used by the voltage divider adjustment circuit 230 in the first embodiment to adjust the voltage divider ratio.

[0122] Figure 8 is a circuit diagram of the resistor circuit 54 according to the third embodiment. The resistor circuit 54 according to this embodiment includes a first resistor path 540 and a second resistor path 542.

[0123] The first resistor path 540 is connected in series with the first resistor R C1 and the second resistor RC2 It consists of the following: The second resistor path 542 is connected in series with the third resistor R C3 and the fourth resistor R C4 It is composed of the following. The first resistor path 540 is connected in parallel with the second resistor path 542. The first resistor R C1 The second resistor R C2 The opposite end and the fourth resistor R C4 The third resistor R C3 The other end is connected to the first node 544, which is connected to capacitor C4. The second resistor R C2 The first resistor R C1 The opposite end and the third resistor R C3 The fourth resistor R C4 The other end is connected to a second node 546, which is connected to the non-inverting input terminal of the PWM comparator 108.

[0124] The equivalent resistance R of resistor circuit 54 C It can be expressed by the following formula. R C =(R C1 +R C2 )×(R C3 +R C4 ) / (R C1 +R C2 +R C3 +R C4 )

[0125] 4th resistor R C4 This is a variable resistor. In this embodiment, the fourth resistor R C4 The resistance value is adjusted after the voltage division ratio in the resistance voltage divider section 52 is adjusted. Specifically, the fourth resistor R C4 The resistance value is the first voltage divider resistor R B11 and the second voltage divider resistor R B12 The combined resistance and the third voltage divider resistor R B13 and the fourth voltage divider resistor R B14 The ratio of the equivalent resistances is the first resistor R C1 and the second resistor R C2 The combined resistance and the third resistor R C3 and the fourth resistor R C4 It is adjusted so that the ratio of the equivalent resistances is the same. That is, the fourth resistor R is adjusted so that the following equation holds true.C4 The resistance value is adjusted. (R B11 +R B12 ) / (R B13 +R B14 )=(R C1 +R C2 ) / (R C3 +R C4 )

[0126] Adjusted voltage V in input voltage divider circuit 522 DIVB2 The partial pressure ratio is k B2 (=(R B13 +R B14 ) / (R B11 +R B12 +R B13 +R B14 When )) the adjustment voltage V DIVB2 V DIVB2 =k B2 ×V IN1 It is represented by [formula]. Ideally, the adjustment voltage V DIVB2 Target voltage V DIVA The voltage division ratio in the input voltage divider circuit 522 is adjusted to match this. In this case, k B2 It can be expressed by the following formula. k B2 =k A ×V dd / V IN1

[0127] In this embodiment, the lamp voltage V RAMP1 Since the amplitude voltage is fixed, the equivalent resistance R C The input voltage V IN1 It should be inversely proportional to R. C / k B2 It is sufficient for R to remain constant. C1 =m×R B11 (where m is a positive number.) C / k B2 =m × (R C1 +R C2 ) holds true. Therefore, R C / k B2 The input voltage V IN1 and output voltage V OUT3 It remains constant and is optimized, independent of R.C2 =m×R B12 , R C3 =m×R B13 and R C4 =m×R B14 That is also true.

[0128] In the first embodiment, the input voltage V of the input voltage divider circuit 222 IN1 The first voltage divider resistor R closest to the applied voltage terminal B1 The resistance value and the output voltage V of the output voltage divider circuit 224 OUT1 The fifth voltage divider resistor R closest to the applied voltage terminal. B5 An example of adjusting the resistance value was explained. In this case, the input voltage V IN1 and output voltage V OUT1 When the voltage becomes relatively large, the first voltage divider resistor R B1 and fifth voltage divider resistor R B5 A complex circuit (for example, a circuit including a level shifter) may be required to switch between the respective resistance values.

[0129] In contrast, in the resistor voltage divider 52 according to the third embodiment, the fourth voltage divider resistor R is closest to the ground of the input voltage divider circuit 222. B14 The resistance value of the 8th voltage divider resistor R, which is closest to the ground of the output voltage divider circuit 524. B18 The resistance values ​​are adjusted. This makes it possible to adjust the voltage division ratio in both the input voltage divider circuit 222 and the output voltage divider circuit 524 with a simple configuration, without requiring complex circuits. This also contributes to reducing the area of ​​the semiconductor chip. Note that the change in the voltage division ratio in the input voltage divider circuit 222 and the output voltage divider circuit 524 is nonlinear with respect to the number of counts.

[0130] (Fourth Embodiment) Figure 9 is a block diagram of the DC / DC converter 4 according to the fourth embodiment. The DC / DC converter 4 according to this embodiment is a step-up / step-down type. The DC / DC converter 4 takes an input voltage V IN1 Step down or step up the voltage to obtain the output voltage V OUT4 This generates the DC / DC converter 4 according to this embodiment, which includes a controller circuit 60 and peripheral circuits 65.

[0131] The controller circuit 60 includes a voltage supply circuit 70, a first error amplifier 100, a clamp circuit 102, a current sense amplifier 104, a second error amplifier 106, a voltage source 120, a sleep comparator 122, a first PWM comparator 600, a second PWM comparator 602, a NAND gate 604, an OR gate 606, a logic circuit 608, level shifters 610, 620, buffer circuits 612, 614, 618, 620, a feedback pin FB, a first gate pin G1, a second gate pin G2, a third gate pin G3, a fourth gate pin G4, resistors R1, R2, and a capacitor C1.

[0132] The peripheral circuit 65 includes a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MN4, an inductor L2, and a capacitor C6. In this embodiment, the first transistor MN1, the second transistor MN2, the third transistor MN3, and the fourth transistor MN4 are each composed of N-channel type MOS transistors.

[0133] The drain of the first transistor MN1 is connected to the input voltage V IN1 The source of the first transistor MN1 is connected to the drain of the second transistor MN2, and the gate of the first transistor MN1 is connected to the first gate pin G1. The source of the second transistor MN2 is grounded, and the gate of the second transistor MN2 is connected to the second gate pin G2.

[0134] The drain of the third transistor MN3 is connected to the feedback pin FB, and the source of the third transistor MN3 is connected to the drain of the fourth transistor MN4. The gate of the third transistor MN3 is connected to the third gate pin G3. The source of the fourth transistor MN4 is grounded, and the gate of the fourth transistor MN4 is connected to the fourth gate pin G4.

[0135] One end of inductor L2 is connected between the first transistor MN1 and the second transistor MN2, and the other end of inductor L2 is connected between the third transistor MN3 and the fourth transistor MN4. One end of capacitor C6 is connected to the feedback pin FB, and the other end of capacitor C6 is grounded. The output voltage V is connected to one end of capacitor C6. OUT4 This will occur.

[0136] The controller circuit 60 according to this embodiment is configured to be switchable between sleep mode and wake-up mode. In sleep mode, the first error amplifier 100, the second error amplifier 106, the first PWM comparator 600, and the second PWM comparator 602 are all in a sleep state. Also in sleep mode, the first transistor MN1, the second transistor MN2, the third transistor MN3, and the fourth transistor MN4 are all off and stopped. In wake-up mode, the first error amplifier 100, the second error amplifier 106, the first PWM comparator 600, and the second PWM comparator 602 are all in an operating state. Also in wake-up mode, the first transistor MN1, the second transistor MN2, the third transistor MN3, and the fourth transistor MN4 can each be switched.

[0137] In this embodiment, the current sense amplifier 104 controls the current I flowing through the inductor L2. L2 Detects the sense voltage V SNS2 The second error amplifier 106 generates the error voltage V ERR1 and sense voltage V SNS2 The second error current I corresponds to the difference between the two. ERR2 It generates the second error current I ERR2 This current flows through resistor R5 of the voltage supply circuit 70, which will be described later, resulting in the comparison voltage V C3 This is generated. Basically, the comparison voltage V C3 The larger the value, the greater the duty cycle, and the controller circuit 60 seamlessly switches from buck mode to boost mode.

[0138] The first PWM comparator 600 receives a periodic first ramp voltage V input to the non-inverting input terminal. RAMP11 The comparison voltage V is then input to the inverting input terminal. C3 By comparing it with the first comparison signal S, CMP11 The second PWM comparator 602 generates the periodic second ramp voltage V input to the non-inverting input terminal. RAMP12 The comparison voltage V is then input to the inverting input terminal. C3 By comparing it with the second comparison signal S, CMP12 Generates the second lamp voltage V RAMP12 The first lamp voltage V RAMP11 This is the inverted voltage, and more specifically, the first ramp voltage V RAMP11 The first ramp voltage V is centered around half the amplitude voltage. RAMP11 This is the inverted voltage.

[0139] The NAND gate 604 receives the first comparison signal S CMP11 and the second comparison signal S CMP12 The first PWM signal S is obtained by inverting the logical AND of the two signals. PWM11 The OR gate 606 generates the first comparison signal S. CMP11 and the second comparison signal S CMP12 The second PWM signal S represents the logical OR of the two signals. PWM12 The logic circuit 608 generates the first PWM signal S PWM11 and the second PWM signal S PWM12 Based on this, control signal S G11 ,S G31 , second gate signal S G2 and the fourth gate signal S G4 Generates.

[0140] The level shifter 610 controls the control signal S G11 Shift the level of the first gate signal S G12 Generates the first gate signal S. G12 This is input to the gate of the first transistor MN1 via the buffer circuit 612 and the first gate pin G1. The second gate signal S G2 This signal is input to the gate of the second transistor MN2 via the buffer circuit 614 and the second gate pin G2. The level shifter 616 receives the control signal SG31 Shift the level of the third gate signal S G32 Generates the third gate signal S. G32 This is input to the gate of the third transistor MN3 via the buffer circuit 618 and the third gate pin G3. The fourth gate signal S G4 This is input to the gate of the fourth transistor MN4 via the buffer circuit 620 and the fourth gate pin G4.

[0141] The voltage supply circuit 70 supplies a comparison voltage V to the first PWM comparator 600 and the second PWM comparator 602, respectively. C3 It supplies the initial voltage. The voltage supply circuit 70 according to this embodiment includes a resistive voltage divider 72, a buffer circuit 74, a resistor circuit 76, a NOT gate 78, and a capacitor C5.

[0142] The resistive voltage divider 72 controls the power supply voltage V dd , input voltage V IN1 Output voltage V OUT4 and clock S CLK Based on this, the bias voltage V C_BIAS4 Generates a bias voltage V. C_BIAS4 In sleep mode, the comparison voltage V is transmitted via switch SW3 and resistor R5. C3 This is supplied as the initial voltage to the first PWM comparator 600 and the second PWM comparator 602, respectively. The detailed configuration of the resistive voltage divider 72 will be described later with reference to Figure 10.

[0143] The buffer circuit 74, NOT gate 78, switch SW3, and capacitor C5 may be connected in the same way as the buffer circuit 42, NOT gate 56, switch SW2, and capacitor C4 of the voltage supply circuit 50 according to the third embodiment. The resistor circuit 76 according to this embodiment consists of a single resistor R5 and is provided between the end of the capacitor C5 opposite to the buffer circuit 74 and the output terminal of the second error amplifier 106. The resistor R5 according to this embodiment is a variable resistor.

[0144] Figure 10 is a block diagram of the resistor voltage divider 72 according to the fourth embodiment. The resistor voltage divider 72 according to this embodiment includes a power supply voltage divider circuit 220, an input voltage divider circuit 722, an output voltage divider circuit 724, a first comparator 726, a second comparator 728, a voltage divider adjustment circuit 730, a switch comparator 732, a first operational amplifier 734, a second operational amplifier 736, a third operational amplifier 738, a switch SW4, and resistors R6 and R7.

[0145] The input voltage divider circuit 722 controls the input voltage V IN1 The voltage is divided, and the first comparison voltage V CMPB21 , second comparison voltage V CMPB22 and the first adjustment voltage V DIVB31 Generates the first comparison voltage V. CMPB21 and second comparison voltage V CMPB22 These are the input comparison voltages, respectively. The input voltage divider circuit 722 has a first voltage divider resistor R connected in series. B21 , second voltage divider resistor R B22 , third voltage divider resistor R B23 and the fourth voltage divider resistor R B24 Includes the first voltage divider resistor R B21 , second voltage divider resistor R B22 , third voltage divider resistor R B23 and the fourth voltage divider resistor R B24 This is the first voltage dividing resistor R according to the first embodiment. B1 , second voltage divider resistor R B2 , third voltage divider resistor R B3 and the fourth voltage divider resistor R B4 It is connected in the same way as the fourth voltage divider resistor R. B24 This is a variable resistor, and its resistance value is the resistance signal S. R8 It is adjusted by [the specified method].

[0146] The output voltage divider circuit 724 outputs V OUT4 The voltage is divided, and the third comparison voltage V CMPB23 , 4th comparison voltage V CMPB24 and the second adjustment voltage V DIVB32 Generates the third comparison voltage V. CMPB23 and the fourth comparison voltage V CMPB24 These are the output comparison voltages, respectively. The output voltage divider circuit 724 has a fifth voltage divider resistor R connected in series. B25 , 6th voltage divider resistor RB26 , the 7th voltage divider resistor R B27 and the 8th voltage divider resistor R B28 Includes the fifth voltage divider resistor R B25 , 6th voltage divider resistor R B26 , the 7th voltage divider resistor R B27 and the 8th voltage divider resistor R B28 This is the fifth voltage dividing resistor R according to the first embodiment. B5 , 6th voltage divider resistor R B6 , the 7th voltage divider resistor R B7 and the 8th voltage divider resistor R B8 It connects in the same way.

[0147] Fifth voltage divider resistor R B25 The resistance value is the first voltage divider resistor R B21 Its resistance value is the same as that of the sixth voltage divider resistor R B26 The resistance value is the second voltage divider resistor R B22 Its resistance value is the same as that of the 7th voltage divider resistor R B27 The resistance value is that of the third voltage divider resistor R B23 It has the same resistance value as the 8th voltage divider resistor R. B28 This is a variable resistor, and its resistance value is the fourth voltage divider resistor R B24 The resistance signal S should be set to have the same resistance value as the other resistance signal. R8 It is adjusted by [the specified method].

[0148] Target voltage V according to this embodiment DIVA The first lamp voltage V RAMP11 and the second lamp voltage V RAMP12 It has the same magnitude as the common amplitude voltage. Target voltage V DIVA This is input to the non-inverting input terminal of the first comparator 726 and the inverting input terminal of the second comparator 728. First regulating voltage V DIVB31 This is the second voltage divider resistor R B22 and the third voltage divider resistor R B23 This occurs between and the second adjustment voltage V DIVB32 This is the sixth voltage divider resistor R B26 and the 7th voltage divider resistor R B27 It occurs between these two points.

[0149] First comparison voltage V CMPB21 This is the first voltage dividing resistor R B21 and the second voltage divider resistor R B22It occurs between and and is input to the first inverting input terminal of the first comparator 726. Second comparison voltage V CMPB22 This is the third voltage divider resistor R B23 and the fourth voltage divider resistor R B24 It occurs between and and is input to the first non-inverting input terminal of the second comparator 728. Third comparison voltage V CMPB23 This is the fifth voltage divider resistor R B25 and the sixth voltage divider resistor R B26 This occurs between and and is input to the second inverting input terminal of the first comparator 726. The fourth comparison voltage V CMPB24 This is the 7th voltage divider resistor R B27 and the 8th voltage divider resistor R B28 This occurs between the two points and is input to the second non-inverting input terminal of the second comparator 728.

[0150] The first comparator 726 has a first comparison voltage V CMPB21 and the third comparison voltage V CMPB23 The larger of the two voltages and the target voltage V DIVA Compared with the down signal S DN2 The second comparator 728 generates the second comparison voltage V CMPB22 and the fourth comparison voltage V CMPB24 The larger of the two voltages and the target voltage V DIVA Compared with the up signal S UP2 Generates.

[0151] The voltage divider adjustment circuit 730 adjusts the voltage division ratio in the input voltage divider circuit 722 and the output voltage divider circuit 724, respectively.

[0152] The voltage divider adjustment circuit 730 according to this embodiment uses an input voltage V IN1 Output voltage V OUT4 If it is greater than (i.e., in step-down mode), the first adjustment voltage V is calculated based on the comparison results of the first comparator 726 and the second comparator 728, respectively. DIVB31 The amplitude voltage (target voltage V DIVA The voltage division ratio in the input voltage divider circuit 722 is adjusted to approach the specified value. Specifically, the voltage divider adjustment circuit 730 adjusts the down signal S DN2 and up signal S UP2Based on this, the voltage division ratio in the input voltage divider circuit 722 can be adjusted in the same way as in the voltage divider adjustment circuit 530 according to the third embodiment.

[0153] The voltage divider adjustment circuit 730 controls the output voltage V OUT4 The input voltage V IN1 If it is greater than (i.e., in boost mode), the second adjustment voltage V is calculated based on the comparison results of the first comparator 726 and the second comparator 728, respectively. DIVB32 The amplitude voltage (target voltage V DIVA The voltage division ratio in the output voltage divider circuit 724 is adjusted to approach the target value. The method for adjusting the voltage division ratio in the output voltage divider circuit 724 is the same as the method for adjusting the voltage division ratio in the input voltage divider circuit 722.

[0154] The voltage divider adjustment circuit 730 controls the input voltage V IN1 Output voltage V OUT4 If it is greater than, the second adjustment voltage V DIVB32 The first adjusted voltage V after adjustment DIVB31 Output voltage V OUT4 The voltage division ratio in the output voltage divider circuit 724 is adjusted so that the voltage obtained by dividing R is obtained. In this embodiment, the voltage division adjustment circuit 730 is R B24 =R B28 The 8th voltage divider resistor R is such that this occurs. B28 Adjust the resistance value. This will satisfy the following equation. Note that in the following equation, the left side is the first adjustment voltage V. DIVB31 This is the voltage division ratio, and the right-hand side is the second regulating voltage V. DIVB32 This is the partial pressure ratio. (R B23 +R B24 ) / (R B21 +R B22 +R B23 +R B24 )=(R B27 +R B28 ) / (R B25 +R B26 +R B27 +R B28 )

[0155] The voltage divider adjustment circuit 730 controls the output voltage V OUT4 The input voltage V IN1If it is greater than, the first regulating voltage V DIVB31 The second adjusted voltage V after adjustment DIVB32 Input voltage V with voltage division ratio OUT1 The voltage division ratio in the input voltage divider circuit 722 is adjusted so that the voltage obtained by dividing R is obtained. Specifically, the voltage divider adjustment circuit 730 is R B24 =R B28 The fourth voltage divider resistor R is set to such a configuration. B24 Adjust the resistance value.

[0156] The first operational amplifier 734 and the second operational amplifier 736 are each configured to form a voltage follower. The first operational amplifier 734 controls the second adjustment voltage V DIVB32 Buffering the first bias voltage V C_BIAS41 (=V DIVB32 ) outputs. First bias voltage V C_BIAS41 This is input to the non-inverting input terminal of the third operational amplifier 738. The second operational amplifier 736 receives the first adjustment voltage V DIVB31 Buffer the first voltage V1 (=V DIVB31 Outputs ).

[0157] Resistor R6 is placed between the output terminal of the second operational amplifier 736 and the inverting input terminal of the third operational amplifier 738. Resistor R7 has the same resistance value as resistor R6 (R6=R7) and is placed between the inverting input terminal of the third operational amplifier 738 and the output terminal of the third operational amplifier 738. The third operational amplifier 738 functions as an inverting amplifier with a gain of -1, and the second bias voltage V C_BIAS42 Outputs.

[0158] In boost mode, the second bias voltage V C_BIAS42 This is the first adjusted voltage V after adjustment. DIV31 The second adjusted voltage V after adjustment DIV32 Subtracting the difference voltage, the lamp voltage (first lamp voltage V) is used. RAMP11 and the second lamp voltage V RAMP12 This voltage is the sum of voltages that are half the amplitude voltage of ). Specifically, the second bias voltage V C_BIAS42 This can be expressed by the following equation (2). V C_BIAS42 =k A / 2×V dd +{k A ×V dd × (V OUT4 -V IN1 )} / (2×V OUT4 )···(2)

[0159] Switch comparator 732 is used when the input voltage V IN1 and output voltage V OUT4 Switch signals S according to the relative magnitudes SW1 Generates a switch signal S. SW1 The second adjustment voltage V DIV32 The first adjustment voltage V DIV31 If it is greater than this, it becomes a high level, and the first regulating voltage V DIV31 The second adjustment voltage V DIV32 If it is greater than this, it may be considered a low level.

[0160] Switch SW4 connects the output terminal 740 of the resistor voltage divider 72 to either the output terminal of the first operational amplifier 734 or the output terminal of the third operational amplifier 738. Switch SW4 receives a switch signal S SW1 When the voltage is low (in step-down mode), the output terminal 740 is connected to the output terminal of the first operational amplifier 734. This results in a bias voltage V being output from the output terminal 740. C_BIAS4 The second adjustment voltage V DIVB32 This is how it works. Switch SW4 receives the switch signal S SW1 When the voltage is high (in boost mode), the output terminal 740 is connected to the output terminal of the third operational amplifier 738. This results in the bias voltage V being output from the output terminal 740. C_BIAS4 The second bias voltage V is expressed by equation (2). C_BIAS42 This is the result.

[0161] Figure 11 is a timing chart showing an example of operation of the DC / DC converter 4 in step-down mode according to the fourth embodiment. 31 Prior to that, the sleep signal S SLP2 The voltage is low, and the controller circuit 60 is in sleep mode. At this time, the comparison voltage V C3 Initial voltage V INIT2 Bias voltage V forC_BIAS4 is generated.

[0162] Timing t 31 at which the sleep signal S SLP2 becomes high level, and the controller circuit 60 enters the wake-up mode. As a result, the bias voltage V C_BIAS4 is used as the initial voltage V C3 of the comparison voltage V INIT2 to switch the first transistor MN1 and the second transistor MN2.

[0163] [[ID=1十九]]As shown in FIG. 11, the first lamp voltage V RAMP1 rises (ramp-up), and the second lamp voltage V RAMP2 falls (dump-down). These two lamp voltages cross at a voltage (k A / 2 × V dd ) that is half of the amplitude voltage.

[0164] When the comparison voltage V C3 is greater than at least one of the two lamp voltages, the first PWM signal S PWM11 becomes high level, the first transistor MN1 turns on, and the second transistor MN2 turns off (T ON2 ). Conversely, when the comparison voltage V C3 is less than both of the two lamp voltages, the first PWM signal S PWM11 becomes low level, the first transistor MN1 turns off, and the second transistor MN2 turns on. Also, when the comparison voltage V C3 is greater than both of the two lamp voltages, the second PWM signal S PWM12 becomes low level, the fourth transistor MN4 turns on, and the third transistor MN3 turns off. Conversely, when the comparison voltage V C3 is less than at least one of the two lamp voltages, the second PWM signal S PWM12 becomes high level, the fourth transistor MN4 turns off, and the third transistor MN3 turns on.

[0165] Looking at it from another perspective, out of the two lamp voltages, k A / 2 × V ddThe triangular wave below this point is the ramp voltage for the step-down mode, k A / 2×V dd The triangular wave above this point is the ramp voltage for the boost mode. A 2 × k A If we replace it with this, the ramp amplitude of the lower triangular wave is k A ×V dd Therefore, the comparison voltage V C3 The relationship between and duty cycle is as follows: Comparison voltage V in the first embodiment C1 This is the same relationship as with duty.

[0166] Figure 12 is a timing chart showing an example of operation of the DC / DC converter 4 in boost mode according to the fourth embodiment. As shown in Figure 12, timing t 41 In the sleep signal S SLP2 The bias voltage V switches from low level to high level. C_BIAS4 Comparing voltage V C3 Initial voltage V INIT3 The third transistor MN3 and the fourth transistor MN4 are switched accordingly.

[0167] The ideal duty cycle in boost mode is (V OUT4 -V IN1 ) / V OUT4 Therefore, the bias voltage V expressed by equation (2) is given by equation (2). C_BIAS42 The comparison voltage V C3 Initial voltage V INIT3 It is desirable that it be given as such.

[0168] (Variation 1) In the first embodiment, an example was described in which the output voltage divider circuit 224 has the same circuit configuration as the input voltage divider circuit 222. However, the output voltage divider circuit 224 may have the same circuit configuration as the input voltage divider circuit 222. DIVB1 It may have any circuit configuration that can achieve the same voltage division ratio as (R B1 +R B2 A first resistor having a resistance value of ) and (R B3 +R B4It has a second resistor with a resistance value of ) and the output voltage V through these two resistors OUT1 The voltage may be divided. The output voltage divider circuit 524 according to the third embodiment is similar.

[0169] (Modification 2) In the first embodiment, when the PWM comparator 108 is in sleep mode, switch SW1 is turned on, and the comparison voltage V is transmitted via switch SW1. C1 The bias voltage V is used as the initial voltage. C_BIAS1 An example of supplying the bias voltage V was explained. However, this is not limited to this example; in sleep mode, the operation of the resistive voltage divider 22 is stopped, and the bias voltage V C_BIAS1 The voltage may be set to ground voltage (i.e., the output node 225 of the output voltage divider circuit 224 is at ground voltage), and switch SW1 may be turned on.

[0170] In this case, when the PWM comparator 108 switches from sleep state to wake-up state, switch SW1 is turned off, the resistor voltage divider 22 operates, and the voltage division ratio in the output voltage divider circuit 224 is adjusted, thereby adjusting the bias voltage V C_BIAS1 This is generated. Bias voltage V C_BIAS1 The comparison voltage V is transmitted via capacitive coupling of capacitor C1. C1 This may be supplied as the initial voltage. This suppresses power consumption in the resistive voltage divider 72 during sleep mode (for example, power consumption due to internal bias current), thereby reducing power consumption.

[0171] (Variation 3) In the fourth embodiment, in the resistive voltage divider 72, the first comparator 726 and the second comparator 728 compare the comparison voltage of the input voltage divider circuit 722 and the comparison voltage of the output voltage divider circuit 724, respectively, to set the target voltage V DIVA An example of selecting a comparison voltage to compare with was explained. However, this is not limited to this example; for example, if the switch comparator 732 is comparing with an input voltage V IN1 and output voltage V OUT4The two voltages are compared, and depending on the comparison result, the first comparator 726 and the second comparator 728 may each determine the comparison voltage to be compared.

[0172] For example, the switch comparator 732 receives an input voltage V IN1 Output voltage V OUT4 If the output voltage V is greater than the first comparator 726 and the second comparator 728 may decide to compare the comparison voltage generated by the input voltage divider circuit 722. The switch comparator 732 then considers the output voltage V. OUT4 The input voltage V IN1 If the value is greater than the given value, the first comparator 726 and the second comparator 728 may each decide to compare the comparison voltages generated by the output voltage divider circuit 724. In addition, a separate comparator may be provided to determine the comparison voltages to be compared, separate from the switch comparator 732.

[0173] (supplement) While the embodiments described herein have been explained using specific terminology, this explanation is merely illustrative to aid understanding and does not limit the scope of this disclosure or the claims. The scope of the present invention is defined by the claims. Furthermore, not only embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention. It is also possible to combine one or more elements of one embodiment with one or more elements of another embodiment.

[0174] (Note) The technology disclosed herein can be understood in one respect as follows:

[0175] (Item 1) A controller circuit for a DC / DC converter that generates an output voltage corresponding to the input voltage, A PWM comparator that compares a periodic ramp voltage with a comparison voltage, The PWM comparator has a voltage supply circuit that supplies an initial voltage for the comparison voltage, The initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage. Controller circuit.

[0176] (Item 2) The voltage supply circuit includes an input voltage divider circuit that divides the input voltage to generate a comparison voltage and an adjustment voltage, an output voltage divider circuit that divides the output voltage to generate a bias voltage, a comparator that compares the amplitude voltage of the ramp voltage with the comparison voltage generated by the input voltage divider circuit, and a voltage divider adjustment circuit that adjusts the voltage division ratio in the input voltage divider circuit and the output voltage divider circuit, respectively. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit so that the adjusted voltage approaches the amplitude voltage based on the comparison result of the comparator, and adjusts the voltage division ratio in the output voltage divider circuit so that the output voltage is divided by the voltage division ratio of the adjusted voltage to generate the bias voltage. The controller circuit described in item 1.

[0177] (Item 3) The input voltage divider circuit uses the comparison voltage generated by the input voltage divider circuit as the first comparison voltage, and further generates a second comparison voltage that is smaller than the first comparison voltage. The voltage supply circuit further includes a second comparator that compares the second comparison voltage with the amplitude voltage when the comparator is designated as a first comparator. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit based on the first comparison result of the first comparator and the second comparison result of the second comparator so that the amplitude voltage is between the voltage of the first comparison voltage and the voltage of the second comparison voltage, and adjusts the voltage division ratio in the output voltage divider circuit so that the bias voltage is generated by dividing the output voltage with a voltage division ratio between the voltage division ratio of the first comparison voltage and the voltage division ratio of the second comparison voltage after adjustment in the input voltage divider circuit. The controller circuit described in item 2.

[0178] (Item 4) The input voltage divider circuit includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor connected in series. The end of the first voltage divider resistor opposite to the second voltage divider resistor is connected to the input voltage application terminal. The end of the fourth voltage divider resistor opposite to the third voltage divider resistor is connected to ground. The first comparison voltage is the voltage between the first voltage divider resistor and the second voltage divider resistor. The second comparison voltage is the voltage between the third voltage divider resistor and the fourth voltage divider resistor. The adjustment voltage is the voltage between the second voltage divider resistor and the third voltage divider resistor. At least one of the first voltage divider resistor and the fourth voltage divider resistor is a variable resistor, The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit by adjusting the resistance values ​​of the first voltage divider resistor and the fourth voltage divider resistor, and adjusts the voltage division ratio in the output voltage divider circuit so that the bias voltage is generated by dividing the output voltage with the voltage division ratio of the adjusted voltage. The controller circuit described in item 3.

[0179] (Item 5) The voltage divider adjustment circuit sequentially changes the voltage division ratio in the input voltage divider circuit based on the first and second comparison results. If the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage, the first and second comparison voltages are increased while down-counting or up-counting. If the comparison result of the second comparator indicates that the second comparison voltage is greater than the amplitude voltage, the first and second comparison voltages are decreased while counting in the opposite direction to when the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage. Based on the count result, the voltage division ratio in the output voltage divider circuit is adjusted. The controller circuit described in item 4.

[0180] (Item 6) The voltage divider adjustment circuit terminates the adjustment of the voltage division ratio in the input voltage divider circuit when the comparison result of the first comparator indicates that the amplitude voltage is smaller than the first comparison voltage, and the comparison result of the second comparator indicates that the second comparison voltage is smaller than the amplitude voltage. A controller circuit as described in any one of items 3 through 5.

[0181] (Item 7) The fourth voltage divider resistor is a variable resistor, The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit by switching the resistance value of the fourth voltage divider resistor. The controller circuit described in item 4 or 5.

[0182] (Item 8) The voltage supply circuit further includes a capacitor provided between the output node of the output voltage divider circuit and the input terminal of the PWM comparator, and a switch connected in parallel to the capacitor. A controller circuit as described in any one of items 2 through 7.

[0183] (Item 9) The voltage supply circuit, when the switch is on, supplies the bias voltage as the initial voltage via the switch. The controller circuit described in item 8.

[0184] (Item 10) The voltage supply circuit is configured such that when the PWM comparator is in sleep mode, the voltage at the output terminal of the output voltage divider circuit is ground voltage and the switch is on; when the PWM comparator switches from sleep mode to wake-up mode, the switch is turned off and the bias voltage generated by adjusting the voltage division ratio in the output voltage divider circuit is supplied as the initial voltage via the capacitive coupling of the capacitor. The controller circuit described in item 8.

[0185] (Item 11) The voltage supply circuit further includes a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator. A controller circuit as described in any one of items 2 through 10.

[0186] (Item 12) The voltage supply circuit further includes a capacitor provided between the output terminal of the buffer circuit and the resistor circuit, or between the resistor circuit and the input terminal of the PWM comparator, and a switch connected in parallel to the capacitor. The controller circuit described in item 11.

[0187] (Item 13) The aforementioned resistor circuit is composed of a variable resistor. The controller circuit described in item 11.

[0188] (Item 14) The voltage supply circuit further includes a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator. The resistor circuit includes a first resistor path consisting of a first resistor and a second resistor connected in series, and a second resistor path consisting of a third resistor and a fourth resistor connected in series. The first resistor path is connected in parallel to the second resistor path, The ratio of the combined resistance of the first and second voltage dividers to the combined resistance of the third and fourth voltage dividers is the same as the ratio of the combined resistance of the first and second resistors to the combined resistance of the third and fourth resistors. The controller circuit described in item 4 or 5.

[0189] (Item 15) The DC / DC converter is of the step-up / step-down type, The controller circuit further includes a second PWM comparator, with the PWM comparator being the first PWM comparator. The first PWM comparator compares the first lamp voltage with a comparison voltage, using the lamp voltage as the first lamp voltage. The second PWM comparator compares the second ramp voltage, which is obtained by inverting the first ramp voltage, with a comparison voltage common to the first PWM comparator. The voltage supply circuit supplies an initial voltage for the comparison voltage to the first PWM comparator and the second PWM comparator, respectively. The controller circuit described in item 1.

[0190] (Item 16) The voltage supply circuit includes an input voltage divider circuit that divides the input voltage to generate an input comparison voltage and a first adjustment voltage, an output voltage divider circuit that divides the output voltage to generate an output comparison voltage and a second adjustment voltage, a comparator, and a voltage divider adjustment circuit that adjusts the voltage division ratio in the input voltage divider circuit and the output voltage divider circuit, respectively. The comparator compares the input comparison voltage or the output comparison voltage with the common amplitude voltage of the first ramp voltage and the second ramp voltage. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit so that the first adjustment voltage approaches the amplitude voltage when the input voltage is greater than the output voltage, based on the comparison result of the comparator, and adjusts the voltage division ratio in the output voltage divider circuit so that the second adjustment voltage is the voltage obtained by dividing the output voltage by the voltage division ratio of the adjusted first adjustment voltage, and adjusts the voltage division ratio in the input voltage divider circuit so that the second adjustment voltage approaches the amplitude voltage when the output voltage is greater than the input voltage, and adjusts the voltage division ratio in the input voltage divider circuit so that the first adjustment voltage is the voltage obtained by dividing the input voltage by the voltage division ratio of the adjusted second adjustment voltage. The controller circuit described in item 15.

[0191] (Item 17) The voltage supply circuit is configured to supply, as the initial voltage, a voltage obtained by adding half the amplitude voltage to the difference voltage obtained by subtracting the adjusted second adjusted voltage from the adjusted first adjusted voltage when the output voltage is greater than the input voltage. The controller circuit described in item 16.

[0192] (Item 18) A controller circuit comprising any one of items 1 to 17, DC / DC converter. [Explanation of Symbols]

[0193] 1, 2, 4 DC / DC converter, 10, 30, 60 controller circuits, 15, 65 peripheral circuits, 20, 40, 70 voltage supply circuits, 22, 52, 72 resistor voltage divider sections, 32 error amplifier circuit, 42, 74 buffer circuits, 44, 54, 76 resistor circuits, 100 first error amplifier, 102 clamp circuit, 104 current sense amplifier, 106, 320 second error amplifier, 108 PWM comparator, 110, 608 logic circuits, 112, 610, 616 level shifters, 114, 612, 614, 618, 620 buffer circuits, 116, 24, 46, 56, 78 NOT gates, 120 voltage source, 122 sleep comparator, 220 power supply voltage divider circuit, 222, 522, 722 input voltage divider circuits, 224, 524, 724 output voltage divider circuits, 225 output node, 226, 526, 726 first comparator, 228, 528, 728 second comparator, 230, 530, 730 voltage divider adjustment circuit, 322 third error amplifier, 420 operational amplifier, 540 first resistor path, 542 second resistor path, 544 first node, 546 second node, 600 first PWM comparator, 602 second PWM comparator, 604 NAND gate, 606 OR gate, 732 switch comparator, 734 first operational amplifier, 736 second operational amplifier, 738 third operational amplifier, 740 output terminal, MH1 high-side transistor, ML1 low-side transistor, MN1 first transistor, MN2 second transistor, MN3 third transistor, MN4 fourth transistor, SW1~SW4 switches, R1~R7 resistors, L1, L2 inductors, C1~C6 capacitors, R A1 ,R A2 voltage dividing resistor, R B1 ,R B11 first voltage dividing resistor, R B2 ,R B12 second voltage dividing resistor, R B3 ,R B13 third voltage dividing resistor, R B4 ,R B14 fourth voltage dividing resistor, R B5 ,R B15 fifth voltage dividing resistor, R B6 ,R B16 sixth voltage dividing resistor, R B7 ,R B177th voltage divider resistor, R B8 ,R B18 8th voltage divider resistor, R C1 1st resistance, R C2 2nd resistance, R C3 3rd resistor, R C4 4th resistance.

Claims

1. A controller circuit for a DC / DC converter that generates an output voltage corresponding to the input voltage, A PWM comparator compares a periodic ramp voltage with a reference voltage, The PWM comparator has a voltage supply circuit that supplies an initial voltage for the comparison voltage, The initial voltage is a voltage corresponding to the ratio of the input voltage to the output voltage. Controller circuit.

2. The voltage supply circuit includes an input voltage divider circuit that divides the input voltage to generate a comparison voltage and an adjustment voltage, an output voltage divider circuit that divides the output voltage to generate a bias voltage, a comparator that compares the amplitude voltage of the ramp voltage with the comparison voltage generated by the input voltage divider circuit, and a voltage divider adjustment circuit that adjusts the voltage division ratio in the input voltage divider circuit and the output voltage divider circuit, respectively. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit so that the adjusted voltage approaches the amplitude voltage based on the comparison result of the comparator, and adjusts the voltage division ratio in the output voltage divider circuit so that the output voltage is divided by the voltage division ratio of the adjusted voltage to generate the bias voltage. The controller circuit according to claim 1.

3. The input voltage divider circuit uses the comparison voltage generated by the input voltage divider circuit as the first comparison voltage, and further generates a second comparison voltage that is smaller than the first comparison voltage. The voltage supply circuit further includes a second comparator that compares the second comparison voltage with the amplitude voltage when the comparator is designated as a first comparator. The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit based on the first comparison result of the first comparator and the second comparison result of the second comparator so that the amplitude voltage is between the voltage of the first comparison voltage and the voltage of the second comparison voltage, and adjusts the voltage division ratio in the output voltage divider circuit so that the bias voltage is generated by dividing the output voltage with a voltage division ratio between the voltage division ratio of the first comparison voltage and the voltage division ratio of the second comparison voltage after adjustment in the input voltage divider circuit. The controller circuit according to claim 2.

4. The input voltage divider circuit includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor connected in series. The end of the first voltage divider resistor opposite to the second voltage divider resistor is connected to the input voltage application terminal. The end of the fourth voltage divider resistor opposite to the third voltage divider resistor is connected to ground. The first comparison voltage is the voltage between the first voltage divider resistor and the second voltage divider resistor. The second comparison voltage is the voltage between the third voltage divider resistor and the fourth voltage divider resistor. The adjustment voltage is the voltage between the second voltage divider resistor and the third voltage divider resistor. At least one of the first voltage divider resistor and the fourth voltage divider resistor is a variable resistor, The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit by adjusting the resistance values ​​of the first voltage divider resistor and the fourth voltage divider resistor, and adjusts the voltage division ratio in the output voltage divider circuit so that the bias voltage is generated by dividing the output voltage with the voltage division ratio of the adjusted voltage. The controller circuit according to claim 3.

5. The voltage divider adjustment circuit sequentially changes the voltage division ratio in the input voltage divider circuit based on the first and second comparison results. If the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage, the first and second comparison voltages are increased while down-counting or up-counting. If the comparison result of the second comparator indicates that the second comparison voltage is greater than the amplitude voltage, the first and second comparison voltages are decreased while counting in the opposite direction to when the first comparison result indicates that the amplitude voltage is greater than the first comparison voltage. Based on the count result, the voltage division ratio in the output voltage divider circuit is adjusted. The controller circuit according to claim 4.

6. The voltage divider adjustment circuit terminates the adjustment of the voltage division ratio in the input voltage divider circuit when the comparison result of the first comparator indicates that the amplitude voltage is smaller than the first comparison voltage, and the comparison result of the second comparator indicates that the second comparison voltage is smaller than the amplitude voltage. The controller circuit according to claim 3.

7. The fourth voltage divider resistor is a variable resistor, The voltage divider adjustment circuit adjusts the voltage division ratio in the input voltage divider circuit by switching the resistance value of the fourth voltage divider resistor. The controller circuit according to claim 4.

8. The voltage supply circuit further includes a capacitor provided between the output node of the output voltage divider circuit and the input terminal of the PWM comparator, and a switch connected in parallel to the capacitor. The controller circuit according to claim 2.

9. The voltage supply circuit, when the switch is on, supplies the bias voltage as the initial voltage via the switch. The controller circuit according to claim 8.

10. The voltage supply circuit is configured such that when the PWM comparator is in sleep mode, the voltage at the output terminal of the output voltage divider circuit is ground voltage and the switch is on; when the PWM comparator switches from sleep mode to wake-up mode, the switch is turned off and the bias voltage generated by adjusting the voltage division ratio in the output voltage divider circuit is supplied as the initial voltage via the capacitive coupling of the capacitor. The controller circuit according to claim 8.

11. The voltage supply circuit further includes a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator. The controller circuit according to claim 2.

12. The voltage supply circuit further includes a capacitor provided between the output terminal of the buffer circuit and the resistor circuit, or between the resistor circuit and the input terminal of the PWM comparator, and a switch connected in parallel to the capacitor. The controller circuit according to claim 11.

13. The aforementioned resistor circuit is composed of a variable resistor. The controller circuit according to claim 11.

14. The voltage supply circuit further includes a buffer circuit provided to buffer the bias voltage generated by the output voltage divider circuit, and a resistor circuit provided between the output terminal of the buffer circuit and the input terminal of the PWM comparator. The resistor circuit includes a first resistor path consisting of a first resistor and a second resistor connected in series, and a second resistor path consisting of a third resistor and a fourth resistor connected in series. The first resistor path is connected in parallel to the second resistor path, The ratio of the combined resistance of the first and second voltage dividers to the combined resistance of the third and fourth voltage dividers is the same as the ratio of the combined resistance of the first and second resistors to the combined resistance of the third and fourth resistors. The controller circuit according to claim 4.

15. The DC / DC converter is of the step-up / step-down type, The controller circuit further includes a second PWM comparator, with the PWM comparator being the first PWM comparator. The first PWM comparator compares the first lamp voltage with a comparison voltage, using the lamp voltage as the first lamp voltage. The second PWM comparator compares the second ramp voltage, which is obtained by inverting the first ramp voltage, with a comparison voltage common to the first PWM comparator. The voltage supply circuit supplies an initial voltage for the comparison voltage to the first PWM comparator and the second PWM comparator, respectively. The controller circuit according to claim 1.

16. The voltage supply circuit includes an input voltage divider circuit that divides the input voltage to generate an input comparison voltage and a first adjustment voltage, an output voltage divider circuit that divides the output voltage to generate an output comparison voltage and a second adjustment voltage, a comparator, and a voltage divider adjustment circuit that adjusts the voltage division ratio in the input voltage divider circuit and the output voltage divider circuit, respectively. The comparator compares the input comparison voltage or the output comparison voltage with the common amplitude voltage of the first ramp voltage and the second ramp voltage. The voltage divider adjustment circuit adjusts, based on the comparison result of the comparator, if the input voltage is greater than the output voltage, the voltage division ratio in the input voltage divider circuit adjusts so that the first adjustment voltage approaches the amplitude voltage, and adjusts the voltage division ratio in the output voltage divider circuit so that the second adjustment voltage is the voltage obtained by dividing the output voltage by the voltage division ratio of the adjusted first adjustment voltage, and if the output voltage is greater than the input voltage, the voltage division ratio in the input voltage divider circuit adjusts so that the second adjustment voltage approaches the amplitude voltage, and adjusts the voltage division ratio in the input voltage divider circuit so that the first adjustment voltage is the voltage obtained by dividing the input voltage by the voltage division ratio of the adjusted second adjustment voltage. The controller circuit according to claim 15.

17. The voltage supply circuit is configured to supply, as the initial voltage, a voltage obtained by adding half the amplitude voltage to the difference voltage obtained by subtracting the adjusted second adjusted voltage from the adjusted first adjusted voltage when the output voltage is greater than the input voltage. The controller circuit according to claim 16.

18. A controller circuit comprising the one described in any one of claims 1 to 17, DC / DC converter.

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