Digital-to-analog conversion circuit and display driver

Abstract

This invention provides a digital-to-analog conversion circuit capable of converting digital data into an analog output voltage with high precision and a wide dynamic range. [Configuration] The digital-to-analog conversion circuit of this disclosure includes a differential amplifier that outputs an output voltage which is the average voltage of the voltages received at a plurality of input terminals, and a decoder that, based on a digital data piece, selects two reference voltages from a plurality of reference voltages as first and second voltages, and distributes and supplies one or the other or both of the first and second voltages to each of the plurality of input terminals of the differential amplifier. The differential amplifier includes a plurality of differential pairs, each including an inverting input terminal that receives a common output voltage, a non-inverting input terminal that receives the voltages received at a plurality of input terminals, and an output pair, the output pairs of which are commonly connected, an amplification stage that generates an output voltage by amplification based on the output of one or both of the commonly connected output pairs, and a control unit that controls one differential pair to an inactive state when the upper bits of the digital data piece represent a predetermined code.

Description

[Technical Field]

[0001] This disclosure relates to a digital-to-analog conversion circuit and a display driver including said digital-to-analog conversion circuit. [Background technology]

[0002] Currently, liquid crystal displays (LCDs) and organic EL displays are the mainstream active-matrix display devices. These display devices have a display panel in which multiple data lines and multiple scan lines are wired in an intersecting manner, and display cells connected to the multiple data lines via pixel switches are arranged in a matrix. The display panel is equipped with a data driver that supplies analog voltage signals corresponding to the grayscale level to the multiple data lines of the display panel, and a scanning driver that supplies scanning signals to control the on / off state of each pixel switch to the multiple scan lines of the display panel. The data driver includes a digital-to-analog conversion unit that converts the digital video signal into an analog voltage corresponding to the brightness level and supplies the amplified voltage signal to each data line of the display panel.

[0003] The following describes the general configuration of the data driver.

[0004] The data driver includes, for example, a shift register, a data register latch, a level shifter, and a digital-to-analog converter.

[0005] The shift register generates multiple latch timing signals synchronized with the clock signal to select a latch in response to a start pulse supplied from the display controller, and supplies these signals to the data register latch. Based on each of the latch timing signals supplied from the shift register, the data register latch captures S (where S is an integer of 2 or more) of the video digital data supplied from the display controller and supplies these S video digital data signals to the level shifter. The level shifter applies a level shift process to each of the S video digital data signals supplied from the data register latch to increase its signal amplitude, and supplies these S level-shifted video digital data signals to the digital-to-analog conversion unit.

[0006] The digital-to-analog conversion section includes a reference voltage group generation section, a decoder section, and an amplification section.

[0007] The reference voltage group generation unit generates multiple reference voltages with different voltage values ​​and supplies them to the decoder unit. For example, the reference voltage group generation unit supplies multiple divided voltages, obtained by dividing the voltage between at least two reference power supply voltages using ladder resistors, to the decoder unit as a group of reference voltages.

[0008] The decoder unit has S decoders, each corresponding to one of the outputs of the data driver. Each decoder is supplied with a group of reference voltages generated by the reference voltage group generation unit, and also receives a video digital data signal supplied from the level shifter. It then selects a reference voltage corresponding to this video digital data signal from among the multiple reference voltages and supplies the selected reference voltage to the amplification unit.

[0009] The amplification unit has S differential amplifiers that individually amplify and output the reference voltage selected by each decoder in the decoder unit.

[0010] By the way, in the digital-to-analog conversion unit described above, the larger the number of reference voltages generated by the reference voltage group generation unit, the more the number of gradations (number of colors) of the luminance levels that can be expressed can be increased. However, increasing the number of reference voltages generated by the reference voltage group generation unit increases the wiring area and the number of switch elements included in the decoder that selects the reference voltages accordingly, and increases the chip size (manufacturing cost) of the data driver.

[0011] Therefore, as the differential amplifier described above, a DA (digital to analog) converter that employs a differential amplifier capable of outputting a plurality of three or more voltage values by interpolating (interpolating) two reference voltages selected based on the luminance level with a predetermined weighting has been proposed (see, for example, FIGS. 2 and 4 of Patent Document 1).

[0012] The DA converter described in Patent Document 1 includes a negative feedback type differential amplifier that outputs an output voltage having one of the four voltage values obtained by interpolating between the two reference voltages based on the two reference voltages. Such differential amplifiers are each driven by the same tail current, the output voltage is commonly feedback-input to each inverting input terminal, and includes four differential pairs that receive one of the two reference voltages at each non-inverting input terminal with a 1-to-1-to-2 weighting.

[0013] In this DA converter, two adjacent reference voltages are selected from the reference voltage group at every four gradations according to the upper bit group of the digital data signal to be converted. And in this DA converter, according to the lower 2 bits in the digital data signal, one or the other of the two selected reference voltages is input to the non-inverting input terminals of all the differential pairs, or one reference voltage is input to the non-inverting input terminals of at least one differential pair and the other reference voltage is input to the non-inverting input terminals of the remaining differential pairs. <00,00092>

[0014] Thus, in the DA converter described in Patent Document 1, all gradations 2 levels (for example, N = 4) of voltages that can be represented by an N-bit digital data signal are KDivide the level (for example, K = 2) into a plurality of sections with each section being one interval. Then, in the DA converter, for each section, two reference voltages selected corresponding to that section are interpolated to obtain 2 K voltages.

Prior Art Documents

Patent Documents

[0015]

Patent Document 1

[0016] [Summary] By the way, in the DA converter described in Patent Document 1, by interpolation using 17 reference voltages (V0, V4, V8, V12, ··· V60, V64), output voltages for 64 gradations from gradation 0 to 63 are obtained (see, for example, FIG. 4 of Patent Document 1). At this time, according to the DA converter, the output voltage Vout corresponding to the maximum (or minimum) gradation 0 is V0, but the output voltage Vout corresponding to the minimum (or maximum) gradation 63 is, (V60 + V64 + 2·V64) / 4 which is.

[0017] Therefore, since the output voltage Vout corresponding to gradation 63 does not match the reference voltage V64, the dynamic range of the output voltage Vout becomes narrower than the range of the reference voltages V0 to V64.

[0018] The digital-to-analog conversion circuit according to this disclosure is a digital-to-analog conversion circuit that converts N-bit (N is an integer of 3 or more) digital data fragments into an analog output voltage and outputs it, comprising: a reference voltage generation unit that generates a plurality of reference voltages having different voltage values; a differential amplifier having a plurality of input terminals and outputting a voltage corresponding to the average value of the voltages received at each of the plurality of input terminals as the output voltage; and a unit that receives the digital data fragments and, based on the digital data fragments, selects two reference voltages with close voltage values ​​from the plurality of reference voltages as the first voltage and the second voltage, and outputs the first voltage and the second voltage to each of the plurality of input terminals of the differential amplifier. A differential amplifier comprises a decoder that distributes and supplies one, the other, or both of the voltages, and includes a plurality of differential pairs, each including an inverting input terminal into which the output voltage is commonly input, a non-inverting input terminal into which one of the voltages received at the plurality of input terminals is supplied as an input voltage, and an output pair, the respective output pairs of which are commonly connected; an amplification stage that generates the output voltage by amplification based on the output of one or both of the commonly connected output pairs; and a control unit that controls one of the plurality of differential pairs to an inactive state when the upper (NK) bit (K is an integer of 2 or more less than N) of the digital data piece represents a predetermined code. [Brief explanation of the drawing]

[0019] [Figure 1] This is a circuit diagram showing the configuration of the digital-to-analog converter 100 as a digital-to-analog converter related to this disclosure. [Figure 2] This figure shows an example of the specifications of the digital-to-analog converter 100. [Figure 3] This figure shows another example of the specifications of the digital-to-analog converter 100. [Figure 4] This is a circuit diagram showing the configuration of the digital-to-analog converter 100_1 as a first modified example of the digital-to-analog converter 100. [Figure 5] This is a circuit diagram showing the configuration of the digital-to-analog converter 100_2, which is a second modified example of the digital-to-analog converter 100. [Figure 6] This is a time chart showing an example of the timing of state switching of the differential pair [11_1, 12_1] by the control unit 40 (40_1). [Figure 7] This is a circuit diagram showing the configuration of the digital-to-analog converter 100_3, which is a third modified example of the digital-to-analog converter 100. [Figure 8] This block diagram shows the configuration of a data driver 18 including a digital-to-analog converter and a display device 200 including the data driver 18.

[0020] [Detailed explanation] The embodiments of this disclosure will be described in detail below with reference to the drawings.

[0021] [Example 1] Figure 1 is a circuit diagram showing an example of the configuration of the digital-to-analog converter 100 as a digital-to-analog converter according to this disclosure.

[0022] The digital-to-analog converter 100 receives N bits of digital data DT (where N is an integer greater than or equal to 3), converts it into an output voltage Vout which has an analog voltage value, and outputs it.

[0023] As shown in Figure 1, the digital-to-analog converter 100 includes a reference voltage generation unit 90, a decoder 50, and a differential amplifier 10.

[0024] The reference voltage generation unit 90 receives a DC reference power supply voltage VGH and a reference power supply voltage VGL that is lower than the reference power supply voltage VGH. Based on the reference power supply voltages VGH and VGL, the reference voltage generation unit 90 generates reference voltages V0 to Vj (where j is an integer of 2 or more) with different voltage values, and supplies these reference voltages V0 to Vj to the decoder 50.

[0025] Decoder 50 includes sub-decoders 50_1 and 50_2.

[0026] The sub-decoder 50_2 receives N-bit digital data DT and reference voltages V0 to Vj. Based on the upper bit group of the digital data DT, for example, the upper (N - K) bit group (K is an integer greater than or equal to 2 and less than N), the sub-decoder 50_2 selects, from the reference voltages V0 to Vj, a pair of voltages (VA, VB) whose voltage values are adjacent to each other as two voltages. The sub-decoder 50_2 supplies the selected two voltages (VA, VB) to the sub-decoder 50_1.

[0027] Based on the lower bit group of the digital data, that is, the lower K bits, the sub-decoder 5*0_1 distributes one, or the other, or both of the two voltages (VA, VB) to 2^K terminals of the differential amplifier*10, that is, the input terminals t<1> to t<2 K >.

[0028] In this way, the sub-decoder 50_1 distributes the voltage group of the voltages (VA, VB) to the input terminals t<1> to t<2 K > respectively, and supplies the distributed voltage group as input voltages V<1> to V<2 K > to the input terminals t<1> to t<2 K > of the differential amplifier 10.

[0029] The differential amplifier 10 includes 2^K N-channel differential pairs [11_1, 12_1] to [11_2 K , 12_2 K , N-channel transistors 13_1 to 13_2 K , a switch 14, a current mirror circuit 20, an amplification stage 30, and a control unit 40.

[0030] Each of the differential pairs [11_1, 12_1] to [11_2 K , 12_2 K is composed of a pair of N-channel transistors whose sources are connected. At this time, the gate of one of the pair of N-channel transistors becomes the non-inverting input terminal of the differential pair, and the gate of the other transistor becomes the inverting input terminal of the differential pair. Also, the drains of the pair of N-channel transistors become the output pair of this differential pair.

[0031] Here, the differential pair [11_1, 12_1] ~ [11_2 K , 12_2 K Each output pair is commonly connected via nodes n21 and n22, as shown in Figure 1. Also, the differential pairs [11_1, 12_1]~[11_2 K , 12_2 K Each non-inverting input terminal corresponds to the input terminal t described above. <1> ~t<2 K Each of these is connected to the respective inverting input terminal, and the respective inverting input terminal is connected to the output terminal Sk for outputting the output voltage Vout.

[0032] Transistors 13_1~13_2 K Each source receives a low-voltage power supply voltage VSSA, and generates a current corresponding to the magnitude of the bias voltage BN received at each gate, which is then passed through each differential pair as a tail current. That is, transistors 13_1~13_2 K The differential pair is [11_1, 12_1]~[11_2K, 12_2 K The tail current m that flows individually through each of the ] <1> Io~m<2 K >Generates Io. Note that transistors 13_2~13_2 K Each drain is a differential pair [11_2, 12_2]~[11_2 K , 12_2 K Each of the sources of [11_1, 12_1] is connected, but the drain of transistor 13_1 is connected to the source of the differential pair [11_1, 12_1] via switch 14.

[0033] Switch 14 is in the off state while receiving a disable signal DS from the control unit 40, and in the on state when it is not receiving the disable signal DS. While switch 14 is in the on state, transistor 13_1 and the differential pair [11_1, 12_1] are electrically connected, so the differential pair [11_1, 12_1] is in the enabled (active) state. On the other hand, when switch 14 is turned off in response to the disable signal DS, transistor 13_1 and the differential pair [11_1, 12_1] are electrically disconnected, so no tail current flows through the differential pair [11_1, 12_1], and it becomes disabled (inactive).

[0034] The current mirror circuit 20 includes P-channel transistors 21 and 22 whose gates are connected to each other and which are of the same size. A high power supply voltage VDDA is applied to the sources of each transistor 21 and 22. The drain of transistor 21 is connected to node n21, and the gate and drain of transistor 22 are connected to node n22. With this configuration, the current mirror circuit 20 is a differential pair [11_1, 12_1]~[11_2 K , 12_2 K It operates as a common load for each.

[0035] The amplification stage 30 is a commonly connected differential pair [11_1, 12_1]~[11_2 K , 12_2 K The unit receives the output signals of one or both of the output pairs (nodes n21 and n22) and amplifies them, then outputs the resulting output voltage Vout from the output terminal Sk.

[0036] The control unit 40 supplies a disable signal DS to the switch 14, which stops the operation of the differential pair [11_1, 12_1], only when all of the upper (NK) bits of the N-bit digital data DT are at logic level 1.

[0037] The operation of the digital-to-analog converter 100 will be explained below with an example.

[0038] Figure 2 shows an example of the specifications of the digital-to-analog converter 100.

[0039] Figure 2 shows an example of the specifications for a digital-to-analog converter 100, where N=4 and K=2, meaning that 4-bit digital data DT is the target of conversion, and the differential pairs included in the differential amplifier 10 are 4 systems [11_1, 12_1] to [11_4, 12_4]. According to these specifications, the control unit 40 supplies a disable signal DS to the switch 14 when both of the upper two bits of the 4-bit digital data DT are at logic level 1. The reference voltage generation unit 90 generates five reference voltages with different voltage values, namely reference voltages V0 to V4 having the following magnitude relationship, and supplies these to the decoder 50.

[0040] V0>V1>V2>V3>V4 Furthermore, in this specification, the ratio of the tail currents flowing through each of the differential pairs [11_1, 12_1] to [11_4, 12_4] is, m <1> Io:m <2> Io:m <3> Io:m <4> Io=1:1:1:1 Let's assume that.

[0041] When decoder 50 receives 4-bit digital data DT corresponding to grayscale levels 0 to 3 as shown in Figure 2, it selects two reference voltages V0 and V1 from among reference voltages V0 to V4 based on the code of the upper two bits of the digital data DT. Then, based on the code of the digital data DT corresponding to each of grayscale levels 0 to 3, decoder 50 selects an input voltage V0 or V1, as shown in Figure 2. <1> ~V <4> This is supplied to the differential pair [11_1, 12_1]~[11_4, 12_4]. Note that the upper two bits of the 4-bit digital data DT corresponding to gradation 0~3 are not logic level

[11] , so the control unit 40 does not supply the disable signal DS to the switch 14. As a result, while receiving the digital data DT corresponding to gradation 0~3, the switch 14 remains in the ON state as shown in Figure 2.

[0042] Therefore, in accordance with the digital data DT corresponding to grayscale levels 0 to 3, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V0, (3·V0+V1) / 4, (2·V0+2·V1) / 4, or (V0+3·V1) / 4, as shown in Figure 2.

[0043] Furthermore, when the decoder 50 receives 4-bit digital data DT corresponding to grayscale levels 4 to 7, it selects two reference voltages V1 and V2 from among reference voltages V0 to V4 based on the code of the upper two bits of the digital data DT. Then, based on the code of the digital data DT corresponding to each of grayscale levels 4 to 7, the decoder 50 selects an input voltage V1 or V2, as shown in Figure 2. <1> ~V <4> This is supplied to the differential pair [11_1, 12_1]~[11_4, 12_4]. Note that the upper two bits of the 4-bit digital data DT corresponding to grayscale levels 4~7 are not logic level

[11] , so the control unit 40 does not supply the disable signal DS to the switch 14. As a result, while receiving the digital data DT corresponding to grayscale levels 4~7, the switch 14 remains in the ON state as shown in Figure 2.

[0044] Therefore, in accordance with the digital data DT corresponding to grayscale levels 4 to 7, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V1, (3·V1+V2) / 4, (2·V1+2·V2) / 4, or (V1+3·V2) / 4, as shown in Figure 2.

[0045] Furthermore, when the decoder 50 receives 4-bit digital data DT corresponding to grayscale levels 8 to 11, it selects two reference voltages V2 and V3 from among reference voltages V0 to V4 based on the code of the upper two bits of the digital data DT. Then, based on the code of the digital data DT corresponding to each of grayscale levels 8 to 11, the decoder 50 selects an input voltage V2 or V3, as shown in Figure 2. <1> ~V <4> This is supplied to the differential pair [11_1, 12_1]~[11_4, 12_4]. Note that the upper two bits of the 4-bit digital data DT corresponding to grayscale levels 8~11 are not logic level

[11] , so the control unit 40 does not supply the disable signal DS to the switch 14. As a result, while receiving the digital data DT corresponding to grayscale levels 8~1, the switch 14 remains in the ON state as shown in Figure 2.

[0046] Therefore, in accordance with the digital data DT corresponding to grayscale levels 8 to 11, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V3, (3·V3+V4) / 4, (2·V3+2·V4) / 4, or (V3+3·V4) / 4, as shown in Figure 2.

[0047] Furthermore, when the decoder 50 receives 4-bit digital data DT corresponding to grayscale levels 12 to 15, it selects two reference voltages V3 and V4 from among the reference voltages V0 to V4 based on the code of the upper two bits of the digital data DT. Then, based on the code of the digital data DT corresponding to each of the grayscale levels 12 to 15, the decoder 50 selects an input voltage V, each having a reference voltage of V3 or V4, as shown in Figure 2. <1> ~V <4> This is supplied to the differential pairs [11_1, 12_1]~[11_4, 12_4].

[0048] Incidentally, since the upper two bits of the 4-bit digital data DT corresponding to grayscale levels 12 to 15 are logic levels

[11] , the control unit 40 supplies a disable signal DS to the switch 14. As a result, while receiving the digital data DT corresponding to grayscale levels 12 to 15, the switch 14 is in the off state as shown in Figure 2, and the differential pair [11_1, 12_1] of the differential pairs [11_1, 12_1] to [11_4, 12_4] is disabled.

[0049] Therefore, in accordance with the digital data DT corresponding to grayscale levels 12 to 15, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V3, (2·V3+V4) / 3, (V3+2·V4) / 3, or V4, as shown in Figure 2.

[0050] Thus, the digital-to-analog converter 100, which satisfies the specifications shown in Figure 2, generates 16 levels of analog output voltage Vout corresponding to each of the gradations 0 to 15 represented by the digital data DT, by interpolation using reference voltages V0 to V4.

[0051] In this case, the digital-to-analog converter 100 is configured to disable the differential pair [11_1, 12_1] when the gradation represented by the digital data DT falls within the gradation range QF of gradations 12 to 15. This ensures that the digital-to-analog converter 100 maintains a constant voltage difference in the output voltage Vout between adjacent gradations within the gradation range QF of gradations 12 to 15, and converts the digital data DT representing the smallest gradation 15 into an output voltage Vout having the voltage level of the reference voltage V4.

[0052] Therefore, the digital-to-analog converter 100 shown in Figures 1 and 2 makes it possible to convert all gradations from 0 to 15, represented by digital data DT, into an output voltage Vout having a wide dynamic range in the range of reference voltage V0 to V4 with high precision.

[0053] Figure 3 shows another example of the specifications of the digital-to-analog converter 100.

[0054] Figure 3 shows an example of the specifications for a digital-to-analog converter 100, where N=5 and K=3, meaning that 5 bits of digital data DT are to be converted, and the differential pairs included in the differential amplifier 10 are four systems: [11_1, 12_1] to [11_4, 12_4]. According to this specification, the control unit 40 supplies a disable signal DS to the switch 14 when both of the upper two (=NK) bits of the 5 bits of digital data DT are at logic level 1. The reference voltage generation unit 90 generates five reference voltages V0 to V4 with different voltage values, similar to the specifications shown in Figure 2, and supplies them to the decoder 50.

[0055] Furthermore, in the specifications shown in Figure 3, the ratio of the tail currents flowing through each of the differential pairs [11_1, 12_1] to [11_4, 12_4] is, m <1> Io:m <2> Io:m <3> Io:m <4> Io=1:1:2:4 Let's assume that.

[0056] When decoder 50 receives 5-bit digital data DT corresponding to grayscale levels 0 to 23 as shown in Figure 3, it selects two reference voltages from reference voltages V0 to V4 based on the code of the upper 2 bits (=NK) of the digital data DT, similar to the operation in the specifications shown in Figure 2. Here, for example, as shown in Figure 3, when decoder 50 receives digital data DT representing grayscale levels within the range of grayscale levels 16 to 23, decoder 50 selects two reference voltages V2 and V3 from reference voltages V0 to V4. Then, based on the code of the digital data DT corresponding to each of the grayscale levels 16 to 23, decoder 50 selects an input voltage V2 or V3, as shown in Figure 3. <1> ~V <4> This is supplied to the differential pair [11_1, 12_1]~[11_4, 12_4]. Note that the upper two bits of the 5-bit digital data DT corresponding to grayscale levels 16~23 are not logic level

[11] , so the control unit 40 does not supply the disable signal DS to the switch 14. As a result, while receiving the digital data DT corresponding to grayscale levels 16~23, the switch 14 remains in the ON state as shown in Figure 3.

[0057] Therefore, in accordance with the digital data DT corresponding to grayscale levels 16 to 23, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V2, (7·V2+V3) / 8, (6·V2+2·V3) / 8, (5·V2+3·V3) / 8, (4·V2+4·V3) / 8, (3·V2+5·V3) / 8, (2·V2+6·V3) / 8, or (V2+7·V3) / 8, as shown in Figure 3.

[0058] On the other hand, when the decoder 50 receives 4-bit digital data DT corresponding to a tone included in the tone range QF of tones 24 to 31, which includes the smallest tone 31, the decoder 50 selects two reference voltages V3 and V4 from among the reference voltages V0 to V4 based on the code of the upper 2 bits of the digital data DT. Then, based on the code of the digital data DT corresponding to each of the tones 24 to 31, the decoder 50 selects an input voltage V, each having a reference voltage of V3 or V4, as shown in Figure 3. <1> ~V <4> This is supplied to the differential pairs [11_1, 12_1]~[11_4, 12_4].

[0059] Incidentally, since the upper two bits of the 4-bit digital data DT corresponding to gradations 24 to 31 included in the gradation range QF are logic levels

[11] , the control unit 40 supplies a disable signal DS to switch 14. As a result, while receiving the digital data DT corresponding to gradations 24 to 31 within the gradation range QF, switch 14 is in the off state as shown in Figure 3, and the differential pair [11_1, 12_1] of the differential pairs [11_1, 12_1] to [11_4, 12_4] is disabled.

[0060] Therefore, in accordance with the digital data DT corresponding to grayscale levels 24 to 31, the digital-to-analog converter 100 outputs an output voltage Vout having voltage levels of V3, (6·V3+V4) / 7, (5·V3+2·V4) / 7, (4·V3+3·V4) / 7, (3·V3+4·V4) / 7, (2·V3+5·V4) / 7, (V3+6·V4) / 7, or V4, as shown in Figure 3.

[0061] Thus, the digital-to-analog converter 100, which conforms to the specifications shown in Figure 3, generates 32 levels of analog output voltage Vout corresponding to each of the grayscale levels 0 to 31 represented by the digital data DT, by interpolation using reference voltages V0 to V4.

[0062] In this case, the digital-to-analog converter 100 sets the differential pair [11_1, 12_1] to a disabled state when the gradation represented by the digital data DT falls within the gradation range QF of gradations 24 to 31. This ensures that the digital-to-analog converter 100 maintains a constant voltage difference in the output voltage Vout between adjacent gradations within the gradation range QF of gradations 24 to 31, and converts the digital data DT representing the smallest gradation 31 into an output voltage Vout having a voltage level equal to the reference voltage V4.

[0063] Therefore, even with a digital-to-analog converter 100 conforming to the specifications shown in Figure 3, it is possible to convert all gradations from 0 to 31 represented by digital data DT into an output voltage Vout having a wide dynamic range in the range of reference voltage V0 to V4 with high precision.

[0064] [Example 2] Figure 4 is a circuit diagram showing the configuration of a digital-to-analog converter 100_1, which is a first modified example of the digital-to-analog converter 100 shown in Figure 1.

[0065] Furthermore, the digital-to-analog converter 100_1 shown in Figure 4 is identical to the digital-to-analog converter 100 shown in Figure 1, except that it uses a differential amplifier 10_1 instead of a differential amplifier 10.

[0066] The differential amplifier 10_1 employs a switch circuit including switches 14a and 14b instead of switch 14 shown in Figure 1 as a circuit for setting the differential pair [11_1, 12_1] to a disabled state, and the other configurations are the same as the differential amplifier 10 shown in Figure 1.

[0067] Switch 14a is provided between one output terminal of the differential pair [11_1, 12_1] and node n21. Switch 14b is provided between the other output terminal of the differential pair [11_1, 12_1] and node n22. Switches 14a and 14b disable the differential pair [11_1, 12_1] by disconnecting the connection between the output pairs of the differential pair [11_1, 12_1] and nodes n21 and n22 in response to the disable signal DS.

[0068] [Example 3] Figure 5 is a circuit diagram showing the configuration of a digital-to-analog converter 100_2, which is a second modified example of the digital-to-analog converter 100 shown in Figure 1.

[0069] Furthermore, the digital-to-analog converter 100_2 is identical to the digital-to-analog converter 100 shown in Figure 1, except that it uses a differential amplifier 10_2 instead of a differential amplifier 10. In Figure 5, the reference voltage generation unit 90 and the decoder 50 are omitted from the description.

[0070] The differential amplifier 10_2 employs a switch circuit including switches 14A to 14D instead of the switch 14 shown in Figure 1, and uses a control unit 40_1 instead of the control unit 40, while the other configurations are the same as the differential amplifier 10 shown in Figure 1.

[0071] The control unit 40_1 receives the upper (NK) bits of the N-bit digital data DT. If the upper (NK) bits of the control unit 40_1 represent a code where all of them are at logic level 1, the control unit 40_1 supplies a disable signal DS1 to switches 14A and 14B and a disable signal DS2 to switches 14C and 14D.

[0072] Switch 14A receives the input voltage V supplied from decoder 50. <1> The switch 14A receives this signal and supplies it to the non-inverting input terminals of the differential pair [11_1, 12_1]. However, when the switch 14A receives the disable signal DS1 from the control unit 40_1, it turns off, and the input voltage V to the non-inverting input terminals of the differential pair [11_1, 12_1] is turned off. <1> Stop supplying it.

[0073] Switch 14B receives the output voltage Vout and supplies it to the inverting input terminals of the differential pair [11_1, 12_1]. However, when switch 14B receives the disable signal DS1, it turns off and stops supplying the output voltage Vout to the inverting input terminals of the differential pair [11_1, 12_1].

[0074] Switch 14C is turned ON only when it receives the disable signal DS2, in which case the low power supply voltage VSSA is applied to the non-inverting input terminals of the differential pair [11_1, 12_1].

[0075] Switch 14D is turned ON only when it receives the disable signal DS2, in which case the low power supply voltage VSSA is applied to the inverting input terminals of the differential pair [11_1, 12_1].

[0076] With the above configuration, the differential amplifier 10_2 applies a low power supply voltage VSSA to the inverting and non-inverting input terminals of the differential pair [11_1, 12_1] in response to the disable signals DS1 and DS2, thereby setting the differential pair [11_1, 12_1] to a disabled state.

[0077] [Example 4] Figure 6 is a time chart showing an example of the timing of state switching of the differential pair [11_1, 12_1] by the control unit 40 (40_1) described above.

[0078] Furthermore, Figure 6 shows the timing of the state switching of the differential pair [11_1, 12_1], using as an example the case where the code of the digital data DT transitions as follows for each period Tcy, according to the specifications shown in Figure 3:

[10111] ,

[11000] ,

[10111] .

[0079] As shown in Figure 6, during the first period Tcy, the 5-bit digital data DT corresponding to the grayscale 23 shown in Figure 3 is received. In this case, since the upper two bits of the digital data DT are not

[11] , the control unit 40 (40_1) does not send the disable signals DS (DS1, DS2). As a result, from the beginning time ts of period Tcy, switches 14, 14a, 14b, 14A, and 14B are in the ON state, switches 14C and 14D are in the OFF state, and the differential pair [11_1, 12_1] remains in the EVERY state.

[0080] In the next period Tcy, the control unit 40 (40_1) receives 5-bit digital data DT corresponding to the grayscale 24 shown in Figure 3. At this time, the upper two bits of the digital data DT are

[11] , so the control unit 40 (40_1) sends a disable signal DS (DS1, DS2) at time tch, which is delayed by a predetermined delay time td from the beginning time ts of this period Tcy. As a result, at time tch, which is delayed by a delay time td from the beginning time ts, switches 14, 14a, 14b, 14A, and 14B switch from the ON state to the OFF state, and switches 14C and 14D switch from the OFF state to the ON state. Consequently, the differential pair [11_1, 12_1] transitions from the enabled state to the disabled state.

[0081] In the next period Tcy, the control unit 40 (40_1) receives 5-bit digital data DT corresponding to the grayscale 23 shown in Figure 3. Since the upper two bits of this digital data DT are not

[11] , the control unit 40 (40_1) does not send the disable signals DS (DS1, DS2). As a result, at the beginning of period Tcy ts, switches 14, 14a, 14b, 14A, and 14B switch from the off state to the on state, and switches 14C and 14D switch from the on state to the off state. Consequently, the differential pair [11_1, 12_1] transitions from the disabled state to the enabled state.

[0082] Thus, when the control unit 40 (40_1) receives digital data DT representing the gradation included in the gradation range QF as shown in Figure 3, it switches the differential pair [11_1, 12_1] from the enabled state to the disabled state at a time tch that is delayed by a predetermined delay time td from the beginning time ts of the period Tcy in which the digital data DT was received. In other words, if the differential pair [11_1, 12_1] is switched to the disabled state at the beginning time ts of the period Tcy, the number of differential pairs responsible for driving the output voltage Vout will be reduced by one stage, and the slew rate of the differential amplifier will decrease by that amount.

[0083] Therefore, when the control unit 40 (40_1) switches the differential pair [11_1, 12_1] to the disabled state, during the initial period of the period Tcy (ts~tch), it generates the output voltage Vout for all differential pairs, including the differential pair [11_1, 12_1], thereby suppressing a decrease in slew rate.

[0084] [Example 5] Figure 7 is a circuit diagram showing the configuration of a digital-to-analog converter 100_3, which is a third modified example of the digital-to-analog converter 100 shown in Figure 1.

[0085] Furthermore, the digital-to-analog converter 100_3 is identical to the digital-to-analog converter 100 shown in Figure 1, except that it uses a differential amplifier 10_3 instead of a differential amplifier 10. In Figure 7, the reference voltage generation unit 90 and the decoder 50 are omitted from the description.

[0086] The differential amplifier 10_3 employs a control unit 40_2 instead of the control unit 40 shown in Figure 1, and also uses transistors 13a_2~13a2 as current sources. K and switches 14_2~14_2 K Aside from the addition of a new component, the configuration is identical to that of the differential amplifier 10 shown in Figure 1.

[0087] The control unit 40_2 receives the upper-order (NK) bits of the digital data DT. If the upper-order (NK) bits of the control unit 40_2 represent a code where all of them are at logic level 1, it supplies the disable signal DS to switch 14 and the disable signal DSX to switches 14_2 to 14_2. K To supply.

[0088] Transistor 13a_2~13a_2 K Each source receives a low-voltage supply voltage VSSA, and the current corresponding to the magnitude of the bias voltage BN received at each gate is drawn by the differential pair [11_2, 12_2]~[11_2 K , 12_2 K It is generated as an auxiliary tail current that flows through each of the ].

[0089] Switch 14_2~14_2 K This is turned ON in response to the disable signal DSX, and transistors 13a_2~13a_2 K The auxiliary tail current generated by each of them is used in the differential pair [11_2, 12_2]~[11_2 K , 12_2 K This is added to each tail current flowing through ].

[0090] In other words, just like with the digital-to-analog converter 100 shown in Figure 7, the differential pair [11_1, 12_1] is disabled in the digital-to-analog converter 100_3 if the gradation indicated by the digital data DT falls within the gradation range QF shown in Figure 2 or Figure 3. Therefore, the number of differential pairs responsible for driving the output voltage Vout is reduced by one stage, and the slew rate of the differential amplifier decreases accordingly.

[0091] Therefore, in the digital-to-analog converter 100_3, when the differential pair [11_1, 12_1] is disabled, the differential pair [11_2, 12_2]~[11_2 K , 12_2 K By increasing the tail current flowing through each channel, the slew rate reduction of the differential amplifier is suppressed.

[0092] Furthermore, not only the digital-to-analog converter 100_3 mentioned above, but also 100, 100_1, or 100_2, have differential pairs [11_2, 12_2]~[11_2 K , 12_2 K Each of these is composed of an N-channel transistor, but they may also be composed of P-channel transistors.

[0093] Furthermore, in the example specification shown in Figure 2, the code for each gray level is represented by a binary code where the digital data DT corresponding to gray level 0 is

[0000] and the digital data DT corresponding to gray level 15 is

[1111] .

[0094] However, the digital data DT may be an inverted version of the logic level of the binary code shown in the specification example in Figure 2, representing grayscale levels 0 to 15. For example, the digital data DT corresponding to grayscale level 0 would be

[1111] , and the digital data DT corresponding to grayscale level 15 would be

[0000] . In this case, the control units (40, 40_1, 40_2) deactivate the differential pair [11_1, 12_1] when the upper (NK) bits of the N-bit digital data fragment, for example, the upper 2 bits of the 4-bit digital data DT in the specification example in Figure 2, are both at logic level 0. In other words, the control unit controls the differential pair [11_1, 12_1] to deactivate when it receives a predetermined code in which all of the upper (NK) bits of the digital data fragment (DT) are at either logic level 0 or 1. Furthermore, upon receiving a digital data fragment (DT) containing such a predetermined code, the decoder (50) will select the maximum or minimum reference voltage (e.g., V0 or V4) from among several reference voltages (e.g., V0 to V4 in Figure 2) as the first or second voltage.

[0095] In short, the digital-to-analog converter of this disclosure may include the following reference voltage generator, differential amplifier, and decoder.

[0096] The reference voltage generation unit (90) generates a plurality of reference voltages (V0 to Vj) having different voltage values ​​from each other.

[0097] The decoder (50) selects two reference voltages with adjacent voltage values ​​from among several reference voltages, based on N (where N is an integer of 3 or more) bits of digital data (DT), as the first and second voltages (e.g., [V0, V1], [V1, V2], [V2, V3], or [V3, V4]). Then, the decoder (50) processes the multiple input terminals (t) of the differential amplifier. <1> ~t<2 K >) are supplied with one or the other or both of the first and second voltages. The differential amplifier (10, 10_1~10_3) includes the following multiple differential pairs, amplification stages, and control. Multiple differential pairs ([11_1, 12_1]~[11_2K , 12_2 K ]) has multiple input terminals (t <1> ~t<2 K The differential has a differential and outputs an output voltage (Vout) that corresponds to the average value of the voltages received at each of the multiple input terminals. Each of the multiple differential pairs includes an inverting input terminal to which the output voltage is commonly input, a non-inverting input terminal to which one of the voltages received at the multiple input terminals is supplied as the input voltage, and an output pair, and the output pairs of each are commonly connected to each other. The amplification stage (30) generates the output voltage by amplification based on the output of one or both of the commonly connected output pairs.

[0098] The control units (40, 40_1, 40_2) control one of the differential pairs ([11_1, 12_1]) of the multiple differential pairs to an inactive state when the upper (NK) bits (K is an integer of 2 or more less than N) of a digital data piece represent a predetermined code (for example, all bits are at logical level 0 or 1).

[0099] Furthermore, if the control unit disables one differential pair, the differential amplifier outputs one voltage level from among 2 to the power of K voltage levels, which include multiple voltages obtained by interpolating between the first and second voltages (e.g., [V0, V1], [V1, V2], [V2, V3], or [V3, V4]) based on the lower K bits of the digital data piece, and the first and second voltages themselves, as the output voltage (Vout) (for example, Figure 2 or Figure 3). On the other hand, if the control unit does not disable this one differential pair, the differential amplifier outputs one voltage level from among 2 to the power of K voltage levels, which include multiple voltages obtained by interpolating between the first and second voltages as described above, and the voltage excluding one of the first and second voltages, as the output voltage (Vout).

[0100] [Example 6] Figure 8 is a block diagram showing the configuration of a data driver 18 including a digital-to-analog converter according to this disclosure, and a display device 200 including the data driver 18.

[0101] The display device 200 includes a display panel 15, a display controller 16, a scanning driver 17, and a data driver 18.

[0102] The display panel 15 is made of, for example, a liquid crystal or organic EL panel, and includes m horizontal scan lines GL1 to GLm (where m is a natural number of 2 or more) extending horizontally in the 2D screen, and n data lines DL1 to DLn (where n is a natural number of 2 or more) extending vertically in the 2D screen. Display cells, which are responsible for pixels, are formed at each intersection of the horizontal scan lines and the data lines.

[0103] The display controller 16 generates a digital video signal DVS based on the video signal VD, which includes various control signals such as a start pulse, a clock signal CLK, vertical and horizontal synchronization signals, and a sequence of digital video data fragments representing the brightness level of each pixel.

[0104] The display controller 16 generates a scanning timing signal synchronized with the horizontal synchronization signal described above and supplies it to the scanning driver 17, and also supplies the video digital signal DVS described above to the data driver 18.

[0105] The scanning driver 17 sequentially applies horizontal scanning pulses to each of the horizontal scanning lines GL1 to GLm of the display panel 15 based on the scanning timing signal supplied from the display controller 16.

[0106] The data driver 18 includes a shift register 80, a data register latch 70, a level shifter 60, a reference voltage generator 90, n decoders 50, and n differential amplifiers 10.

[0107] The display controller 16 generates a digital video signal DVS based on the video signal VD, which includes various control signals such as a start pulse, a clock signal CLK, vertical and horizontal synchronization signals, and a series of digital video data fragments representing the brightness level of each pixel as a digital value, and supplies this to the data driver 18.

[0108] The shift register 80 generates multiple latch timing signals in synchronization with the clock signal CLK to select a latch in response to a start pulse included in the video digital signal DVS, and supplies these signals to the data register latch 70.

[0109] Based on each of the latch timing signals supplied from the shift register 80, the data register latch 70 captures a predetermined number (e.g., n) of video digital data fragments included in the video digital signal DVS, and supplies n video digital data signals representing each video digital data fragment to the level shifter 60.

[0110] The level shifter 60 applies a level shift process to each of the n video digital data signals supplied from the data register latch 70, increasing the signal amplitude of each signal, and supplies the n level-shifted video digital data signals obtained from this process to each decoder 50.

[0111] The reference voltage generation unit 90 receives a DC reference power supply voltage VGH and a reference power supply voltage VGL that is lower than the reference power supply voltage VGH. Based on the reference power supply voltages VGH and VGL, the reference voltage generation unit 90 generates reference voltages V0 to Vj, each with a different voltage value, and supplies these reference voltages V0 to Vj to each of the n decoders 50, which are provided corresponding to the n output channels of the data driver 18.

[0112] Each decoder 50 selects a pair of reference voltages from the above-mentioned group of reference voltages that correspond to the video digital data signal level-shifted by the level shifter 60. Then, each decoder 50 supplies the selected pair of reference voltages as two voltages (VA, VB) to the differential amplifiers 10, which are provided corresponding to each of the n output channels of the data driver 18.

[0113] The differential amplifier 10 generates one of, for example, 16 levels of output voltage Vout obtained by interpolating between the input voltages VA and VB, and outputs a drive signal having this output voltage Vout. At this time, the n drive signals output from the n differential amplifiers 10 are supplied as drive signals S1 to Sn to the data lines DL1 to DLn of the display panel 15, respectively.

[0114] Here, the decoder 50, differential amplifier 10, and reference voltage generation unit 90 provided for each output of the data driver 18 shown in Figure 8 are the digital-to-analog converters 100, 100_1 to 100_3 shown in Figures 1, 4, 5, or 7.

[0115] In other words, each decoder 50 shown in Figure 8 selects a pair of adjacent voltages (VA, VB) from the reference voltages V0 to Vj generated by the reference voltage generation unit 90 based on the video digital data signal supplied from the level shifter 60. Then, each decoder 50 sends the two selected voltages (VA, VB) to the input terminal t of the differential amplifier 10. <1> ~t<2 K > Distribute and supply to >

[0116] Therefore, by configuring the output stage of the data driver 18 with digital-to-analog converters 100, 100_1 to 100_3, it becomes possible to convert the video digital signal DVS into an analog drive signal with a wide dynamic range in the range of reference voltage V0 to Vj generated by the reference voltage generation unit 90 with high precision and output it.

[0117] Furthermore, this disclosure is not limited to the embodiments described above, and various improvements and design modifications are possible without departing from the spirit of this disclosure.

[0118] [Note] This specification discloses the following configuration:

[0119] (Composition 1) A digital-to-analog conversion circuit that converts an N-bit (N is an integer greater than or equal to 3) digital data fragment into an analog output voltage and outputs it, comprising: a reference voltage generation unit that generates a plurality of reference voltages having different voltage values; a differential amplifier having a plurality of input terminals and outputting a voltage corresponding to the average value of the voltages received at each of the plurality of input terminals as the output voltage; and a unit that receives the digital data fragment and, based on the digital data fragment, selects two reference voltages with close voltage values ​​from the plurality of reference voltages as the first voltage and the second voltage, and applies one or the other of the first voltage and the second voltage to each of the plurality of input terminals of the differential amplifier. A digital-to-analog conversion circuit comprising: a decoder that distributes and supplies both; a differential amplifier comprising: a plurality of differential pairs, each including an inverting input terminal into which the output voltage is commonly input, a non-inverting input terminal into which one of the voltages received at the plurality of input terminals is supplied as an input voltage, and an output pair, the respective output pairs of which are commonly connected; an amplification stage that generates the output voltage by amplification based on the output of one or both of the commonly connected output pairs; and a control unit that controls one of the plurality of differential pairs to an inactive state when the upper (NK) bit (K is an integer of 2 or more less than N) of the digital data piece represents a predetermined code.

[0120] (Configuration 2) The differential amplifier outputs, when the control unit puts the 1 differential pair into the deactivated state, one of 2 to the power of K voltage levels, which include a plurality of voltages obtained by interpolating between the first voltage and the second voltage based on the lower K bits of the digital data piece, and the first voltage and the second voltage, as the output voltage; and when the control unit does not put the 1 differential pair into the deactivated state, one of 2 to the power of K voltage levels, which includes a plurality of voltages obtained by interpolating between the first voltage and the second voltage based on the lower K bits of the digital data piece, and a voltage excluding one of the first voltage and the second voltage, as the output voltage, the digital-to-analog conversion circuit according to configuration 1 above.

[0121] (Composition 3) The digital-to-analog conversion circuit according to configuration 1 or 2, wherein the predetermined code is a code in which all of the upper-order (NK) bits of the digital data piece are at one of logic levels, 0 or 1, and when the decoder receives the digital data piece in which the upper-order (NK) bits are the predetermined code, it selects the largest or smallest reference voltage among the plurality of reference voltages as the first voltage or the second voltage.

[0122] (Composition 4) The decoder is a digital-to-analog conversion circuit according to any one of the above configurations 1 to 3, comprising: a first sub-decoder that selects a first voltage and a second voltage from a plurality of reference voltages based on the upper (NK) bits of the digital data piece; and a second sub-decoder that, based on the lower K bits of the N-bit digital data piece, distributes and supplies one or the other or both of the first voltage and the second voltage selected by the first sub-decoder to each of the plurality of input terminals of the differential amplifier.

[0123] (Composition 5) The digital-to-analog conversion circuit according to any one of the above configurations 1 to 4, wherein the differential amplifier is composed of 2 to the power of K differential pairs having identical characteristics.

[0124] (Composition 6) The digital-to-analog conversion circuit according to any one of the above configurations 1 to 5, wherein the control unit includes a first switch that controls the 1 differential pair to the inactive state by being turned off when the upper (NK) bit of the digital data piece represents a predetermined code, thereby interrupting the tail current flowing to the 1 differential pair.

[0125] (Composition 7) A digital-to-analog conversion circuit according to any one of the above configurations 1 to 6, comprising a first node that connects one output of each of the output pairs of the plurality of differential pairs in common, and a second node that connects the other output of each of the output pairs of the plurality of differential pairs in common, wherein the control unit includes a switch circuit that controls the one differential pair to the inactive state by disconnecting the connection between one output of the one differential pair and the first node, and by disconnecting the connection between the other output of the one differential pair and the second node, when the upper (NK) bit of the digital data piece represents a predetermined code.

[0126] (Composition 8) The digital-to-analog conversion circuit according to any one of the above configurations 1 to 7, wherein the 1 differential pair includes a first transistor whose gate is the non-inverting input terminal and a second transistor whose gate is the inverting input terminal, and the control unit includes a switch circuit that controls the 1 differential pair to the inactive state by interrupting the supply of the first or second voltage to the non-inverting input terminal of the 1 differential pair and applying a predetermined low potential to the gate of the first transistor to turn off the first transistor, and interrupting the supply of the output voltage to the inverting input terminal of the 1 differential pair and applying a predetermined low potential to the gate of the second transistor to turn off the second transistor, when the upper (NK) bit of the digital data piece represents a predetermined code.

[0127] (Composition 9) The digital-to-analog conversion circuit receives a sequence of digital data fragments at a predetermined period, and the control unit, upon receiving a digital data fragment in which the upper-order (NK) bit represents a predetermined code, deactivates the differential pair 1 at a predetermined delay time from the beginning of the period in which the digital data fragment was received, according to any one of the above configurations 6 to 8.

[0128] (Composition 10) The control unit controls the 1 differential pair to the inactive state and increases the current value of the tail current flowing to each of the differential pairs from the plurality of differential pairs excluding the 1 differential pair, the digital-to-analog conversion circuit according to any one of the above configurations 6 to 8.

[0129] (Composition 11) A display driver comprising a plurality of the digital-to-analog converters described in Configuration 1 above, wherein each digital video data piece representing the brightness level of each pixel as a digital value is converted by the plurality of digital-to-analog converters into a plurality of output voltages, each having an analog voltage value, and a plurality of drive signals each having a plurality of output voltages are supplied to a plurality of data lines of the display panel. [Explanation of Symbols]

[0130] 10, 10⁻¹, 10⁻², 10⁻³ differential amplifier 11_1~11_2 K , 12_1~12_2 K Differential 14, 14a, 14b, 14A~14D switches 40, 40_1, 40_2 Control Unit 100, 100_1, 100_2, 100_3 Digital-to-Analog Converter

Claims

1. A digital-to-analog conversion circuit that converts N bits (where N is an integer greater than or equal to 3) of digital data into an analog output voltage and outputs it, A reference voltage generation unit that generates multiple reference voltages having different voltage values ​​from each other, A differential amplifier having multiple input terminals, which outputs a voltage corresponding to the average value of the voltages received at each of the multiple input terminals as the output voltage, The differential amplifier includes a decoder that receives the digital data fragment, selects two reference voltages with close voltage values ​​from among the plurality of reference voltages based on the digital data fragment, and supplies one or the other or both of the first and second voltages to each of the plurality of input terminals of the differential amplifier, The differential amplifier is Each of the following differential pairs includes an inverting input terminal into which the output voltage is commonly input, a non-inverting input terminal into which one of the voltages received at the plurality of input terminals is supplied as the input voltage, and an output pair, with each of the output pairs being commonly connected to each other. An amplification stage that generates the output voltage by amplification based on the output of one or both outputs of the commonly connected output pair, A digital-to-analog conversion circuit including a control unit that controls one of the plurality of differential pairs to an inactive state when the upper (N-K) bits (where K is an integer of 2 or more less than N) of the digital data piece represent a predetermined code.

2. The differential amplifier is When the control unit puts the 1 differential pair into the deactivated state, it outputs one voltage level from among 2 to the power of K voltage levels, which include a plurality of voltages obtained by interpolating between the first voltage and the second voltage based on the lower K bits of the digital data piece, and the first voltage and the second voltage, as the output voltage. If the control unit does not put the first differential pair into the deactivated state, the control unit outputs one voltage level from among 2 to the power of K voltage levels, which include the plurality of voltages obtained by interpolating between the first voltage and the second voltage based on the lower K bits of the digital data piece, and the voltage excluding one of the first voltage and the second voltage, as the output voltage, the digital-to-analog conversion circuit according to claim 1.

3. The predetermined code is a code in which all of the upper (N-K) bits of the digital data piece are at one of two logic levels, 0 or 1. The digital-to-analog conversion circuit according to claim 1 or 2, wherein when the decoder receives the digital data piece in which the upper (N-K) bits are a predetermined code, it selects the largest or smallest reference voltage among the plurality of reference voltages as the first or second voltage.

4. The decoder mentioned above is A first sub-decoder that selects the first voltage and the second voltage from the plurality of reference voltages based on the upper (N-K) bits of the digital data piece, The digital-to-analog conversion circuit according to claim 1, further comprising: a second sub-decoder that, based on the lower K bits of the N-bit digital data fragment, distributes and supplies one or the other or both of the first voltage and the second voltage selected by the first sub-decoder to each of the plurality of input terminals of the differential amplifier.

5. The digital-to-analog conversion circuit according to claim 1, wherein the differential amplifier is composed of 2 to the power of K differential pairs having identical characteristics.

6. The digital-to-analog conversion circuit according to claim 1, wherein the control unit includes a first switch that controls the first differential pair to the inactive state by being turned off when the upper (N-K) bits of the digital data piece represent a predetermined code, thereby interrupting the tail current flowing to the first differential pair.

7. It includes a first node that connects one output of each of the plurality of differential pairs to each other, and a second node that connects the other output of each of the plurality of differential pairs to each other. The control unit, The digital-to-analog conversion circuit according to claim 1, which includes a switch circuit that controls the first differential pair to the inactive state by disconnecting the connection between one output of the first differential pair and the first node, and by disconnecting the connection between the other output of the first differential pair and the second node, when the upper (N-K) bits of the digital data piece represent the predetermined code.

8. The differential pair described above includes a first transistor whose gate is the non-inverting input terminal and a second transistor whose gate is the inverting input terminal, The control unit, The digital-to-analog conversion circuit according to claim 1, which includes a switch circuit that controls the differential pair to the inactive state by, when the upper (N-K) bits of the digital data piece represent the predetermined code, by applying a predetermined low potential to the gate of the first transistor to interrupt the supply of the first or second voltage to the non-inverting input terminal of the differential pair and turn off the first transistor, and by applying a predetermined low potential to the gate of the second transistor to interrupt the supply of the output voltage to the inverting input terminal of the differential pair and turn off the second transistor.

9. The digital-to-analog conversion circuit receives the sequence of digital data fragments at a predetermined period, The digital-to-analog conversion circuit according to any one of claims 6 to 8, wherein the control unit, upon receiving the digital data piece in which the upper-order (N-K) bits represent a predetermined code, deactivates the differential pair 1 at a predetermined delay time from the beginning of the cycle in which the digital data piece was received.

10. The control unit controls the 1 differential pair to the inactive state and increases the current value of the tail current flowing to each of the differential pairs from the plurality of differential pairs excluding the 1 differential pair, the digital-to-analog conversion circuit according to any one of claims 6 to 8.

11. A plurality of the digital-to-analog converters described in claim 1, A display driver that converts each digital video data fragment, which represents the brightness level of each pixel as a digital value, into a plurality of output voltages, each having an analog voltage value, using a plurality of digital-to-analog converters, and supplies a plurality of drive signals, each having a plurality of output voltages, to a plurality of data lines of a display panel.

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