Switching control circuits, flyback converters, power supplies, and electrical equipment.

Abstract

This invention provides a switching control circuit that suppresses malfunctions of the protection mechanism regardless of the input voltage. [Solution] The switching control circuit (1, 1A, 1B) includes a first control circuit (3) configured to turn off the switching element (M1) when a current detection signal (Vcs) corresponding to the current (Ip) flowing through the switching element (M1) on the primary side of the flyback transformer (FT) reaches a first threshold (V1), and a second control circuit (4) configured to turn off the switching element (M1) after a fixed time (Tm) has elapsed since the switching element (M1) was turned on while the current detection signal (Vcs) had not reached a second threshold (V2) which is smaller than the first threshold (V1). The second control circuit (4) includes a fixed time setting circuit (42, 44, 45) configured to change the fixed time (Tm).

Description

Technical Field

[0001] The present disclosure relates to a switching control circuit, a flyback converter using the switching control circuit, a power supply device using the flyback converter, and an electrical device using the power supply device.

Background Art

[0002] In a control IC (Integrated Circuit) used in an isolated power supply device using a switching element, a current detection unit is used to monitor the primary current flowing through a primary power switch (Si-MOSFET [Metal Oxide Semiconductor Field Effect Transistor], SiC-MOSFET, or GaN-HEMT (High Electron Mobility Transistor)), and the on / off of the power switch is often controlled according to the primary current (see, for example, Patent Document 1).

[0003] In such an isolated power supply device, a protection mechanism for protecting the control IC is provided when a short circuit occurs in the current detection unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In such a power supply device, when the input voltage is low, the protection mechanism may malfunction.

[0006] A switching control circuit according to one aspect of the present disclosure is configured to control the switching of a switching element connected to the primary coil of a flyback transformer. The switching control circuit includes a first control circuit configured to turn off the switching element when a current detection signal output from a current detection circuit configured to detect the current flowing through the switching element reaches a first threshold, and a second control circuit configured to turn off the switching element after a fixed time has elapsed since the switching element was turned on while the current detection signal had not reached a second threshold smaller than the first threshold. The second control circuit includes a fixed time setting circuit configured to change the fixed time. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows the overall configuration of the power supply unit. [Figure 2] Figure 2 is a circuit diagram showing a fixed time setting circuit. [Figure 3] Figure 3 shows an example of the setting operation for setting the confirmed time. [Figure 4] Figure 4 shows an example of the setting operation for setting the fixed time when the source and ground of a switching element are short-circuited. [Figure 5] Figure 5 shows the configuration of the switching control circuit of the second embodiment. [Figure 6] Figure 6 shows an example of the setting operation for setting the confirmed time. [Figure 7] Figure 7 shows an example of a setting operation for setting the fixed time when the source and ground of a switching element are short-circuited. [Figure 8] Figure 8 shows the configuration of the switching control circuit of the third embodiment. [Figure 9] Figure 9 shows an example of the configuration of electrical equipment, including a power supply unit.

[0008] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced drawings, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In this specification, for the sake of simplification of description, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be indicated, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated.

[0009] In this specification, "connection" between any circuit element, wiring, or multiple parts forming a circuit includes both mechanical connection and electrical connection, in other words, a state in which electricity flows. In short, "to connect" includes "to connect electrically."

[0010] Furthermore, "ground" refers to a reference conductive part having a reference potential of 0V (zero volts), or the potential of 0V itself. The reference conductive part is formed of a conductor such as metal. In the embodiments of this disclosure, voltages shown without specifying a reference represent voltages relative to the ground voltage.

[0011] A switch can be either on or off. When the switch is on, there is conductivity between its two ends. Conversely, when the switch is off, there is no conductivity between its two ends. In the following explanation, the on state and the off state can also be simply referred to as on and off, respectively.

[0012] As an example of a switching element that constitutes a switch, a MOS field-effect transistor (Metal Oxide Semiconductor Field Effect Transistor) is sometimes used. A MOS field-effect transistor is a transistor whose gate structure consists of at least three layers: "a layer made of a conductor or a semiconductor with low resistance such as polysilicon," "an insulating layer," and "a P-channel, N-channel, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field-effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. In the following explanation, a P-channel MOS field-effect transistor will be referred to as a PMOSFET, and an N-channel MOS field-effect transistor as an NMOSFET.

[0013] <First Embodiment> A first embodiment of the present disclosure will be described with reference to the drawings. Figure 1 is a diagram showing the overall configuration of the power supply unit 100. The power supply unit 100 shown in Figure 1 is an isolated DC / DC converter, or flyback converter, that electrically isolates the primary circuit system from the secondary circuit system and generates a desired output voltage Vout from the input voltage Vin input to the primary circuit system and outputs it to the secondary circuit system.

[0014] As shown in Figure 1, the power supply unit 100 comprises a switching control circuit 1, capacitors C1 and C2, diode D1, switching element M1 (NMOSFET in this figure), resistors R1 to R3, and a flyback transformer FT. Furthermore, when an AC input voltage is supplied to the power supply unit 100, a rectifier circuit (such as a diode bridge) that converts the AC input voltage to a DC input voltage Vin may be provided in the preceding stage.

[0015] Resistors R1 to R3 are connected in series. The first terminals of the series-connected resistors R1, R2, and R3 are connected to the application terminal of the supply voltage Vreg. The second terminals of the series-connected resistors R1, R2, and R3 are connected to ground. Resistors R1, R2, and R3 divide the supply voltage Vreg, supplying the voltage at the connection point of resistor R1 and resistor R2 as the first threshold voltage V1 and the voltage at the connection point of resistor R2 and resistor R3 as the second threshold voltage V2 to the switching control circuit 1. Note that the first threshold voltage V1 is greater than the second threshold voltage V2.

[0016] The flyback transformer FT includes a primary coil Lp and a secondary coil Ls configured to be magnetically coupled to each other. The number of turns Np and Ns of the primary coil Lp and secondary coil Ls, respectively, can be arbitrarily adjusted to obtain the desired output voltage Vout (= Vin × (Ns / Np) × (Ton / Toff), where Ton is the on period of the switching element M1 and Toff is the off period). For example, the more turns Np or fewer turns Ns, the lower the output voltage Vout will be, and conversely, the fewer turns Np or more turns Ns, the higher the output voltage Vout will be.

[0017] The first terminals of both capacitor C1 and primary coil Lp are connected to the input voltage Vin. The second terminal of capacitor C1 is connected to ground. The second terminal of primary coil Lp is connected to the drain of switching element M1. The gate of switching element M1 is connected to the input gate drive signal G1. The source of switching element M1 is connected to the current detection circuit 2, which will be described later.

[0018] The first terminal of the secondary coil Ls is connected to the anode of diode D1. The cathode of diode D1 and the first terminal of capacitor C1 are both connected to the output terminal of the output voltage Vout. The second terminals of both the secondary coil Ls and capacitor C1 are both connected to ground.

[0019] The switching element M1 turns on / off the primary current Ip flowing through the primary coil Lp by conducting / interrupting the current path from the application terminal of the input voltage Vin to the ground of the primary circuit system via the primary coil Lp according to the gate drive signal G1. When the switching element M1 is an NMOSFET, the switching element M1 turns on when the gate drive signal G1 is at a high level and turns off when the gate drive signal G1 is at a low level. Also, when the switching element M1 is a PMOSFET, the operation is opposite to that of the NMOSFET.

[0020] The basic operation of the power supply device 100 will be briefly described. During the on-period Ton of the switching element M1, a primary current Ip flows from the application terminal of the input voltage Vin through the primary coil Lp and the switching element M1 to the ground. As a result, electrical energy is stored in the primary coil Lp.

[0021] Thereafter, when the switching element M1 is turned off, an induced voltage is generated in the secondary coil Ls magnetically coupled to the primary coil Lp. As a result, a secondary current Is flows from the secondary coil Ls through the diode D1 and the capacitor C2 to the ground. At this time, an output voltage Vout obtained by rectifying and smoothing the induced voltage of the secondary coil Ls is applied to the output terminal of the output voltage Vout.

[0022] Thereafter, by turning on / off the switching element M1, the same switching output operation as described above is repeated.

[0023] <Switching control circuit 1 (First embodiment)> Next, the details of the switching control circuit 1 will be described with reference to the drawings. The switching control circuit 1 of this configuration example is a semiconductor device (so-called power control IC) provided in the primary circuit system and serving as the control main body of the power supply device 100.

[0024] As shown in FIG. 1, the switching control circuit 1 includes a current detection circuit 2, a first control circuit 3, a second control circuit 4, a logic circuit 5, a drive circuit 6, and a voltage dividing circuit 7.

[0025] The current detection circuit 2 is connected between the source and ground of the switching element M1 and generates a current detection signal Vcs corresponding to the primary current Ip (corresponding to the detection current) flowing through the ON-state switching element M1. The current detection circuit 2 includes a sense resistor 21. The sense resistor 21 is connected between the source and ground of the switching element M1 and outputs the voltage across its terminals as the current detection signal Vcs. Therefore, the current detection signal Vcs (=Ip × R2, where Rcs is the resistance value of the sense resistor 21) becomes higher as the primary current Ip increases and lower as the primary current Ip decreases.

[0026] The first control circuit 3 includes a first comparator 31. The first comparator 31 compares the current detection signal Vcs input to the non-inverting input terminal (+) with a first threshold V1 input to the inverting input terminal (-) and generates a current limiting signal CSLIM. Therefore, the current limiting signal CSLIM becomes high level when the current detection signal Vcs is higher than the first threshold V1, and becomes low level when the current detection signal Vcs is lower than the first threshold V1. The current limiting signal CSLIM is a signal that turns off the switching element M1. In other words, the first control circuit 3 is a circuit configured to turn off the switching element M1 when the detection signal reaches the first threshold. The current limiting signal CSLIM is a signal that limits the current flowing through the switching element M1, or in other words, a signal that limits overcurrent.

[0027] The second control circuit 4 includes a second comparator 41, a fixed time setting circuit 42, and an AND gate 43. The second comparator 41 compares a second threshold V2 input to the non-inverting input terminal (+) with a current detection signal Vcs input to the inverting input terminal (-) to generate a short-circuit detection signal SHT. Therefore, the short-circuit detection signal SHT is low level when the current detection signal Vcs is higher than the second threshold V2, and high level when the current detection signal Vcs is lower than the second threshold V2. For example, if the source and ground of the switching element M1 are short-circuited due to a malfunction in the current detection circuit 2, a high-level short-circuit detection signal SHT will continue to be output.

[0028] The fixed time setting circuit 42 sets the fixed time Tm by generating a time setting signal STM according to the input voltage Vin (in this embodiment, the voltage divider Vdiv of the input voltage Vin) applied to the switching element M1. More specifically, the fixed time setting circuit 42 shortens the fixed time Tm as the input voltage Vin increases, and extends the fixed time Tm as the input voltage Vin decreases.

[0029] The AND gate 43 outputs a short-circuit stop signal SHT2 by performing a logical AND operation between the short-circuit detection signal SHT and the time setting signal STM. Therefore, the short-circuit stop signal SHT2 is high when both the short-circuit detection signal SHT and the time setting signal STM are high, and low otherwise.

[0030] In the switching control circuit 1, the current detection circuit 2 adjusts the duty cycle of the switching element M1 and controls the output voltage Vout based on the current detection signal Vcs corresponding to the primary current Ip. At this time, if the source and ground of the switching element M1 are short-circuited, the current detection signal Vcs cannot be detected, and the output voltage Vout cannot be controlled. If the primary current Ip becomes large, a malfunction may occur in the switching element M1. To suppress such malfunctions, the second control circuit 4 detects that the source and ground of the switching element M1 are short-circuited and controls the switching element M1 so that excessive current does not flow even if a short circuit occurs.

[0031] In the switching control circuit 1, if the source and ground of the switching element M1 are short-circuited, the current detection signal Vcs will not rise. Therefore, the switching control circuit 1 determines that a short circuit has occurred if the current detection signal Vcs does not exceed the second threshold V2 for a predetermined time, in this case, the fixed time Tm, and controls the switching element M1 to the off state. The fixed time setting circuit 42 adjusts the length of the fixed time Tm to suppress the false determination that a short circuit has occurred even when the input voltage Vin is low and the rise of the current detection signal Vcs is gradual. Details of the operation of the switching control circuit 1 will be described later.

[0032] Logic circuit 5 includes an OR gate 51 and an RS flip-flop 52. The OR gate 51 outputs a reset signal RST by performing a logical OR operation between the current limiting signal CSLIM and the short-circuit stop signal SHT2. Therefore, the reset signal RST is high when at least one of the current limiting signal CSLIM and the short-circuit stop signal SHT2 is high, and low when both are low.

[0033] The RS flip-flop 52 switches the logic level of the gate control signal S1 output from the output terminal (Q) in response to the set signal SET input to the set terminal (S) and the reset signal RST input to the reset terminal (R). For example, the gate control signal S1 is set to a high level triggered by the pulse edge (e.g., rising edge) of the set signal SET, and reset to a low level triggered by the pulse edge (e.g., rising edge) of the reset signal RST.

[0034] The drive circuit 6 includes a gate driver. The gate driver receives the input of the gate control signal S1 and generates a gate drive signal G1. The gate drive signal G1 is, for example, high level when the gate control signal S1 is high level, and low level when the gate control signal S1 is low level. The drive circuit 6, for example, amplifies the gate control signal S1 to generate a gate drive signal G1 with a voltage that can control the switching element M1 to the ON state. In other words, the gate control signal S1 is a signal that notifies the drive circuit 6 of the ON duty cycle of the switching element M1, and the gate drive signal G1 is a signal for driving the switching element M1.

[0035] The voltage divider circuit 7 includes resistors 71 and 72. Resistors 71 and 72 are connected in series between the application terminal of the input voltage Vin and ground, and output a divided voltage Vdiv from the connection point of resistors 71 and 72. The divided voltage Vdiv is supplied to the fixed time setting circuit 42 of the second control circuit 4. Note that if the input voltage Vin is within the input dynamic range of the fixed time setting circuit 42, it is not necessarily required to provide the voltage divider circuit 7, and the input voltage Vin may be directly input to the fixed time setting circuit 42.

[0036] Details of the fixed time setting circuit 42 will be described with reference to the drawings. Figure 2 is a circuit diagram showing the fixed time setting circuit 42. Figure 2 shows the voltage divider circuit 7 and the fixed time setting circuit 42. As shown in Figure 2, the fixed time setting circuit 42 includes a buffer 421, a current mirror 422, a transistor 423 (NMOSFET), a current source 424, a slope voltage generation circuit 425, a comparator 426, a resistor 427, and an inverter circuit 428.

[0037] The non-inverting input terminal (+) of buffer 421 is connected to the application terminal of the voltage divider voltage Vdiv. The inverting input terminal (-) of buffer 421 is connected to the application terminal of the feedback voltage Vfb (= the connection point between the source of transistor 423 and the first terminal of resistor 427). The output terminal of buffer 421 is connected to the gate of transistor 423. Buffer 421, connected in this manner, controls the gate of transistor 423 so that the difference between the voltage divider voltage Vdiv and the feedback voltage Vfb is zero; in other words, so that the feedback voltage Vfb matches the voltage divider voltage Vdiv.

[0038] The drain of transistor 423 is connected to the input terminal of current mirror 422 (= input terminal of reference current Ir). The source of transistor 423 and the first terminal of resistor 427 are both connected to the inverting input terminal (-) of buffer 421 as the application terminals for the feedback voltage Vfb. The second terminal of resistor 427 is connected to ground. In this way, transistor 423 and resistor 427 are connected in series on the current path through which the reference current Ir flows, and they output a feedback voltage Vfb (= Ir × R4, where R4 is the resistance value of resistor 427) corresponding to the reference current Ir from the connection point between them. Therefore, the reference current Ir (= Vdiv / R4) increases as the input voltage Vin increases and decreases as the input voltage Vin decreases.

[0039] The current mirror 422 has transistors M41 and M42. Transistors M41 and M42 are PMOSFETs. The sources of transistors M41 and M42 are connected to the application terminals of the supply voltage Vreg. The gates of transistors M41 and M42 are connected to each other, and the connection point of the gates of transistors M41 and M42 is connected to the connection point of the drain of transistor M41 and the drain of transistor 423. The drain of transistor M42 is connected to the output terminal of the current mirror 422. In other words, an adjustment current I1, which is a replica of the reference current Ir, is output from the drain of transistor M42.

[0040] The buffer 421, current mirror 422, and transistor 423 constitute the current generation circuit 40X.

[0041] The current mirror 422 generates a regulating current I1 by duplicating the reference current Ir. The drain of transistor M42 of the current mirror 422 is connected to the output terminal of the current source 424. Therefore, at the connection point between the output terminal of the current mirror 422 and the output terminal of the current source 424, the regulating current I1 and the reference current Id output from the current source 424 are combined.

[0042] The current source 424 is a circuit configured to output a reference current Id based on the supply voltage Vreg. The input terminal of the current source 424 is connected to the application terminal of the supply voltage Vreg, and its output terminal is connected to the output terminal of the current mirror 422.

[0043] The slope voltage generation circuit 425 includes a capacitor C3 and a transistor M43 (in this case, an NMOSFET). The drain of transistor M43 and the first terminal of capacitor C3 are both connected to the connection point between the output terminal of current mirror 422 and the output terminal of current source 424. The source of transistor M43 and the second terminal of capacitor C3 are both connected to ground.

[0044] The gate of transistor M43 is connected to inverter circuit 428. The gate control signal S1 output from RS flip-flop 52 of logic circuit 5 is input to the input terminal of inverter circuit 428. An inverted gate control signal S1B, which is the inverted gate control signal, is output from the output terminal of inverter circuit 428. In other words, the inverted gate control signal S1B is input to the gate of transistor M43. Transistor M43 is controlled on / off by the inverted gate control signal S1B. Transistor M43 is in the off state when the inverted gate control signal S1B is low level, and in the on state when the inverted gate control signal S1B is high level.

[0045] When transistor M43 is in the off state, capacitor C3 of the slope voltage generation circuit 425 is charged by the combined current Ic (=I1+Id), which is the sum of the adjustment current I1 output from the current mirror 422 and the reference current Id output from the current source 424. As a result, the slope voltage Vslp drawn from the first terminal of capacitor C3 rises with a slope corresponding to the combined current Ic. On the other hand, when transistor M43 is in the on state, the terminals of capacitor C3 are short-circuited via transistor M43. Therefore, the charge stored in capacitor C3 is discharged, and the slope voltage Vslp is reset to 0V. In this way, the slope voltage Vslp becomes a slope waveform (sawtooth waveform) synchronized with the inverting gate control signal S1B.

[0046] Furthermore, the adjustment current I1, i.e., the combined current Ic, increases as the input voltage Vin increases and decreases as the input voltage Vin decreases. Consequently, the slope of the slope voltage Vslp increases as the input voltage Vin increases and decreases as the input voltage Vin decreases. In other words, the slope of the slope voltage Vslp changes according to the input voltage Vin.

[0047] Comparator 426 generates a time setting signal STM by comparing a reference voltage V3 input to the inverting input terminal (-) with a slope voltage Vslp input to the non-inverting input terminal (+). The time setting signal STM is low when the reference voltage V3 is higher than the slope voltage Vslp, and high when the reference voltage V3 is lower than the slope voltage Vslp. The time setting signal STM is used as a trigger signal to set the expiration timing of the confirmation time Tm, which is the time until it is confirmed that the source and ground of the switching element M1 are short-circuited (details will be described later).

[0048] In the fixed time setting circuit 42, the reference current Id output from the current source 424 is supplied to increase the adjustment current I1 output from the current mirror 422. If the adjustment current I1 alone is sufficient to output a slope voltage Vslp with a slope sufficient to set the fixed time Tm from the slope voltage generation circuit 425, the current source 424 may be omitted.

[0049] <Confirmed time setting operation> Figure 3 shows an example of the setting operation for setting the fixed time Tm. Figure 4 shows an example of the setting operation for setting the fixed time Tm when the source and ground of the switching element M1 are short-circuited.

[0050] In the diagrams shown in Figures 3 and 4, the input voltage Vin, set signal SET, primary current Ip, current detection signal Vcs, gate control signal S1, inverting gate control signal S1B, gate drive signal G1, current limiting signal CSLIM, short circuit detection signal SHT, short circuit stop signal SHT2, reset signal RST, slope voltage Vslp, and time setting signal STM are shown from top to bottom.

[0051] Furthermore, Figure 3 shows the operation when the input voltage Vin is the first input voltage Vin1 from time t1 to t5, and the operation when the input voltage Vin2 is lower than the first input voltage Vin1 from time t6 to t10.

[0052] First, let's explain the operation of the switching control circuit 1 when the source and ground of the switching element M1 are not short-circuited. At time t1, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, and the gate drive signal G1 rises to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow, so the current detection signal Vcs rises with a slope corresponding to the primary current Ip. Note that at time t1, the current detection signal Vcs is smaller than the second threshold V2, so the short-circuit detection signal SHT is at a high level. Furthermore, since the time setting signal STM is at a low level, the short-circuit stop signal SHT2, which is the output of the AND gate 43, is at a low level.

[0053] Furthermore, at time t1, the divided voltage Vdiv is input to buffer 421, and transistor 423 is controlled. When transistor 423 is controlled, the divided voltage Vdiv, that is, the reference current Ir corresponding to the first input voltage Vin1, is drawn from current mirror 422, and an adjustment current I1, which is a duplicate of the reference current Ir, is output from current mirror 422.

[0054] At time t1, the inverting gate control signal S1B falls from a high level to a low level. As a result, transistor M43 turns off, and capacitor C3 is charged by the combined current Ic, which is the sum of the adjustment current I1 and the reference current Id. The slope voltage Vslp drawn from the first terminal of capacitor C3 rises with a slope corresponding to the combined current Ic.

[0055] At time t2, when the current detection signal Vcs becomes higher than the second threshold V2, the short-circuit detection signal SHT falls from a high level to a low level.

[0056] At time t3, when the slope voltage Vslp becomes higher than the reference voltage V3, the time setting signal STM rises to a high level. The time from time t1 to time t3 is the fixed time Tm (here, fixed time Tm1). At this time, since the short-circuit detection signal SHT is at a low level, the short-circuit stop signal SHT2 remains at a low level. In other words, in the switching control circuit 1, from the time the set signal SET rises to a high level until the fixed time Tm1 has elapsed, the short-circuit stop signal SHT2, which turns off the switching element M1, is kept at a low level, regardless of the level of the short-circuit detection signal SHT.

[0057] At time t4, when the current detection signal Vcs becomes higher than the first threshold V1, the current limiting signal CSLIM switches from a low level to a high level. This causes the reset signal RST to rise from a low level to a high level. Then, the gate control signal S1 and the gate drive signal G1 fall from a high level to a low level. As a result, the switching element M1 turns off.

[0058] Furthermore, at time t4, the inverting gate control signal S1B switches from a low level to a high level, the slope voltage generation circuit 425 is reset, and the slope voltage Vslp decreases to "0". As a result, the time setting signal STM switches from a high level to a low level.

[0059] The current detection signal Vcs decreases at a constant rate after the switching element M1 turns off. The short-circuit detection signal SHT switches from a low level to a high level when the current detection signal Vcs becomes less than the second threshold V2. In other words, the short-circuit detection signal SHT rises from a low level to a high level with a delay from time t4. Therefore, if the input voltage Vin is the first input voltage Vin1 and the current detection signal Vcs corresponding to the primary current Ip is detected, there is no period in which both the short-circuit detection signal SHT and the time setting signal STM are at a high level. Consequently, the short-circuit stop signal SHT2 does not rise to a high level. In other words, a short circuit between the source and ground of the switching element M1 is not detected.

[0060] Next, referring to times t6 to t10, we will explain the case where the input voltage Vin is the second input voltage Vin2.

[0061] At time t7, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, and the gate drive signal G1 rises to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow. This causes the current detection signal Vcs to rise with a slope corresponding to the primary current Ip. When the input voltage Vin is the second input voltage Vin2, the primary current Ip is smaller than when the first input voltage Vin1, and the slope of the current detection signal Vcs is smaller. At time t1, since the current detection signal Vcs is smaller than the second threshold V2, the short-circuit detection signal SHT is at a high level. Furthermore, since the time setting signal STM is at a low level, the short-circuit stop signal SHT2, which is the output of the AND gate 43, is at a low level.

[0062] Furthermore, at time t7, the divided voltage Vdiv is input to buffer 421, and transistor 423 is controlled. When transistor 423 is controlled, the divided voltage Vdiv, that is, the reference current Ir corresponding to the second input voltage Vin2, is drawn from current mirror 422, and an adjustment current I1, which is a duplicate of the reference current Ir, is output from current mirror 422.

[0063] At time t7, the inverting gate control signal S1B falls from a high level to a low level. As a result, transistor M43 turns off, and capacitor C3 is charged by the combined current Ic, which is the sum of the adjustment current I1 and the reference current Id. The slope voltage Vslp drawn from the first terminal of capacitor C3 rises with a slope corresponding to the combined current Ic. Since the second input voltage Vin2 is lower than the first input voltage Vin1, the slope of the slope voltage Vslp is smaller than when the input voltage Vin is the first input voltage Vin1.

[0064] At time t8, when the current detection signal Vcs becomes higher than the second threshold V2, the short-circuit detection signal SHT falls from a high level to a low level. Note that the slope of the current detection signal Vcs is smaller than when the input voltage Vin is the first input voltage Vin1. Therefore, the time Tm3 from time t7 to time t8 is longer than the time from time t1 to time t2.

[0065] At time t9, when the slope voltage Vslp becomes higher than the reference voltage V3, the time setting signal STM rises to a high level. The time from time t1 to time t3 is the fixed time Tm (here, fixed time Tm2). The slope of the slope voltage Vslp is smaller than when the input voltage Vin is the first input voltage Vin1. Therefore, fixed time Tm2 is longer than fixed time Tm1.

[0066] At this time, since the short-circuit detection signal SHT is at a low level, the short-circuit stop signal SHT2 remains at a low level. In other words, in the switching control circuit 1, from the time the set signal SET rises to a high level until the set time Tm2 has elapsed, the short-circuit stop signal SHT2, which turns off the switching element M1, is maintained at a low level regardless of the level of the short-circuit detection signal SHT.

[0067] At time t10, when the current detection signal Vcs becomes higher than the first threshold V1, the current limiting signal CSLIM switches from a low level to a high level. This causes the reset signal RST to rise from a low level to a high level. Then, the gate control signal S1 and the gate drive signal G1 fall from a high level to a low level. As a result, the switching element M1 turns off.

[0068] Furthermore, at time t10, the inverting gate control signal S1B switches from a low level to a high level, the slope voltage generation circuit 425 is reset, and the slope voltage Vslp decreases to "0". As a result, the time setting signal STM switches from a high level to a low level.

[0069] The current detection signal Vcs decreases at a constant rate after the switching element M1 turns off. Therefore, the short-circuit detection signal SHT rises from a low level to a high level with a delay from time t10. In other words, when the input voltage Vin is the first input voltage Vin1 and the current detection signal Vcs corresponding to the primary current Ip is detected, there is no period in which both the short-circuit detection signal SHT and the time setting signal STM are at a high level. Therefore, the short-circuit stop signal SHT2 does not rise to a high level. In other words, a short circuit between the source and ground of the switching element M1 is not detected.

[0070] In conventional switching control circuits, the set time Tm was fixed to a constant value. In this case, if the input voltage Vin is small and the time Tm3 is longer than the set time Tm, even if the source and ground of the switching element M1 are not short-circuited, the time setting signal STM may rise to a high level and the short-circuit stop signal SHT2 may rise to a high level before the short-circuit detection signal SHT falls to a low level. In this case, even though the switching control circuit is operating correctly, it may be mistakenly determined that the source and ground of the switching element M1 are short-circuited, and a sufficient output voltage Vout may not be output.

[0071] In the switching control circuit 1 of this embodiment, the fixed time Tm is changed in accordance with the input voltage Vin, so even when the input voltage Vin is low, a stable and accurate output voltage Vout can be output.

[0072] In the switching control circuit 1, the confirmation time Tm2 can be set by the reference current Id and the reference voltage V3. By setting the confirmation time Tm2 to be longer than time Tm3 when the input voltage Vin is at its minimum acceptable value, it is possible to suppress the misjudgment of a short circuit between the source and ground of the switching element M1.

[0073] Next, we will explain the operation of the switching control circuit 1 when the source and ground of the switching element M1 are short-circuited.

[0074] As shown in Figure 4, at time t11, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, and the gate drive signal G1 rises to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow. Since the switching element M1 is short-circuited to ground, the current detection signal Vcs remains "0". At time t11, the current detection signal Vcs is less than the second threshold V2, so the short-circuit detection signal SHT is at a high level. Furthermore, since the time setting signal STM is at a low level, the short-circuit stop signal SHT2, which is the output of the AND gate 43, is also at a low level.

[0075] Furthermore, at time t11, the divided voltage Vdiv is input to buffer 421, and transistor 423 is controlled. When transistor 423 is controlled, the divided voltage Vdiv, that is, the reference current Ir corresponding to the first input voltage Vin1, is drawn from current mirror 422, and an adjustment current I1, which is a duplicate of the reference current Ir, is output from current mirror 422.

[0076] At time t11, the inverting gate control signal S1B falls from a high level to a low level. As a result, transistor M43 turns off, and capacitor C3 is charged by the combined current Ic, which is the sum of the adjustment current I1 and the reference current Id. The slope voltage Vslp drawn from the first terminal of capacitor C3 rises with a slope corresponding to the combined current Ic.

[0077] Even after time has elapsed since time t11, the current detection signal Vcs remains "0".

[0078] At time t12, when the slope voltage Vslp becomes higher than the reference voltage V3, the time setting signal STM rises to a high level. The time from time t11 to time t12 is the fixed time Tm (here, fixed time Tm4). At this time, since the short-circuit detection signal SHT is at a high level, the short-circuit stop signal SHT2 rises to a high level. As a result, the reset signal RST rises from a low level to a high level. Then, the gate control signal S1 and the gate drive signal G1 fall from a high level to a low level. Consequently, the switching element M1 turns off.

[0079] In this way, the switching control circuit 1 can accurately determine a short circuit between the source and ground of the switching element M1. The switching control circuit 1 can set the confirmation time Tm4 using the reference current Id and the reference voltage V3. Then, when the input voltage Vin is at its maximum allowable value, the primary current Ip flowing through the switching element M1 during confirmation time Tm4 is set to fall within the allowable range.

[0080] As a result, the switching control circuit 1 can prevent misjudging a short circuit between the source and ground of the switching element M1 when the input voltage Vin is small. Furthermore, it can accurately determine whether the source and ground of the switching element M1 are short-circuited, and it can also prevent a current larger than the allowable current from flowing through the switching element M1.

[0081] <Switching control circuit 1A (second embodiment)> Figure 5 shows the configuration of the switching control circuit 1A of the second embodiment. The switching control circuit 1A of this embodiment employs a fixed time setting circuit 44 instead of the fixed time setting circuit 42 of the switching control circuit 1 of the first embodiment (Figure 2). Also, the voltage divider circuit 7 is omitted. The other parts of the switching control circuit 1A have the same configuration as the switching control circuit 1. Therefore, parts of the switching control circuit 1A that are substantially the same as those of the switching control circuit 1 are denoted by the same reference numerals, and detailed descriptions of the same parts are omitted.

[0082] As shown in Figure 5, the fixed time setting circuit 44 includes a reference voltage generation circuit 441, a comparator 442, and a flip-flop 443 (in this case, an RS flip-flop).

[0083] The reference voltage generation circuit 441 includes resistors R41 and R42 connected in series, and a transistor 445 (NMOSFET). The first ends of the series-connected resistors R41 and R42 are connected to the application terminal of the supply voltage Vreg, and the second ends are connected to the drain of transistor 445. The source of transistor 445 is connected to ground. The gate of transistor 445 is input to the time limit signal SLT output from the output terminal (Q) of flip-flop 443. Transistor 445 is controlled on / off by the time limit signal SLT. Transistor 445 is ON when the time limit signal SLT is high, and OFF when the time limit signal SLT is low.

[0084] When transistor 445 is in the off state, the reference voltage V4 is approximately the same as the supply voltage Vreg (let's call it the first voltage V41). Also, when transistor 445 is in the on state, the reference voltage V4 is the voltage divided by resistors R41 and R42 (let's call it the second voltage V42). <Vregとする)となる。

[0085] The capacitor C3 of the slope voltage generation circuit 425 is charged by the reference current Id1 output from the current source 440. As a result, the slope voltage Vslp1 drawn from the first terminal of capacitor C3 rises with a slope corresponding to the reference current Id1.

[0086] Comparator 442 generates a time setting signal STM by comparing a reference voltage V4 input to the inverting input terminal (-) with a slope voltage Vslp1 input to the non-inverting input terminal (+). The time setting signal STM is low level when the reference voltage V4 is higher than the slope voltage Vslp1, and high level when the reference voltage V4 is lower than the slope voltage Vslp1.

[0087] The flip-flop 443 switches the logic level of the time limit signal SLT output from the output terminal (Q) according to the time setting signal STM input to the set terminal (S) and the reset signal (in this case, CSLIM) input to the reset terminal (R). For example, the gate control signal S1 is set to a high level triggered by the edge of the time setting signal STM (e.g., the rising edge) and reset to a low level triggered by the pulse edge of the reset signal CSLIM (e.g., the rising edge). Here, the current limit signal CSLIM is used as the reset signal for the flip-flop, but it is not limited to this. For example, a signal that detects whether the current detection circuit 2 is not short-circuited can be widely used as the reset signal. That is, when the current detection circuit 2 is not short-circuited, the reference voltage V4 becomes a first voltage V41 with a voltage value approximately the same as the supply voltage Vreg, and when it is short-circuited, it becomes a second voltage V42, which is divided by resistors R41 and R42.

[0088] <Confirmed time setting operation> Figure 6 shows an example of the setting operation for setting the fixed time. Figure 7 shows an example of the setting operation for setting the fixed time Tm when the source and ground of the switching element are short-circuited. The diagrams in Figures 6 and 7 show the same signals as in Figures 3 and 4, except that the time limit signal SLT is shown.

[0089] First, we will explain the operation of the switching control circuit 1A when the source and ground of the switching element M1 are not short-circuited.

[0090] As shown in Figure 6, at time t21, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, and the gate drive signal G1 rises to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow, so the current detection signal Vcs rises with a slope corresponding to the primary current Ip. Note that at time t1, the current detection signal Vcs is smaller than the second threshold V2, so the short-circuit detection signal SHT is at a high level. Furthermore, since the time setting signal STM is at a low level, the short-circuit stop signal SHT2, which is the output of the AND gate 43, is at a low level.

[0091] Furthermore, at time t21, the inverting gate control signal S1B falls from a high level to a low level. As a result, transistor M43 turns off, and capacitor C3 is charged by the reference current Id1 generated by the current source 440. The slope voltage Vslp1 drawn from the first terminal of capacitor C3 rises with a slope corresponding to the reference current Id1. Note that in the switching control circuit 1A, the reference current Id1 is constant regardless of the input voltage Vin. In other words, the slope of the slope voltage Vslp1 is constant regardless of the input voltage Vin.

[0092] At time t22, when the current detection signal Vcs becomes higher than the second threshold V2, the short-circuit detection signal SHT falls from a high level to a low level.

[0093] At time t23, when the current detection signal Vcs becomes higher than the first threshold V1, the current limiting signal CSLIM switches from a low level to a high level. This causes the reset signal RST to rise from a low level to a high level. Then, the gate control signal S1 and the gate drive signal G1 fall from a high level to a low level. As a result, the switching element M1 turns off.

[0094] At time t23, when the slope voltage Vslp becomes higher than the first voltage V41 (=Vreg), the time setting signal STM rises to a high level. The time from time t21 to time t23 is the fixed time Tm (here, the first fixed time Tm5). At this time, since the short-circuit detection signal SHT is at a low level, the short-circuit stop signal SHT2 remains at a low level. In other words, in the switching control circuit 1, from the time the set signal SET rises to a high level until the first fixed time Tm5 has elapsed, the short-circuit stop signal SHT2, which turns off the switching element M1, is kept at a low level, regardless of the level of the short-circuit detection signal SHT.

[0095] Furthermore, at time t23, the inverting gate control signal S1B switches from a low level to a high level, the slope voltage generation circuit 425 is reset, and the slope voltage Vslp is reset to "0". As a result, the time setting signal STM switches from a high level to a low level.

[0096] The current detection signal Vcs decreases at a constant rate after the switching element M1 turns off. The short-circuit detection signal SHT rises from a low level to a high level with a delay from time t23. In other words, if the input voltage Vin is the first input voltage Vin1 and the current detection signal Vcs corresponding to the primary current Ip is detected, there is no period in which both the short-circuit detection signal SHT and the time setting signal STM are at a high level. Therefore, the short-circuit stop signal SHT2 does not rise to a high level. In other words, a short circuit between the source and ground of the switching element M1 is not detected.

[0097] At time t23, the time setting signal STM rises to a high level, causing the time limit signal SLT to also rise to a high level. However, the high-level current limit signal CSLIM resets flip-flop 443, causing the time limit signal SLT to immediately fall to a low level. Transistor 445 briefly turns on and then returns to the off state. As a result, the reference voltage V4 briefly drops to the second voltage V42 before returning to the first voltage V41. Note that Figure 6 omits the illustration of the short-term change in the reference voltage V4.

[0098] In this configuration, the first determinative time Tm5 is set so that the time at which the current detection signal Vcs becomes greater than the first threshold V1 is the same as the time at which the slope voltage Vslp1 becomes greater than the reference voltage V4 (=V41). However, it is not limited to this, and the first determinative time Tm5 may be set so that the switching element M1 switches to the off state before the primary current Ip reaches the maximum current that the switching element M1 can handle. The first determinative time Tm5 is determined by the capacitance of the capacitor C3 and the reference current Id1 generated by the current source 440.

[0099] If the source and ground of the switching element M1 are not short-circuited, the on / off state of the switching element M1 is controlled by the current limiting signal CSLIM. Therefore, the fixed time setting circuit 42 sets the fixed time so that it becomes the first fixed time Tm5.

[0100] Next, we will explain the operation of the switching control circuit 1A when the source and ground of the switching element M1 are short-circuited.

[0101] As shown in Figure 7, at time t31, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, and the gate drive signal G1 rises to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow. Since the switching element M1 is short-circuited to ground, the current detection signal Vcs remains "0". At time t31, the current detection signal Vcs is less than the second threshold V2, so the short-circuit detection signal SHT is at a high level. Furthermore, since the time setting signal STM is at a low level, the short-circuit stop signal SHT2, which is the output of the AND gate 43, is also at a low level.

[0102] Furthermore, at time t31, the inverting gate control signal S1B falls from a high level to a low level. As a result, transistor M43 turns off, and capacitor C3 is charged by the reference current Id1 generated by the current source 440. The slope voltage Vslp1 drawn from the first terminal of capacitor C3 rises with a slope corresponding to the reference current Id1.

[0103] Even after time has elapsed since time t31, the current detection signal Vcs remains "0".

[0104] At time t32, when the slope voltage Vslp1 becomes higher than the reference voltage V4, the time setting signal STM rises to a high level. The time from time t31 to time t32 is the fixed time Tm (here, the first fixed time Tm5). At this time, since the short-circuit detection signal SHT is at a high level, the short-circuit stop signal SHT2 rises to a high level. As a result, the reset signal RST rises from a low level to a high level. Then, the gate control signal S1 and the gate drive signal G1 fall from a high level to a low level. As a result, the switching element M1 turns off.

[0105] Then, at time t32, the time setting signal STM rises to a high level, generating the time limit signal SLT. Since the current limit signal CSLIM remains at a low level, the time limit signal SLT is held at a high level. This keeps transistor 445 of the reference voltage generation circuit 441 in the ON state. As a result, the reference voltage V4 is divided by resistors R41 and R42, and the second voltage V42( <V41=Vreg)となる。

[0106] At time t33, when the set signal SET rises to a high level, the gate control signal S1 is set to a high level, causing the gate drive signal G1 to rise to a high level. As a result, the switching element M1 turns on, and the primary current Ip begins to flow. Similarly, the slope voltage Vslp1 rises.

[0107] At time t34, when the slope voltage Vslp1 becomes higher than the reference voltage V42, the time setting signal STM rises to a high level. The time from time t33 to time t34 is the definite time Tm (here, the second definite time Tm6). The slope of the slope voltage Vslp1 is constant, and the reference voltage V4 decreases from the first voltage V41 to the second voltage V42. Therefore, the second definite time Tm6 is shorter than the first definite time Tm5.

[0108] In other words, when the source and ground of the switching element M1 are short-circuited, the second definite time Tm6 for the timing when the second and subsequent set signals SET rise to a high level is made shorter than the first definite time Tm5. The switching element M1 can be controlled so that it switches to the off state before the primary current Ip when the source and ground of the switching element M1 exceeds the allowable current of the switching element M1.

[0109] This allows the first confirmation time Tm5 to be set to a sufficiently long duration, thereby suppressing the misdetection of a short circuit between the source and ground of the switching element M1 when the input voltage Vin is small. Furthermore, it enables accurate detection of a short circuit between the source and ground of the switching element M1, and also suppresses the flow of a current larger than the allowable current through the switching element M1.

[0110] <Switching control circuit 1B (third embodiment)> Figure 8 shows the configuration of the switching control circuit 1B of the third embodiment. The switching control circuit 1B of this embodiment employs a fixed time setting circuit 45 instead of the fixed time setting circuit 44 of the switching control circuit 1A of the second embodiment (Figure 5). The other parts of the switching control circuit 1B have the same configuration as the switching control circuit 1A. Therefore, the same reference numerals are used for parts of the switching control circuit 1B that are substantially the same as those of the switching control circuit 1A, and detailed explanations of these same parts are omitted. In addition, the voltage divider circuit 7 used in the switching control circuit 1 is used in the switching control circuit 1.

[0111] As shown in Figure 8, the fixed time setting circuit 45 omits the flip-flop 443 and includes an AD converter 451, a logic unit 452, a DA converter 453, a first current source 454, and a second current source 455.

[0112] The AD converter 451 converts the analog input signal AI (= divided voltage Vdiv), which corresponds to the input voltage Vin, into a digital input signal DI.

[0113] The logic unit 452 generates a digital output signal DO from the digital input signal DI. The digital output signal DO includes information regarding the current values ​​of the reference currents I5 and I6 generated by the first current source 454 and the second current source 455, respectively.

[0114] The DA converter 453 converts the digital output signal DO into an analog output signal AO.

[0115] The first current source 454 generates a first reference current I5 corresponding to the analog output signal AO and outputs it to the reference voltage generation circuit (resistor 456). The first terminal of resistor 456 is connected to the output terminal of the first current source 454, and the second terminal is connected to ground. Resistor 456 generates a reference voltage V5 (= I5 × R5, where R5 is the resistance value of resistor 456) at its first terminal. The first reference current I5 is generated to be large when the input voltage Vin is high and small when the input voltage Vin is low.

[0116] The second current source 455 generates a reference current I6 corresponding to the analog output signal AO and outputs it to the slope voltage generation circuit 425. The capacitor C3 of the slope voltage generation circuit 425 is charged by the reference current I5. As a result, the slope voltage Vslp2 drawn from the first terminal of capacitor C3 rises with a slope corresponding to the second reference current I6. The second reference current I6 is generated to be large when the input voltage Vin is high and small when it is low.

[0117] Comparator 442 generates a time setting signal STM by comparing a reference voltage V4 input to the inverting input terminal (-) with a slope voltage Vslp2 input to the non-inverting input terminal (+).

[0118] Thus, as in the switching control circuit 1B, the same operation can be achieved by using a digital fixed-time setting circuit 45 instead of an analog fixed-time setting circuit 44.

[0119] <Usage> Figure 9 shows an example configuration of electrical equipment 200 including a power supply unit 100. Examples of electrical equipment 200 include devices that receive signals from an external source and transmit them to a control unit in continuously operating equipment such as industrial robots and conveying equipment.

[0120] As shown in Figure 9, the electrical equipment 200 includes a power supply unit 100, a power source 300, and an actuator 400. The power source 300 is configured to include, for example, a battery, a substation, etc., and is a power supply source that supplies an input voltage Vin to the power supply unit 100.

[0121] The power supply unit 100 has one of the above configurations and supplies the output voltage Vout generated from the input voltage Vin to the actuator 400.

[0122] The actuator 400 is configured to operate using an output voltage Vout, and examples include rotary motors, linear motors, solenoids, etc. In addition to the actuator 400, other devices that operate using the output voltage Vout output from the power supply unit 100, such as a computing unit, control unit, and inverter, can be widely used as the device that supplies the output voltage Vout from the power supply unit 100.

[0123] <Other> The embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention is indicated by the claims rather than by the description of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0124] <Note> The various embodiments described above will be summarized below.

[0125] The switching control circuits (1, 1A, 1B) described above are configured to control the switching of a switching element (M1) connected to the primary coil (Lp) of a flyback transformer (FT). A first control circuit (3) is configured to turn off the switching element (M1) when the current detection signal (Vcs) output from a current detection circuit (2), which is configured to detect the current (Ip) flowing through the switching element (M1), reaches a first threshold (V1), The system includes a second control circuit (4) configured to turn off the switching element (M1) after a fixed time (Tm) has elapsed since the switching element (M1) was turned on while the current detection signal (Vcs) did not reach a second threshold (V2) which is smaller than the first threshold (V1), The second control circuit (4) has a configuration (first configuration) that includes fixed time setting circuits (42, 44, 45) configured to change the fixed time (Tm).

[0126] In the switching control circuit (1) of the first configuration described above, the fixed time setting circuit (42) is configured to adjust the fixed time (Tm) based on the input voltage (Vin) supplied to the primary coil (Lp) (second configuration).

[0127] In the switching control circuit (1) of the second configuration described above, the fixed time setting circuit (42) is configured to shorten the fixed time (Tm) when the input voltage (Vin) supplied to the primary coil (Lp) is large compared to when it is small (third configuration).

[0128] In the switching control circuit (1) having any of the above configurations 1 to 3, the fixed time setting circuit (42) is: A current generation circuit (40X) configured to generate an adjustment current (I1) corresponding to the input voltage (Vin) supplied to the primary coil (Lp), A current source (424) configured to supply a reference current (Id) of a predetermined current value, A slope voltage generation circuit (425) is configured to generate a slope voltage (Vslp) by charging and discharging a capacitor (C3) using a combined current (Ic) obtained by combining a reference current (Id) and an adjustment current (I1), The system includes a comparator (426) configured to compare a slope voltage (Vslp) with a predetermined reference voltage (V3) and output a high-level signal (STM) when the slope voltage (Vslp) is greater than the reference voltage (V3), This configuration (fourth configuration) uses a time setting signal (STM) that outputs a signal (STM) from the comparator (426) to set the definite time (Tm).

[0129] In the switching control circuit (1A) of the first configuration described above, the fixed time setting circuit (44) is configured to set a first fixed time (Tm5) and a second fixed time (Tm6) that is shorter than the first fixed time (Tm5). This configuration (the fifth configuration) sets a first set time (Tm5) immediately after the switching element (M1) is initially turned ON, and sets a second set time (Tm6) if the current detection signal (Vcs) does not reach the first threshold (V1).

[0130] In the switching control circuit (1A) of the fifth configuration described above, the fixed time setting circuit (44) includes a current source (440) configured to supply a reference current (Id1) of a predetermined current value, A slope voltage generation circuit (425) is configured to generate a slope voltage (Vslp1) by charging and discharging a capacitor (C3) using a reference current (Id1), A reference voltage generation circuit (441) is configured to generate a first voltage (V41) and a second voltage (V42) lower than the first voltage (V41) as a reference voltage (V4), A comparator (442) is configured to compare the slope voltage (Vslp) with a reference voltage (V4) and output a high-level signal (STM) when the slope voltage (Vslp) is higher than the reference voltage (V4). The flip-flop (443) is configured such that the output of a comparator (442) is input to the set terminal, and a reset signal (CSLIM) that limits the overcurrent of the switching element (M1) is input to the reset terminal. The reference voltage generation circuit (441) is controlled by the output of the flip-flop (443), outputting a second voltage (V42) when the output of the flip-flop (443) is high, and outputting a first voltage (V41) when it is low. The sixth configuration is one in which the signal (STM) output from the comparator (442) is a time setting signal (STM) that sets the definite time (Tm).

[0131] In the switching control circuit (1B) of the first configuration described above, the fixed time setting circuit (45) is: An AD converter (451) configured to convert an analog input signal (AI) corresponding to an input voltage (Vin) into a digital input signal (DI), A logic unit (452) configured to generate a digital output signal (DO) from a digital input signal (DI), A DA converter (453) configured to convert a digital output signal (DO) to an analog output signal (AO), A first current source (454) is configured to supply a first reference current (I5) with a current value corresponding to the input voltage (Vin) in response to an analog output signal (AO), A second current source (455) is configured to supply a second reference current (I6) with a current value corresponding to the input voltage (Vin) in response to an analog output signal (AO), A reference voltage generation circuit (456) configured to generate a reference voltage (V5) corresponding to a first reference current (I5), A slope voltage generation circuit (425) is configured to generate a slope voltage (Vslp2) by charging and discharging a capacitor (C3) using a second reference current (I6), The seventh configuration includes a comparator (442) that compares a slope voltage (Vslp2) with a reference voltage (V5) and outputs a high-level signal (STM) when the slope voltage (Vslp2) is higher than the reference voltage (V5).

[0132] The flyback converter described above has a configuration (configuration 8) comprising a switching control circuit (1, 1A, 1B) having the configuration described in any of the first to seventh above, and a flyback transformer (FT).

[0133] The power supply unit (100) described above has a configuration (9th configuration) that includes the flyback converter of the 8th configuration described above.

[0134] The electrical equipment (200) described above has a configuration (10th configuration) that includes the power supply unit (100) of the 9th configuration described above. [Explanation of Symbols]

[0135] 1, 1A, 1B Switching Control Circuit 2 Current detection circuit 3. First control circuit 4. Second control circuit 5 Logic Circuits 6. Drive Circuit 7. Voltage divider circuit 21 Sense Resistance 31 First Comparator 40X current generation circuit 41. Second Comparator 42 Fixed Time Setting Circuit 421 buffers 422 Current Mirror 423 Transistors 424 Current Source 425 Slope Voltage Generation Circuit 426 Comparator 427 resistors 428 Inverter Circuit 43 AND Gate 44 Fixed Time Setting Circuit 440 Current Source 441 Reference Voltage Generation Circuit 442 Comparator 443 Flip-flops 445 transistors 45 Fixed Time Setting Circuit 451 AD Converter 452 Logic Section 453 DA converter 454 Current Source 455 Current Source 456 resistors 51 OR Gate 52 RS Flip-Flops 61 Gate Driver 71 Resistors 72 resistors 100 Power supply 200 Electrical equipment 300 power source 400 actuators AI Analog Input Signal AO Analog Output Signal DI Digital Input Signal DO Digital Output Signal C1, C2, C3 Capacitors CSLIM current limiting signal (reset signal) D1 diode FT Flyback Transformer I1 Adjustment current I5, I6 reference current Ic composite current Id, Id1, Ir Reference current Ip primary current Is secondary current Lp Primary Coil Ls secondary coil M1 Switching element M41, M42, M43 transistors R1, R2, R3, R41, R42 resistance S1 Gate control signal S1B Inverted Gate Control Signal G1 Gate drive signal SET Set signal RST reset signal SHT Short Circuit Detection Signal SHT2 Short-circuit stop signal SLT Time Limit Signal STM Time Setting Signal Tm Confirmation Time Tm1 Confirmed time Tm2 confirmed time Tm3 time Tm4 Confirmed time Tm5 First definite time Tm6 2nd confirmed time Ton On Period V1 First threshold V2 Second threshold V3 Reference Voltage V4 Reference Voltage V41 First Voltage V42 Second Voltage V5 Reference Voltage Vcs current detection signal Vdiv divided voltage Vfb feedback voltage Vin Input Voltage Vin1 First input voltage Vin2 Second input voltage Vout output voltage Vreg supply voltage Vslp slope voltage Vslp1 Slope Voltage Vslp2 Slope Voltage

Claims

1. A switching control circuit configured to control the switching of a switching element connected to the primary coil of a flyback transformer, A first control circuit is configured to turn off the switching element when the current detection signal output from a current detection circuit, which is configured to detect the current flowing through the switching element, reaches a first threshold value. The circuit includes a second control circuit configured to turn off the switching element after a fixed time has elapsed since the switching element was turned on while the current detection signal does not reach a second threshold that is smaller than a first threshold, The second control circuit is a switching control circuit having a fixed time setting circuit configured to change the fixed time.

2. The switching control circuit according to claim 1, wherein the fixed time setting circuit is configured to adjust the fixed time based on the input voltage supplied to the primary coil.

3. The switching control circuit according to claim 2, wherein the fixed time setting circuit is configured to shorten the fixed time when the input voltage supplied to the primary coil is large compared to when it is small.

4. The aforementioned fixed time setting circuit is A current generation circuit configured to generate an adjustment current corresponding to the input voltage supplied to the primary coil, A current source configured to supply a reference current of a predetermined current value, A slope voltage generation circuit configured to generate a slope voltage by charging and discharging a capacitor using a combined current obtained by combining the aforementioned reference current and the aforementioned adjustment current, A comparator is configured to compare the slope voltage with a predetermined reference voltage and output a high-level signal when the slope voltage is greater than the reference voltage. The switching control circuit according to claim 1, wherein the signal output from the comparator is a time setting signal for setting the fixed time.

5. The aforementioned fixed time setting circuit is configured to set a first fixed time and a second fixed time that is shorter than the first fixed time. The switching control circuit according to claim 1, wherein the first determinative time is set immediately after the switching element is first turned on, and the second determinative time is set when the current detection signal does not reach the first threshold.

6. The aforementioned fixed time setting circuit includes a current source configured to supply a reference current of a predetermined current value, A slope voltage generation circuit configured to generate a slope voltage by charging and discharging a capacitor using the aforementioned reference current, A reference voltage generation circuit configured to generate a first voltage and a second voltage lower than the first voltage as reference voltages, A comparator configured to compare the slope voltage with the reference voltage and output a high-level signal when the slope voltage is higher than the reference voltage, The flip-flop is configured such that the output of the comparator is input to the set terminal, and a reset signal to limit the overcurrent of the switching element is input to the reset terminal, The reference voltage generation circuit is controlled by the output of the flip-flop, and outputs the second voltage when the output of the flip-flop is high level, and outputs the first voltage when it is low level. The switching control circuit according to claim 1, wherein the signal output from the comparator is a time setting signal for setting the fixed time.

7. The aforementioned fixed time setting circuit is An AD converter configured to convert an analog input signal corresponding to the input voltage supplied to the primary coil into a digital input signal, A logic unit configured to generate a digital output signal from the aforementioned digital input signal, A DA converter configured to convert the aforementioned digital output signal into an analog output signal, A first current source configured to supply a first reference current with a current value corresponding to the input voltage in accordance with the analog output signal, A second current source configured to supply a second reference current with a current value corresponding to the input voltage in accordance with the analog output signal, A reference voltage generation circuit having a configuration capable of generating a reference voltage corresponding to the first reference current, A slope voltage generation circuit configured to generate a slope voltage by charging and discharging a capacitor using the second reference current, A switch control device according to claim 1, comprising a comparator configured to compare the slope voltage with the reference voltage and output a high-level signal when the slope voltage is higher than the reference voltage.

8. A switching control circuit according to any one of claims 1 to 7, A flyback converter having the aforementioned flyback transformer.

9. A power supply device having a flyback converter as described in claim 8.

10. An electrical device having a power supply device as described in claim 9.

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