Battery monitor with low power mode

Abstract

This invention provides a low-power battery monitor and a method for doing so. [Solution] The oscillator has an enable input and an oscillator output. The voltage regulator has an enable input. The logic circuit has a counter having a control input, a control output, a status output, and a clock input coupled to the oscillator output. The control output is coupled to the enable inputs of the oscillator and the voltage regulator. The logic circuit is configured to enable the oscillator by asserting a control signal at the control output to a first logic state in response to a first control value at the control input, causing the counter to count and disabling the voltage regulator. In response to the counter reaching a final value, it sets a status signal at the status output to a first logic state and asserts a control signal at the control output to a second logic state, disabling the oscillator and enabling the voltage regulator.

Description

Technical Field

[0001] Integrated circuits operating on a battery or other limited energy source may benefit from low-power states to extend their operating life. Integrated circuits with a large number of digital gates may benefit from power gates (e.g., power transistors) that completely cut off the power to the integrated circuit when it is off. External conditions, such as the connection of a battery charger, turn on the power gate and wake up the integrated circuit, so a wake-up signal is provided. In the case of an integrated circuit implementing a timing function such as a battery monitor, a complete loss of power prevents the integrated circuit from maintaining time information.

Summary of the Invention

[0002] In one example, the device includes an oscillator having an oscillator control input and an oscillator output. A voltage regulator has a voltage regulator input, a voltage regulator output, and a voltage regulator control input. The voltage regulator is configured to be deactivated based on the voltage regulator control input having a signal of a first logic state and activated based on the signal being in a second logic state. A first logic circuit has a clock input, a first control output, a second control output, a third control output, and a status output. The clock input is coupled to the oscillator output. The first control output is coupled to the oscillator control input. The second control output is coupled to the voltage regulator control input. The first logic circuit has a counter that counts based on the clock from the oscillator received at the clock input. The first logic circuit asserts a status signal at the status output based on whether the counter has expired. A second logic circuit has a status input and a voltage supply input. The status input is coupled to the status output of the first logic circuit. The voltage supply input is coupled to the voltage regulator output. The second logic circuit is configured to update a time value based on a status signal from the first logic circuit. The switch circuit has a control terminal, a first switch circuit terminal, and a second switch circuit terminal. The control terminal of the switch circuit is coupled to a third control output. The first switch circuit terminal is coupled to a power supply terminal. The second switch circuit terminal is coupled to a voltage regulator input.

[0003] In another example, the device includes an oscillator having an oscillator control input and an oscillator output. A voltage regulator has a voltage regulator input, a voltage regulator output, and a voltage regulator control input. The voltage regulator is configured to be deactivated on the basis that the voltage regulator control input has a signal of a first logic state and activated on the basis that the signal is in a second logic state. A first logic circuit has a clock input, a first control output, a second control output, a third control output, and a status output. The clock input is coupled to the oscillator output. The first control output is coupled to the oscillator control input. The second control output is coupled to the voltage regulator control input. The first logic circuit has a counter that counts based on the clock from the oscillator received at the clock input. The first logic circuit asserts a status signal at the status output based on whether the counter has expired. A second logic circuit has a status input and a voltage supply input. The status input is coupled to the status output of the first logic circuit. The voltage supply input is coupled to the voltage regulator output. The second logic circuit is configured to update the time value based on the status signal from the first logic circuit.

[0004] In another example, the device includes an oscillator having an enable input and an oscillator output. A voltage regulator has an enable input. A logic circuit has a control input, a control output, and a status output. The logic circuit has a counter having a clock input coupled to the oscillator output. The control output is coupled to the enable inputs of the oscillator and the voltage regulator. The logic circuit is configured to assert a control signal at the control output to a first logic state in response to a first control value at the control input to enable the oscillator, cause the counter to start counting, disable the voltage regulator, and, in response to the counter reaching a final value, set a status signal at the status output to a first logic state, and assert a control signal at the control output to a second logic state in order to disable the oscillator and enable the voltage regulator.

[0005] In yet another example, the device includes a microcontroller having a status input. The microcontroller is configured to determine, upon power-up, that the logical state in the status input is a first logical state, and to update a time value in response to the determination that the status input is a first logical state.

[0006] In a further example, a method includes transitioning a battery monitor to a first power state and enabling an oscillator to generate a clock. This method also includes determining the expiration of a time period based on the clock, transitioning the battery monitor to a second power state in which the battery monitor consumes more power than in the first power state, updating a time value in non-volatile memory using logic circuits, and returning the battery monitor to the first power state. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a battery monitor in one example.

[0008] [Figure 2] This is a schematic diagram of the logic circuit included in the battery monitor shown in Figure 1, as an example.

[0009] [Figure 3] This is a timing diagram illustrating the operation of the logic circuit in Figure 2, as an example.

[0010] [Figure 4] This is a flowchart illustrating the operation of a battery monitor in one example. [Modes for carrying out the invention]

[0011] In drawings, the same reference numeral or other reference numerals are used to indicate identical or similar features (of function and / or structure).

[0012] Figure 1 is a schematic diagram of a battery monitor 100 in one example. The battery 90 is connected to the input terminal 102 of the battery monitor 100. The battery monitor 100 determines the status of the battery 90, including its age, charge level, and temperature. The battery monitor 100 includes a switch circuit 110, voltage regulators 120 and 130, logic circuits 140 and 150, an oscillator 160, inverters 162 and 164, a reference circuit 170, a comparator 180, and a voltage detection circuit 190. In one example, all components shown in Figure 1, except for the battery 90, are part of a single device (e.g., an integrated circuit, IC). In some examples, some of the components in Figure 1 are fabricated on one IC, while others are fabricated on different ICs, and multiple ICs are packaged together as a single device.

[0013] The switch circuit 110 includes switch terminals 110a and 110b and control terminals 110c and 110d. The switch circuit 110 includes transistors M1, M2, and M3 and resistor R1. In this example, transistor M1 is a p-channel field-effect transistor (PFET), and transistors M2 and M3 are n-channel field-effect transistors (NFETs). The source of transistor M1 and one terminal of resistor R1 are coupled to switch terminal 110a, which receives the input voltage VPWR from battery 90. The gate of transistor M1 and the drains of transistors M2 and M3 are coupled to the other terminal of resistor R1. The drain of transistor M1 is coupled to switch terminal 110b, which provides the output voltage VOUT when transistor M1 is on. Control terminal 110c is coupled to the gate of transistor M2, and control terminal 110d is coupled to the gate of transistor M3. The sources of transistors M2 and M3 are coupled to supply terminal 101 (e.g., ground). When either or both of transistors M2 and M3 are on, the gate of transistor M1 discharges at least partially, thereby turning on transistor M1. When transistor M1 is on, the output voltage VOUT is approximately equal to the battery voltage (VPWR).

[0014] The voltage regulator 120 includes an input 120a and an output 120b. Input 120a is coupled to the switch terminal 110b and receives a voltage VOUT. The voltage regulator 120 generates a voltage AVDD at output 120b. In the example in Figure 1, the voltage regulator 120 includes a current source I1, a Zener diode D1, and a transistor M4 (e.g., an NFET). Input 120a is coupled to the current source I1 and the drain of transistor M4. The source of transistor M4 is coupled to output 120b. The gate of transistor M4 is coupled to the cathode of Zener diode D1 and the current source I1. The anode of Zener diode D1 is coupled to the supply terminal 101. The current source I1 provides a bias current for Zener diode D1, and Zener diode D1 clamps the gate voltage of transistor M4. The output voltage AVDD from the voltage regulator 120 is approximately equal to the gate voltage of transistor M4 minus the threshold voltage of M4. While transistor M1 is ON, voltage regulator 120 generates voltage AVDD, which is supplied to voltage regulator 130, logic circuit 150, oscillator 160, inverters 162 and 164, reference circuit 170, and comparator 180.

[0015] The voltage regulator 130 includes a voltage regulator input 130a, a voltage regulator output 130b, and a voltage regulator control input 130c. The voltage regulator input 130a is coupled to the output 120b of the voltage regulator 120 and receives the voltage AVDD. The voltage regulator 130 can be enabled or disabled via the voltage regulator control input 130c. The signal ENABLE 131 is provided to the voltage regulator control input 130c. In one example, ENABLE 131, which is logic high, enables the voltage regulator 130, causing it to generate the voltage DVDD at the voltage regulator output 130b. ENABLE 131, which is logic low, disables the voltage regulator 130, preventing it from generating the voltage DVDD.

[0016] The voltage regulator 130 includes an operational amplifier 132 and a transistor M5 (e.g., an NFET). The voltage regulator input 130a is coupled to the drain of transistor M5. The negative (-) input of the operational amplifier 132 is coupled to the source of transistor M5 and the voltage regulator output 130b. A reference circuit 170 (e.g., a bandgap reference circuit) generates a reference voltage VREF at its output 170b, which is coupled to the positive (+) input of the operational amplifier 132. In the example in Figure 1, the negative input of the operational amplifier 132 has a voltage approximately equal to VREF, and therefore the voltage DVDD at the voltage regulator output 130b is approximately equal to VREF.

[0017] The voltage regulator control input 130c is coupled to the operational amplifier 132. When the enable signal 131 is logic high at the voltage regulator control input 130c, the operational amplifier 132 is powered on (activated), and the voltage regulator 130 generates voltage DVDD. Conversely, when the enable signal 131 is logic low, the operational amplifier 132 is powered off (disabled), thereby preventing the voltage regulator 130 from generating voltage DVDD.

[0018] The logic circuit 140 may include a microcontroller 141 that executes machine instructions. The logic circuit 140 may also include other logic circuits, such as logic gates and flip-flops. The logic circuit 140 has a status input 140a, a power input 140b, and a control output 140c. When the voltage regulator 130 is enabled, the logic circuit 140 receives its operating voltage DVDD from the voltage regulator 130 at its power input 140b. When the enable signal 131 is logic low, the voltage regulator 130 is enabled and generates an output voltage DVDD that powers on the logic circuit 140. When the enable signal 131 is logic low, the voltage regulator 130 is disabled, thereby turning off power to the logic circuit 140.

[0019] Logic circuit 150 has a clock input 150a, control inputs 150b and 150c, control outputs 150d, 150e, and 150f, and a status output 150g. An example of logic circuit 150 is shown in Figure 2 and described below. Logic circuit 150 receives voltage AVDD as its operating power at power input 150i and therefore remains powered on even when voltage regulator 130 is disabled. Generally, logic circuit 150 consumes less power than logic circuit 140. Oscillator 160 has an enable input 160a, a trim input 160b, and an output 160c. When activated, oscillator 160 generates an output clock VOSC 163 at its output 160c. The frequency of clock VOSC 163 is relatively low, and therefore oscillator 160 consumes relatively little power. In one example, the frequency of clock VOSC is 10Hz to 100kHz. In one specific example, the frequency is 1 kHz. The output 160c of the oscillator 160 is coupled to the clock input 150a of the logic circuit 150.

[0020] The control output 150d of the logic circuit 150 is coupled to the input of the inverter 164, providing the signal SHTDWN0 to the inverter 164. The control output 150e of the logic circuit 150 is coupled to the enable input 160a of the oscillator 160 and the input of the inverter 162, providing the signal SHTDWN1 to the inverter 162 and the enable input 160a of the oscillator. The output of the inverter 162 is coupled to the voltage regulator control input 130c. Therefore, the logic state of the signal SHTDWN1 determines whether the voltage regulator 130 is enabled (when SHTDWN1=1) or disabled (when SHTDWN1=0).

[0021] The status output 150g of logic circuit 150 is coupled to the status input 140a of logic circuit 140, providing the status signal SHT1WAKE to logic circuit 140. The control output 140c of logic circuit 140 is coupled to the control input 150b of logic circuit 150. In one example, the control output 140c is an n-bit (e.g., 8-bit) digital value (DIG_CTRL[n:0]) through which any of several parameters or commands can be communicated from logic circuit 140 to logic circuit 150. For example, logic circuit 140 may provide a trim value to logic circuit 150 via control output 140c. The trim value may be predetermined to control the frequency of the clock VOSC and may be loaded into non-volatile memory within logic circuit 140. Logic circuit 150 relays the trim value TRIM_LAT to oscillator 160, thereby allowing oscillator 160 to adjust the frequency of the clock VOSC generated by the oscillator. In another example, logic circuit 140 can provide commands to logic circuit 150 via control output 140c, and logic circuit 150 can implement any of the multiple lower power states described later.

[0022] When activated, comparator 180 compares voltage VPWR to voltage VREF to determine whether the voltage from battery 90 is greater than (or equal to) VREF or less than VREF. Comparator 180 generates an output signal PGOOD at its output, at a logic high level if VPWR is greater than VREF, and at a logic low level if VPWR is less than VREF. The output of comparator 180 is coupled to the gate of transistor M2. In response to PGOOD being a logic high, transistor M2 turns on, thereby turning on transistor M1. In response to PGOOD being a logic low (which also occurs when comparator 180 is disabled), transistor M2 turns off. The output of inverter 164 is coupled to the enable input 180a of comparator 180. In response to the signal SHTDWN0 from the control output 150d of logic circuit 150 being a logic high, inverter 164 sets its output signal to a logic low, thereby disabling comparator 180. In response to the signal SHTDWN0 from the control output 150d of the logic circuit 150 being logic low, the output signal from the inverter 164 becomes logic high, thereby activating the comparator 180.

[0023] The voltage detection circuit 190 has an input 190a and an output 190b. The input 190a may be coupled, for example, to the terminals of a charger for charging a battery 90. The voltage detection circuit 190 detects the presence or absence of a signal at input 190a. In response to the detection of a signal at its input 190a, the voltage detection circuit 190 asserts the output signal WAKE 193 at its output 190b (e.g., logic high). If no signal is detected at input 190a, the voltage detection circuit 190 does not assert the output signal WAKE 193 at its output 190b (e.g., WAKE 193 is logic low). In one example, input 190a is coupled to the power input of a circuit within the voltage detection circuit. In response to the presence of a signal at input 190a, such a circuit is powered on and the signal WAKE 193 is put into a logic high state.

[0024] The output 190b of the voltage detection circuit 190 is coupled to the control input 150c of the logic circuit 150 and the gate of the transistor M3. Thus, in response to the detection of a signal at the input 190a, the voltage detection circuit 190 asserts WAKE193 to a logic high level, thereby turning on the transistor M3. When the transistor M3 is on, the transistor M1 is turned on. Also, the logic circuit 150 detects when WAKE193 is asserted high. The function of the logic circuit 140 in response to the signal WAKE193 being logic high will be described later.

[0025] The output 120b of the voltage regulator 120 provides the voltage AVDD to the logic circuit 150, the oscillator 160, the inverters 162 and 164, the reference circuit 170, and the comparator 180. As described above, when activated, the voltage regulator 130 provides the voltage DVDD for powering the logic circuit 140. The battery monitor 100 implements a plurality of power states. In the wake state, the transistor M1 is on, the voltage regulator 120 generates the voltage AVDD, the logic circuit 150, the inverters 162 and 164, the reference circuit 170, and the comparator 180 are powered on, the voltage regulator 130 is activated, and the logic circuit 140 is powered. The oscillator 160 also receives the voltage AVDD, is deactivated in the wake state, and is activated when the signal SHTDWN1 is logic high.

[0026] The battery monitor 100 also implements at least two lower power states (lower power than the wake state), a shutdown state 0 and a shutdown state 1. The battery monitor 100 consumes less power in shutdown state 0 than in shutdown state 1. When in shutdown state 1 and not in shutdown state 0, the battery monitor 100 can determine the aging of the battery. The logic circuit 140 can issue a command to the logic circuit 150 via the control output 140c (e.g., by setting the signal SHTDWN0 to logic high) to transition from the wake state to shutdown state 0, whereby the inverter 162 is inverted to the logic low state. When the output of the inverter 162 is logic low, the comparator 180 is disabled and the transistor M2 is turned off, thereby also turning off the transistor M1. When the transistor M1 is turned off, the voltage regulators 120 and 130 do not generate the output voltages AVDD and DVDD respectively, and the logic circuits 140 and 150, the oscillator 160, the inverters 162 and 164, the reference circuit 170, and the comparator 180 are turned off. The voltage detection circuit 190 is also off, but turns on when a signal is present at its input 190a.

[0027] External events such as connecting a system including the battery 90 and the battery monitor 100 to a charger can wake up the battery monitor 100 from shutdown state 0. In response to the signal WAKE193 being logic high, the transistor M3 is turned on, thereby also turning on the transistor M1. When the transistor M1 is turned on, the voltage regulator 120 generates the voltage AVDD, thereby turning on the logic circuits 140 and 150, the oscillator 160, the inverters 162 and 164, the reference circuit 170, and the comparator 180. The logic circuit 150 forces the signals SHTDWN0 and SHTDWN1 to the logic low state in response to the logic high assertion of the signal WAKE193, thereby ensuring that both shutdown state 0 and shutdown state 1 are disabled. This enables the voltage regulator 130, and thus the logic circuit 140 is powered on.

[0028] When the system wakes up from shutdown state 0, the battery monitor 100 returns to the wake state. While in the wake state, the battery monitor 100 can monitor the state of the battery 90, including determining its age and health. However, the battery monitor 100 cannot track the elapsed time while in shutdown state 0. Therefore, when the battery monitor 100 returns to the wake state from shutdown state 0, it cannot determine how long it was in shutdown state 0.

[0029] The use of shutdown state 1 allows the battery monitor 100 to implement a lower power state to conserve battery power while remaining in a state where it can track elapsed time. While in the wake state, logic circuit 140 can issue commands to logic circuit 150 via control output 140c (for example, by setting signal SHTDWN1 to logic high), which causes logic circuit 150 to disable voltage regulator 130 and enable oscillator 160. In shutdown state 1, switch M1 remains on, voltage regulator 120 generates output voltage AVDD, and logic circuits 140 and 150, oscillator 160, inverters 162 and 164, reference circuit 170, and comparator 180 are on. In shutdown state 1, voltage regulator 130 is disabled, and therefore logic circuit 140 is off. A counter in logic circuit 150 (described later) counts pulses of clock VOSC 163 from oscillator 160. When the counter expires (which may be a value programmed by logic circuit 140 before it issues a command to logic circuit 150 to enter shutdown state 1), logic circuit 140 responds by transitioning from shutdown state 1 to wake state. Logic circuit 140 also sets the logic level of the status signal SHTWAKE to, for example, logic high. In wake state, the voltage regulator 130 is activated and logic circuit 140 is powered on. Logic circuit 140 (e.g., its microcontroller 141) determines the logic state of the status signal SHTWAKE. In one example, logic high of the status signal SHTWAKE means that logic circuit 140 has been powered on following a predetermined time period implemented by the oscillator 160 and the counters in logic circuit 150. Logic circuit 140 updates the time value in non-volatile memory, taking into account the time period implemented by the counters. For example, logic circuit 140 may increment the value in non-volatile memory to correspond to the time elapsed during shutdown state 1.However, if the voltage detection circuit 190 initiates a wake state when a signal is detected at input 190a, the logic circuit 140 will be powered on, but the status signal SHTWAKE will be logic 0. Because the length of time elapsed before the voltage detection circuit 190 detected a signal at input 190a is uncertain, the logic circuit 140 may not update its time value (for example, it may postpone updating the time value).

[0030] The use of shutdown state 1 is possible, for example, during the shipment of a product including a battery 90 and a battery monitor 100. During such a shipment, the battery monitor 100 alternates between the wake state and shutdown state 1, staying in shutdown state 1 longer than the wake state, for example, to conserve power. The battery monitor 100 transitions to the wake state after each predetermined time period (via a counter in the logic circuit 150), so that the logic circuit 140 can update the time value to check the health and condition of the battery 90 and continue to track the aging of the battery 90.

[0031] Figure 2 is a schematic diagram of an example of logic circuit 150. In this example, logic circuit 150 includes a counter 202, latches 210, 214, 218 and 222, OR gates 230 and 232, and an inverter 234. Counter 202 has inputs 202a, 202b and 202c and output 202d. Clock input 150a is coupled to input 202a and provides counter 202 with the clock signal VOSC from oscillator 160 when oscillator 160 is enabled. The digital value DIG_CTRL[n:0] includes bits corresponding to the DIGITAL_CONFIG signal, DIGITAL_RESET signal, DIGITAL_SHTDWN0 signal, DIGITAL_SHTDWN1 signal, and DIGITAL_TRIM signal, respectively, as shown in Figure 2. DIGITAL_CONFIG is provided to input 202b, and DIGITAL_RESET is provided to input 202c. DIGITAL_SHTDWN0 and DIGITAL_SHTDWN1 are provided to the set inputs of latches 214 and 218, respectively. Logic circuit 140 generates a reset signal DIGITAL_RESET for resetting the counter. The reset of logic circuit 150 is performed before entering shutdown state 1, setting the registers within logic 150 to known states. Logic circuit 150 can provide control bits, such as a count value, to input 202b of counter 202. Counter 202 counts pulses of the clock signal VOSC, and when the counter reaches a programmed count value, it asserts the output signal OSC_RESET, for example, to the logic high state. The digital value DIG_CTRL[n:0] may also include the trim value DIGITAL_TRIM for oscillator 160.

[0032] The output 202d of counter 202 is coupled to the set input of latch 210. The output 214a of latch 214 is coupled to the input 230b of OR gate 230, and the signal DIGITAL_RESET is provided to the input 230a of OR gate 230. The output signal from latch 214 is the control signal SHTDWN0. OR gate 230 logically ORs the output signal from latch 214 and the reset signal DIGITAL_RESET together. The output of OR gate 230 is coupled to the reset (RST) input of latch 210. The output 210a of 210 is coupled to the status output 150g of logic circuit 150, providing the status signal SHT1WAKE.

[0033] The trim value DIGITAL_TRIM is provided to the data (D) input 222a of latch 222. The DIGITAL_RESET signal is provided to the input of inverter 234, and the output of inverter 234 is coupled to the clock input 222c of latch 222. The output 222b of latch 222 is coupled to the control output 150f of logic circuit 150. On the falling edge of the reset signal DIGITAL_RESET, latch 222 latches the trim value to its output 222b as the output trim value TRIM_LAT, so that the trim value can be preserved even when logic circuit 140 (which provides the trim value) is turned off when the voltage regulator 130 is disabled.

[0034] As described above, logic circuit 140 can issue a command to logic circuit 150 via the value DIG_CTRL[n:0] to instruct logic circuit 150 to implement shutdown state 0 or shutdown state 1. The logic high of signal DIGITAL_SHTDOWN0 sets latch 214 and forces its output 214a signal SHTDWN0 to the logic high level. The logic high of signal DIGITAL_SHTDOWN0 sets latch 214 and forces its output 214a signal SHTDWN0 to the logic high level. OR gate 232 has inputs 232a, 232b, and 232c. The output 214a of latch 214 is coupled to input 232a. The output 202d of counter 202 is coupled to input 232c. The control input 150c of logic circuit 150 is coupled to input 232b. The OR gate 232 logically ORs the signals SHTDWN0, OSC_RESET, and WAKE together. If any of these signals is logically high, latch 218 is reset, forcing signal SHTDWN1 to a logically low level, thereby ensuring that shutdown state 1 is aborted or not activated. When signal WAKE 193 is logically high, this indicates that a signal has been detected at input 190a of the voltage detection circuit 190, and both latches 214 and 218 are reset, thereby ending both shutdown states 0 and 1 and thereby implementing the wake state.

[0035] Figure 3 is a timing diagram illustrating the operation of the logic circuit 150 in Figure 2. The timing diagram in Figure 3 includes the signals DIGITAL_SHTDWN1, DIGITAL_RESET, DIGITAL_TRIM, TRIM_LAT, SHTDWN1, and SHT1WAKE, and the voltage DVDD. Referring to Figures 2 and 3, the logic circuit 140 may assert the signal DIGITAL_RESET to have a rising edge 312. The rising edge 312 of the signal DIGITAL_RESET resets the latch 210, thereby forcing the signal SHT1WAKE to have a falling edge 352, which resets the signal SHT1WAKE so that it can be asserted to a logic high level when the counter 202 subsequently expires. The logic circuit 150 may provide a trim value to the logic circuit 150 while the signal DIGITAL_RESET is at a logic high. Furthermore, the logic circuit 140 can load an end count value (or start count value) into the counter 202. The logic circuit 140 can then deassert the digital reset signal DIGITAL_RESET to a logic low (falling edge 314). The falling edge 314 of the signal DIGITAL_RESET clocks latch 222 at time 332, thereby latching the trim value from the logic circuit 140 to the oscillator 160 as the trim value TRIM_LAT.

[0036] Next, the logic circuit 140 can force the signal DIGITAL_SHTDWN1 to a high logic level starting on the rising edge 302 in order to initiate shutdown state 1. The rising edge 302 of the signal DIGITAL_SHTDWN1 sets a latch 218, thereby forcing the signal SHTDWN1 to a high logic level starting on the rising edge 342.

[0037] In response to the signal SHTDWN1 being logic high, the voltage regulator 130 is disabled and the oscillator 160 is enabled. As a result of the voltage regulator 130 being disabled, the voltage DVDD drops to approximately 0V, shutting off the logic circuit 140 and causing the signal DIGITAL_SHTDWN1 to be logic low, as indicated by the falling edge 304. Arrow 347 represents the length of time (e.g., 1 hour) that the counter 202 counts before the counter expires. When the counter reaches its end count value, the counter's output signal OSC_RESET (Figure 2) becomes logic high, resulting in at least two responses. First, the logic high signal OSC_RESET sets latch 210, thereby forcing the signal SHT1WAKE to the logic high level marked by the rising edge 354. Second, the logic high signal OSC_RESET resets latch 218, thereby forcing the signal SHTDWN1 to the logic low level, as indicated by the falling edge 344. When signal SHTDWN1 is logically low, the voltage regulator 130 is activated, and voltage DVDD returns to its regulated level. Thus, during shutdown state 1, voltage DVDD is off for a time period 324. During that time period, the battery monitor 100 consumes significantly less power than during the wake state, but more power than during shutdown state 0.

[0038] Figure 4 is a flowchart 400 illustrating the operation method of the battery monitor 100. In the example in Figure 4, this method includes operation 402 which transitions the battery monitor 100 to a first power state. In one example, the first power state is shutdown state 1. In operation 404, an oscillator, such as oscillator 160, is activated and starts generating a clock (e.g., VOSC). Determination operation 406 determines whether a certain time period has expired. In one example, counter 202 is used to count the pulses of the clock VOSC until the counter's closing value is reached. If the time period has expired ("yes" branch), operation 408 includes setting the status signal SHT1WAKE. If the time period has not expired, 410 includes determining whether the signal WAKE193 is set. If the signal WAKE193 is not set, control is looped back to determination operation 406. If the time period has expired or the signal WAKE 193 is set, this method includes, in operation 412, transitioning the battery monitor 100 to a second power state. In one example, the second power state is the wake state. In determination operation 414, this method includes determining whether the status signal SHT1WAKE is set. If the status signal SHT1WAKE is set (for example, due to the expiration of counter 202), this method includes, in operation 416, updating the time value. In one example, the logic circuit 140 (for example, the microcontroller 141) updates the time value as described above. If the status signal SHT1WAKE is not set (for example, due to the charger being connected and waking the battery charger), this method includes, in operation 418, performing normal wake state operations such as monitoring battery temperature and status.

[0039] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, device A is connected to device B via intermediary component C, such that device B is controlled by device A via a control signal generated by device A, provided that intermediary component C does not alter the functional relationship between device A and device B.

[0040] Furthermore, in this specification, the phrase "based on ~" means "based at least in part on ~". Therefore, if X is based on Y, X may be based on Y and any number of other factors.

[0041] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by the manufacturer to perform that function, and / or may be configurable (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the construction and / or layout of hardware components, via the interconnection of the devices, or a combination thereof.

[0042] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean the interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0043] Circuits or devices described herein as including specific components may instead be adapted to be coupled with those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current sources) may instead include only semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted, at or after manufacture, for example by an end user and / or a third party, to be coupled with at least some of the passive elements and / or power sources to form the described structure.

[0044] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuit elements. For example, field-effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN transistors or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in conjunction with the devices described herein. Transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0045] In the claims, the control input and current terminals of a transistor may be referred to. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0046] In this specification, an FET is "on" or "enabled" to mean that a conductive channel exists in the FET and that drain current can flow through the FET. In this specification, an FET is "off" or "disabled" to mean that a conductive channel does not exist and therefore no drain current flows through the FET. However, an off FET may still have current flowing through the transistor's body diode.

[0047] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available before component replacement. Components indicated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the indicated resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0048] While certain elements of the examples described are included in the integrated circuit and other elements are outside the integrated circuit, additional or fewer features may be incorporated into the integrated circuit in other exemplary embodiments. Also, some or all of the features illustrated as being outside the integrated circuit may be included in the integrated circuit, and / or some of the features illustrated as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0049] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise stated herein, "about," "approximately," or "substantially" preceding a parameter means that it is within + / - 10% of that parameter, or, if the parameter is zero, a reasonable range value near zero.

[0050] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a device, An oscillator having an oscillator control input and an oscillator output, A voltage regulator having a voltage regulator input, a voltage regulator output, and a voltage regulator control input, wherein the voltage regulator control input is configured to be deactivated based on having a signal in a first logic state and to be activated based on the signal being in a second logic state, A first logic circuit having a clock input, a first control output, a second control output, a third control output, and a status output, wherein the clock input is coupled to the oscillator output, the first control output is coupled to the oscillator control input, the second control output is coupled to the voltage regulator control input, the first logic circuit has a counter that counts based on the clock from the oscillator received at the clock input, and the first logic circuit asserts a status signal at the status output based on whether the counter has expired, A second logic circuit having a status input and a power input, wherein the status input is coupled to the status output of the first logic circuit, the power input is coupled to the voltage regulator output, and the second logic circuit is configured to update a time value based on the status signal from the first logic circuit, A switch circuit having a control terminal, a first switch circuit terminal, and a second switch circuit terminal, wherein the control terminal of the switch circuit is coupled to the third control output, the first switch circuit terminal is coupled to the power supply terminal, and the second switch circuit terminal is coupled to the voltage regulator input, A device including a device.

2. The apparatus according to claim 1, The counter has a counter input that is coupled to the clock input of the first logic circuit, and the counter has a counter output. A device in which the first logic circuit includes a latch having a latch input and a latch output, wherein the latch input is coupled to the counter output and the latch output is coupled to the status output.

3. The apparatus according to claim 1, wherein the oscillator is configured to generate the clock having a frequency in the range of 10 Hz to 100 kHz.

4. The apparatus according to claim 1, wherein the second logic circuit is configured to provide a trim value to the first logic circuit, and the first logic circuit is configured to configure the oscillator based on the trim value.

5. The apparatus according to claim 1, wherein the voltage regulator is a first voltage regulator and has a first voltage regulator input, and the first logic circuit has a first logic circuit power input, The apparatus further includes a second voltage regulator having a second voltage regulator input and a second voltage regulator output, wherein the second voltage regulator input is coupled to the second switch circuit terminal and the second voltage regulator output is coupled to the first voltage regulator input and the first logic circuit power input.

6. It is a device, An oscillator having an oscillator control input and an oscillator output, A voltage regulator having a voltage regulator input, a voltage regulator output, and a voltage regulator control input, wherein the voltage regulator control input is configured to be deactivated based on having a signal in a first logic state and to be activated based on the signal being in a second logic state, A first logic circuit having a clock input, a first control output, a second control output, a third control output, and a status output, wherein the clock input is coupled to the oscillator output, the first control output is coupled to the oscillator control input, the second control output is coupled to the voltage regulator control input, the first logic circuit has a counter configured to count based on the clock received from the oscillator at the clock input, and the first logic circuit is configured to assert a status signal at the status output based on whether the counter has expired, A second logic circuit having a status input and a power input, wherein the status input is coupled to the status output of the first logic circuit, the power input is coupled to the voltage regulator output, and the second logic circuit is configured to update a time value based on the status signal from the first logic circuit, A device including a device.

7. The apparatus according to claim 6, A device further comprising a switch circuit having a control terminal, a first switch circuit terminal, and a second switch circuit terminal, wherein the control terminal of the switch circuit is coupled to the third control output and the second switch circuit terminal is coupled to the voltage regulator output.

8. The apparatus according to claim 1, The counter has a counter input that is coupled to the clock input of the first logic circuit, and the counter has a counter output. A device in which the first logic circuit includes a latch having a latch input and a latch output, wherein the latch input is coupled to the counter output and the latch output is coupled to the status output.

9. It is a device, Includes a microcontroller with status inputs, The aforementioned microcontroller When power is turned on, it is determined that the logical state in the status input is in the first logical state. A device configured to update a time value in response to determining that the status input is in the first logical state.

10. The apparatus according to claim 9, further comprising a non-volatile memory, wherein the microcontroller is configured to update the time value in the non-volatile memory.

11. The apparatus according to claim 9, wherein the microcontroller is configured to output a command to transition the apparatus to a first power state after updating the time value when the status input is in the first logical state.

12. The apparatus according to claim 9, wherein the microcontroller is When power is turned on, it is determined that the logical state in the status input is in the second logical state, A device configured to postpone updating the time value when the status input is in the second logical state.

13. It is a device, An oscillator having an enable input and an oscillator output, A voltage regulator having an enable input, A logic circuit having a control input, a control output, and a status output, Includes, The logic circuit has a counter, the counter has a clock input coupled to the oscillator output, and the control output is coupled to the enable inputs of the oscillator and the voltage regulator. The aforementioned logic circuit In response to the first control value at the control input, the control signal at the control output is asserted to a first logic state to activate the oscillator, the counter starts counting, and the voltage regulator is disabled. In response to the counter reaching its closing value, the status signal in the status output is set to a first logical state, the control signal in the control output is asserted to a second logical state, the oscillator is disabled, and the voltage regulator is enabled. A device configured in such a way.

14. The apparatus according to claim 13, wherein the voltage regulator is a first voltage regulator, the control output is a first control output, and the logic circuit has a second control output and a logic circuit power input. The aforementioned device A second voltage regulator having a second voltage regulator input and a second voltage regulator output, wherein the second voltage regulator output is coupled to the logic circuit power input, A switch circuit having a control input and a switch circuit terminal, wherein the control input of the switch circuit is coupled to the second control output and the switch circuit terminal is coupled to the second voltage regulator input, A device including a device.

15. The apparatus according to claim 13, wherein the counter has a counter output, the logic circuit includes a latch having an input coupled to the counter output, and the latch also has a latch output coupled to the status output.

16. The apparatus according to claim 13, wherein the logic circuit is configured to receive a trim value at the control input and to configure the oscillator based on the trim value.

17. It is a method, To transition the battery monitor to the first power state, Enable the oscillator to generate a clock, Determining the expiration of a certain time period based on the aforementioned clock, Transitioning the battery monitor to a second power state, wherein the battery monitor consumes more power in the second power state than in the first power state. Updating the time value in non-volatile memory using logic circuits, The battery monitor is transitioned to return to the first power state, Methods that include...

18. A method according to claim 17, wherein the clock has pulses, and determining the expiration of the time period includes starting a counter to count the pulses.

19. The method according to claim 17, further, The wake signal is detected by the battery monitor, The battery monitor is switched to the second power state, The logic circuit determines whether the battery monitor has entered the second power state based on the wake signal or the expiration of the time period. When the logic circuit determines that the battery monitor has entered the second power state based on the expiration of the time period, it updates the time value. If the logic circuit determines, based on the wake signal, that the battery monitor has entered the second power state, it will refrain from updating the time value. Methods that include...

20. A method according to claim 17, wherein transitioning the battery monitor to the first power state includes turning off power to the logic circuit.

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