Image sensor

Abstract

To provide an image sensor. [Solution] The image sensor 3 comprises a first substrate 20 having a first photoelectric conversion unit 13 that converts light into electric charge, a second substrate 30 which is laminated together with the first substrate and has a circuit unit including a first processing unit 16 that performs signal processing on a first signal based on the electric charge converted by the first photoelectric conversion unit, and a first connection part which electrically connects the first substrate and the second substrate and includes pads 23, 33 including a first conductive member that is arranged to face each other in the lamination direction in which the first substrate and the second substrate are laminated, and first signal lines 24-26, 34 which are electrically connected to the pads and output the first signal to the first processing unit. The first signal line has a first portion that extends along the lamination direction and a second portion that extends along a direction intersecting the lamination direction.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] Conventionally, a stacked imaging device in which a first semiconductor chip on which a pixel array is formed and a second semiconductor chip on which an AD conversion unit and a logic circuit are formed are stacked is known (for example, Patent Document 1). In the imaging device of Patent Document 1, each pixel in the first semiconductor chip and each AD conversion unit in the second semiconductor chip are connected by a conductive via. However, the degree of freedom in the layout of other wirings is restricted by the conductive vias.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to a first aspect of the present invention, an imaging device includes a first substrate having a first photoelectric conversion unit that converts light into charges, a substrate laminated together with the first substrate, and a circuit unit including a first processing unit that performs signal processing on a first signal based on the charges converted by the first photoelectric conversion unit. A second substrate having a connection portion that electrically connects the first substrate and the second substrate, a first joint portion including a first conductive member disposed so as to face each other in a stacking direction in which the first substrate and the second substrate are stacked, and a first joint portion that is electrically connected to the first joint portion and outputs the first signal to the first processing unit. A first connection portion having a first signal line for the above, and the first signal line has a first portion extending along the stacking direction and a second portion extending along a direction intersecting the stacking direction.

Brief Description of the Drawings

[0005] [Figure 1]A schematic cross-sectional view showing the configuration of the imaging device according to the first embodiment. [Figure 2] A plan view of the image sensor of the first embodiment, as seen from the imaging surface side. [Figure 3] A cross-sectional view of a portion of the image sensor of the first embodiment. [Figure 4] A diagram showing the pixels of the image sensor and the configuration of the circuit unit of the first embodiment. [Figure 5] A cross-sectional view of a portion of the image sensor of the second embodiment. [Modes for carrying out the invention]

[0006] (First Embodiment) Figure 1 shows an example of the configuration of a camera 1, which is an example of an imaging device according to the first embodiment. In Figure 1, the X, Y, and Z directions indicated by arrows are considered positive directions (+). The X, Y, and Z directions are mutually orthogonal. Furthermore, the X, Y, and Z directions shown in subsequent figures are the same as those shown in Figure 1.

[0007] Camera 1 comprises an imaging optical system (imaging optical system) 2, an image sensor 3, an imaging control unit 4, a memory 5, a display unit 6, and an operation unit 7. The imaging optical system 2 has multiple lenses, including a focus adjustment lens (focus lens), and an aperture diaphragm, and forms an image of the subject on the image sensor 3. The imaging optical system 2 may be detachable from camera 1.

[0008] The image sensor 3 is an image sensor such as a CMOS image sensor or a CCD image sensor. The image sensor 3 receives the light beam that has passed through the imaging optical system 2 and captures the subject image formed by the imaging optical system 2. Multiple pixels, each having a photoelectric conversion unit, are arranged in a two-dimensional manner (row and column directions) on the image sensor 3. The image sensor 3 generates a signal by photoelectric conversion of the received light and outputs the generated signal to the imaging control unit 4.

[0009] Memory 5 is a recording medium such as a memory card. Image data, control programs, etc., are stored in Memory 5. Writing data to and reading data from Memory 5 is controlled by the image capture control unit 4. The display unit 6 displays images based on image data, shooting-related information such as shutter speed and aperture value, and menu screens, etc. The operation unit 7 includes a release button, a power switch, various setting switches such as switches for switching between various modes, and outputs signals based on each operation to the image capture control unit 4.

[0010] The image capture control unit 4 is composed of a processor such as a CPU, FPGA, or ASIC, and memory such as ROM or RAM, and controls each part of the camera 1 based on a control program. The image capture control unit 4 supplies signals to the image sensor 3 to control its operation. When taking still images, taking video, or displaying a live view image of the subject on the display unit 6, the image capture control unit 4 causes the image sensor 3 to capture an image of the subject and outputs a signal.

[0011] The imaging control unit 4 generates image data by performing various image processing operations on the signal output from the image sensor 3. The imaging control unit 4 also acts as an image data generation unit 4, generating still image data and moving image data based on the signal output from the image sensor 3. Image processing includes image processing such as grayscale conversion and color interpolation.

[0012] (First embodiment of the image sensor) Next, the configuration of the image sensor 3 of the first embodiment will be described with reference to Figures 2 to 4. Figure 2 shows the image sensor 3 of the first embodiment as viewed from the light incident side (-Z side). The image sensor 3 has a plurality of pixels 10 arranged in the X direction (horizontal direction) and the Y direction (vertical direction). The number of pixels 10 may be 1000 or more in each of the X and Y directions.

[0013] A horizontal control unit HC is provided at the -X-direction end of a region (pixel region) in which multiple pixels 10 are arranged, and a vertical control unit VC is provided at the +Y-direction end. The horizontal control unit HC and the vertical control unit VC together are also called the element control unit CU. Multiple pixels 10 are arranged, for example, in a so-called Bayer array. Some of the pixels 10 may also be used for so-called image plane phase-detection focus detection.

[0014] Figure 3 shows a cross-section (XZ plane) of the pixel region of the image sensor 3. Note that Figure 3 shows only a portion of the cross-section of the pixel region of the image sensor 3. The image sensor 3 is an image sensor in which a first substrate 20 and a second substrate 30 are stacked in the Z direction. The first substrate 20 and the second substrate 30 are made of semiconductors such as silicon. The image sensor 3 is provided with a plurality of pixels 10, indicated by dashed lines. Each pixel 10 has a microlens 11, a color filter 12, a photoelectric conversion unit 13, and a readout circuit 14. Note that a single pixel 10 may have multiple photoelectric conversion units 13 or multiple readout circuits 14.

[0015] The first substrate 20 is provided with a photoelectric conversion unit 13 and a readout circuit 14. The photoelectric conversion unit 13 converts light incident on the first substrate 20 into electric charge. The photoelectric conversion unit 13 is composed of, for example, a photodiode. The readout circuit 14 outputs a pixel signal based on the charge generated by the photoelectric conversion unit 13 to the vertical wiring, which will be described later. The configuration of the readout circuit 14 will be described later.

[0016] The microlens 11 is provided on the light incident side (-Z direction side) of the first substrate 20. The microlens 11 focuses the light incident on the first substrate 20 onto the photoelectric conversion unit 13. The color filter 12 is provided between the microlens 11 and the photoelectric conversion unit 13. The color filter 12 has spectral characteristics such that light of a specific wavelength is incident on each photoelectric conversion unit 13. The color filter 12 has spectral characteristics defined by the Bayer array.

[0017] On the second substrate 30, a plurality of circuit units 15 indicated by a broken-line frame are provided. The circuit unit 15 includes a processing unit 16 that processes the signal output from the reading circuit 14 and a control unit 17 that controls the reading circuit 14.

[0018] On the surface of the first substrate 20 on the side of the second substrate 30 (+Z direction side), a first wiring layer 21 including a first insulating layer 22, pads 23, and wirings 24 to 29, etc. is provided. On the other hand, on the surface of the second substrate 30 on the side of the first substrate 20 (-Z direction side), a second wiring layer 31 including a second insulating layer 32, pads 33, and wirings 34 to 39, etc. is provided.

[0019] Similar to the wirings constituting a general semiconductor integrated circuit, the wirings 24 to 29 and the wirings 34 to 39 are formed by forming a conductor such as metal on the first substrate 20 or the second substrate 30 by lithography technology. Therefore, the wirings 24 to 29 and the wirings 34 to 39 include the wirings 26 to 29, 37 to 39 (hereinafter also referred to as "horizontal wirings") that generally extend parallel in the XY plane direction parallel to the surface of the first substrate 20 or the second substrate 30. Further, the wirings 24 to 29 and the wirings 34 to 39 include the wirings 24, 25, 34 (hereinafter also referred to as "vertical wirings") that generally extend parallel in the Z direction perpendicular to the surface of the first substrate 20 or the second substrate 30.

[0020] The horizontal wirings 26 to 29, 37 to 39 are formed in respective wiring layers. The horizontal wirings 26 to 29, 37 to 39 are formed, for example, by patterning a layer of a conductor such as metal formed on the surface of the first substrate 20 or the second substrate 30 by lithography. Alternatively, the horizontal wirings 26 to 29, 37 to 39 may be formed, for example, by forming grooves by lithography in an insulating layer formed on the surface of the first substrate 20 or the second substrate 30 and filling the grooves with a conductor such as metal.

[0021] Also, the vertical wirings 24, 25, 34 are so-called VIA plugs formed in the vertical direction (Z direction) in an insulating layer formed on, for example, the first substrate 20 or the second substrate 30. Each of the vertical wirings 24, 25, 34 may be one VIA plug extending in the Z direction. Alternatively, the vertical wirings 24, 25, 34 may be formed by laminating a plurality of VIA plugs extending in the Z direction at the same position in the XY plane. Also, the first insulating layer 22 and the second insulating layer 32 may be insulating layers formed by laminating a plurality of insulating layers.

[0022] Note that the wirings 24 to 29 and the wirings 34 to 39 shown in FIG. 3 are merely examples, and the total number thereof is not limited to the number shown in FIG. 3. The total number of the horizontal wirings and the vertical wirings may be more than the number shown in FIG. 3. In the present embodiment, the individual wiring layers in which the horizontal wirings 26 to 29 are respectively formed and the first insulating layer 22 in which the vertical wirings 24, 25 are formed are collectively referred to as the first wiring layer 21. Similarly, the individual wiring layers in which the horizontal wirings 37 to 39 are respectively formed and the second insulating layer 32 in which the vertical wiring 34 is formed are collectively referred to as the second wiring layer 31.

[0023] The first insulating layer 22 included in the first wiring layer 21 and the second insulating layer 32 included in the second wiring layer 31 are joined (laminated) at the joining surface (lamination surface) 50. Each of the readout circuits 14 provided on the first substrate 20 is electrically connected to at least one or more vertical wirings 24, either directly or via other wirings. The lower end (+Z direction side end) of the vertical wiring 24 is connected to one end of the horizontal wiring 26 in the first wiring layer 21. Then, the other end of the horizontal wiring 26 is connected to the upper end (-Z direction side end) of the vertical wiring 25. The lower end (+Z direction side end) of the vertical wiring 25 is connected to the pad 23 which is a connection electrode.

[0024] Pads 23 and 33 are connecting electrodes and are joined at the bonding surface 50. The upper end (-Z direction end) of the vertical wiring 34 is connected to pad 33. The lower end (+Z direction end) of the vertical wiring 34 is electrically connected, for example, directly to one of the processing units 16 provided on the second substrate 30, or via other wiring. Pads 23 and 33 constitute a joint that connects wiring 24-29 in the first wiring layer 21 formed on the first substrate 20 and wiring 34-39 in the second wiring layer 31 formed on the second substrate 30.

[0025] In this embodiment, the vertical wiring 24, horizontal wiring 26, vertical wiring 25, pad 23, pad 33, and vertical wiring 34 described above are collectively referred to as the "first connection section." Furthermore, the first connection portion is a wiring that connects a pixel provided on the first substrate 20 and a circuit unit 15 provided on the second substrate 30, which are separated in the Z direction (vertical direction), and is a wiring that extends in the Z direction. Of the first connection portions, the horizontal wiring 26 extends in the XY plane direction (horizontal direction) and is bent relative to the other first connection portions, so the horizontal wiring 26 is also called the "bent portion".

[0026] At the same Z position where the bent portion 26 (horizontal wiring 26) is located, other horizontal wirings 26a other than the bent portion 26 may be formed. In other words, a portion of the many horizontal wirings 26, 26a within the same wiring layer may be used as the bent portion 26. In the first embodiment of the image sensor 3, the bent portion 26 is provided in the second layer of horizontal wiring 26, 26a in the -Z direction from the bonding surface 50 within the wiring layer 21. However, the bent portion 26 may also be provided in the first layer of horizontal wiring 29 in the -Z direction from the bonding surface 50 within the wiring layer 21. The bent portion 26 may also be provided in the third or higher layer of horizontal wiring in the -Z direction from the bonding surface 50 within the wiring layer 21, as long as it is on the side closer to the bonding surface 50.

[0027] In the above description, one first connection part electrically connects each of the read circuits 14 provided on the first board 20 to the processing unit 16 provided on the second board 30 corresponding to each read circuit 14. However, the first connection portion may also be one of the various control lines (selection control line SEL, etc.) described later, which electrically connect each read circuit 14 provided on the first board 20 to the control unit 17 provided on the second board 30 corresponding to each read circuit 14. As described later, if multiple control units 17 are provided corresponding to each read circuit 14, there may be multiple first connection portions depending on the number of control units 17.

[0028] The horizontal wiring 39 shown in Figure 3 is, for example, wiring that supplies power supply voltage, GND voltage, or control signals to each control unit 17 provided on the second board 30. Figure 3 shows, for example, an example in which the horizontal wiring 39 is connected to each control unit 17. However, in addition to the horizontal wiring 39 shown in Figure 3, there may also be horizontal wiring that supplies power supply voltage, GND voltage, or control signals to each processing unit 16, or to which output signals from the processing unit 16 are output.

[0029] Figure 4 shows the configuration of the photoelectric conversion unit 13 and readout circuit 14 included in the pixel 10 provided on the first substrate 20, and the processing unit 16 and control unit 17 (17a to 17d) included in the circuit unit 15 provided on the second substrate 30. In the image sensor 3 of the first embodiment, the pixel 10 is configured as, for example, a so-called 4-transistor type CMOS image sensor pixel.

[0030] The photoelectric conversion unit 13 generates electric charge by photoelectric conversion of light incident on the first substrate 20. The photoelectric conversion unit 13 is composed of, for example, a photodiode. The readout circuit 14 reads out the pixel signal based on the charge generated by the photoelectric conversion unit 13. The readout circuit 14 has a transfer unit TX, an output unit TR, a floating diffusion (FD) FD, an amplification unit TA, and an output unit OU including a selection unit TS.

[0031] The transfer unit TX transfers the charge photoelectrically converted in the photoelectric conversion unit 13 to the floating diffusion FD. In other words, the transfer unit TX is a transfer transistor TX that forms a charge transfer path between the photoelectric conversion unit 13 and the floating diffusion FD. The floating diffusion FD receives the charge converted photoelectrically by the photoelectric conversion unit 13 via the transfer unit. The floating diffusion FD stores the charge converted photoelectrically by the photoelectric conversion unit 13 via the transfer unit TX. In other words, the floating diffusion FD is a charge storage unit.

[0032] The discharge transistor TR resets the potential of the floating diffusion to the reference potential by discharging the charge accumulated in the floating diffusion FD. The discharge transistor TR is a reset transistor TR that resets the potential of the floating diffusion to the reference potential.

[0033] The output unit OU outputs the pixel signal generated by the charge of the floating diffusion FD to the signal line SL. The signal line SL is one of the first connection units (23-26, 33-34). The signal line SL is wiring for outputting the pixel signal to the processing unit 16. The output unit OU has an amplification unit TA and a selection unit TS. The amplification unit TA is an amplification transistor TA that generates the pixel signal from the charge of the floating diffusion FD. The selection unit TS is a selection transistor TS that controls the connection between the pixel 10 and the signal line SL. The selection unit TS outputs the pixel signal generated by the amplification unit TA to the signal line SL.

[0034] The analog signal (pixel signal) output from the output section OU of the readout circuit 14 on the first substrate 20 is transmitted via the signal line SL to the processing unit 16 of the circuit unit 15 on the second substrate 30. The processing unit 16 includes, for example, an analog-to-digital conversion circuit ADC and a current source CS. The analog-to-digital conversion circuit ADC converts the analog signal (pixel signal) output from the selection transistor TS of the readout circuit 14 into a digital signal. The vertical wiring 24, 25, and 34 described above include at least a portion of the signal line SL for transmitting pixel signals from the pixel 10 to the readout ADC.

[0035] The circuit unit 15 has a plurality of control units 17 (17a to 15d). In this embodiment, the selection control unit 17a, the voltage control unit 17b, the reset control unit 17c, and the transfer control unit 17d are collectively or individually referred to as "control unit 17". The selection control unit 17a is electrically connected to the gate of the selection transistor TS of the readout circuit 14 via the selection control line SEL, which is one of the first connection sections (23-26, 33-34). In other words, the selection control unit 17a controls the selection transistor TS.

[0036] The voltage control unit 17b controls the supply of power voltage to the readout circuit 14 or the photoelectric conversion unit 13 via the power supply voltage line VDD, which is one of the first connection units (23-26, 33-34). The reset control unit 17c is electrically connected to the gate of the reset transistor TR of the readout circuit 14 via the reset control line RST, which is one of the first connection points (23-26, 33-34). In other words, the reset control unit 17c controls the reset transistor TR.

[0037] The transfer control unit 17d is electrically connected to the gate of the transfer transistor TX of the readout circuit 14 via the transfer control line TRN, which is one of the first connection points (23-26, 33-34) shown in Figure 3. In other words, the transfer control unit 17d controls the transfer transistor TX.

[0038] Hereinafter, the selection control line SEL, the reset control line RST, and the transfer control line TRN will be collectively referred to as "control lines." The control lines are the wiring that sends control signals from the control unit 17 to the readout circuit 14 to control each transistor. The control signals for controlling each transistor are transmitted from the control unit 17 to at least a portion of the horizontal wiring 27 and 28 via the first connection points (23-26, 33-34).

[0039] The image sensor 3 of the first embodiment is equipped with a plurality of processing units 16 corresponding to the number of pixels 10. Therefore, the image sensor 3 can read out a pixel signal for each pixel 10. In other words, the image sensor 3 can read out and process pixel signals generated by multiple pixels 10 at high speed. The image sensor 3 of the first embodiment is equipped with a plurality of control units 17 corresponding to the number of pixels 10. Therefore, the image sensor 3 can control each pixel 10 individually. In other words, the image sensor 3 can set different exposure times for each pixel and generate and output pixel signals.

[0040] Depending on the configuration of the image sensor 3, the period of arrangement of pixels 10 having a photoelectric conversion unit 13 and a readout circuit 14 in the X or Y direction may differ from the period of arrangement of circuit units 15 having a processing unit 16 and a control unit 17 in the X or Y direction. In other words, the spacing between two adjacent pixels 10 in the X or Y direction (pixel pitch) may differ from the spacing between two adjacent circuit units 15 in the X or Y direction (circuit pitch). This is because the second substrate 30 needs to accommodate circuits other than the circuit units 15. On the other hand, the first substrate 20 needs to accommodate pixels 10 at regular and equal intervals. For example, the second substrate 30 needs to accommodate control circuits 15e that control each predetermined number of circuit units 15 arranged in the X or Y direction. The circuits arranged on the second substrate 30 are not limited to control circuits 15e, but may also include other circuits such as shift registers and memory units.

[0041] Therefore, the width (circuit pitch) of the circuit unit 15 in the X or Y direction must be smaller than the width (pixel pitch) of the pixels 10 in the X or Y direction. As a result, the period of arrangement of the pixels 10 in the X or Y direction may differ from the period of arrangement of the circuit unit 15 in the X or Y direction.

[0042] In this case, some of the multiple circuit units 15 cannot be placed directly below (+Z direction) the corresponding pixel 10, and will be placed at a position offset in the X or Y direction from directly below the pixel 10. In particular, some of the multiple circuit units 15 cannot be placed directly below (+Z direction) the readout circuit 14 of the corresponding pixel 10, and will be placed at a position offset in the X or Y direction from directly below the readout circuit 14. The problem that a corresponding circuit unit 15 cannot be placed directly below a pixel 10 arises because the image sensor 3 of the first embodiment has a configuration in which a circuit unit 15 is placed for each pixel 10.

[0043] In the first embodiment, the image sensor 3 adjusts for positional misalignment in the X or Y direction caused by the difference between the periodicity of the arrangement of the pixels 10 and the periodicity of the arrangement of the circuit unit 15 using the bent portion 26 in the first connection portion (23-26, 33-34). As a result, the image sensor 3 of the first embodiment solves the problem that a circuit unit 15 cannot be placed directly below a pixel 10 due to the difference between the periodicity of the arrangement of the pixels 10 and the periodicity of the arrangement of the circuit unit 15.

[0044] Specifically, as shown in Figure 3, the image sensor 3 of the first embodiment has pads 33 that connect to vertical wiring 34 extending directly upward (-Z direction) from each circuit unit 15. The pads 33 are positioned approximately directly above the circuit unit 15. Therefore, the period of the arrangement of the junctions (pads 23, 33) in the X or Y direction is set to match the period of the arrangement of the circuit unit 15. Furthermore, the image sensor 3 of the first embodiment has a bent portion 26 positioned in the first wiring layer 21 to adjust and match the positions of the pixel 10 and the junction 23 in the X or Y direction. As a result, even if the period of the arrangement of the pixel 10 and the period of the arrangement of the circuit unit 15 differ in the X or Y direction, the pixel 10 (readout circuit 14) and the circuit unit 15 can be electrically connected by the first connection portions (23-26, 33-34). In other words, even if the pixel pitch and the circuit pitch are different, the pixel 10 (readout circuit 14) and the circuit unit 15 can be electrically connected by the first connection parts (23-26, 33-34).

[0045] The direction of the bend in the bending portion 26 (direction of bending) may be, for example, the same as the X direction or Y direction as the direction of the arrangement of the pixels 10. Alternatively, the bent portion 26 may include a first portion extending in one direction within the XY plane and a first portion extending in a direction intersecting that direction within the XY plane. In other words, the bent portion 26 may include a portion that bends within the XY plane itself.

[0046] Incidentally, there are many horizontal wirings 27-29, for example, for controlling the readout circuit 14, near the first substrate 20. Also, there are many horizontal wirings 37-39, for example, for controlling the processing unit 16 or the control unit 17, near the second substrate 30. Therefore, forming a bent portion 26 near the first substrate 20 would cause problems with the layout of the horizontal wiring 27 and 28 for controlling the read circuit 14. Specifically, the degree of freedom in the wiring layout of the horizontal wiring 27 and 28 would be limited by the bent portion 26. In addition, the density of the wiring of the horizontal wiring 27 and 28 would be reduced by the bent portion 26.

[0047] If a bent portion 26 is formed near the second substrate 30, it will cause problems with the layout of the horizontal wiring 38 and 39 for controlling the processing unit 16 or the control unit 17. Specifically, the degree of freedom in the wiring layout of the horizontal wiring 38 and 39 will be limited. In addition, the density of the wiring of the horizontal wiring 38 and 39 will be reduced by the bent portion 26.

[0048] The horizontal wiring 26-29 included in the first wiring layer 21 includes wiring for controlling the pixels 10, a GND line for supplying a GND voltage to the pixels 10, and a power line for supplying a power supply voltage to the pixels 10. The wiring for controlling the pixels 10 is, for example, wiring for controlling the transfer transistor TX, reset transistor TR, and selection transistor TS included in the pixels 10, respectively. Of these, the wiring for controlling the transfer transistor TX or the reset transistor TR may be provided for each pixel 10, or for each pixel block containing a predetermined number of pixels 10.

[0049] The wiring that controls these transistors (hereinafter also referred to as "first control lines") is provided in the first wiring layer 21 at a position close to the first substrate 20 (on the first substrate side, in the -Z direction) in order to control the transfer transistor TX, the reset transistor TR, and the selection transistor TS. In other words, the horizontal wiring 27 and 28 located near the first substrate 20 will contain many first control lines.

[0050] GND lines and power lines are provided in common to multiple pixels 10 or multiple pixel blocks. Therefore, GND lines and power lines are provided in the first wiring layer 21 at a position further from the first substrate 20 than the first control lines (towards the second substrate, in the +Z direction). In other words, GND lines and power lines are provided at a position close to the bonding surface 50. Also, as mentioned above, many first control lines are arranged near the pixels 10, i.e., near the first substrate 20. Therefore, GND lines and power lines are provided in the first wiring layer 21 at a position further from the first substrate 20 than the first control lines. That is, the horizontal wiring 29 located far from the first substrate 20 in the first wiring layer 21 contains many GND lines and power lines.

[0051] The horizontal wiring 37-39 included in the second wiring layer 31 includes wiring for controlling the processing unit 16 or the control unit 17, a GND line for supplying a GND voltage to the processing unit 16 or the control unit 17, and a power line for supplying a power supply voltage to the processing unit 16 or the control unit 17. The wiring for controlling the processing unit 16 or the control unit 17 is, for example, wiring for controlling various switching elements such as transistors included in the processing unit 16 or the control unit 17.

[0052] The wiring that controls these transistors (hereinafter also referred to as "second control lines") is provided in the second wiring layer 31 at a position close to the second substrate 30 (on the second substrate side, in the +Z direction) in order to control various switching elements. That is, the horizontal wiring 38 and 39 located near the second substrate 30 contains many second control lines.

[0053] GND lines and power lines are provided in common to multiple processing units 16 or multiple control units 17. Therefore, GND lines and power lines are provided in the second wiring layer 31 at a position further from the second substrate 30 than the second control lines (towards the first substrate, in the -Z direction). In other words, GND lines and power lines are provided at a position close to the junction surface 50. Also, as described above, many second control lines are located near the processing units 16 or control units 17, that is, near the second substrate 30. Therefore, GND lines and power lines are provided in the second wiring layer 31 at a position further from the second substrate 30 than the second control lines. That is, the horizontal wiring 37 located far from the second substrate 30 in the second wiring layer 31 contains many GND lines and power lines.

[0054] The control lines transmit high-frequency control signals to control each transistor and switching element. Therefore, the control lines can be a source of noise for the signal lines SL, including the bent portion 26. Conversely, the bent portion 26 of the signal lines SL can be a source of noise for the control lines.

[0055] To avoid this, the image sensor 3 of the first embodiment is provided with bent portions 26 in areas other than the vicinity of the first substrate 20 and the vicinity of the second substrate 30. In other words, the image sensor 3 of the first embodiment is provided with bent portions 26 near the bonding surface 50. With this configuration, the image sensor 3 of the first embodiment does not have its freedom of wiring layout for the other wirings 27, 28, 37, and 38 restricted by the first connection portions (23-26, 33-34) including the bent portions 26, and the horizontal wirings 27, 28, 37, and 38 can be wired in an optimal layout. This prevents a decrease in the integration density of the wirings 27, 28, 37, and 38.

[0056] Furthermore, the image sensor 3 of the first embodiment has a bent portion 26 located away from the first control lines (horizontal wiring 27, 28) located near the first substrate 20 and the second control lines (horizontal wiring 38, 39) located near the second substrate 30. In other words, the image sensor 3 of the first embodiment has a bent portion 26 located near the joint. This configuration allows the image sensor 3 of the first embodiment to suppress the influence of noise from these control lines on the bent portion 26. Conversely, it can also suppress the influence of noise from these bent portions 26 on the control lines.

[0057] Furthermore, the image sensor 3 of the first embodiment has a bent portion 26 located close to the GND line and the power line. Since a constant voltage is basically applied to the GND line and the power line, the influence of noise on the signal line SL, including the bent portion 26, is small. In addition, the GND line and the power line are less susceptible to noise from the bent portion 26 of the signal line SL. With this configuration, the image sensor 3 of the first embodiment can minimize the influence of noise on the bent portion 26. Furthermore, the influence of noise from the bent portion 26 can also be minimized.

[0058] Furthermore, the image sensor 3 may be positioned at a certain distance from the first substrate 20 and the second substrate 30, rather than having the bent portion 26 near the first substrate 20 and the second substrate 30. For example, the image sensor 3 may have a bent portion 26 at a distance of at least 1 / 4 of the distance between the first substrate 20 and the second substrate 30 from each of the first substrate 20 and the second substrate 30. This does not restrict the degree of freedom in the wiring layout of the horizontal wiring 27, 28 for controlling the readout circuit 14, and the horizontal wiring 37, 38 for controlling the processing unit 16 or control unit 17, etc. Therefore, the horizontal wiring 27, 28, 37, 38 can be wired in an optimal layout.

[0059] Furthermore, the image sensor 3 may have at least two wiring layers (horizontal wiring 27, 28, or horizontal wiring 37, 38) between the first substrate 20 and the bent portion 26, and between the second substrate 30 and the bent portion 26. This does not restrict the degree of freedom in the wiring layout of the horizontal wiring 27, 28 for controlling the readout circuit 14, and the horizontal wiring 37, 38 for controlling the processing unit 16 or control unit 17, etc. Therefore, the horizontal wiring 27, 28, 37, 38 can be wired in an optimal layout.

[0060] In the first embodiment, the first connection portion (23-26, 33-34) has a first wiring portion (24-26) provided on the first wiring layer 21, a second wiring portion (34) provided on the second wiring layer 31, and pads 23 and 33 which are joining portions that connect the first wiring portion and the second wiring portion. The bent portion 26 is provided in the vicinity of the joining portions, pads 23 and 33. In other words, the bent portion 26 is provided on the side closer to the joining portions, pads 23 and 33, than to the first substrate 20 and the second substrate 30.

[0061] (Second embodiment of the image sensor) Next, the configuration of the image sensor 3a of the second embodiment will be described with reference to Figure 5. The image sensor 3a of the second embodiment shares most of its configuration with the image sensor 3 of the first embodiment described above. In the following, common components are denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0062] Figure 5 is a diagram showing a cross-section (XZ plane) of the pixel 10 portion of the image sensor 3a of the second embodiment, and is similar to Figure 3 described above. The image sensor 3a of the second embodiment differs from the image sensor 3 of the first embodiment in that the electrical connection between the readout circuit 14 and the processing unit 16 or control unit 17 is made by vertical wiring 24, pads 23, pads 33, vertical wiring 35, horizontal wiring 36, and vertical wiring 34.

[0063] In this embodiment, the vertical wiring 24, pad 23, pad 33, vertical wiring 35, horizontal wiring 36, and vertical wiring 34 described above are collectively referred to as the "second connection section." The first connection section and the second connection section described above are also collectively referred to as the "connection section," or each of them individually.

[0064] In the image sensor 3a of the second embodiment, the second connection portion (23-24, 33-36) has a first portion (24) provided on the first wiring layer 21, a second portion (34-36) provided on the second wiring layer 31, and pads 23, 33 which are joining portions that connect the first portion and the second portion. In the image sensor 3a of the second embodiment, the horizontal wiring 36, which is the bent portion, is located in the second portion, which is closer to the second substrate 30 than the pads 23 and 33, which are the joining portions.

[0065] Specifically, as shown in Figure 5, the image sensor 3a of the second embodiment has pads 23 connected to vertical wiring 24 extending directly downward (+Z direction) from the readout circuit 14 of each pixel 10. The pads 23 are positioned approximately directly below the pixel 10 (readout circuit 14). Therefore, the period of the arrangement of the junctions (pads 23, 33) in the X or Y direction is set to match the period of the arrangement of the readout circuit 14 of the pixel 10. Furthermore, the image sensor 3a of the second embodiment has a bent portion 26 positioned in the second wiring layer 31 to adjust and match the positions of the junctions 33 and the circuit unit 15 in the X or Y direction. As a result, even if the period of the arrangement of the pixel 10 and the period of the arrangement of the circuit unit 15 differ in the X or Y direction, the readout circuit 14 and the circuit unit 15 can be electrically connected by the first connection portions (23-26, 33-34). This allows the pixels 10 (readout circuit 14) and the circuit unit 15 to be electrically connected by the first connection parts (23-26, 33-34) even if the period of the arrangement of the pixels 10 and the period of the arrangement of the circuit unit 15 in the X or Y direction are different. In other words, even if the pixel pitch and the circuit pitch are different, the pixels 10 (readout circuit 14) and the circuit unit 15 can be electrically connected by the first connection parts (23-26, 33-34).

[0066] The period of the arrangement of pixels 10 in the X or Y direction is generally uniform within the imaging plane (-Z side XY plane) of the image sensor 3a. Therefore, in the second embodiment, the image sensor 3a has the bonding portions (pads 23, 33) arranged at generally equal intervals in the X or Y direction. In other words, the bonding portions (pads 23, 33) are generally uniformly arranged on the bonding surface 50. As a result, the electrical influence that the bonding portions have on the readout circuit 14 and circuit unit 15 can be made generally uniform in the direction within the imaging plane (XY direction), and noise unevenness within the imaging plane can be suppressed.

[0067] In the second embodiment, the configuration and use of the horizontal wirings 27, 28, 37-39, etc., are the same as in the first embodiment described above. In the second embodiment, the configuration and use of the bent portion (horizontal wiring 36) are the same as in the first embodiment described above. In the second embodiment, the positional relationship between the first substrate 20 and the second substrate 30 and the bent portion (horizontal wiring 36) in the Z direction is the same as in the first embodiment described above. In the second embodiment, the positional relationship between the horizontal wirings 27, 28, 37-39 and the bent portion (horizontal wiring 36) in the Z direction is the same as in the first embodiment described above. In the second embodiment, the positional relationship between the joint pads 23, 33 and the bent portion in the Z direction is the same as in the first embodiment described above. In addition, as in the first embodiment described above, other horizontal wirings 36a other than the bent portion may be formed at the same Z position where the bent portion is located.

[0068] In the second embodiment as well, the upper end of the vertical wiring 24 is electrically connected to the read circuit 14 provided on the first substrate 20, either directly or via other wiring. The lower end of the vertical wiring 34 is electrically connected to the processing unit 16 or control unit 17 provided on the second substrate 30, either directly or via other wiring.

[0069] In the first embodiment or the second embodiment, the image sensor 3a has its bent portions 26 and 36 located in the first or second part near the pads 23 and 33, which are the joining portions. This reduces the impact on the wiring layout for controlling the readout circuit 14, processing unit 16, or control unit 17, etc. Furthermore, the bent portions 26 and 36 may be provided at a distance of no more than 1 / 4 of the distance between the first substrate 20 and the second substrate 30 from the joint pads 23 and 33. This reduces the impact on the wiring layout for controlling the read circuit 14, processing unit 16, or control unit 17, etc.

[0070] Pads 23 and 33 refer to electrodes whose area in the XY plane is larger than the area of ​​the vertical wiring 24, 25, and 34. However, if the first substrate 20 and the second substrate 30 can be stacked with high positional accuracy, it is not necessary to increase the area of ​​the joint. In this case, electrodes with an area in the XY plane similar to the area of ​​the vertical wiring 24, 25, and 34 may be used as the joint.

[0071] In the image sensors 3 and 3a of each of the embodiments described above, the photoelectric conversion unit 13 and the readout circuit 14, which are located on the first substrate 20, are each provided with connection parts (23-26, 33-36) that connect to the processing unit 16 or control unit 17 of the second substrate 30. However, the number of connection points (23-26, 33-36) may be less than the number of readout circuits 14. For example, on the imaging surface of the image sensor 3 shown in Figure 2, one connection point (23-26, 33-36) may be provided for multiple pixels 10 (for example, 4x4 in Figure 2) each located within a block BC enclosed by a dashed line. In other words, one connection point (23-26, 33-36) is shared by multiple pixels 10 located within block BC. Alternatively, one circuit unit 15 may be provided for multiple pixels 10 located within block BC. In other words, one circuit unit 15 is shared by multiple pixels 10 located within block BC.

[0072] In this case, the signals (pixel signals) generated by the multiple photoelectric conversion units 13, each having multiple pixels 10 within a single block BC, are sequentially output to the processing unit 16 of the second substrate 30 via a single connection (23-26, 33-36). Control signals from the control units 17a-17d of the second substrate 30 are also sequentially or simultaneously output to the multiple readout circuits 14 contained within a single block BC of the first substrate 20 via a single connection (23-26, 33-36).

[0073] Furthermore, even in image sensors 3 and 3a, which have a configuration in which one connection part and circuit unit 15 (processing unit 16, control unit 17) are provided for each block BC having multiple pixels 10, the problem arises that the corresponding circuit unit 15 cannot be placed directly below each block BC. However, as described above, this problem is solved in the first embodiment by providing a bent portion 26 in the wiring layer 21 of the image sensor 3, and in the second embodiment by providing a bent portion 36 in the wiring layer 31 of the image sensor 3a.

[0074] Furthermore, in the image sensor 3a of the second embodiment, similar to the image sensor 3 of the first embodiment described above, many control lines are arranged near the substrate 20 and near the substrate 30 to transmit high-frequency control signals for controlling various transistors or switching elements. Therefore, in the image sensor 3a of the second embodiment, by providing a bent portion 36 in a part other than the vicinity of the first substrate 20 and the vicinity of the second substrate 30, the influence of noise from the control lines to the bent portion 36 and the influence of noise from the bent portion 36 to the control lines are reduced.

[0075] In the image sensor 3a of the second embodiment, the bent portion 36 is provided in the second horizontal wiring 36, 36a in the +Z direction from the bonding surface 50 within the wiring layer 31. However, the bent portion 36 may also be provided in the first horizontal wiring 40 in the +Z direction from the bonding surface 50 within the wiring layer 31. The bent portion 36 may also be provided in the third or higher horizontal wiring in the +Z direction from the bonding surface 50 within the wiring layer 31, as long as it is on the side closer to the bonding surface 50.

[0076] Both the image sensor 3 of the first embodiment and the image sensor 3a of the second embodiment are so-called stacked sensors, formed by stacking a first substrate 20 and a second substrate 30. As a result, numerous control lines for controlling transistors and other components formed on each substrate are formed near the first substrate 20 and near the second substrate 30. Providing bent portions 26 and 36 in locations other than near the first substrate 20 and the second substrate 30 is a configuration unique to stacked sensors in order to suppress the influence of noise from these control lines and to ensure flexibility in placement. In other words, providing bent portions 26 and 36 near the joints (pads 23 and 33) of the first substrate 20 and the second substrate 30 is a configuration unique to stacked sensors.

[0077] In the image sensors 3 and 3a of the embodiments described above, the length of the connection parts (23-26, 33-36) connected to each readout circuit 14 differs depending on the length of the bent parts 26 and 36 included therein. Therefore, the impedance of each connection part (23-26, 33-36) may differ depending on the length of the bent parts 26 and 36. If the impedance of each connection part (23-26, 33-36) changes, striped noise associated with the change in impedance may occur in the image obtained from the image sensors 3 and 3a.

[0078] To avoid this striped noise, the thickness (wire width) of the wiring at each connection point (23-26, 33-36) may be varied based on the length of the bent sections 26 and 36 so that the impedance of each connection point is approximately equal. Alternatively, to minimize the impedance fluctuation at each connection point (23-26, 33-36), conductors with low electrical resistance may be used for the wiring layers used in the bent sections 26 and 36.

[0079] Alternatively, connection points where the bent portions 26 and 36 are shorter than those of other connection points, so that the impedance of each connection point is approximately equal, may have a component that generates electrical resistance. Alternatively, to avoid this striped noise, the characteristics of the current source CS connected to each connection point (23-26, 33-36) may be varied according to the length of the bent sections 26 and 36 included in each connection point. The characteristic of the current source CS to be varied is, for example, the amount of current supplied.

[0080] (1) The image sensors 3 and 3a of each of the above embodiments include, from a first viewpoint, a first substrate 20 on which a photoelectric conversion unit 13 that converts light into electric charge and a readout circuit 14 that outputs a signal based on the charge generated by the photoelectric conversion unit 13 are provided; a second substrate 30 laminated on the first substrate 20 and on which a processing unit 16 that processes the signal output from the readout circuit 14 is provided; and a bending portion 26 and 36 that bends outside the vicinity of the first substrate 20 and the second substrate 30, and a connecting portion (23-26, 33-36) that electrically connects the readout circuit 14 and the processing unit 16. With this configuration, even if the X-direction or Y-direction arrangement periods of the photoelectric conversion unit 13 or the readout circuit 14 and the corresponding processing unit 16 are different, they can be electrically connected by the connecting parts (23-26, 33-36).

[0081] Furthermore, by positioning the bent sections 26 and 36 away from the vicinity of the first and second substrates 20 and 30 where various types of wiring are concentrated, the bent sections 26 and 36 can be positioned without adversely affecting the layout of other wiring. This prevents an increase in impedance in the various types of wiring.

[0082] (2) The image sensors 3 and 3a of each of the above embodiments include, from a second viewpoint, a first substrate 20 on which a photoelectric conversion unit 13 that converts light into electric charge and a readout circuit 14 that outputs a signal based on the charge generated by the photoelectric conversion unit 13 are provided; a second substrate 30 laminated on the first substrate 20 and on which a control unit 17 that controls the readout circuit 14 is provided; and a connection part (23-26, 33-36) that has bent parts 26 and 36 that bend outside the vicinity of the first substrate 20 and the second substrate 30 and electrically connects the readout circuit 14 and the control unit 17. With this configuration, even if the periodicity of the arrangement of the photoelectric conversion unit 13 or the readout circuit 14 and the corresponding control unit 17 in the X or Y direction is different, the two can be electrically connected by the connecting parts (23-26, 33-36). Furthermore, by positioning the bent sections 26 and 36 away from the vicinity of the first and second substrates 20 and 30 where various types of wiring are concentrated, the bent sections 26 and 36 can be positioned without adversely affecting the layout of other wiring. This prevents an increase in impedance in the various types of wiring.

[0083] (3) Furthermore, by configuring the connection parts (23-26, 33-36) so that there are no bent portions 26, 36 near the first substrate 20 and near the second substrate 30, the degree of freedom in the layout of various wirings can be further increased and the increase in impedance of various wirings can be further suppressed. (4) Furthermore, by configuring the bent portions 26 and 36 to be located at a distance of 1 / 4 or more of the distance between the first substrate 20 and the second substrate 30 from the first substrate 20 and the second substrate 30, the degree of freedom in the layout of various wirings can be further increased, and the increase in impedance of various wirings can be further suppressed.

[0084] (5) Furthermore, by providing a plurality of wiring layers 26-28, 36-38 between the first substrate 20 and the second substrate 30, and by providing the bent portions 26, 36 in the wiring layers, the manufacturing costs of the wiring layers and the bent portions can be reduced. (6) Furthermore, by providing at least two wiring layers 27, 28, 37, and 38 between the first substrate 20 and the bent portions 26, 36, and between the second substrate 30 and the bent portions 26, 36, the wiring layers 27, 28, 37, and 38 can be used to wire the electrical circuits formed on the first substrate 20 and the second substrate 30.

[0085] Although various embodiments and modifications have been described above, the present invention is not limited to these. Furthermore, each embodiment and modification may be applied individually or in combination. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0086] The disclosures of the following priority application are incorporated herein by reference. Japanese Patent Application No. 2019-180783 (filed September 30, 2019) [Explanation of Symbols]

[0087] 1: Imaging device, 2: Imaging lens, 3: Image sensor, 4: Imaging control unit (generation unit), 5: Lens movement unit, BC: Pixel block, HC: Horizontal control unit, VC: Vertical control unit, CU: Element control unit, 10: Pixel, 20: First substrate, 30: Second substrate, 11: Microlens, 12: Color filter, 13: Photoelectric conversion unit, 14: Readout circuit, 15: Circuit unit, 16: Processing unit, 17: Control unit, 17a: Selection control unit, 17b: Voltage control unit, 17c: Reset control unit, 17d: Transfer control unit, 21: First layer, 2 2: First insulating layer, 24-29: Wiring, 31: Second layer, 32: Second insulating layer, 34-40: Wiring, 23, 33: Pads, 50: Junction surface, TX: Transfer section (transfer transistor), TR: Discharge section (reset transistor), TA: Amplifier section (amplifier transistor), TS: Selection section (selection transistor), FD: Floating diffusion (FD), TRN: Transfer control line, RST: Reset control line, VDD: Power supply voltage line, SEL: Selection control line, SL: Output signal line, ADC: Readout section, CS: Current source

Claims

[Claim 1] A first substrate having a first photoelectric conversion unit that converts light into electric charge, A second substrate laminated together with the first substrate, having a circuit section including a first processing unit that performs signal processing on a first signal based on the charge converted by the first photoelectric conversion unit, A connection portion for electrically connecting the first substrate and the second substrate, comprising: a first joint portion including a first conductive member arranged to face each other in the stacking direction in which the first substrate and the second substrate are stacked; and a first signal line electrically connected to the first joint portion for outputting the first signal to the first processing unit. Equipped with, The first signal line has a first portion extended along the stacking direction and a second portion extended along a direction intersecting the stacking direction. Image sensor.

Images