Method for decoding multi-level low-density parity check codes, error correction decoding device, control circuit, and program storage medium

Abstract

The objective is to obtain a method for decoding a multi-variable low-density parity check code that can reduce the amount of memory in the memory device constituting the decoding circuit for the multi-variable low-density parity check code, and also reduce the amount of computation required. [Solution] The decoding method for a multi-variable low-density parity check code involves performing row operations and column operations on the result of binary expansion of the Galois field elements that constitute the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

Description

[Technical Field]

[0001] This disclosure relates to a method for decoding a multi-source low-density parity check code, an error correction decoding device, a control circuit, and a programmable storage medium. [Background technology]

[0002] When q is an integer greater than 2, decoding of a q-element low-density parity check code is performed using a message-passing decoding method, similar to decoding a two-element low-density parity check code. This method involves estimating the transmitted bits and transmitted codeword by exchanging numerical values ​​called messages between adjacent nodes on the Tanner graph. In the following, low-density parity check may be referred to as "LDPC," which is an abbreviation for "Low Density Parity Check."

[0003] Figure 7 is a diagram illustrating the row operation in message-passing decoding. In the row operation in message-passing decoding, the message mij(α)(α∈GF(q)) transmitted from the check node pi(i=1,2,···,m) to its adjacent bit node cj(j∈Ai) in Figure 7 is updated. Figure 8 is a diagram illustrating the column operation in message-passing decoding. In the column operation in message-passing decoding, the message mji(α)(α∈GF(q)) transmitted from the bit node cj(j=1,2,···,n) to its adjacent check node pi(i∈Bj) in Figure 8 is updated.

[0004] The above row and column operations are repeated a predetermined number of times to perform the decoding process using the message passing decoding method. In the row operation, when updating the message mij(α)(α∈GF(q)), calculations are performed for all q possible values ​​for α. In the column operation, when updating the message mji(α)(α∈GF(q)), calculations are performed for all q possible values ​​for α. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Yu Maeda, Haruhiko Kaneko, "Configuration and Evaluation of Multi-Level Cell Flash Memory for Multi-Level Cell Flash Memory," 8th Forum on Information Science and Technology, Information Processing Society of Japan, September 2009, Vol. 1, pp. 217-222. [Overview of the project] [Problems that the invention aims to solve]

[0006] In the conventional decoding process for q-element LDPC codes when q is an integer greater than 2, the intermediate values ​​stored in the row and column operations require row and column operations for each of the q elements (the number of elements constituting each symbol) for each non-zero component of the check matrix. Therefore, the conventional decoding process for q-element LDPC codes has the problem of requiring a large amount of memory resources in the row and column operations, and of the computational load being large for all elements of the symbol.

[0007] This disclosure has been made in view of the above, and aims to provide a method for decoding a multi-variable low-density parity check code that can reduce the amount of memory in the memory device constituting the decoding circuit for the multi-variable low-density parity check code and reduce the amount of computation. [Means for solving the problem]

[0008] To solve the above-mentioned problems and achieve the objective, the decoding method for a multi-variable low-density parity check code according to this disclosure is characterized in that, in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field, row operations and column operations are performed on the result of binary expansion of the elements of the Galois field that constitute the check matrix. [Effects of the Invention]

[0009] The decoding method of the multi - ary low - density parity - check code according to the present disclosure has the effect of reducing the memory amount of the storage device constituting the decoding circuit of the multi - ary low - density parity - check code and reducing the amount of computation.

Brief Description of Drawings

[0010] [Figure 1] Figure showing the configuration of the error - correction decoding device according to Embodiment 1 [Figure 2] Figure showing the hardware configuration when the function of the error - correction decoding device according to Embodiment 1 is realized by hardware [Figure 3] Figure showing the hardware configuration when the function of the error - correction decoding device according to Embodiment 1 is realized by software [Figure 4] Figure showing the control circuit for controlling the operations executed by the error - correction decoding device according to Embodiment 1 [Figure 5] Figure showing the program storage medium storing the program for controlling the operations executed by the error - correction decoding device according to Embodiment 1 [Figure 6] Figure showing an example of the check matrix constituting the multi - ary low - density parity - check code [Figure 7] Figure for explaining the row operation processing in the message - passing decoding method [Figure 8] Figure for explaining the column operation processing in the message - passing decoding method

Modes for Carrying Out the Invention

[0011] Hereinafter, the decoding method of the multi - ary low - density parity - check code, the error - correction decoding device, the control circuit, and the program storage medium according to the embodiment will be described in detail based on the drawings.

[0012] Embodiment 1. First, the configuration of the error correction decoding device 50 according to Embodiment 1 will be described. Figure 1 is a diagram showing the configuration of the error correction decoding device 50 according to Embodiment 1. The error correction decoding device 50 includes a storage means 1 for storing soft determination information of received data, and an intermediate value storage means 2 which includes a plurality of register files for updating data during the decoding process of LDPC codes, which is performed using the data stored in the storage means 1 as initial values. At least a portion of each of the storage means 1 and the intermediate value storage means 2 is composed of memory such as semiconductor memory.

[0013] The error correction decoding device 50 further includes a control means 3 for controlling the operation of multiple components of the error correction decoding device 50, and a binary expansion check matrix table 4 which has information indicating the addresses of data to be read from the intermediate value storage means 2 when row operation processing and column operation processing. At least a portion of the binary expansion check matrix table 4 is composed of memory such as semiconductor memory. The error correction decoding device 50 further includes a selection means 5 for selecting values ​​to be read from the intermediate value storage means 2 according to the values ​​in the binary expansion check matrix table 4, a row operation means 6 for performing row operation processing of LDPC decoding, and a column operation means 7 for performing column operation processing of LDPC decoding.

[0014] Next, the operation of the error correction decoding device 50 will be described. The following operations are controlled by the control means 3. First, the received soft judgment data is input to the storage means 1. The control means 3 causes the soft judgment data of each bit to be stored in the storage means 1. After the storage of soft judgment data for one code in the storage means 1 is complete, the control means 3 writes the contents of the storage means 1 to the intermediate value storage means 2 according to the structure of the column weights obtained by binary expansion of the elements of the Galois field which are components of the check matrix that constitute the LDPC code.

[0015] For example, if the column weight of the first column of the check matrix when it is binary expanded is K1, the control means 3 copies K1 soft decision data bits of the first bit stored in the storage means 1 and writes them to the intermediate value storage means 2 from address 0 to address (K1-1). K1 is an integer greater than or equal to 2. If the column weight of the second column of the check matrix when it is binary expanded is K2, the control means 3 copies K2 soft decision data bits of the second bit stored in the storage means 1 and writes them to the intermediate value storage means 2 from address K1 to address (K1+K2-1). K2 is an integer greater than or equal to 2. The control means 3 continues the above operations in the same manner until it reaches the last column of the check matrix, thereby initializing the intermediate value storage means 2.

[0016] Once the writing of the soft judgment data to the intermediate value storage means 2 is complete, the error correction decoding device 50 repeats row arithmetic processing and column arithmetic processing a predetermined number of times.

[0017] In each row calculation process, the selection means 5 selects non-zero data for each row of the binary expanded check matrix from the intermediate value storage means 2. The address information used by the selection means 5 when selecting data from the intermediate value storage means 2 is read by the selection means 5 based on the addresses of the values ​​shown in the binary expanded check matrix table 4. The selection means 5 inputs the selected data to the row calculation means 6.

[0018] The row arithmetic unit 6 performs row arithmetic processing for LDPC decoding using a commonly used algorithm such as a min-sum algorithm or an offset min-sum algorithm, depending on the LDPC decoding algorithm. Based on the results calculated by the row arithmetic unit 6, the values ​​read from the intermediate value storage unit 2 are updated. Row arithmetic processing is performed on all rows of the check matrix that has been binary expanded.

[0019] In each column calculation process, the selection means 5 selects non-zero component data for each column of the binary expanded check matrix from the intermediate value storage means 2. The address information used by the selection means 5 when selecting data from the intermediate value storage means 2 is read by the selection means 5 based on the addresses of the values ​​shown in the binary expanded check matrix table 4. The selection means 5 inputs the selected data into the column calculation means 7.

[0020] The column arithmetic unit 7 performs an addition operation by adding the input soft-decision information of each bit read from the storage unit 1 with the data input from the intermediate value storage unit 2. When the addition operation is repeated, the column arithmetic unit 7 outputs the result of subtracting its own data from the sum of all the input data, and updates the value read from the intermediate value storage unit 2. When performing the final column arithmetic operation which is predetermined, the column arithmetic unit 7 outputs the decoded result based on the sign of the addition result.

[0021] While conventional methods require memory elements for all elements, the error correction decoding device 50 according to Embodiment 1 reduces the amount of memory required for the data stored in the intermediate value storage means 2 because, as a result of binary expansion of the elements of the Galois field constituting the check matrix, memory elements are only required for non-zero components.

[0022] Furthermore, the error correction decoding device 50 can reduce the amount of memory used in row and column arithmetic operations, thereby reducing the amount of computation required to update the values ​​stored in the intermediate value storage means 2.

[0023] In other words, the decoding method and error correction decoding device 50 for a multi-variable low-density parity check code according to Embodiment 1 performs row and column operations on the result of binary expansion of the Galois field elements of the components constituting the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field. Therefore, the decoding method and error correction decoding device 50 for a multi-variable low-density parity check code according to Embodiment 1 can reduce the amount of memory in the storage device constituting the decoding circuit for the multi-variable low-density parity check code and reduce the amount of computation.

[0024] Figure 2 shows the hardware configuration when the functions of the error correction decoding device 50 according to Embodiment 1 are implemented in hardware. Figure 2 shows a processing circuit 8 that performs hardware processing as hardware that realizes the functions of the error correction decoding device 50. The processing circuit 8 is dedicated hardware. The processing circuit 8 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0025] All functions of the multiple components constituting the error correction decoding device 50, namely the storage means 1, intermediate value storage means 2, control means 3, binary expansion check matrix table 4, selection means 5, row calculation means 6, and column calculation means 7, may be realized by a single processing circuit 8. Alternatively, multiple processing circuits 8 may be provided that correspond one-to-one with each of the multiple components, and the functions of each of the multiple components may be realized by the corresponding processing circuit 8 among the multiple processing circuits 8.

[0026] Figure 3 shows the hardware configuration when the functions of the error correction decoding device 50 according to Embodiment 1 are implemented in software. Figure 3 shows a processor 9 and memory 10 that implement the functions of the error correction decoding device 50 in software. At least some of the functions of the multiple components that constitute the error correction decoding device 50, namely the storage means 1, intermediate value storage means 2, control means 3, binary expansion check matrix table 4, selection means 5, row calculation means 6, and column calculation means 7, may be implemented by the processor 9.

[0027] If at least some of the functions of the multiple components are implemented by the processor 9, then at least some of the functions are implemented by the processor 9 and software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in memory 10. The processor 9 implements at least some of the functions of the multiple components by reading and executing the program stored in memory 10.

[0028] The error correction decoding device 50, when at least some of the functions of the plurality of components are implemented by the processor 9, has a memory 10 for storing a program in which a storage step for storing input data, an intermediate value storage step, a control step, a selection step, a row calculation step, and a column calculation step will be executed as a result. The program can also be said to cause the computer to execute the procedures or methods of the storage step, intermediate value storage step, control step, selection step, row calculation step, and column calculation step.

[0029] The processor 9 is a CPU (Central Processing Unit), processing system, arithmetic system, microprocessor, or DSP (Digital Signal Processor). The memory 10 is, for example, a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Registered Trademark) (Electrically Erasable Programmable Read-Only Memory), magnetic disk, flexible disk, optical disk, compact disk, minidisc, or DVD (Digital Versatile Disk).

[0030] The functions of the multiple components constituting the error correction decoding device 50, namely the storage means 1, intermediate value storage means 2, control means 3, binary expansion check matrix table 4, selection means 5, row calculation means 6, and column calculation means 7, can be realized by hardware, software, firmware, or a combination thereof. For example, the functions of the row calculation means 6 and column calculation means 7 may be realized by a processing circuit 8, which is dedicated hardware, while the functions of the storage means 1, intermediate value storage means 2, control means 3, binary expansion check matrix table 4, and selection means 5 may be realized by a processor 9 and memory 10. The processor 9 can realize the functions of some or all of the multiple components constituting the error correction decoding device 50 by reading and executing a program stored in memory 10.

[0031] Figure 4 shows a control circuit 11 that controls the operations performed by the error correction decoding device 50 according to Embodiment 1. The control circuit 11 causes the error correction decoding device 50 to perform row operations and column operations on the results of binary expansion of the Galois field elements that constitute the check matrix in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

[0032] FIG. 5 is a diagram showing a program storage medium 12 that stores a program for controlling operations executed by an error correction decoding device 50 according to Embodiment 1. The program storage medium 12 stores a program for causing the error correction decoding device 50 to perform row operation processing and column operation processing on the result of binary expansion of the elements of the Galois field that constitute the components of the check matrix in a multi-dimensional low-density parity-check code that constructs symbols using the elements of the Galois field.

[0033] Embodiment 2. FIG. 6 is a diagram showing an example of a check matrix H that constitutes a multi-dimensional low-density parity-check code. Regarding the check matrix H in FIG. 6, as an example, the case where elements of the Galois field over GF(2 4 ) are used with 1 symbol being 4 bits will be described. Let the primitive polynomial that constitutes the Galois field be p(x) = x 4 + x + 1, and let the root of p(x) = 0 be α.

[0034] When the check matrix H is composed of elements of the Galois field of GF(2 m ), for the received sequence x, since xH T = 0, the received sequence x is symbol-divided every m bits to generate m binary equations, and row operation processing is performed. In Embodiment 2, m is an integer of 2 or more. For example, the following relational expression (1) holds from the equation in the first row of the check matrix H shown in FIG. 6. X2*H 12 + X4*H 14 + X6*H 16 = 0 ···(1)

[0035] H 12 = α 0 、H 14 = α 1 、H 16 = α 3 Let X2, X4, X6 be binary-expanded, and let X2 = (x21, x22, x23, x24), X4 = (x41, x42, x43, x44), X6 = (x61, x62, x63, x64). Then, the following relational expressions (2) to (4) hold. X2*H 12=(x21,x22,x23,x24) ···(2) X4*H 14 =(x42,x43,x44+x41,x41) ···(3) X6*H 16 =(x64+x61,x62+x61,x63+x62,x63) ...(4)

[0036] From relational equations (1) to (4), for example, for the parity node P1 of the first bit, X2*H 12 +X4*H 14 +X6*H 16 Perform row operations on each component and update the value of check node P1=(p11,p12,p13,p14). Similarly, update the values ​​of check nodes P2, P3, and P4.

[0037] Regarding column operations, for example, for the first 4 bits, the non-zero component of the first column of the check matrix H is H for the check nodes P1 to P4 that were updated in the previous row operation. 21 ,H 31 Regarding P2=(p21,p22,p23,p24), P3=(p31,p32,p33,p34), H 21 =α 2 H 31 =α 3 In the case of P2*H 21 This is expressed by the following relation (5), P3*H 31 This can be expressed by the following relation (6). P2*H 21 =(p23,p24+p21,p22+p21,p22) ···(5) P3*H 31 =(p34+p31,p32+p31,p33+p32,p33) ...(6)

[0038] For example, for information node X1=(x11,x12,x13,x14), P2*H 21 +P3*H 31Column operations are performed on each component to update the value of information node X1=(x11,x12,x13,x14). Similarly, calculations are performed on the second column and beyond of the check matrix H to update the values ​​of information nodes X2,X3,X4,X5,X6.

[0039] As described above, in Embodiment 2, m is an integer of 2 or more and the elements of the check matrix H that constitutes the multi-variable low-density parity check code are GF(2 m If it is composed of elements of the Galois field of ), then for a received sequence x, xH T Since this equals 0, the received sequence x is symbol-partitioned into m bits to generate m binary expressions, and row operations are performed.

[0040] As described above, it is not necessary to store the original number of bit nodes and check nodes for each non-zero component of the check matrix; decoding can be performed by storing only the number of elements equal to the bit width when the matrix is ​​binary expanded.

[0041] Furthermore, by reducing the amount of memory used in row and column arithmetic operations, the amount of computation required to update the values ​​stored in the intermediate value storage means can be reduced.

[0042] The configurations shown in the above embodiments are examples only, and it is possible to combine them with other known technologies, combine different embodiments, and omit or modify parts of the configuration without departing from the spirit of the invention. [Explanation of Symbols]

[0043] 1. Storage means, 2. Intermediate value storage means, 3. Control means, 4. Binary expansion check matrix table, 5. Selection means, 6. Row arithmetic means, 7. Column arithmetic means, 8. Processing circuit, 9. Processor, 10. Memory, 11. Control circuit, 12. Program storage medium, 50. Error correction decoding device.

Claims

1. A method for decoding a multivariate low-density parity check code, in which symbols are constructed using elements of a Galois field, characterized by performing row operations and column operations on the results of binary expansion of the elements of the Galois field that constitute the check matrix.

2. m is an integer greater than or equal to 2, and the elements of the check matrix H that constitutes the multi-variable low-density parity check code are GF(2 ｍ If it is composed of elements of the Galois field of ), then for a received sequence x, xH Ｔ The method for decoding a multi-level low-density parity check code according to claim 1, characterized in that, since = 0, the received sequence x is symbol-divided into m bits to generate m binary expressions, and the row operation is performed.

3. An error correction decoding device characterized by performing row operations and column operations on the results of binary expansion of the Galois field elements that constitute the check matrix, in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

4. A control circuit in a multi-variable low-density parity check code, in which symbols are constructed using elements of a Galois field, characterized in that it causes an error correction decoding device to perform row and column operations on the results of binary expansion of the elements of the Galois field that constitute the components of the check matrix.

5. A program storage medium characterized by storing a program that causes an error correction decoding device to perform row and column operations on the results of binary expansion of the Galois field elements that constitute the check matrix, in a multi-variable low-density parity check code in which symbols are constructed using elements of a Galois field.

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