mDiP semiconductor device including backfilled vias

Abstract

This invention provides a method for ensuring electrically low-resistance junctions between stacked mirror die-pair (mDiP) semiconductor devices. [Solution] The mDiP semiconductor device 172 includes deep trench vias 154 on its upper and / or lower surfaces, each having a portion backfilled with a conductive material. Backfilling the deep trench vias 154 ensures that the microbumps of both mDiPs 172 are coplanar with their respective surfaces, thereby minimizing resistance and ensuring a reliable bond. Furthermore, the enlarged size ensures a substantial overlap even if there is a slight misalignment between the first set of deep trench vias 154 and the second set of deep trench vias 154.

Description

Technical Field

[0001] Due to the remarkable growth in the demand for portable household appliances, the need for large-capacity memory devices has been increasing. Non-volatile semiconductor memory devices such as flash memory cards are widely used to meet the ever-growing requirements for the storage and exchange of digital information. The portability, versatility, and customized design of non-volatile memory products, along with their high reliability and ultra-high capacity, make such memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs, mobile phones, and solid-state drives (SSDs).

[0002] Applications of artificial intelligence (AI) and machine learning (ML) require advanced memory and computing solutions with high performance, low power consumption, low latency, and high bandwidth to support intensive read and write operations during the feature training and inference phases. To meet these requirements, 3D Bit Cost Scalable (BiCS) technology has emerged as a viable solution, providing rapid scaling and achieving higher memory capacity per die.

[0003] Conventionally, to increase the memory capacity, multi-die stacking of BiCS memory dies using, for example, wire bonding has been adopted. However, this approach has significant drawbacks, including limitations in the thickness of the semiconductor die. In particular, since there is always a trend to provide a larger memory capacity in a smaller form factor, semiconductor devices are made as thin as possible and are currently fabricated to be about 36 micrometers (μm) or less. However, mechanical or thermal stress factors cause die warping, chipping, and / or cracking during semiconductor package manufacturing, becoming a barrier to further reduction in the thickness of the semiconductor die.

[0004] Furthermore, conventional multi-die stacking methods face significant limitations in meeting customer requirements for compute-in-memory capabilities in artificial intelligence / machine learning (AI / ML) applications. One major drawback is high pin capacitance, which increases power consumption, degrades signal integrity, and thereby reduces overall performance. Additionally, conventional stacking techniques have limited parallelism, restricting the number of simultaneous read and write operations, which is critical for high-speed AI / ML workloads. Higher read latency is another concern, as data access times are longer due to increased interconnection distances and signal propagation delays between stacked dies. Reliability issues associated with microbumps exacerbate these challenges, as microbump-induced stress, electromigration, and thermal cycling can lead to performance degradation and potential failures over time. These limitations, collectively, hinder the adoption of conventional multi-die stacking for AI / ML compute-in-memory architectures, requiring innovative design approaches to overcome these constraints.

[0005] To address these challenges, mirror die pair (mDiP) bonding methods have been developed in which two memory wafers are bonded facing each other. Facing bonding significantly reduces warping and allows for even thinner wafers without causing chipping and / or cracking during semiconductor package processing or assembly. Furthermore, die pairs effectively double memory capacity and enable increased parallelism and bandwidth for computational applications. Electrical connectivity in mDiP die stacks is achieved using through-silicon vias (TSVs) or other high-aspect-ratio deep trench vias that efficiently route high-voltage signals, logic signals, I / O signals, and other signals from the controller die to the memory die.

[0006] This method presents new challenges, for example, in via formation. Conventional TSV formation results in underfilled vias, where a concave meniscus forms at the top and / or bottom of each TSV. Underfilled TSVs can result in high resistance and voids. In other words, underfilled TSVs are electrically isolated. These defects can lead to significant signal transmission loss, data corruption, computational inference latency, and reliability concerns, which can impair product performance and field applicability or use. [Brief explanation of the drawing]

[0007] [Figure 1] This is a flowchart for forming an mDiP memory device according to an embodiment of this technology. [Figure 2] This is a top view of a first semiconductor wafer and a first semiconductor die formed therefrom, according to an embodiment of the present technology. [Figure 3] This is a top view of a second semiconductor wafer and a second semiconductor die formed therefrom, according to an embodiment of the present technology. [Figure 4] This is a cross-sectional end view of the first semiconductor of the first wafer die according to an embodiment of this technology. [Figure 5] This is a cross-sectional end view of the second semiconductor die of the second wafer according to an embodiment of this technology. [Figure 6] This is a cross-sectional end view of a first wafer and a second wafer bonded together to form a CBA memory wafer according to an embodiment of this technology. [Figure 7] This is a cross-sectional end view of a first CBA memory wafer and a second CBA memory wafer arranged to be joined together according to an embodiment of this technology. [Figure 8] This is a cross-sectional end view of a first CBA memory wafer and a second CBA memory wafer joined together to form an mDiP memory wafer according to an embodiment of this technology. [Figure 9] This is a flowchart for forming an mDiP semiconductor memory device from stacked mDiP memory wafers according to an embodiment of this technology. [Figure 10] This is a cross-sectional end view of an mDiP memory wafer having a first surface that has been thinned in a backgrinding and polishing process according to an embodiment of the present technology. [Figure 11] This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer, showing a concave meniscus formed in deep trench vias after thinning of the first wafer surface according to an embodiment of this technology. [Figure 12] This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer, showing the processing of deep trench vias for expanding vias on the first surface according to an embodiment of the present technology. [Figure 13] This is an enlarged cross-sectional view of the first surface of an mDiP memory wafer, showing a deep trench via having an enlarged filling section on the first surface according to an embodiment of the present technology. [Figure 14] This is a cross-sectional end view of an mDiP memory wafer having a second surface thinned in a backgrinding and polishing process according to an embodiment of the present technology. [Figure 15] This is a cross-sectional end view of a pair of mDiP memory wafers joined to each other in an enlarged filled surface section according to an embodiment of this technology. [Figure 16] This is an enlarged cross-sectional edge view of the bonded and enlarged filled surface section of deep trench vias from a first mDiP memory wafer and a second mDiP memory wafer bonded together, according to an embodiment of the present technology. [Figure 17] This is an enlarged cross-sectional edge view of the bonded surface sections of deep trench vias from a first mDiP memory wafer and a second mDiP memory wafer, bonded together, according to an alternative embodiment of the present technology. [Figure 18] This is an enlarged cross-sectional edge view of the bonded surface sections of deep trench vias from first and second bonded mDiP memory wafers according to a further alternative embodiment of the present technology. [Figure 19] This is a cross-sectional end view of multiple mDiPs stacked on a substrate according to an embodiment of this technology. [Modes for carrying out the invention]

[0008] This technology will be described with reference to drawings relating to a mirror die pair (mDiP) semiconductor device including deep trench vias, the upper and / or lower surfaces of the mDiP device including portions backfilled with a conductive material, in embodiments. As described in the background art section, processing of an mDiP semiconductor wafer results in vias having a concave meniscus on the first and / or second surface of the mDiP wafer. By backfilling these concave meniscuses, it is possible to ensure an electrically coupled, solid, and low-resistance bond, for example, with another mDiP semiconductor device or wafer.

[0009] In one example, the backfilled portions of deep trench vias from two bonded mDiP wafers may be enlarged first and then backfilled. This allows for a larger bonding surface area of ​​the bonding pad or microbump. In a further example, when a first via and a second via in adjacent mDiP wafers are bonded to each other, the surface portion of the first via may be enlarged and backfilled, while the surface portion of the second via may be made smaller and backfilled. This increases the likelihood that the second via will fit entirely within the bonding surface or footprint of the second via, thus minimizing the resistivity of the bonding pad or microbump. In another example, similar to the above example, the surface portions of both vias being bonded to each other may be made smaller and backfilled.

[0010] It should be understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the invention to those skilled in the art. In fact, the invention is intended to encompass alternative forms, modifications, and equivalents of these embodiments, which are included in the scope and spirit of the invention as defined by the appended claims. Furthermore, the following detailed description of the invention includes numerous specific details in order to provide a complete understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without such specific details.

[0011] The terms “top” and “bottom,” “upper” and “lower,” and “vertical” and “horizontal,” and their forms, as may be used herein, are for illustrative and illustrative purposes only and do not mean to limit the description of the technique insofar as the items being referenced are interchangeable in position and orientation. Also, as used herein, the terms “substantially” and / or “about” mean that a given dimension or parameter may vary within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±0.15 mm, or ±2.5% of a given dimension.

[0012] For the purposes of this disclosure, physical or electrical connections may be direct or indirect (e.g., through one or more other parts). Where it is referred that a first element is connected, fixed, mounted or coupled to a second element (physically or electrically), the first and second elements may be directly connected, fixed, mounted or coupled to each other, or they may be indirectly connected, fixed, mounted or coupled to each other (physically or electrically). When it is said that a first element is directly connected, fixed, mounted or coupled to a second element, there are no intervening elements between the first and second elements (elements other than adhesive or molten metal used to connect, fix, mount or couple the first and second elements).

[0013] Embodiments of this technology will be described with reference to the flowcharts in Figures 1 and 9, and the figures in Figures 2 to 8 and 10 to 19. In step 200, the first semiconductor wafer 100 may be processed into several first semiconductor dies 102, such as memory array semiconductor dies, as shown in Figure 2. The first semiconductor wafer 100 may start as an ingot of wafer material, which may be single-crystal silicon grown according to either a Czochralski (CZ) process or a floating zone (FZ) process. However, in further embodiments, the first wafer 100 may be formed from other materials by other processes.

[0014] The semiconductor wafer 100 may be cut from an ingot and polished on both a first main plane 104 and a second main plane 105 (Figure 4) opposite the first main plane 104 to provide a smooth surface. The first main plane 104 may undergo various processing steps to divide the wafer 100 into each first semiconductor die 102 and to form the integrated circuits of each first semiconductor die 102 on and / or inside the first main plane 104. In the shown embodiments, each die 102 may have four separate (independently accessible) memory planes, or channels CH0 to CH3. Each channel may consist of more or fewer planes. The memory planes within each channel may be independently controlled. The separate, independently accessible memory planes increase the bandwidth of the die 102, although the separate memory planes may be omitted in further embodiments. Figure 2 further illustrates details of a single semiconductor die 102, including a pattern of bonding pads or microbump pads 106, as described below.

[0015] As shown in the cross-sectional end view of FIG. 4, the processing of the wafer 100 in step 200 can include the formation of an integrated circuit memory cell array 122 formed on a semiconductor or dielectric substrate including layer 124. A reticle can be used to transfer the integrated circuit pattern of each semiconductor die 102 in a photolithography process. The wafer with the transferred pattern can then undergo various processes such as etching, ion implantation, and deposition to create the actual semiconductor components and interconnects necessary to construct the integrated circuit of the semiconductor die 102. In an embodiment, the integrated circuit can be a memory cell array 122 formed as a 3D stacked memory structure having a string of memory cells formed in layers. However, it is understood that the first semiconductor die 102 can be processed to include an integrated circuit other than a 3D stacked memory structure. As described above, in an embodiment, the memory array 122 on each semiconductor die 102 can include separate memory planes for each of channels CH0 to CH3. A passivation layer 128, in one example, an oxide layer or other dielectric layer, can be formed above the metal interconnect layer 130.

[0016] After the formation of the memory cell array 122, in step 204, internal electrical connections can be formed within the first semiconductor die 102. The internal electrical connections can include multiple layers of metal interconnects 130, vias 132, and deep trench vias 134 formed sequentially through the layers of the substrate 124. As described below, the deep trench vias 134 extend through the completed mDiP semiconductor device, and the vias 132 can extend partially through one or more dies of the mDiP semiconductor device. Each via 132, 134 can include sidewalls, barrier metal, and filled metal as described below. In an embodiment, the metal to be filled can be copper, aluminum, their alloys, or other conductive compounds as described below.

[0017] As is known in the art, metal interconnects 130, vias 132, and deep trench vias 134 can be formed by a damascene process, one layer at a time, using, for example, photolithography processes and thin film deposition processes. Photolithography processes can include, for example, pattern definition, plasma, chemical, or dry etching and polishing. Thin film deposition processes can include, for example, sputtering and / or chemical vapor deposition. Metal interconnects 130 can be formed of various conductive metals including, for example, copper and copper alloys known in the art, and vias 132 can be lined and / or filled with various conductive metals including, for example, tungsten, copper, and copper alloys, as is known in the art. As can be seen, for example, in FIG. 4, metal interconnects 130, vias 132, and deep trench vias 134 can be formed to and through memory cell array 102 such that they are adapted to carry signals from and to memory cell array 122, from logic devices, and from host devices.

[0018] In step 208, microbump pads 106 can be formed on the first (active) major plane 104 of the first semiconductor die 102. As shown in FIGS. 2 and 4, these bump pads can be formed over vias 132 and / or 134 and can be used to transfer signals between the semiconductor die 102. The bump pads can be etched into the passivation layer 128, and each bump pad 106 can be formed to cover the liner 136. As is known in the art, bump pads 106 can be formed of, for example, copper, aluminum, and their alloys, and liner 136 can be formed of, for example, a titanium / titanium nitride stack such as Ti / TiN / Ti, although these materials can vary in further embodiments. Bump pads 106 and liner 136 can be applied by deposition and / or plating techniques. The integrated circuit memory array 122 can be electrically connected to the bump pads 106 by metal interconnects 130 and vias 132, 134.

[0019] In step 210, the first (active) surface 104 of the wafer 100 may be supported on a transient carrier (not shown), and the second (inactive) surface 105 may be thinned in a backgrinding process to the final thickness of the wafer 100 (shown in Figure 4). Thinning of the wafer 100 may expose deep trench vias 134 on the second surface 105. Subsequently, in step 212, microbump pads 108 may be formed on the deep trench vias 134 on the inactive surface 105, for example, as shown in Figure 4.

[0020] Figure 2 shows an exemplary pattern of a first semiconductor die 102 on wafer 100. However, the pattern and number of first semiconductor dies 102 shown on wafer 100 in Figure 2 are for illustrative purposes only, and wafer 100 may contain more or fewer first semiconductor dies 102 in different patterns than those shown in further embodiments. Similarly, the patterns and number of pads 106 and microbumps 108 on the first semiconductor die 102 shown in Figures 2 and 4 are for illustrative purposes only. Each first die 102 may contain more pads 106 and / or microbumps 108 than those shown in further embodiments, and may include a variety of other patterns and densities of pads 106 and / or microbumps 108.

[0021] Before, after, or in parallel with the formation of the first semiconductor die on wafer 100, as shown in Figure 3, in step 220, the second semiconductor wafer 110 may be processed into several second semiconductor dies 112, such as CMOS logic circuit dies. The semiconductor wafer 110 may start as an ingot of single-crystal silicon grown according to either CZ, FZ, or other processes. The second semiconductor wafer 110 may be cut and polished on both the first main surface 114 and the second main surface 115 (Figure 5) opposite the first main surface 114 to provide a smooth surface. The first main surface 114 may undergo various processing steps to divide the second wafer 110 into each second semiconductor die 112 and to form integrated circuits of each second semiconductor die 112 on and / or inside the first main surface 114. Figure 3 further illustrates the details of a single semiconductor die 112, including the pattern of the microbump pads 116, as described below.

[0022] In one embodiment, the second semiconductor die 112 may be processed to include an integrated circuit 142 formed within a semiconductor or dielectric substrate 144, as shown in the cross-sectional end view of Figure 5. The integrated circuit 142 may be configured as a logic circuit for controlling read / write operations of one or more integrated memory cell arrays 122. The logic circuit may be manufactured using CMOS technology, but in further embodiments, the logic circuit may be manufactured using other technology. The second semiconductor die 112 may include other and / or additional integrated circuits in further embodiments, as described below. A passivation layer, in one example an oxide layer or other dielectric layer 148, may be formed on the top surface 114.

[0023] After the formation of the CMOS logic circuit 142, in step 224, internal electrical connections may be formed within the second semiconductor die 112. The internal electrical connections may include multiple layers of metal interconnects 150, vias 152, and deep trench vias 154 formed above the logic circuit 142. The metal interconnects 150, vias 152, and deep trench vias 154 may be formed in the same manner as the interconnects 130, vias 132, and deep trench vias 134 described above for die 102.

[0024] For example, as shown in Figure 5, the metal interconnects 150 and vias 152 are connected to the CMOS logic circuit 142 to carry signals to and from the logic circuit 142. In step 228, the microbump pads 116 may be formed on the main plane 114 of the second semiconductor die 112. As shown in Figures 3 and 5, these bump pads may be located above the vias 152. As described below, the bump pads 116 are provided for transferring signals to and from the semiconductor die 112. The bump pads may be etched within the passivation layer 148 and may include a liner 156. The bump pads 116 and liner 156 may be formed in the same manner as the bump pads 106 and liner 136 described above. The CMOS logic circuit 142 may be electrically connected to the bump pads 116 by the metal interconnects 150 and vias 152, 154.

[0025] The number and pattern of the second semiconductor dies 112 on the wafer 110 in Figure 3 are for illustrative purposes only, and the wafer 110 may, in further embodiments, include more or fewer second semiconductor dies 112 and other patterns of the dies 112. Similarly, the patterns of the pads 116 on the second semiconductor dies 112, and the number of bump pads 116, are shown for illustrative purposes only. In further embodiments, each second die 112 may include more bump pads 116 than shown, and may include a variety of other patterns and densities of the bump pads 116.

[0026] Once the manufacturing of the first semiconductor die 102 and the second semiconductor die 112 is complete, in step 230, the first semiconductor wafer 100 and the second semiconductor wafer 110 can be fixed together such that each memory die 102 is bonded to the CMOS logic circuit die 112. The bonded wafers 100 and 110 are referred to herein as CBA memory wafers 158, and each pair of bonded dies 102 and 112 are referred to herein as CBA memory dies 160. An example of a completed CBA memory die 160 is shown, for example, in the cross-sectional end view of Figure 6.

[0027] To bond dies 102 and 112, the first semiconductor wafer 100 may be inverted (relative to the diagram in Figure 4), and the bump pads 106 and 116 of each die 102 and 112 may be physically and electrically coupled to one another. As shown and described, the number and pattern of bump pads 106 may match the number and pattern of bump pads 116 such that the pads are aligned with each other when dies 102 and 112 are bonded to each other. In embodiments where the number and pattern of bump pads 106 and 116 are not symmetrical with respect to the central vertical axis through the die, the number and pattern of bump pads 106 may be a mirror image of the number and pattern of bump pads 116 such that the pads 106 and 116 are aligned when die 102 is inverted.

[0028] The first semiconductor die 102 and the second semiconductor die 112 within the CBA memory die 160 can be joined to each other by first aligning the bump pads 106 and 116 on their respective dies 102 and 112 with respect to each other. Subsequently, the bump pads 106 and 116 can be joined to each other by any of various joining techniques, depending in part on the bump pad size and bump pad spacing (i.e., bump pad pitch). These joining techniques include, for example, Cu-Cu joining, oxide-oxide joining, and hybrid joining. The size and pitch of the bump pads may be determined by the number of electrical interconnections required for the CBA memory die.

[0029] In step 226, two CBA memory wafers 158 can be joined facing each other to form a mirror die pair (mDiP) wafer. As described in the background art section, joining wafers facing each other solves problems such as warping and chipping in the packaging process or assembly. The active surfaces 104 of the first and second CBA memory wafers 158 can be joined facing each other as shown in Figures 7 and 8. Figures 9 and 10 show further details of this joining at the die level.

[0030] As shown in Figure 7, one of the CBA memory wafers 158 can be flipped over and placed on top of the second CBA memory wafer 158 so that the bump pads 108 on each of the CBA wafers 158 are aligned with one another. The individual dies of the CBA memory wafer 158 are referred to herein as dies 160. The bump pads 108 of each CBA memory wafer 158, when joined together, can be physically joined to each other by Cu-Cu junctions, oxide-oxide junctions, and hybrid junctions, among others. Other wafer-wafer joining techniques are also possible. Such further techniques include various dielectric-dielectric joining techniques, including silicon-silicon junctions and silicon-silicon dioxide junctions. The two joined CBA memory wafers 158a and 158b are referred herein as a mirror die pair (mDiP) wafer 170, as shown in Figure 8. The individual dies joined facing each other within the mDiP wafer are referred herein as mDiP 172.

[0031] Next, with reference to the flowchart in Figure 9, further processing to transform the mDiP wafer 170 into a completed mDiP semiconductor device will be described. As shown in Figure 8, the mDiP wafer 170 has a first main plane (inert) surface 174 and a second main plane (inert) surface 176 on the opposite side. One of the CBA memory wafers 158 (e.g., the upper CBA wafer 158a) undergoes a backgrinding process on the main plane 174 in step 230, which can thin the wafer 110 of the first CBA memory wafer 158a from, for example, 760 μm to a final thickness that may range from 10 μm to 36 μm. The surface 174 can then be polished in step 232. This structure is shown in Figure 10. It will be understood that in further embodiments, the final thickness of the thinned wafer 110 may be greater or less than the above range.

[0032] The backgrinding and polishing processes of steps 230 and 232 can expose deep trench vias 154 on the main plane 174 of the upper CBA memory wafer 158a. However, as described in the background art section, the backgrinding and polishing processes may also cause a concave meniscus to form on the vias 154 on the surface 174. This feature is shown in detail in Figure 11. Figure 11 shows deep trench vias 154 formed on the substrate 124. Each deep trench via 154 may include a sidewall 180, a barrier metal 182, and a filler metal 184, as described above. The sidewall 180 may be formed of an oxide such as silicon oxide. The barrier metal 182 may be, for example, titanium nitride and / or titanium (TiN / Ti). The filler metal 184 may be, for example, copper, aluminum, and alloys thereof. The barrier metal 182 and filler metal 184 may be other low-resistance metals, metal alloys, Si / metal alloys, or other binary or ternary compounds. Figure 11 shows the concave meniscus 186 formed on the main plane 174 within each deep trench via 154.

[0033] The concave meniscuses of various deep trench vias 154 exposed on surface 174 are processed as described below with respect to Figures 12 and 13. In step 234, the ends of the vias 154 on surface 174 are enlarged as shown by reference numeral 188 in Figure 12. The enlarged portion 188 can remove the concave meniscus 186 in each deep trench via 154. The deep trench vias 154 may have a diameter of 1 μm to 10 μm (before step 234), although the diameter of the deep trench vias 154 may be larger or smaller in further embodiments. In step 234, the ends of the vias 154 on surface 174 may be enlarged by 10% to 100%. In further examples, the ends of the vias 154 on surface 174 may be enlarged by 25% to 75%. In further examples, the ends of the vias 154 on surface 174 may be enlarged by 40% to 60%. These various ranges are merely examples, and the ends of the vias 154 on the surface 174 may be enlarged or reduced beyond these ranges in further embodiments. The depth of the via enlargement from the surface 174 may be 1 μm to 5 μm, but the depth of the via enlargement may be smaller or larger than this range in further embodiments.

[0034] The deep trench vias 154 may be enlarged on the surface 174 by various techniques, including, for example, chemical etching, plasma etching, laser ablation, ion and reactive ion etching, deep reactive ion etching, and wet etching. It is understood that the via enlargement in step 234 may be enlarged by other methods in further embodiments. The shape of the enlarged portion may be circular and concentric with the rest of each deep trench via 154. The enlarged portion in each deep trench via 154 may have other shapes in further embodiments.

[0035] In step 238, the enlarged portion 188 may be backfilled with a conductive, low-resistance metal, such as copper, aluminum, and alloys thereof, to form an enlarged micropad 190, as shown in Figure 13. In embodiments, the backfill metal forming the enlarged micropad 190 may be the same as the filler metal 184 forming the remainder of the conductive portion of the deep trench via 154.

[0036] Next, as shown in Figure 14, the mDiP wafer 170 can be turned over and the first main plane 174 can be supported on the temporary carrier 192. Subsequently, the above steps can be repeated on the second main plane 176. In particular, the surface 176 can be thinned in backgrinding and polishing steps 240 and 242 to expose the deep trench vias 154 and form a concave meniscus as described above. In step 244, an enlarged portion 188 can be formed on each deep trench via 154 of the second main flat surface 176, and in step 248, the enlarged portion can be backfilled to form an enlarged micropad 190 on each deep trench via 154 of the second main flat surface 176, as shown in Figure 14.

[0037] Figures 10 and 14 show individual mDiP172 for simplicity, but during the manufacturing stage, the mDiP172 are still part of their respective mDiP wafers 170. After forming the enlarged micropad 190 on the second main plane 176, in step 250, the mDiP wafer 170 can be supported on a dicing tape and the mDiP wafer 170 can be diced to form individual mDiP172. Each of these mDiP172 includes a first CBA memory die 160a and a second CBA memory die 160b mounted facing each other. The mDiP memory wafer 170 can be diced into individual mDiP172 using, for example, stealth laser dicing. In further embodiments, saw blades and other conventional methods can be used. After dicing, the dicing tape can be separated and spread to facilitate picking of the mDiP172 from the dicing tape by a pick-and-place robot (not shown).

[0038] According to an embodiment of this technology, when the respective CBA memory wafers 158a and 158b are mounted facing each other with their active surfaces facing each other, the different coefficients of thermal expansion cancel each other out, as do the strains resulting from materials with different coefficients of thermal expansion. As a result of this cancellation, the warping of the mDiP 172 is largely or completely eliminated.

[0039] Furthermore, the backfilled enlarged microbumps 190 ensure that each mDiP 172 can be stacked on top of each other and easily, reliably, and effectively joined to one another physically and electrically. Figure 15 shows a pair of mDiP 172s electrically and physically joined to each other by the enlarged microbumps 190. Figure 16 shows an enlarged sub-view of a pair of mDiPs with enlarged microbumps 190 of deep trench vias 154 joined to each other. The backfilled material ensures that the microbumps 190 of both mDiP 172s are coplanar with their respective surfaces, thereby minimizing resistance and ensuring a secure bond. Furthermore, the enlarged size ensures a substantial overlap even if there is a slight misalignment between the first set of deep trench vias 154 and the second set of deep trench vias 154.

[0040] In some embodiments, the enlarged micropad 190 may have a diameter at least larger than that of the filler metal 184. Such embodiments are shown in Figure 16. In further embodiments, the enlarged micropad 190 as a whole may have a diameter larger than that of the rest of the deep trench via (including the sidewall 180, barrier metal 182, and filler metal 184). Such embodiments are shown in Figure 13.

[0041] In the embodiments described above, the tip of the deep trench via 154 is treated by enlarging the via in step 234 and then backfilling the enlarged via in step 238. In further embodiments, the enlargement step 234 may be omitted. In this embodiment, the deep trench via, including the concave meniscus 186 shown in Figure 11, may be simply filled in step 238 with a conductive metal so that the surface of the deep trench via 154 is coplanar with the surface 174.

[0042] Figure 17 shows an alternative embodiment of the present technology. In this embodiment, one of the main (inactive) planar surfaces of the mDiP (e.g., surface 176) includes an enlarged microbump 190, as described above. However, the opposite main (inactive) plane (174 in this example) includes a deep trench via 154 formed using a reduced-size microbump 194. The reduced microbump 194 can be formed in the same way as the enlarged microbump 190. A portion of each of the deep trench vias 154 near the surface may be removed by chemical etching or other techniques described above. The portion of the space formed by the removed material may then be backfilled with a metal, e.g., the same metal used for the filler metal 184. The backfilled metal may be shaped, for example, as a trapezoid with a diameter that decreases as the microbump approaches the mDiP surface 174.

[0043] In this embodiment, the tip of the reduced-size microbump 194, which is coplanar with the surface of the mDiP, may have a smaller diameter than the filler material 184 to which the reduced-size microbump 194 is bonded. As shown in Figure 17, the reduced-diameter microbump 194 is perfectly aligned within the enlarged microbump 190, even if there is some misalignment of the bonded mDiP 172. This perfect overlap reduces contact resistance and improves signal transmission between the bonded mDiP 172s.

[0044] Figure 18 shows a further embodiment of the present technology, in which deep trench vias 154 in both the first main plane 174 and the second main plane 176 are formed with reduced-size microbumps 194. Thus, when a pair of mDiPs are joined to each other, the reduced-size microbumps 194 on the first mDiP 172 are electrically coupled to the reduced-size microbumps 194 on the second mDiP 172.

[0045] Figure 19 is a cross-sectional end view of an mDiP semiconductor device 195 formed from a number of stacked and interconnected mDiPs 172. A deep trench via 154 is shown extending through the entire mDiP semiconductor device 195. The deep trench via 154 may be connected to a controller die 196 mounted on the base of the device 195. The controller die 196 may be, for example, an ASIC, or a dedicated processor such as an AI processor or graphics processing unit. Generally, the controller die controls the transfer of data to and from the memory cells of the mDiPs 172 in the stack. As described above, each mDiP 172 may consist of a memory die having multiple planes, thus allowing multiple read / write operations to be performed in parallel to a single memory die of the mDiP 172. This significantly increases the bandwidth of input / output operations to and from the mDiP semiconductor device 195. The controller die 196 may be mounted on a host device (not shown), such as a printed circuit board.

[0046] The mDiP semiconductor device 195 can be encapsulated within a mold compound 198 that protects the mDiP 172 in the stack. The encapsulation process can be performed by placing the mDiP semiconductor device 195, or a panel of the mDiP semiconductor device 195, within a mold chase and injecting a liquid mold compound to cover the mDiP 172 and the controller die 196. In further embodiments, other encapsulation processes, including, for example, FFT (Flow Free Thin) compression molding, can be used. The mold compound 198 may include, for example, solid epoxy resin, phenolic resin, fused silica, crystalline silica, carbon black, and / or metal hydroxides. Such molding materials are available, for example, from Sumitomo Corporation and Nitto Denko Corporation, both headquartered in Japan. Other encapsulants from other manufacturers are also possible.

[0047] Referring again to Figures 4 to 6, in the above-described embodiment, when forming the CBA memory die 160, the inactive surface 105 of the memory die 102 is thinned to expose the deep trench vias 134. Then, as described above, the microbump pads 108 can be formed on the exposed deep trench vias 134. Next, the mDiP 170 can be formed by joining a pair of CBA memory dies 160 facing each other by physically and electrically coupling the microbump pads 108 of each CBA memory die 160 together, as shown in Figure 8.

[0048] In a further embodiment of the present technology, instead of forming a microbump pad 108 on an exposed deep trench via 134 (Figure 4), an enlarged microbump 190 or a reduced-size microbump 194 may be formed on the exposed deep trench via 134. In this embodiment, the microbump 190 and / or reduced-size microbump 194 may be formed on the exposed end of the deep trench via 134 as described above with respect to Figures 12-13 and 16-18.

[0049] In the embodiments described above, the backfilled vias 190 and 194 are formed on the exposed main plane of the mDiP. However, the backfilled vias 190 and 194 of this technology may be used on other types of finished semiconductor devices, including, for example, CBA semiconductor devices and other semiconductor memory devices. Furthermore, it is understood that backfilled microbumps may be formed on any via of this technology, regardless of whether the via is exposed after wafer thinning.

[0050] In summary, an example of the present technology relates to a semiconductor device comprising a group of one or more semiconductor dies, wherein the first group of one or more semiconductor dies comprises a memory die, a first main plane, a second main plane, a first set of vias exposed on the first main plane, each via comprising a conductive material and having a concave meniscus on the first main plane, and a conductive backfill material that backfills the concave meniscus within each via, the conductive backfill material making each via coplanar with the first main plane.

[0051] In another example, the technology relates to a mirror die pair (mDiP) semiconductor device comprising a first group of semiconductor dies, the first group of semiconductor dies comprising a first memory die, a first CMOS logic circuit die bonded to the first memory die, a first main plane, a second main plane opposite the first main plane, and a first set of vias exposed on the first main plane, each via of the first set of vias comprising a conductive material and having a concave meniscus on the first main plane, and the first set of vias A conductive backfill material for backfilling the concave meniscus within each of the vias, wherein the conductive backfill material makes each of the vias of the first set of vias coplanar with the first main plane; and a second group of semiconductor dies bonded to a first group of semiconductor dies, the second group of semiconductor dies comprising a second CMOS logic circuit die bonded to a second memory die, a third main plane, and a fourth seed surface opposite the third main plane.

[0052] In a further example, the technology relates to a semiconductor device comprising a group of one or more semiconductor dies, wherein the first group of one or more semiconductor dies comprises a memory die, a first main plane, a second main plane, a first set of vias exposed on the first main plane, each of which comprises a conductive material and has a concave meniscus on the first main plane, and conductive backfilling means for backfilling the concave meniscus within each via and making each via coplanar with the first main plane.

[0053] The detailed description of the invention described herein is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described herein have been selected to best illustrate the principles of the invention and its practical applications, so that those skilled in the art can make the most effective use of the invention by making various modifications to various embodiments suitable for a particular intended use. The scope of the invention is intended to be defined by the claims appended herein.

Claims

1. It is a semiconductor device, A group of one or more semiconductor dies, wherein the first group of one or more semiconductor dies is Memory die and The first principal plane and, The second main plane and, A first set of vias exposed in the first main plane, wherein each via in the first set of vias contains a conductive material and has a concave meniscus in the first main plane, A semiconductor device comprising a conductive backfill material for backfilling the concave meniscus within each of the vias, wherein the conductive backfill material makes each of the vias coplanar with the first main plane.

2. The semiconductor device according to claim 1, wherein each portion of the via containing the conductive backfill material has a diameter that is enlarged relative to the remaining portion of the via.

3. The semiconductor device according to claim 1, wherein each portion of the via containing the conductive backfill material has a trapezoidal shape that narrows toward the first main plane.

4. The semiconductor device according to claim 1, wherein each portion of the via containing the conductive backfill material has a diameter that matches the diameter of the remaining portion of the via.

5. The semiconductor device according to claim 1, wherein the backfill material and the conductive material are the same.

6. The group of one or more semiconductor dies includes a first group of one or more semiconductor dies, the memory die includes a first memory die, and the semiconductor device is The third principal plane and The fourth principal plane, A second set of vias exposed in the fourth main plane, wherein each via of the second set of vias contains a conductive material and has a concave meniscus in the fourth main plane, A semiconductor device according to claim 1, comprising a conductive backfill material for backfilling the concave meniscus within each of the vias of the second set of vias, wherein the conductive backfill material makes each of the vias of the second set of vias coplanar with the fourth main plane.

7. The semiconductor device according to claim 6, wherein the first group and the second group of one or more semiconductor dies are physically and electrically coupled to each other in the second main plane and the third main plane.

8. The semiconductor device according to claim 6, wherein the second main plane and the third main plane include bump pads, and the bump pads on the second plane and the third plane are electrically and physically coupled to each other, joining the first group and the second group of one or more semiconductor dies.

9. The semiconductor device according to claim 8, wherein the portion of the first set of vias containing the conductive backfill material has a diameter enlarged relative to the rest of the vias in the first set, and the portion of the second set of vias containing the conductive backfill material has a diameter enlarged relative to the rest of the vias in the second set.

10. The semiconductor device according to claim 8, wherein the portion of the first set of vias containing the conductive backfill material has a diameter enlarged relative to the rest of the first set of vias, and the portion of the second set of vias containing the conductive backfill material has a trapezoidal shape that narrows toward the fourth main plane.

11. The semiconductor device according to claim 8, wherein the portion of the first set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the first main plane, and the portion of the second set of vias including the conductive backfill material has a trapezoidal shape that narrows toward the fourth main plane.

12. A mirror die pair (mDiP) semiconductor device, A first group of semiconductor dies, wherein the first group of semiconductor dies is The first memory die, A first CMOS logic circuit die bonded to the first memory die, The first principal plane and, The first principal plane and the second principal plane opposite to it, A first set of vias exposed in the first main plane, wherein each via in the first set of vias contains a conductive material and has a concave meniscus in the first main plane, A backfill material for backfilling the concave meniscus within each of the first set of vias, wherein the backfill material makes each of the first set of vias coplanar with the first main plane, A first group of semiconductor dies, including, A second group of semiconductor dies bonded to the first group of semiconductor dies, wherein the second group of semiconductor dies is The second memory die, A second CMOS logic circuit die bonded to the second memory die, The third principal plane and The fourth principal plane opposite to the third principal plane, A second group of semiconductor dies, mDiP semiconductor devices, including those mentioned above.

13. The mDiP semiconductor device according to claim 12, wherein each portion of the via in the first set of vias containing the conductive backfill material has a diameter that is enlarged relative to the remaining portion of each of the vias in the first set of vias.

14. The mDiP semiconductor device according to claim 12, wherein each portion of the vias in the first set of vias containing the conductive backfill material has a trapezoidal shape that narrows toward the first main plane.

15. The mDiP semiconductor device according to claim 12, wherein each portion of the via in the first set of vias containing the conductive backfill material has a diameter that matches the diameter of the conductive material in each of the vias in the first set of vias.

16. The mDiP semiconductor device according to claim 12, wherein the backfill material and the conductive material are the same.

17. The second set of semiconductor dies described above is A second set of vias exposed in the fourth main plane, wherein each via of the second set of vias contains a conductive material and has a concave meniscus in the fourth main plane, A conductive backfill material for backfilling the concave meniscus within each of the vias of the second set of vias, wherein the conductive backfill material makes each of the vias of the second set of vias coplanar with the fourth main plane, The mDiP semiconductor device according to claim 12, further comprising:

18. The mDiP semiconductor device according to claim 17, wherein the first group of semiconductor dies and the second group of semiconductor dies are physically and electrically coupled to each other facing each other on the second surface and the third surface.

19. The mDiP semiconductor device according to claim 10, wherein the portions of the first set of vias and the portions of the second set of vias, which include the conductive backfill material, each have a diameter that is enlarged relative to the rest of the first set of vias and the rest of the second set of vias, and the enlarged diameter vias enhance the electrical connections between the mDiP semiconductor devices in the stack of the mDiP semiconductor devices.

20. It is a semiconductor device, A group of one or more semiconductor dies, wherein the first group of one or more semiconductor dies is Memory die and The first principal plane and, The second main plane and, A first set of vias exposed in the first main plane, wherein each via in the first set of vias contains a conductive material and has a concave meniscus in the first main plane, A semiconductor device comprising: a backfilling means for backfilling the concave meniscus within each via and making each via coplanar with the first main plane.

Images