Packaging substrate and semiconductor package including the same

Abstract

The present invention provides a packaging substrate and a semiconductor package containing the same, which offer excellent thermomechanical reliability and long-term durability. [Solution] The packaging substrate 100 includes a cavity region 11 in which elements are housed and a core substrate 10 on which the cavity region is arranged. The core substrate is a glass substrate. The cavity region includes a housing portion 12, which is a space formed by recessing a part of the core substrate; a side surface 13 formed in the thickness direction of the core substrate to form the outer edge of the housing portion; and an elastic layer 30 arranged adjacent to the side surface. The elastic modulus of the elastic layer is 2 Gpa to 15 Gpa. The surface energy of the elastic layer is 15 dyn / cm to 35 dyn / cm. Such a packaging substrate can have excellent thermomechanical reliability and long-term durability.

Description

Technical Field

[0001] Embodiments relate to a packaging substrate having excellent thermomechanical reliability and long-term durability, and a semiconductor package including the same.

[0002] [Cross-reference to Related Applications] This application claims priority to U.S. Provisional Application No. 63 / 427,427, filed with the United States Patent and Trademark Office on November 22, 2022, the content of which is hereby incorporated by reference in its entirety into the present invention.

Background Art

[0003] In fabricating electronic components, the process of implementing a circuit on a semiconductor wafer is called the front-end (FE) process, and the process of assembling the wafer into a state where it can be used as an actual product is called the back-end (BE) process, and this back-end process includes a packaging process.

[0004] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron line widths in nanometer units, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively, there is no technology to perfectly package this. Therefore, the electrical performance of a semiconductor may be determined by the packaging technology and the electrical connections thereby, rather than the performance of the semiconductor technology itself.

[0005] As materials for packaging substrates, ceramics or resins are applied. In the case of ceramic substrates, it is not easy to mount high-performance high-frequency semiconductor elements because of their high resistance value or high dielectric constant. In the case of resin substrates, relatively high-performance high-frequency semiconductor elements can be mounted, but there is a limit to reducing the wiring pitch.

[0006] Recently, research has been progressing on applying silicon and glass to high-end packaging substrates. By forming through-holes in silicon or glass substrates and applying conductive materials to these holes, the length of wiring between the device and the motherboard can be shortened, resulting in superior electrical characteristics. [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of this embodiment is to provide a packaging substrate with excellent thermomechanical reliability and long-term durability, and a semiconductor package containing the same. [Means for solving the problem]

[0008] A packaging substrate according to one embodiment of this specification includes a cavity region in which an element is housed, and a core substrate on which the cavity region is arranged.

[0009] The core substrate is a glass substrate. The cavity region includes a housing portion which is a space formed by a recess in a part of the core substrate, a side surface which is formed on the inside in the thickness direction of the core substrate and forms the outer edge of the housing portion, and an elastic layer which is disposed adjacent to the side surface.

[0010] The elastic modulus of the aforementioned elastic layer is 2 Gpa to 15 Gpa.

[0011] The thermal expansion coefficient of the elastic layer may be 30 ppm / °C to 70 ppm / °C.

[0012] The packaging substrate may include a redistribution layer disposed on the core substrate.

[0013] The redistribution layer may include an insulating layer and an electrically conductive layer disposed within the insulating layer.

[0014] The difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the elastic layer may be 60 ppm / °C or less.

[0015] The thermal expansion coefficient of the core substrate may be 5 ppm / °C to 20 ppm / °C.

[0016] The side surface of the cavity region may have an angle of 60 degrees or more and less than 90 degrees with respect to the lower surface of the core substrate.

[0017] The elastic layer may have a minimum thickness of 2 μm to 45 μm in the in-plane direction of the core substrate.

[0018] The elastic layer may be placed in contact with the side surface of the cavity region.

[0019] The Ra value (arithmetic mean roughness) of the side surface of the cavity region may be between 1 μm and 50 μm.

[0020] The surface energy of the elastic layer may be 15 dyn / cm to 35 dyn / cm.

[0021] The packaging substrate may include a buffer layer located beneath the core substrate.

[0022] The thermal expansion coefficient of the buffer layer is 10 ppm / °C to 50 ppm / °C.

[0023] Other embodiments of this specification include a packaging substrate comprising a cavity region in which elements are housed, and a core substrate on which the cavity region is arranged.

[0024] The cavity region includes a housing portion which is a space formed by recessing a part of the core substrate, two or more elements housed in the housing portion, and an elastic layer disposed in at least a part of the space formed between the elements.

[0025] The elastic modulus of the aforementioned elastic layer is 2 Gpa to 15 Gpa.

[0026] Another semiconductor package according to an embodiment of the present specification includes the packaging substrate and a main board electrically connected to the packaging substrate.

Advantages of the Invention

[0027] The packaging substrate of the embodiment can exhibit excellent thermo-mechanical reliability and long-term durability.

Brief Description of the Drawings

[0028] [Figure 1A] It is a plan view for explaining a packaging substrate according to an embodiment of the present specification. [Figure 1B] It is a cross-sectional view taken along the line A-A' of FIG. 1A. [Figure 2] It is a cross-sectional view for explaining a packaging substrate according to another embodiment of the present specification. [Figure 3] It is a cross-sectional view for explaining a packaging substrate according to still another embodiment of the present specification. [Figure 4] It is a cross-sectional view for explaining a packaging substrate according to still another embodiment of the present specification. [Figure 5] It is a cross-sectional view for explaining a packaging substrate according to still another embodiment of the present specification. [Figure 6] It is a cross-sectional view for explaining a packaging substrate according to still another embodiment of the present specification. [Figure 7] It is a cross-sectional view for explaining a packaging substrate according to still another embodiment of the present specification.

Best Mode for Carrying Out the Invention

[0029] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. However, the present invention can be realized in various different forms and is not limited to the embodiments described herein. The same reference numerals are given to similar parts throughout the specification.

[0030] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0031] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0033] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0034] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0035] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0036] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.

[0037] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.

[0038] In this specification, unless otherwise specified, a fine line means a line with a width of 5 μm or less, and more specifically, a line with a width of 1 to 4 μm or less.

[0039] In this specification, the difference between value A and value B refers to the absolute value obtained by subtracting value B from value A.

[0040] In this specification, unless otherwise specified, the physical properties of each component within the packaging substrate are assumed to have been measured at room temperature. Room temperature is defined as 20°C to 25°C.

[0041] The manufacturing process for semiconductors in which elements are placed within a cavity includes the process of placing semiconductor elements within the cavity of a core substrate, followed by the formation of multiple build-up layers on the core substrate. These build-up layers are formed through a process that involves tens to hundreds of heating and deheating cycles. During this process, mismatches in the thermal expansion coefficients of the elements and the substrate can repeatedly apply stress to the elements, potentially leading to damage to the elements or substrate, or the loss of electrical connections between the elements and other components within the package.

[0042] Furthermore, heat is generated during the operation of the components within the packaging substrate, and this heat induces thermal expansion of the core substrate and the main board. At this time, the difference in thermal expansion characteristics between the core substrate and the main board can cause warping of the core substrate, which can reduce the reliability of the packaging substrate and the components embedded in the substrate. Such problems occur more frequently as the area of ​​the substrate and components increases.

[0043] The inventors of the embodiment confirmed that by applying an elastic layer to the cavity region and adjusting the elastic modulus of the elastic layer, they could provide a packaging substrate with excellent thermomechanical reliability and long-term durability, and thus completed the embodiment.

[0044] The following provides a detailed explanation of specific examples.

[0045] Structure of the packaging substrate Figure 1A is a plan view illustrating a packaging substrate 100 according to one embodiment of this specification. Figure 1B is a cross-sectional view taken along the line A-A' in Figure 1A. The packaging substrate 100 of the embodiment will be described with reference to Figures 1A and 1B.

[0046] A packaging substrate 100 according to one embodiment of this specification includes a cavity region 11 in which an element 20 is housed, and a core substrate 10 on which the cavity region 11 is arranged.

[0047] The core substrate 10 serves as a support in the packaging substrate 100. The core substrate 10 is separated from the redistribution layer or bumps that are placed above or below it.

[0048] The core substrate 10 may be a substrate selected from a ceramic substrate, a glass substrate, or a combination thereof.

[0049] The ceramic substrate may, for example, be a silicon-based ceramic substrate or a glass-based ceramic substrate. The silicon-based ceramic substrate may be a substrate that includes, in part or in whole, a silicon substrate, a silicon carbide substrate, etc. The glass-based ceramic substrate may be a substrate that includes, in part or in whole, a quartz substrate, a sapphire substrate, etc.

[0050] Examples of glass substrates that can be used include alkali borosilicate glass plates, alkali-free borosilicate glass plates, alkali-free alkaline earth borosilicate glass plates, and any glass plate used in electronic components. Glass substrates for electronic devices can be used, and examples include those manufactured by Schott, AGC, Corning, etc., but are not limited to these.

[0051] The thickness of the core substrate 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. In this case, the thickness refers to the thickness of the core substrate in the portion excluding the cavity region. When a core substrate having such a thickness is applied, it can be used with excellent utility as a substrate for semiconductor packaging.

[0052] The cavity region 11 includes a housing portion 12, which is a space formed by a recess in a part of the core substrate 10; a side surface 13 formed on the inside in the thickness direction Dt of the core substrate and forming the outer edge of the housing portion 12; and an elastic layer 30 arranged adjacent to the side surface 13.

[0053] The housing portion 12 may be formed by the core substrate 10 penetrating vertically (see Figure 1B). However, it is not limited to this, and the housing portion 12 may also be formed by the core substrate 10 not penetrating vertically, but by a partial recess on the upper or lower surface of the core substrate 10 (not shown).

[0054] The side surface 13 of the cavity region may, but is not limited to, form a perpendicular surface to the upper or lower surface of the core substrate 10. When the core substrate 10 is observed in cross-section, the side surface 13 of the cavity region may form an inclined surface or a curved surface.

[0055] Elements can be placed in the housing section 12. The elements may include not only semiconductor elements such as CPUs, GPUs, and memory chips, but also capacitor elements, transistor elements, impedance elements, and other modules. In other words, any semiconductor element that can be mounted on a semiconductor device can be used as the element without limitation.

[0056] The elastic layer 30 may be positioned adjacent to the side surface 13 of the cavity region. The elastic layer 30 can stably fix the element placed on the cavity region 11 and also have the function of buffering the stress applied to the element by the thermal expansion of the core substrate 10 during repeated heating / cooling processes.

[0057] The elastic layer 30 may be positioned in contact with the side surface 13 of the cavity region. The elastic layer 30 may be positioned at a distance from the side surface 13 of the cavity region.

[0058] A heat dissipation layer (not shown) may be placed between the elastic layer 30 and the side surface 13 of the cavity region. The heat dissipation layer can effectively suppress overheating of the packaging substrate by releasing the heat generated in the cavity region during the device drive process to the outside of the packaging substrate.

[0059] The heat dissipation layer may be made of a separate heat dissipation material, and a metal layer having both electrical conductivity and heat dissipation properties may be used. When a metal layer is used as the heat dissipation layer, the metal layer may be grounded to the outside and may be arranged in a form embedded in a separate insulating material.

[0060] A binder resin containing a filler may be used as the material for the heat dissipation layer. The filler may be a material with high thermal conductivity. For example, the binder resin may be an epoxy resin, and the filler may be a metal filler or a carbonaceous filler.

[0061] The thermal conductivity of the heat dissipation layer may be 300 W / mK to 450 W / mK. The heat dissipation layer may be made of the same material as the electrically conductive layer contained within the redistribution layer, which will be detailed below.

[0062] The elastic layer 30 may be positioned in contact with the element placed in the cavity region. The elastic layer 30 may also be positioned at a distance from the element placed in the cavity region.

[0063] As a method for forming the elastic layer 30, one can, but is not limited to, a method in which an element is placed in the housing 12, and then a heated and pressurized resin film or resin composition for manufacturing the elastic layer is embedded in the space formed around the element and cured. For example, a method in which the cured and molded elastic layer is placed in the internal space within the cavity region may also be applied.

[0064] In practice, the thickness T of the elastic layer 30 in the in-plane direction Dp of the core substrate can be controlled. This can help the elastic layer stably fix the element while effectively buffering the thermal stress applied to the element.

[0065] The aforementioned thickness can be measured using a TEM (Transmission Electron Microscope). However, the thickness may also be measured by methods other than TEM.

[0066] The elastic layer 30 may have a thickness T of 3 μm to 50 μm in the in-plane direction Dp of the core substrate. The thickness T may be 5 μm or more. The thickness T may be 10 μm or more. The thickness T may be 15 μm or more. The thickness T may be 20 μm or more. The thickness T may be 25 μm or more. The thickness T may be 45 μm or less. The thickness T may be 40 μm or less. In such cases, the elastic layer 30 can provide the packaging substrate with excellent long-term durability.

[0067] Figure 2 is a conceptual diagram illustrating a packaging substrate 100 according to another embodiment of this specification. Specific examples will be described below with reference to Figure 2.

[0068] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A and 1B above. The differences will be explained below.

[0069] The side surface 13 of the cavity region may be an inclined plane or a curved surface. "Inclined" means that the side surface 13 is not substantially parallel to the thickness direction Dt of the core substrate.

[0070] The side surface 13 of the cavity region may have an angle θ of 60 degrees or more and less than 90 degrees with respect to the lower surface 14 of the core substrate. The elastic layer 30 may have a minimum thickness Tmin in the in-plane direction Dp of the core substrate of 2 μm to 45 μm.

[0071] In one embodiment, the angle θ of the side surface 13 of the cavity region with respect to the lower surface 14 of the core substrate and the thickness distribution of the elastic layer 30 can be controlled simultaneously to adjust the space between the element (not shown) placed on the cavity region 11 and the side surface 13 of the cavity region. Through this, the heated and pressurized resin film for manufacturing the elastic layer can be smoothly embedded in the space, effectively suppressing the generation of voids in the elastic layer 30. At the same time, a stable stress buffering function can be provided to the elastic layer 30.

[0072] The angle θ may be 60 degrees or more and less than 90 degrees. The angle θ may be 70 degrees or more. The angle θ may be 75 degrees or more. The angle θ may be 89 degrees or less. The angle θ may be 87 degrees or less.

[0073] The minimum value Tmin can be 2 μm to 45 μm. The minimum value Tmin may be 3 μm or more. The minimum value Tmin may be 5 μm or more. The minimum value Tmin may be 10 μm or more. The minimum value Tmin may be 15 μm or more. The minimum value Tmin may be 20 μm or more. The minimum value Tmin may be 40 μm or less. The minimum value Tmin may be 35 μm or less.

[0074] In such cases, the elastic layer can stably fix the element placed in the cavity region and effectively protect the element from thermal stress.

[0075] The elastic layer 30 may have a maximum thickness Tmax in the in-plane direction Dp of the core substrate of 3 μm to 50 μm. The maximum Tmax may be 5 μm or more. The maximum Tmax may be 10 μm or more. The maximum Tmax may be 15 μm or more. The maximum Tmax may be 20 μm or more. The maximum Tmax may be 25 μm or more. The maximum Tmax may be 45 μm or less. The maximum Tmax may be 40 μm or less. In such cases, during the formation process of the elastic layer, the molten resin film or resin composition for the elastic layer can be smoothly filled into the internal space around the element.

[0076] The aforementioned thickness can be measured using a TEM (Transmission Electron Microscope).

[0077] Figure 3 is a conceptual diagram illustrating a packaging substrate according to another embodiment of this specification. The following examples will be described with reference to Figure 3.

[0078] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A, 1B, and 2 above. The differences will be explained below.

[0079] The packaging substrate 100 may further include an element 20. The element 20 may be arranged in the housing portion 12.

[0080] The packaging substrate 100 may have a structure in which the element 20 is embedded in an elastic layer 30. That is, the elastic layer 30 may have a structure that surrounds not only the sides of the element 20, but also the top and / or bottom surfaces. In such a case, the elastic layer 30 placed on the top and / or bottom surfaces of the element 20 can act as an insulating layer.

[0081] The elastic layer 30 disposed on the upper and / or lower surface of the element 20 may include an electrically conductive layer 35. The electrically conductive layer 35 may have the function of electrically connecting the element 20 to a redistribution layer (not shown) which may be disposed on the core substrate 10.

[0082] In this embodiment, the thickness T of the elastic layer 30 in the in-plane direction Dp of the core substrate can be controlled. The thickness T of the elastic layer 30 in the in-plane direction Dp of the core substrate is measured in the elastic layer 30 located between the side surface 13 of the cavity region and the cavity element 20.

[0083] The explanation of the thickness T of the elastic layer 30 in the in-plane direction Dp of the core substrate is omitted as it overlaps with the explanation given above.

[0084] The elastic layer 30 described above can be formed by the following method. The element 20 can be placed in a space within the cavity region 11 that can accommodate the element. When placing the element 20 in the cavity region 11, an adhesive film can be applied to the element 20 to fix it in place.

[0085] Subsequently, the resin composition for the elastic layer can be filled into the empty space in the cavity region 11 other than the volume occupied by the element 20, and the filled resin composition can be cured to form an elastic layer 30 on the upper and side portions of the element 20. Examples of methods for filling the resin composition for the elastic layer include injecting the composition using a nozzle such as a syringe, or filling the composition through screen printing.

[0086] An elastic layer 30 can also be formed on the lower part of element 20 using the same method.

[0087] Figure 4 is a conceptual diagram illustrating a packaging substrate according to yet another embodiment of this specification. Specific examples will be described below with reference to Figure 4.

[0088] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A, 1B, 2, and 3 above. The differences will be explained below.

[0089] The packaging substrate 100 may include a redistribution layer 40 disposed on the core substrate 10. The redistribution layer 40 may include an insulating layer (not shown) and an electrically conductive layer (not shown) disposed within the insulating layer.

[0090] In the redistribution layer 40, insulating layers and electrically conductive layers may be arranged in a mixed manner. The redistribution layer 40 may be formed in a manner in which electrically conductive layers having predetermined positions and shapes are embedded within insulating layers. At least a portion of the redistribution layer 40 may be formed of electrically conductive layers as fine wires. The redistribution layer 40 may be electrically connected to the cavity element 20.

[0091] The redistribution layer 40 can be formed by a process of repeatedly forming and removing an insulating layer and an electrically conductive layer.

[0092] The insulating layer may, but is not limited to, be formed through a build-up layer material such as Ajinomoto's ABF (Ajinomoto Build-up Film) or an undercoat material.

[0093] The electrically conductive layer may contain an electrically conductive material. For example, the electrically conductive layer may contain at least one of copper, nickel, aluminum, gold, and silver.

[0094] Figure 5 is a cross-sectional view illustrating a packaging substrate according to yet another embodiment of this specification. An example will be described with reference to Figure 5.

[0095] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A, 1B, 2, 3, and 4 above. The differences will be explained below.

[0096] The packaging substrate 100 includes elements 20 housed in the housing section and may further include a redistribution layer 40 and / or bumps 50 located beneath the core substrate 10.

[0097] The explanation of the redistribution layer 40 located beneath the core substrate 10 will be omitted as it will overlap with the content described above.

[0098] The redistribution layer 40 placed on the core substrate 10 and the redistribution layer 40 placed below the core substrate 10 can be electrically connected to each other by an electrically conductive layer (not shown) that penetrates the core substrate 10 according to a predetermined arrangement diagram.

[0099] The bump 50 may be positioned beneath the core substrate 10 in a predetermined configuration. For example, the bump 50 may be positioned on a portion of the underside of the packaging substrate 100 so as to be in contact with the main board or the like.

[0100] Figure 6 is a cross-sectional view illustrating a packaging substrate 100 according to yet another embodiment of this specification. An example will be described with reference to Figure 6.

[0101] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A, 1B, 2, 3, 4, and 5. The differences will be explained below.

[0102] The packaging substrate 100 may further include a buffer layer 60 placed beneath the core substrate 10.

[0103] The buffer layer 60 can have thermal expansion characteristics controlled within a predetermined range in the embodiment. When the packaging substrate 100 is mounted on the main board (not shown), the buffer layer 60 can have the function of effectively reducing thermal stress caused by the mismatch in thermal expansion coefficients between the core substrate 10 and the main board.

[0104] The buffer layer 60 may include an electrically conductive layer (not shown). The electrically conductive layer has the function of electrically connecting an element (not shown) placed in the cavity region with a redistribution layer (not shown) formed beneath the core substrate 10.

[0105] The material of the buffer layer 60 is not limited as long as it has insulating properties and the thermal expansion properties of the buffer layer as detailed below. For example, the material of the buffer layer may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material which contains reinforcing materials such as glass fibers or inorganic fillers.

[0106] A redistribution layer may be further included below the buffer layer 60. The explanation of the redistribution layer is omitted here as it overlaps with what was previously described.

[0107] Figure 7 is a cross-sectional view illustrating a packaging substrate 100 according to yet another embodiment of this specification. An example will be described with reference to Figure 7.

[0108] The packaging substrate 100 includes a cavity region 11 in which the elements are housed, and a core substrate 10 on which the cavity region 11 is arranged. The specific configuration of the packaging substrate 100 is the same as that described in Figures 1A, 1B, 2, 3, 4, 5, and 6 above. The differences will be explained below.

[0109] A packaging substrate 100 according to another embodiment of this specification includes a cavity region 11 in which the element 20 is housed, and a core substrate 10 on which the cavity region 11 is arranged.

[0110] The cavity region 11 includes a housing portion (not shown) which is a space formed by recessing a part of the core substrate 10, two or more elements 20 housed in the housing portion, and an elastic layer 30 disposed in at least a part of the space formed between the elements.

[0111] At least one of the aforementioned elements may be positioned at a distance from one or more other elements. That is, a space may be formed between one element and other elements.

[0112] The elastic layer 30 can effectively alleviate the stress formed between elements due to thermal expansion of the core substrate that occurs during the redistribution layer formation process or the element driving process.

[0113] The explanation of the core substrate, elements, and elastic layer structure will be omitted as it will overlap with the content described above.

[0114] Physical properties of elastic layers An elastic layer 30 having an elastic modulus value within a predetermined range in the embodiment can be applied to the packaging substrate. Specifically, an elastic layer 30 having a lower elastic modulus value than the core substrate 10 can stably fix the element 20 placed in the cavity region 11 while effectively preventing cracks from occurring in the core substrate 10 due to thermal stress formed between the core substrate 10 and the element 20 in a high-temperature environment.

[0115] The elastic modulus of the elastic layer 30 can be measured through dynamic mechanical analysis (DMA).

[0116] The elastic modulus of the elastic layer 30 can be 2 Gpa to 15 Gpa. The elastic modulus may be 5 Gpa or higher. The elastic modulus may be 12 Gpa or lower. The elastic modulus may be 10 Gpa or lower. In such cases, damage to the semiconductor package due to a mismatch in the thermal expansion coefficients of the core substrate and the element can be effectively suppressed.

[0117] The elastic layer 30, having controlled thermal expansion characteristics, can effectively reduce the stress acting on the element 20 due to the thermal expansion of the elastic layer 30 itself in high-temperature environments. Furthermore, the degree of mismatch in thermal expansion coefficients between the elastic layer 30 and the insulating layer in the redistribution layer 40 is reduced, further improving the reliability of the packaging substrate 100.

[0118] The thermal expansion coefficient of the elastic layer may be 30 ppm / °C to 70 ppm / °C. The thermal expansion coefficient may be 35 ppm / °C or higher. The thermal expansion coefficient may be 40 ppm / °C or higher. The thermal expansion coefficient may be 65 ppm / °C or lower. The thermal expansion coefficient may be 60 ppm / °C or lower. In such cases, damage to the packaging substrate in environments exposed to high temperatures can be effectively suppressed.

[0119] The difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the elastic layer 30 may be 60 ppm / °C or less. The difference may be 50 ppm / °C or less. The difference may be 40 ppm / °C or less. The difference may be 30 ppm / °C or less. The difference may be 20 ppm / °C or less. The difference may be 10 ppm / °C or less. The difference may be 1 ppm / °C or more. In such cases, damage to electrical connections due to a mismatch in the thermal expansion characteristics of the insulating layer and the elastic layer can be suppressed.

[0120] The coefficient of thermal expansion can be measured using a thermal mechanical analyzer (TMA) with thermomechanical analysis. For example, the coefficient of thermal expansion can be measured using the TMA of TA Instruments' Q400 model.

[0121] The elastic layer 30 can be placed in contact with the side surface 13 of the cavity region. In this case, the roughness characteristics of the side surface 13 of the cavity region can be controlled to be within a range predetermined in the embodiment. Through this, the adhesion force between the core substrate 10 and the elastic layer 30 can be further improved by the anchoring effect at the interface between the side surface 13 of the cavity region in contact with the elastic layer 30 and the elastic layer 30.

[0122] The Ra value, which is the arithmetic mean roughness of the side surface 13 of the cavity region, is measured using a roughness measuring instrument in accordance with ISO 4287.

[0123] The Ra value of the side surface 13 of the cavity region may be 1 μm to 50 μm. The Ra value may be 5 μm or more. The Ra value may be 10 μm or more. The Ra value may be 15 μm or more. The Ra value may be 45 μm or less. The Ra value may be 40 μm or less. The Ra value may be 35 μm or less. In such cases, the elastic layer can be attached to the side surface of the cavity region even more stably.

[0124] The surface energy of the elastic layer may be between 15 dyn / cm and 35 dyn / cm.

[0125] The elastic layer in the embodiment can have controlled surface energy characteristics. In such a case, the elastic layer will have improved affinity to the glass core substrate, and the adhesion of the elastic layer to the substrate surface can be further improved. At the same time, by adjusting the dielectric loss tangent characteristics of the elastic layer, it is possible to suppress excessive power loss or heat generation during the device's operation.

[0126] The surface energy of an elastic layer can be measured using a surface analyzer.

[0127] The surface energy of the elastic layer can be 15 dyn / cm to 35 dyn / cm. The surface energy may be 17 dyn / cm or higher. The surface energy may be 20 dyn / cm or higher. The surface energy may be 22 dyn / cm or higher. The surface energy may be 32 dyn / cm or lower. The surface energy may be 30 dyn / cm or lower. The surface energy may be 28 dyn / cm or lower. In such cases, it is possible to provide an elastic layer that has excellent adhesion to the glass substrate and controls the generation of heat due to the operation of the element.

[0128] Composition of the elastic layer The elastic layer 30 can be formed through a resin composition for elastic layers.

[0129] The resin composition for the elastic layer may be in the form of a film.

[0130] The resin composition for the elastic layer may include an epoxy resin. The cured epoxy resin acts as the matrix resin within the elastic layer 30.

[0131] The epoxy resin may, for example, be at least one selected from the group consisting of cresol novolac type epoxy resins, dicyclopentadiene type epoxy resins, biphenyl type epoxy resins, bisphenol A type epoxy resins, and cyclic epoxy resins, but is not limited thereto.

[0132] One concrete example is the application of an elastomer resin epoxidized with epoxy resin. Through this, the elastic layer 30 can be given further improved elasticity, which can help suppress the occurrence of defects in the core substrate and the element.

[0133] The epoxidized elastomer may, by example, be at least one selected from the group consisting of epoxidized polymers and copolymers of epoxidized C4-C11 conjugated dienes, polymers and copolymers of epoxidized epihalohydrins, epoxidized ethylene / propylene copolymers, and epoxidized conjugated diene butyl elastomers, but is not limited to these.

[0134] The epoxy resin may further contain acrylic repeating units. This can help to adjust the elasticity of the elastic layer 30 so that the cavity element 20 can be stably fixed in place.

[0135] The resin composition for the elastic layer may further contain an imide compound. The imide compound may help the elastic layer 30 have a relatively low coefficient of thermal expansion and improved heat resistance. The imide compound may, by example, include at least one of maleimide, nadiimide, and itaconimide.

[0136] The resin composition for the elastic layer may further contain a filler. The filler may be an organic filler and / or an inorganic filler.

[0137] The inorganic filler contained in the resin composition for the elastic layer has the function of lowering the coefficient of thermal expansion of the elastic layer 30. The inorganic filler may, by example, be at least one selected from the group consisting of fillers made of talc, silica, calcium carbonate, mica, quartz, glass fiber, graphite, and alumina, but is not limited thereto.

[0138] Organic fillers in the resin composition for the elastic layer may help to give the elastic layer 30 further improved elasticity. Examples of organic fillers include, but are not limited to, block copolymers such as polymethyl methacrylate-b-polybutyl acrylate-b-polymethyl methacrylate, CTBN (Carboxyl-Terminate Butadiene Acylonitrile), and the like.

[0139] The resin composition for the elastic layer may further contain a curing agent. The curing agent has the function of initiating the crosslinking reaction of the epoxy resin. Examples of curing agents may include amine compounds, carboxylic acid compounds, phenolic compounds, and the like.

[0140] Thermal expansion characteristics of each component of the packaging substrate In practice, the difference in thermal expansion coefficients between the constituent elements of the packaging substrate 100 can be adjusted. Through this, the stress applied to the cavity element 20 or the core substrate 10 during the process of forming build-up layers above or below the core substrate 10 or during the element driving process can be effectively reduced.

[0141] The thermal expansion coefficients of each component can be measured using a thermal mechanical analyzer (TMA) with thermomechanical analysis. For example, the thermal expansion coefficient can be measured using the TMA of TA Instruments' Q400 model.

[0142] The difference between the thermal expansion coefficient of the core substrate 10 and the thermal expansion coefficient of the cavity element 20 may be 15 ppm / °C or less. The difference may be 10 ppm / °C or less. The difference may be 5 ppm / °C or less. The difference may be 1 ppm / °C or more. Through this, it is possible to suppress the formation of excessive stress inside the semiconductor package during the formation process of the redistribution layer 40.

[0143] The difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the core substrate 10 may be 25 ppm / °C or less. The difference may be 23 ppm / °C or less. The difference may be 20 ppm / °C or less. The difference may be 17 ppm / °C or less. The difference may be 1 ppm / °C or more. In such cases, damage to electrical connections within the packaging substrate due to mismatch in thermal expansion coefficients between the insulating layer and the core substrate can be effectively suppressed.

[0144] The thermal expansion coefficient of the core substrate 10 may be 5 ppm / °C to 20 ppm / °C. The thermal expansion coefficient may be 15 ppm / °C or less. The thermal expansion coefficient may be 12 ppm / °C or less. The thermal expansion coefficient may be 10 ppm / °C or less. In such cases, while suppressing excessive expansion of the core substrate during the formation process of the redistribution layer 40, it is possible to effectively suppress a decrease in board-level reliability due to a mismatch in thermal expansion characteristics between the main board and the core substrate during the device driving process.

[0145] The thermal expansion coefficient of the insulating layer may be between 5 ppm / °C and 40 ppm / °C. The thermal expansion coefficient may also be 35 ppm / °C or less. It may also be 30 ppm / °C or less. It may also be 25 ppm / °C or less. It may also be 10 ppm / °C or more. In such cases, the degree of mismatch in thermal expansion coefficients between the insulating layer and the core substrate, and between the insulating layer and the electrically conductive layer, can be reduced in terms of thermal expansion characteristics.

[0146] The thermal expansion coefficient of element 20 may be 10 ppm / °C or less. The thermal expansion coefficient may be 7 ppm / °C or less. The thermal expansion coefficient may be 1 ppm / °C or more.

[0147] The thermal expansion coefficient of the buffer layer 60 may be 10 ppm / °C to 50 ppm / °C. The thermal expansion coefficient may be 15 ppm / °C or higher. The thermal expansion coefficient may be 20 ppm / °C or higher. The thermal expansion coefficient may be 45 ppm / °C or lower. The thermal expansion coefficient may be 40 ppm / °C or lower. In such cases, the degree of warping of the core substrate due to mismatch in thermal expansion coefficients between the core substrate and the main board can be effectively reduced.

[0148] Semiconductor packages Other embodiments of this specification include a semiconductor package comprising a packaging substrate and a main board (not shown) electrically connected to the packaging substrate.

[0149] The packaging board can be mounted on the main board and electrically connected to it.

[0150] The mainboard is not limited to those commonly used in the field of semiconductor equipment.

[0151] The explanation of the packaging substrate will be omitted as it will overlap with the content mentioned above.

[0152] The difference between the thermal expansion coefficient of the main board and the thermal expansion coefficient of the core board can be between 10 ppm / °C and 50 ppm / °C. The difference may be 45 ppm / °C or less. The difference may be 40 ppm / °C or less. In such cases, the warping of the core board due to the mismatch in thermal expansion coefficients between the core board and the main board can be effectively reduced.

[0153] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of symbols]

[0154] 100 Packaging substrates 10 Core boards 11 Cavity Area 12 Storage Unit 13 Side view of the cavity area 14. Bottom surface of the core substrate 20 elements 30 Elastic layer 35 Electrically conductive layer 40 Redistribution layer 50 Bump 60 buffer layers T: Thickness of the elastic layer in the in-plane direction of the core substrate. Tmax is the maximum thickness of the elastic layer in the in-plane direction of the core substrate. Tmin: Minimum thickness of the elastic layer in the core substrate in the in-plane direction. Dt core substrate thickness direction In-plane direction of Dp core substrate θ is the angle between the side surface of the cavity region and the bottom surface of the core substrate.

Claims

1. The system includes a cavity region in which the element is housed, and a core substrate on which the cavity region is arranged. The core substrate is a glass substrate, The cavity region includes a housing portion which is a space formed by a recess in a part of the core substrate, a side surface which is formed on the inside in the thickness direction of the core substrate and forms the outer edge of the housing portion, and an elastic layer which is disposed adjacent to the side surface. The elastic modulus of the elastic layer is 2 Gpa to 15 Gpa. A packaging substrate having a surface energy of 15 dyn / cm to 35 dyn / cm for the elastic layer.

2. The packaging substrate according to claim 1, wherein the coefficient of thermal expansion of the elastic layer is 30 ppm / °C to 70 ppm / °C.

3. Includes a redistribution layer disposed on the core substrate, The rewiring layer includes an insulating layer and an electrically conductive layer disposed within the insulating layer. The packaging substrate according to claim 1, wherein the difference between the thermal expansion coefficient of the insulating layer and the thermal expansion coefficient of the elastic layer is 60 ppm / °C or less.

4. The packaging substrate according to claim 1, wherein the thermal expansion coefficient of the core substrate is 5 ppm / °C to 20 ppm / °C.

5. The side surface of the cavity region has an angle of 60 degrees or more and less than 90 degrees with respect to the lower surface of the core substrate. The packaging substrate according to claim 1, wherein the elastic layer has a minimum thickness in the in-plane direction of the core substrate of 2 μm to 45 μm.

6. The elastic layer is disposed in contact with the side surface of the cavity region. The packaging substrate according to claim 1, wherein the Ra value (arithmetic mean roughness) of the side surface of the cavity region is 1 μm to 50 μm.

7. Includes a buffer layer disposed beneath the core substrate, The packaging substrate according to claim 1, wherein the thermal expansion coefficient of the buffer layer is 10 ppm / °C to 50 ppm / °C.

8. The system includes a cavity region in which the element is housed, and a core substrate on which the cavity region is arranged. The core substrate is a glass substrate, The cavity region includes a housing portion which is a space formed by recessing a part of the core substrate, two or more elements housed in the housing portion, and an elastic layer disposed in at least a part of the space formed between the elements. The elastic modulus of the elastic layer is 2 Gpa to 15 Gpa. A packaging substrate having a surface energy of 15 dyn / cm to 35 dyn / cm for the elastic layer.

9. A semiconductor package comprising a packaging substrate according to claim 1, and a main board electrically connected to the packaging substrate.

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