Semiconductor substrates, substrates for crystal growth

Abstract

To provide a semiconductor substrate and a crystal growth substrate that are less prone to defects at the substrate periphery. [Solution] The crystal growth substrate TK comprises a main substrate, a first seed pattern P1 located above the main substrate and in a region including the center of the main substrate in a plan view, a second seed pattern P2 located above the main substrate and around the first seed pattern, a first semiconductor layer extending from the first seed pattern and a second semiconductor layer extending from the second seed pattern, wherein the first seed pattern is a pattern in which a plurality of first seed portions S1 with a first direction D1 as the longitudinal direction are arranged in a stripe shape, and the second seed pattern includes second seed portions S2 and third seed portions S3 with a longitudinal direction different from the first direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and the like.

Background Art

[0002] Patent Document 1 discloses a method of forming a semiconductor layer by the ELO (Epitaxial Lateral Overgrowth) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The conventional technology has a problem that defects occur at the periphery of the substrate (for example, debris, or hillocks, etc. occur).

Means for Solving the Problems

[0005] The semiconductor substrate according to the present disclosure includes a main substrate, a first seed pattern located above the main substrate and in a region including the center of the main substrate in plan view, a second seed pattern located above the main substrate and surrounding the first seed pattern, a first semiconductor layer extending from the first seed pattern, and a second semiconductor layer extending from the second seed pattern. The first seed pattern is a pattern in which a plurality of first seed portions having a first direction as a longitudinal direction are arranged in a stripe shape, and the second seed pattern includes a second seed portion and a third seed portion having a direction different from the first direction as a longitudinal direction.

Effects of the Invention

[0006] In the semiconductor substrate according to the present disclosure, it is difficult for defects to occur at the periphery of the substrate.

Brief Description of the Drawings

[0007] [Figure 1] This is a plan view showing an example of the configuration of a semiconductor substrate. [Figure 2] This is a plan view showing the configuration of the crystal growth substrate included in a semiconductor substrate. [Figure 3] This is a cross-sectional view showing an example of the configuration of a semiconductor substrate. [Figure 4] This is a cross-sectional view showing an example of the configuration of a semiconductor substrate. [Figure 5] This is a cross-sectional view showing an example of the configuration of a semiconductor substrate. [Figure 6] This is a plan view showing an example of the overall configuration of a semiconductor substrate. [Figure 7] This is a plan view showing an example of the overall configuration of a substrate for crystal growth. [Figure 8] This is a cross-sectional view showing an example of a semiconductor substrate manufacturing method. [Figure 9] This is a cross-sectional view showing an example of a semiconductor substrate manufacturing method. [Figure 10] This is a cross-sectional view showing an example of a semiconductor substrate manufacturing method. [Figure 11] This is a plan view showing an example of the configuration of a substrate for crystal growth. [Figure 12] This is a plan view showing an example of the configuration of a substrate for crystal growth. [Figure 13] This is a plan view showing an example of the configuration of a substrate for crystal growth. [Figure 14] This is a plan view showing an example of the configuration of a substrate for crystal growth. [Figure 15] This is a plan view showing an example of the configuration of a substrate for crystal growth. [Figure 16] This is a cross-sectional view showing a method for manufacturing a substrate for crystal growth. [Figure 17] This is a cross-sectional view showing an example of the configuration of a substrate for crystal growth. [Figure 18] This is a cross-sectional view showing an example of the configuration of a substrate for crystal growth. [Figure 19] This is a flowchart showing a method for manufacturing semiconductor devices. [Figure 20] This is a block diagram of semiconductor device manufacturing equipment. [Figure 21] It is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 22] It is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 23] It is a cross-sectional view showing a method for manufacturing a semiconductor device.

Embodiments for Carrying Out the Invention

[0008] The present embodiment will be described with reference to FIGS. 1 to 23. FIG. 1 is a plan view showing a configuration example of a semiconductor substrate. FIG. 2 is a plan view showing a configuration of a substrate for crystal growth included in the semiconductor substrate. FIGS. 3 to 5 are cross-sectional views showing configuration examples of the semiconductor substrate. FIG. 6 is a plan view showing an overall configuration example of the semiconductor substrate. FIG. 7 is a plan view showing an overall configuration example of the substrate for crystal growth. In the following, the description of "numerical value A to numerical value B" regarding a physical quantity means that the physical quantity is A or more and B or less.

[0009] As shown in FIGS. 1 to 7, the semiconductor substrate 10 includes a main substrate 1, a first seed pattern P1 located above the main substrate 1 and in a region including the center of the main substrate 1 in plan view, a second seed pattern P2 located above the main substrate 1 and around the first seed pattern P1 in plan view, a first semiconductor layer 8F extending from the first seed pattern P1, and a second semiconductor layer 8S extending from the second seed pattern P2. The substrate for crystal growth TK is a substrate that serves as a base for the growth of the first semiconductor layer 8F and the second semiconductor layer 8S in the semiconductor substrate 10. For example, the substrate for crystal growth TK may include the main substrate 1 and the seed layer 4, and may also include a buffer layer under the seed layer 4. The first seed pattern P1 is a pattern of a portion (central portion CA) in the substrate for crystal growth TK that couples with the first semiconductor layer 8F. The second seed pattern P2 is a pattern of a portion (outer peripheral portion GA) in the substrate for crystal growth TK that couples with the second semiconductor layer 8S.

[0010] The first seed pattern P1 includes a first seed section S1 whose longitudinal direction is the first direction D1. The first seed pattern P1 includes a plurality of first seed sections S1. The first seed pattern P1 is a pattern in which a plurality of first seed sections S1 are arranged in a stripe-like pattern. For example, the first seed pattern P1 is a pattern in which a plurality of first seed sections S1 are adjacent to each other in a direction perpendicular to the first direction D1. The second seed pattern P2 includes a second seed section S2 and a third seed section S3 whose longitudinal direction is the second direction D2, which is different from the first direction D1. The second seed pattern P2 includes a plurality of outer peripheral seed sections GS whose longitudinal direction is the second direction D2, which is different from the first direction D1, and the plurality of outer peripheral seed sections GS include the second and third seed sections S2 and S3.

[0011] For example, the second seed pattern P2 includes a second seed portion S2 whose longitudinal direction is a second direction D2 different from the first direction D1, and a third seed portion S3 adjacent to the second seed portion S2, whose longitudinal direction is the second direction D2. For example, the third seed portion S3 may have a shape in which its longitudinal direction is different from the first direction D1 and the second direction D2. The first seed portion S1 is the starting point for the growth of the first semiconductor layer 8F. The second seed portion S2 and the third seed portion S3 are the starting points for the growth of the second semiconductor layer 8S. The third seed portion S3 may not be the starting point for the growth of the second semiconductor layer 8S, but rather the starting point for the growth of the third semiconductor layer 8T.

[0012] In the semiconductor substrate 10, the second seed pattern P2 is located around the first seed pattern P1. This allows raw materials to be consumed on the second seed pattern P2 during the process of forming the first semiconductor layer 8F (for example, the second semiconductor layer 8S is formed), thereby reducing the occurrence of defects at the substrate periphery (generation of unintended structures such as debris and hillocks), and providing a semiconductor substrate 10 in which this is achieved. The semiconductor substrate 10 may include a crystal growth substrate TK (template substrate) containing the first seed pattern P1 and the second seed pattern P2.

[0013] As shown in Figures 2 and 7, the crystal growth substrate TK includes a first seed pattern P1 and a second seed pattern P2. In the crystal growth substrate TK, the first seed pattern P1 is the pattern of the region where the first semiconductor layer 8F is grown. In the crystal growth substrate TK, the second seed pattern P2 is the pattern of the region where the second semiconductor layer 8S is grown. The second seed pattern P2 is located around the first seed pattern P1.

[0014] The first seed pattern P1 includes a first seed section S1 whose longitudinal direction is the first direction D1. The first seed pattern P1 includes a plurality of first seed sections S1. The first seed pattern P1 is a pattern in which a plurality of first seed sections S1 are arranged in a stripe-like pattern. For example, the first seed pattern P1 is a pattern in which a plurality of first seed sections S1 are adjacent to each other in a direction perpendicular to the first direction D1. The second seed pattern P2 includes a second seed section S2 whose longitudinal direction is the second direction D2, which is different from the first direction D1. The second seed pattern P2 includes a plurality of outer peripheral seed sections GS whose longitudinal direction is the second direction D2, which is different from the first direction D1, and the plurality of outer peripheral seed sections GS include the second and third seed sections S2 and S3. The second and third seed sections S2 and S3 may be adjacent to each other. Multiple outer peripheral seed portions GS may include seed portions whose longitudinal direction is different from the second direction D2.

[0015] In a comparative example where a semiconductor layer is formed using a crystal growth substrate that does not have a second seed pattern and has the periphery of the first seed pattern covered by a mask, the semiconductor layer material is not consumed around the first seed pattern, resulting in the formation of debris on the mask and edge growth on the first semiconductor layer formed on the first seed pattern. Furthermore, for example, when a semiconductor layer is formed using a crystal growth substrate that does not have a second seed pattern and does not have a mask around the first seed pattern, hillocks are formed due to defects in the exposed seed layer. In contrast, by using a crystal growth substrate TK, the material is appropriately consumed on the second seed pattern P2 including the second and third seed portions S2 and S3, reducing the occurrence of defects at the substrate periphery. The spacing PK between the first seed pattern P1 and the second seed pattern P2 (for example, the distance between the first and second seed portions S1 and S2) may be 20 [μm] to 500 [μm]. When the spacing PK is 500 [μm] or less, the risk of debris or edge growth can be reduced. When the spacing PK is 20 [μm] or more, the risk of semiconductor layers (for example, the first and second semiconductor layers 8F and 8S) associating with each other can be reduced.

[0016] For example, in a comparative example where a crystal growth substrate in which the longitudinal direction of multiple second seed portions is the same as the longitudinal direction of the first seed portion is used, and the first semiconductor layer is formed by growing the semiconductor in a direction perpendicular to the first direction using the ELO (Epitaxial Lateral Overgrowth) method, the multiple second semiconductor layers grown from the multiple second seed portions also grow in the lateral direction, and as a result of the multiple second semiconductor layers assembling, hillocks are formed on the second semiconductor layer. In contrast, when a crystal growth substrate TK is used and the first semiconductor layer 8F is formed by growing the semiconductor crystal in a direction perpendicular to the first direction D1 using the ELO method, the longitudinal direction of the second seed portion S2 is different from that of the first seed portion, so the lateral growth of the second semiconductor layer 8S grown from the second seed portion S2 can be suppressed.

[0017] As shown in Figures 1 and 2, the semiconductor substrate 10 may include a first non-seeded portion MF along the first seeded portion S1 and a second non-seeded portion MS along the second seeded portion S2 and the third seeded portion S3. The first non-seeded portion MF and the second non-seeded portion MS may be growth suppression regions that suppress the longitudinal growth of the nitride semiconductor.

[0018] The area of ​​the second seed pattern P2 is smaller than the area of ​​the first seed pattern P1. For example, the area of ​​the second seed pattern P2 may be 1 / 5 or less of the area of ​​the first seed pattern P1. For example, the area of ​​the second seed pattern P2 may be 1 / 10 or less of the area of ​​the first seed pattern P1. For example, the area of ​​the second seed pattern P2 may be 1 / 20 or less of the area of ​​the first seed pattern P1.

[0019] The first seed pattern P1 is a region for growing a nitride semiconductor layer to form a semiconductor device. The first semiconductor layer 8F is a semiconductor layer for forming a semiconductor device. The second seed pattern P2 is a region for growing a nitride semiconductor layer to reduce the occurrence of defects at the substrate edge. The second semiconductor section 8S is a semiconductor layer to reduce the occurrence of defects at the substrate edge. If the area of ​​the second seed pattern P2 is smaller than the area of ​​the first seed pattern P1, more semiconductor devices can be manufactured using the semiconductor substrate 10.

[0020] As shown in Figures 3 to 5, the semiconductor substrate 10 may include a main substrate 1 and a seed layer 4 located above the main substrate 1 and containing a first seed pattern P1 and a second seed pattern P2. The semiconductor substrate 10 may also include a mask pattern 6 located above the main substrate 1. The mask pattern 6 may include a first non-seeded area MF and a second non-seeded area MS. The mask pattern 6 may function as a selective growth mask to suppress the vertical growth of nitride semiconductor from the upper surface of the seed layer 4. The mask pattern 6 may include at least one of a silicon nitride film and a silicon oxide film.

[0021] The main substrate 1 may be a different type of substrate with a different lattice constant from the nitride semiconductor (for example, a sapphire substrate, a silicon substrate, or a silicon carbide substrate). The crystal growth substrate TK and the semiconductor substrate 10 may be disc-shaped. The crystal growth substrate TK and the semiconductor substrate 10 may have notches (orientation flats, or notches, etc.) indicating the crystal direction.

[0022] The first semiconductor layer 8F may contain a nitride semiconductor as its main component. A nitride semiconductor can be represented, for example, as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1). Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), or InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples of GaN-based semiconductors include GaN, AlGaN, AlGaInN, or InGaN. The first semiconductor layer 8F may be doped (e.g., n-type including a donor) or undoped. The first semiconductor layer 8F may be a nitride semiconductor for forming a semiconductor device. The second semiconductor layer 8S may be a nitride semiconductor for ~.

[0023] A semiconductor substrate is a substrate that contains a semiconductor. The main substrate 1 may contain a semiconductor (for example, silicon or silicon carbide) or it may not contain a semiconductor. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate. The seed layer 4 (first and second seed patterns P1 and P2) may contain a nitride semiconductor.

[0024] As shown in Figures 1 and 2, the second seed portion S2 and the second semiconductor layer 8S may be located in the outer peripheral region GA of the semiconductor substrate 10. The third seed portion S3 and the third semiconductor layer 8T may be located in the outer peripheral region GA. The outer peripheral region GA may be annular. The first seed portion S1 and the first semiconductor layer 8F may be located in the central region (non-peripheral region) CA, which is inside the outer peripheral region GA.

[0025] As shown in Figure 6, in the central part CA, multiple ridge-like semiconductor regions U are arranged in the second direction D2. One of the multiple ridge-like semiconductor regions U may be the first semiconductor layer 8F. The multiple ridge-like semiconductor regions U may include ridge-like semiconductor regions U that are greater in distance from the center of the substrate in the second direction D2 than the first semiconductor layer 8F, and shorter than the first semiconductor layer 8F (less in length in the first direction D1).

[0026] The semiconductor substrate 10 may include a mask pattern 6 located above the main substrate 1. In the peripheral GA, the inverted pattern of the mask pattern 6 may correspond to the second seed pattern P2. The mask pattern 6 may be located above the seed layer 4.

[0027] The second seed pattern P2 may be stripe-shaped. The widths (lengths in the first direction D1) of the second seed portion S2 and the third seed portion S3 may be equal. The first direction D1 and the second direction D2 may be orthogonal. As shown in Figures 6 and 7, the first direction D1 may be perpendicular to the orientation flat FR of the main substrate 1.

[0028] The first semiconductor layer 8F and the second semiconductor layer 8S may contain a nitride semiconductor. The first semiconductor layer 8F and the second semiconductor layer 8S may be a nitride semiconductor crystal. The first direction D1 may be the m-axis direction (<1-100> direction) of the nitride semiconductor. The second direction D2 may be the a-axis direction (<11-20> direction) of the nitride semiconductor. The third direction D3 may be the c-axis direction ( <0001> It can be a direction.

[0029] As shown in Figure 1, the second semiconductor layer 8S may be adjacent to a plurality of ridge-like semiconductor portions U arranged in the second direction D2. The ends of each of the plurality of ridge-like semiconductor portions U (including the first semiconductor layer 8F) may be tapered. Since the plurality of ridge-like semiconductor portions U (including the first semiconductor layer 8F) become shorter as they move away from the center of the substrate in the second direction D2, the tip positions of the plurality of ridge-like semiconductor portions U will be downward sloping to the right (or downward sloping to the left). The second semiconductor layer 8S may have a sloped surface FS (a surface oblique to the m-plane of the nitride semiconductor) that slopes downward to the right or left in a plan view.

[0030] The crystal growth substrate TK includes a ridge portion R. The upper part of the ridge portion R may be the first seed portion S1. The ridge portion R may include a convex portion Q on the upper surface of the main substrate. As shown in Figure 4, a convex portion Q on the upper surface of the main substrate may also be formed on the outer peripheral portion GA. As shown in Figure 5, a convex portion on the upper surface of the main substrate may not be formed on the outer peripheral portion GA.

[0031] The first semiconductor layer 8F does not need to be in contact with the first non-seed portion MF. That is, the first semiconductor layer 8F may include a base portion B1 coupled to the first seed portion S1 and a wing portion W1 extending from the base portion B1 in a first direction D1, with a gap JD located between the wing portion W1 and the first non-seed portion MF, and the wing portion W1 may be in a floating state.

[0032] As shown in Figure 3, the first semiconductor layer 8F can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the first seed portion S1. Of the first semiconductor layer 8F, the base portion B1 located above the first seed portion S1 becomes a dislocation inheritance portion with many through-dislocations, while the wing portion W1 becomes a low-defect portion with a smaller through-dislocation density compared to the dislocation inheritance portion. The wing portion W1 grows laterally above the first non-seed portion MF and its growth is stopped before it meets the wing portion WS, which grows laterally in the opposite direction. That is, a gap GP is formed between the wing portions W1 and WS.

[0033] As shown in Figures 3 to 5, the first semiconductor layer 8F may be located above the first seed portion S1 and the first non-seed portion MF, and the second semiconductor layer 8S may be located above the second seed portion S2. The thickness of the second semiconductor layer 8S (height in the c-axis direction = length in the third direction D3) may be smaller than the thickness of the first semiconductor layer 8F. This ensures the thickness of the void JD near the outer peripheral GA (height in the third direction D3).

[0034] The width of the second non-seed portion MS (width in the first direction D1) may be smaller than the width of the second seed portion S2 (maximum width in the first direction D1). The width of the second seed portion S2 (maximum width) may be larger than the width of the first seed portion S1 (width in the second direction D2). The width of the second seed portion S2 (maximum width) may be larger than the width of the first non-seed portion MF (width in the second direction D2). The area of ​​the second non-seed portion MS may be smaller than the area of ​​the second seed portion S2. If the height of the second semiconductor layer 8S is greater than the height of the first semiconductor layer 8F, there is a risk that the transfer of the first semiconductor layer 8F will be inhibited by the second semiconductor layer 8S during the process of forming a semiconductor device using the first semiconductor layer 8F. If the area of ​​the second non-seed portion MS is smaller than the area of ​​the second seed portion S2, the region in the second seed pattern where raw material is consumed and the second semiconductor layer 8S is formed becomes larger, thus reducing the risk that the height of the second semiconductor layer 8S will be greater than the height of the first semiconductor layer 8F formed on the first seed portion S1.

[0035] The width of the second non-seed portion MS (width in the first direction D1) may be smaller than the width of the second semiconductor layer 8S (maximum width in the first direction D1). The width of the second semiconductor layer 8S (maximum width) may be larger than the width of the first semiconductor layer 8F (width in the second direction D2). The width of the second semiconductor layer 8S (maximum width) may be larger than the width of the first non-seed portion MF (width in the second direction D2).

[0036] The width of the second seed portion S2 (width in the first direction D1) may be five times or more, or even ten times or more, the width of the second non-seed portion MS (width in the first direction D1). This ensures sufficient thickness of the void JD near the outer periphery GA (height in the third direction D3), and reduces in-plane variation in the thickness of the void JD.

[0037] When the outer peripheral GA is annular, the width of the outer peripheral GA (length in the direction perpendicular to the tangent) may be 20 [μm] to 1000 [μm]. The width (maximum width) of the second seed portion S2 may be 20 [μm] or more, or 50 [μm] or more. This makes it possible to avoid edge growth (abnormal growth) of the first semiconductor layer 8F near the outer peripheral GA. The width (maximum width) of the second seed portion S2 may be 500 [μm] or less. The width (maximum width) of the second semiconductor layer 8S may be 20 [μm] or more, or 50 [μm] or more. The width (maximum width) of the second semiconductor layer 8S may be 500 [μm] or less.

[0038] The semiconductor substrate 10 comprises a third semiconductor layer 8T located on a third seed portion S3, and the second semiconductor layer 8S and the third semiconductor layer 8T may be single crystals of nitride semiconductors. In a plan view, the second semiconductor layer 8S and the third semiconductor layer 8T may be adjacent to each other via a second non-seed portion MS. A plan view means viewing (including perspective) in the direction normal to the semiconductor substrate 10 or the crystal growth substrate TK (corresponding to viewing in the vertical direction in a cross-sectional view).

[0039] Figures 8 and 9 are cross-sectional views showing an example of a semiconductor substrate manufacturing method. As shown in Figure 8, the first seed portion S1 may be for lateral growth of the nitride semiconductor (for growth in the second direction D2, which is the a-axis direction), and the first semiconductor layer 8F may grow on the first seed portion S1 and the first non-seed portion MF. As shown in Figure 9, the second seed portion S2 and the third seed portion S3 may be for longitudinal growth of the nitride semiconductor (for growth in the third direction D3, which is the c-axis direction), and the second semiconductor layer 8S may grow on the second seed portion S2, while the third semiconductor layer 8T may grow on the third seed portion S3.

[0040] Figure 10 is a cross-sectional view showing an example of a semiconductor substrate manufacturing method. In Figure 8, a gap JD is located between the wing portion W1 and the first non-seed portion MF of the first semiconductor layer 8F, but the configuration is not limited to this. As shown in Figure 10, the wing portion W1 of the first semiconductor layer 8F may be in contact with the first non-seed portion MF (mask pattern 6). As shown in Figure 10, the seed layer 4 may be formed over the entire upper surface of the main substrate 1, and the inverted patterns (opening patterns) of the mask pattern 6 located on the seed layer 4 may correspond to the first and second seed patterns P1 and P2.

[0041] Figures 11 and 12 are plan views showing examples of the configuration of a crystal growth substrate. In Figures 2 and 7, the first direction D1 and the second direction D2 are orthogonal, but the configuration is not limited to this. The longitudinal direction (second direction D2) of the stripe-shaped second and third seed portions S2 and S3 is preferably the a-axis direction of the first semiconductor layer 8F (for example, a hexagonal nitride semiconductor crystal). For this reason, as shown in Figure 11, the second direction D2 may be the direction obtained by rotating the direction DH orthogonal to the first direction D1 (the longitudinal direction of the first seed portion S1) 120 degrees counterclockwise. Alternatively, as shown in Figure 12, the second direction D2 may be the direction obtained by rotating the direction DH orthogonal to the first direction D1 120 degrees clockwise.

[0042] Figures 13 and 14 are plan views showing examples of the configuration of a crystal growth substrate. As shown in Figures 13 and 14, the second seed pattern P2 of the outer peripheral GA may be a multiple ring shape having the same center (substrate center). In this case, the longitudinal direction D2 of the second and third seed portions S2 and S3 may be in the direction along the circumference.

[0043] Figure 15 is a plan view showing an example of the configuration of a crystal growth substrate. As shown in Figure 15, the second seed pattern P2 may include second and third seed portions S2 and S3 with the second direction D2 as the longitudinal direction, and fourth and fifth seed portions S4 and S5 with the fourth direction D4 as the longitudinal direction. The second and fourth seed portions S2 and S4 may be connected or separated as shown in Figure 15. The third and fifth seed portions S3 and S5 may be connected or separated as shown in Figure 15.

[0044] In Figure 15, the third direction D3 is the thickness direction of the crystal growth substrate TK, and the second direction D2 and the fourth direction D4 may be the a-axis direction of the first semiconductor layer 8F (for example, a hexagonal nitride semiconductor crystal). For example, the second direction D2 may be the direction obtained by rotating the direction DH perpendicular to the first direction D1 120 degrees counterclockwise, and the fourth direction D4 may be the direction obtained by rotating the direction DH perpendicular to the first direction D1 120 degrees clockwise.

[0045] Figure 16 is a cross-sectional view showing a method for manufacturing a crystal growth substrate. In Figure 16, a planar seed layer SJ and a planar resist are deposited on a main substrate 1, and the planar resist is patterned. Then, using the resist pattern Z as a mask, the planar seed layer SJ is patterned and the main substrate 1 is excised (formation of upper surface protrusions). After that, the resist pattern Z and the exposed parts of the main substrate 1 are covered with a planar mask MJ, the resist pattern Z is removed, and the mask on the resist is lifted off to obtain a crystal growth substrate TK.

[0046] The first seed section S1 is supplied with argon or oxygen in 2 × 10⁻⁶ units. 18 / cm 3 It may be composed of nitride semiconductors (such as AlN, AlON, or GaN-based semiconductors) containing the above. The planar seed layer SJ (including the first seed portion S1) may be formed by sputtering.

[0047] Figures 17 and 18 are cross-sectional views showing examples of the configuration of a crystal growth substrate. As shown in Figures 17 and 18, the semiconductor substrate 10 comprises a main substrate 1 and a seed layer 4 located above the main substrate 1, where the first to third seed portions S1 to S3 are unmodified regions AX of the seed layer 4, and the first unseeded portion MF and the second unseeded portion MS may be modified regions AY of the seed layer 4.

[0048] In this case, the resist film deposited on the seed layer 4 is patterned, and the exposed seed material is surface-modified in the irradiated area by, for example, plasma, thereby forming the modified region AY. Specific examples of plasma include argon plasma, oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture thereof. In Figures 17 and 18, the unmodified region AX (first to third seed portions S1 to S3) may be aluminum nitride, and the modified region AY (first unseeded portion MF and second unseeded portion MS) may be aluminum oxynitride.

[0049] Figure 19 is a flowchart illustrating a method for manufacturing a semiconductor device. Figure 20 is a block diagram showing a semiconductor device manufacturing apparatus. Figures 21 to 23 are cross-sectional views illustrating a method for manufacturing a semiconductor device. As shown in Figures 19 and 21 to 23, the method for manufacturing a semiconductor device includes a step S10 for preparing a semiconductor substrate 10, a step for forming a functional layer 9 on top of a first semiconductor layer 8F, and a step S30 for separating at least a portion of the first semiconductor layer 8F and the functional layer 9 from the main substrate 1 and the seed layer 4. The functional layer 9 may include an active layer (e.g., an emissive layer). In addition to the active layer, the functional layer 9 may include a p-type semiconductor layer and an electrode (e.g., an anode).

[0050] The semiconductor substrate manufacturing apparatus 50 shown in Figure 20 comprises an apparatus M15 that performs process S10 in Figure 19, an apparatus M25 that performs process S20, an apparatus M35 that performs process S30, and a control device M5 that controls apparatuses M15, M25, and M35. Apparatus M25 may be an MOCVD apparatus.

[0051] In Figure 21, after bonding the functional layer 9 to the mounting substrate MK via the solder layer HD, the element portion XA including the wing portion W1 and the functional layer 9 can be separated as a semiconductor device 20 (e.g., a semiconductor chip) by peeling the first semiconductor layer 8F from the first seed portion S1. Furthermore, a semiconductor device 30 including the mounting substrate MK and the semiconductor device 20 is obtained. The void JD under the wing portion W1 facilitates the peeling of the first semiconductor layer 8F. During the peeling of the first semiconductor layer 8F, at least one of the base portion B1 and the first seed portion S1 is fractured.

[0052] The element XA and the element XB adjacent to it in the second direction D2 do not need to be separated from the crystal growth substrate TK, which allows for selective transfer where the transfer density is lower than the element density.

[0053] The second semiconductor layer 8S of the outer periphery GA does not need to be separated from the seed layer 4 (second seed portion S2). In other words, the second and third semiconductor layers 8S·8T may function as sacrificial layers or dummy layers.

[0054] Figures 22 and 23 show that a semiconductor substrate 10 is prepared, which includes an electrode EA (e.g., an anode) in the functional layer 9 and a tether portion TZ (a portion connecting the main body and base below the active layer) in the wing portion W, and a mounting substrate MK including a pad electrode PD. After the anode E1 is bonded to the pad electrode PD of the mounting substrate MK via a solder layer HD, the tether portion TZ is broken to separate the wing portion W1 (part of the first semiconductor layer 8F) from the first seed portion S1, and the element portion XA including the wing portion W1 and the functional layer 9 can be separated as a semiconductor device 20. Furthermore, a semiconductor device 30 including the mounting substrate MK and the semiconductor device 20 is obtained. The air gap JD on the wing portion W1 facilitates the breaking of the tether portion TZ.

[0055] Specific examples of semiconductor devices 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, or transistors (including power transistors and high electron mobility transistors).

[0056] Specific examples of semiconductor devices 30 include display devices, communication devices, laser emitters, lighting devices, information processing devices, sensing devices, power control devices, and the like.

[0057] [Examples] As the main substrate 1, a silicon substrate, silicon carbide substrate (4H-SiC, 6H-SiC substrate), sapphire substrate, nitride substrate (GaN, AlN substrate, etc.), or ScMgAlO substrate can be used.

[0058] As the seed layer 4, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, or Al, etc., formed at a low temperature (below 500°C) may be used. The thickness of the seed layer 4 is, for example, 10 nm to 500 nm.

[0059] In Example 1, an AlN film (seed layer 4) was deposited on top of the main substrate, which was either a sapphire or silicon substrate, using the sputtering method. By using sputtering methods such as parallel plate sputtering, magnetron sputtering, or pulsed sputtering, low-temperature and low-cost film deposition is possible. Alternatively, a highly crystalline AlN film may be formed using the MOCVD method.

[0060] A buffer layer may be formed between the main substrate 1 and the seed layer 4 (e.g., a nitride semiconductor layer), and the buffer layer improves the crystallinity and flatness of the seed layer 4. The buffer layer may be planar or may have a shape that matches the pattern (P1·P2) of the seed layer 4 (e.g., stripe shape). As the buffer layer, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, or Al, etc., formed at a low temperature (below 500°C) may be used. The thickness of the buffer layer is, for example, about 10 nm to 500 nm.

[0061] The mask pattern 6 is formed on the main substrate 1 using a material that suppresses the longitudinal growth of nitride semiconductors and enables lateral growth. Examples of materials for the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., as well as silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, or high-melting-point metals (e.g., molybdenum, tungsten, or platinum). The mask pattern 6 may be a single layer film made of one of these materials, or a multilayer film made by combining multiple of these materials. The thickness of the mask pattern 6 is, for example, 5 nm to 2 μm.

[0062] The first semiconductor layer 8F, the second semiconductor layer 8S, and the third semiconductor layer 8T (collectively referred to as semiconductor layer 8 as appropriate) are formed on a crystal growth substrate TK using an MOCVD apparatus. In Example 1, semiconductor layer 8 was a GaN layer, with a growth temperature of 1000-1200 degrees Celsius, a V / III ratio of 500-20000, and a growth pressure of 50 kPa. To make semiconductor layer 8 n-type, it may be doped by flowing SiH4 through it. Even without introducing SiH4, it is possible to perform Si doping with Si evaporated from the mask pattern by using a Si-containing material, such as SiO2 or SiN, in the mask pattern.

[0063] It is preferable to set the film deposition conditions in at least two stages. In the first stage, the film deposition temperature is set to about 1030°C and V / III is set to about 2000 to form growth nuclei (vertical growth areas) of the first semiconductor layer 8F (see Figure 8). The thickness (height) of the growth nuclei may be about 0.2 to 3.0 [μm]. The width of the growth nuclei may be about the same as the width of the ridge area R (width of the first seed area S1) or slightly exceeding the size in the a-axis direction (second direction). In the second stage, the film deposition temperature is raised to about 100°C to grow the wing area W1 (GaN layer) from the growth nuclei in the lateral direction (a-axis direction), and growth is stopped when the width of the gap GP between the wing areas growing in opposite directions on the void reaches a specified value (for example, 10 μm or less).

[0064] (Appendix) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and these variations are also included in the embodiments.

[0065] Disclosure 1: A semiconductor substrate comprising a first seed pattern, a first semiconductor layer connected to the first seed pattern, a second seed pattern, and a second semiconductor layer connected to the second seed pattern, wherein the first seed pattern is located inside the second seed pattern, the first seed pattern includes a first seed portion with a first direction as its longitudinal direction, and the second seed pattern includes a second seed portion with a second direction different from the first direction as its longitudinal direction, and a third seed portion adjacent to the second seed portion with the second direction as its longitudinal direction.

[0066] Disclosure Item 2: In Disclosure Item 1, the second seed pattern is striped.

[0067] Disclosure Item 3: In Disclosure Item 1 or 2, the first direction and the second direction are orthogonal.

[0068] Disclosure Item 4: In any one of Disclosure Items 1 to 3, the widths of the second seed portion and the third seed portion are equal.

[0069] Disclosure Item 5: In any one of Disclosure Items 1 to 4, the first semiconductor layer and the second semiconductor layer include a nitride semiconductor, and the first direction is the m-axis direction of the nitride semiconductor.

[0070] Disclosure Item 6: In Disclosure Item 5, the first semiconductor layer and the second semiconductor layer include a nitride semiconductor, and the second direction is the a-axis direction of the nitride semiconductor.

[0071] Disclosure Item 7: In any one of Disclosure Items 1 to 6, the first semiconductor layer includes a first non-seed portion along the first seed portion and a second non-seed portion along the second seed portion and the third seed portion, wherein the first semiconductor layer is located above the first seed portion and the first non-seed portion, and the second semiconductor layer is located above the second seed portion.

[0072] Disclosure Item 8: In Disclosure Item 7, the width of the second non-seeded portion is smaller than the width of the second seeded portion.

[0073] Disclosure Item 9: In any one of Disclosure Items 1 to 8, the width of the second seed portion is greater than the width of the first seed portion.

[0074] Disclosure Item 10: In Disclosure Item 7, the width of the second seed portion is greater than the width of the first non-seed portion.

[0075] Disclosure Item 11: In any one of Disclosure Items 1 to 10, the second seed portion and the second semiconductor layer are located on the outer periphery.

[0076] Disclosure Item 12: In Disclosure Item 11, the outer periphery is annular.

[0077] Disclosure Item 13: In Disclosure Item 7, the first semiconductor layer does not contact the first non-seed portion.

[0078] Disclosure Item 14: In any one of Disclosure Items 1 to 13, the present invention comprises a main substrate and a seed layer located above the main substrate and including the first seed pattern and the second seed pattern.

[0079] Disclosure Item 15: In Disclosure Item 14, a mask pattern is provided located above the seed layer, and in the outer periphery, the inverted pattern of the mask pattern corresponds to the second seed pattern.

[0080] Disclosure Item 16: In Disclosure Item 7, the width of the second seed portion is five times or more the width of the second non-seed portion.

[0081] Disclosure Item 17: In Disclosure Item 13, the width of the second seed portion is 10 times or more the width of the second non-seed portion.

[0082] Disclosure Item 18: In any one of Disclosure Items 1 to 17, the width of the second seed portion is 20 [μm] or more.

[0083] Disclosure Item 19: In any one of Disclosure Items 1 to 18, the width of the second seed portion is 500 [μm] or less.

[0084] Disclosure Item 20: In any one of Disclosure Items 1 to 19, a third semiconductor layer is provided located on the third seed portion, wherein the second semiconductor layer and the third semiconductor layer are single crystals of nitride semiconductors.

[0085] Disclosure Item 21: In Disclosure Item 14, the first semiconductor layer and the second semiconductor layer include a nitride semiconductor, and the main substrate is a different type of substrate with a different lattice constant from the nitride semiconductor.

[0086] Disclosure Item 22: In Disclosure Item 7, the device comprises a main substrate and a seed layer located above the main substrate, wherein the second seed portion is an unmodified region of the seed layer, and the second non-seed portion is a modified region of the seed layer.

[0087] Disclosure Item 23: In any one of Disclosure Items 1 to 22, the first seed portion is for lateral growth of the nitride semiconductor, and the second seed portion and the third seed portion are for longitudinal growth of the nitride semiconductor.

[0088] Disclosure 24: A crystal growth substrate comprising a first seed pattern and a second seed pattern, wherein the first seed pattern is located inward of the second seed pattern, the first seed pattern includes a first seed portion with a first direction as its longitudinal direction, and the second seed pattern includes a second seed portion with a second direction different from the first direction as its longitudinal direction, and a third seed portion adjacent to the second seed portion with the second direction as its longitudinal direction.

[0089] Disclosure Item 25: A method for manufacturing a semiconductor device, comprising the steps of preparing a semiconductor substrate according to any one of Disclosure Items 1 to 23, and forming a functional layer on top of the first semiconductor layer.

[0090] Disclosure Item 26: In Disclosure Item 25, the semiconductor substrate comprises a main substrate and a seed layer located above the main substrate and including the first seed pattern and the second seed pattern, and includes a step of separating at least a portion of the first semiconductor layer and the functional layer from the main substrate and the seed layer.

[0091] Disclosure Item 27: In Disclosure Item 26, the second semiconductor layer is not separated from the seed layer.

[0092] Disclosure Item 28: A semiconductor device manufacturing apparatus comprising an apparatus for performing each of the processes described in Disclosure Item 25, and a control device for controlling the apparatus.

[0093] Disclosure Item 29: A semiconductor substrate comprising a main substrate, a first seed pattern located above the main substrate and in a region including the center of the main substrate in a plan view, a second seed pattern located above the main substrate and around the first seed pattern, a first semiconductor layer extending from the first seed pattern, and a second semiconductor layer extending from the second seed pattern, wherein the first seed pattern is a pattern in which a plurality of first seed portions are arranged in a stripe shape with a first direction as its longitudinal direction, and the second seed pattern includes second seed portions and third seed portions with a longitudinal direction different from the first direction.

[0094] Disclosure Item 30: In any one of Disclosure Items 1 to 29, the area of ​​the second seed pattern is smaller than the area of ​​the first seed pattern.

[0095] Disclosure Item 31: In any one of Disclosure Items 1 to 30, the first semiconductor layer is a nitride semiconductor layer for forming a semiconductor device, and the second semiconductor layer is a nitride semiconductor layer for reducing defects at the substrate periphery.

[0096] Disclosure 32: A crystal growth substrate comprising a main substrate, a first seed pattern located above the main substrate and in a plan view in a region including the center of the main substrate, and a second seed pattern located above the main substrate and in a plan view in a region including the center of the main substrate, wherein the first seed pattern is a pattern in which a plurality of first seed portions are arranged in a stripe shape with a first direction as the longitudinal direction, and the second seed pattern includes second seed portions and third seed portions with a longitudinal direction different from the first direction.

[0097] Disclosure Item 33: In any one of Disclosure Items 1 to 32, the first seed pattern grows a nitride semiconductor layer for forming a semiconductor device, and the second seed pattern grows a nitride semiconductor layer for reducing defects at the substrate periphery. [Explanation of Symbols]

[0098] 1 Main board 4. Seed Layer 6 Mask Patterns 10 Semiconductor substrates 20 Semiconductor Devices 30 Semiconductor Devices 8F First Semiconductor Layer 8S Second Semiconductor Layer 8T Third Semiconductor Layer TK crystal growth substrate P1 First Seed Pattern P2 First Seed Pattern S1 1st Seed Division S2 Second seed section (outer seed section) S3 Third seed section (outer seed section) MF 1st Non-Seed Division MS 2nd Non-Seed Section GA outer periphery JD void W1 Wing section B1 Base

Claims

1. Main board and A first seed pattern located above the main substrate and in a plan view, in a region including the center of the main substrate, and a second seed pattern located around the first seed pattern, The device comprises a first semiconductor layer extending from the first seed pattern and a second semiconductor layer extending from the second seed pattern, The first seed pattern is a pattern in which a plurality of first seed portions are arranged in a stripe shape with the first direction being the longitudinal direction. The second seed pattern is a semiconductor substrate including a second seed portion and a third seed portion, with the longitudinal direction being a second direction different from the first direction.

2. The semiconductor substrate according to claim 1, wherein the second seed pattern is a stripe shape including the second seed portion and the third seed portion.

3. The semiconductor substrate according to claim 1, wherein the first direction and the second direction are orthogonal.

4. The semiconductor substrate according to claim 1, wherein the widths of the second seed portion and the third seed portion are equal.

5. The first semiconductor layer and the second semiconductor layer include a nitride semiconductor, The semiconductor substrate according to claim 1, wherein the first direction is the m-axis direction of the nitride semiconductor.

6. The semiconductor substrate according to claim 5, wherein the second direction is the a-axis direction of the nitride semiconductor.

7. The second seed section and the third seed section are adjacent to each other, It includes a first non-seeded portion along one of the plurality of first seeded portions, and a second non-seeded portion along the second seeded portion and the third seeded portion, The first semiconductor layer is located above the first seed portion and the first non-seed portion. The semiconductor substrate according to claim 1, wherein the second semiconductor layer is located above the second seed portion.

8. The semiconductor substrate according to claim 7, wherein the width of the second non-seed portion is smaller than the width of the second seed portion.

9. The semiconductor substrate according to claim 1, wherein the width of the second seed portion is greater than the width of the first seed portion.

10. The semiconductor substrate according to claim 7, wherein the width of the second seed portion is greater than the width of the first non-seed portion.

11. The semiconductor substrate according to any one of claims 1 to 10, wherein the second seed portion and the second semiconductor layer are located on the outer periphery.

12. The semiconductor substrate according to claim 11, wherein the outer peripheral portion is annular.

13. The semiconductor substrate according to claim 7, wherein the first semiconductor layer does not come into contact with the first non-seed portion.

14. A semiconductor substrate according to any one of claims 1 to 10, comprising a seed layer located above the main substrate and including the first seed pattern and the second seed pattern.

15. The second seed pattern is located on the outer periphery, It comprises a mask pattern located above the seed layer, The semiconductor substrate according to claim 14, wherein in the outer peripheral portion, the inverted pattern of the mask pattern corresponds to the second seed pattern.

16. The semiconductor substrate according to claim 7, wherein the width of the second seed portion is five times or more the width of the second non-seed portion.

17. The semiconductor substrate according to claim 7, wherein the width of the second seed portion is 10 times or more the width of the second non-seed portion.

18. The semiconductor substrate according to any one of claims 1 to 10, wherein the width of the second seed portion is 20 [μm] or more.

19. The semiconductor substrate according to any one of claims 1 to 10, wherein the width of the second seed portion is 500 [μm] or less.

20. The semiconductor substrate according to any one of claims 1 to 10, wherein the second semiconductor layer is a single crystal of a nitride semiconductor.

21. The first semiconductor layer and the second semiconductor layer include a nitride semiconductor, The semiconductor substrate according to any one of claims 1 to 10, wherein the main substrate is a different type of substrate with a different lattice constant from the nitride semiconductor.

22. The semiconductor substrate according to any one of claims 1 to 10, wherein the first seed portion is a region for growing a nitride semiconductor in the vertical direction and in the horizontal direction, and the second seed portion is a region for growing a nitride semiconductor only in the vertical direction.

23. The semiconductor substrate according to any one of claims 1 to 10, wherein the area of ​​the second seed pattern is smaller than the area of ​​the first seed pattern.

24. The semiconductor substrate according to any one of claims 1 to 10, wherein the first semiconductor layer is a nitride semiconductor layer for forming a semiconductor device, and the second semiconductor layer is a nitride semiconductor layer for reducing defects at the substrate periphery.

25. Main board and A first seed pattern is located above the main substrate and, in a plan view, is located in a region including the center of the main substrate. The substrate comprises a second seed pattern located above the main substrate and positioned around the first seed pattern in a plan view, The first seed pattern is a pattern in which a plurality of first seed portions are arranged in a stripe shape with the first direction being the longitudinal direction. The second seed pattern is a crystal growth substrate including a second seed portion and a third seed portion, the second seed pattern having a longitudinal direction different from the first direction.

26. The crystal growth substrate according to claim 25, wherein the first seed pattern is used to grow a nitride semiconductor layer for forming a semiconductor device, and the second seed pattern is used to grow a nitride semiconductor layer for reducing defects at the substrate periphery.

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